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From: lee.m.hamel@intel.com
To: "devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Wu, Hao A" <hao.a.wu@intel.com>, "Ni, Ray" <ray.ni@intel.com>
Subject: [PATCH] Edk2/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c:XhcCreateUsbHc: check return value of XHC_PAGESIZE_OFFSET
Date: Sat, 18 Jun 2022 02:37:41 +0000	[thread overview]
Message-ID: <MW3PR11MB471652395BE0113E3A5876D7A3AE9@MW3PR11MB4716.namprd11.prod.outlook.com> (raw)

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3954

--- C:\Edk2\MdeModulePkg\Bus\Pci\XhciDxe\Xhci.c         Tue Jun 14 21:29:21 2022 UTC
+++ C:\myEdk2\MdeModulePkg\Bus\Pci\XhciDxe\Xhci.c Tue Jun 14 21:26:57 2022 UTC
@@ -1,7 +1,7 @@
/** @file
   The XHCI controller driver.
-Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -1813,7 +1813,12 @@
   // This xHC supports a page size of 2^(n+12) if bit n is Set. For example,
   // if bit 0 is Set, the xHC supports 4k byte page sizes.
   //
-  PageSize      = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;
+  PageSize      = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET);
+  if(PageSize == 0xFFFFFFFF) {
+  DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: error reading XHC_PAGESIZE_OFFSET\n"));
+    goto ON_ERROR;
+  }
+  PageSize      &= XHC_PAGESIZE_MASK;
   Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12);
   ExtCapReg              = (UINT16)(Xhc->HcCParams.Data.ExtCapReg);


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             reply	other threads:[~2022-06-18  2:37 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-18  2:37 lee.m.hamel [this message]
2022-06-20  1:46 ` [PATCH] Edk2/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c:XhcCreateUsbHc: check return value of XHC_PAGESIZE_OFFSET Wu, Hao A

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