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Tue, 14 Dec 2021 21:44:32 +0000 Received: from MW3PR11MB4747.namprd11.prod.outlook.com ([fe80::7850:1961:886:ddbe]) by MW3PR11MB4747.namprd11.prod.outlook.com ([fe80::7850:1961:886:ddbe%8]) with mapi id 15.20.4778.018; Tue, 14 Dec 2021 21:44:32 +0000 From: "Oram, Isaac W" To: "devel@edk2.groups.io" , "Oram, Isaac W" , "KARPAGAVINAYAGAM, MANICKAVASAKAM" CC: "Desimone, Nathaniel L" , "DOPPALAPUDI, HARIKRISHNA" , "Jha, Manish" , "Ponnusamy, Suresh" , "Bobroff, Zachary" Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V2] WhitleyOpenBoardPkg : Support for Junction City Platform Thread-Topic: [edk2-devel] [edk2-platforms] [PATCH V2] WhitleyOpenBoardPkg : Support for Junction City Platform Thread-Index: AQHX7JT8abc+CypldEyo0gWNbRzEjawpZVSwgAkoxAA= Date: Tue, 14 Dec 2021 21:44:32 +0000 Message-ID: References: <20211209003702.965-1-manickavasakamk@ami.com> <16BEF337B8707555.7398@groups.io> In-Reply-To: <16BEF337B8707555.7398@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.6.200.16 dlp-reaction: no-action authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Pushed as: 871ce778eb..c14a67ee2a -----Original Message----- From: devel@edk2.groups.io On Behalf Of Oram, Isaac = W Sent: Wednesday, December 8, 2021 5:52 PM To: devel@edk2.groups.io; KARPAGAVINAYAGAM, MANICKAVASAKAM Cc: Desimone, Nathaniel L ; DOPPALAPUDI, HA= RIKRISHNA ; Jha, Manish ; sureshkuma= rp@ami.com; Bobroff, Zachary Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V2] WhitleyOpenBoardPkg := Support for Junction City Platform Reviewed-by: Isaac Oram -----Original Message----- From: devel@edk2.groups.io On Behalf Of manickavasak= am karpagavinayagam via groups.io Sent: Wednesday, December 8, 2021 4:37 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Desimone, Nathaniel L ; DOPPALAPUDI, HARIKRISHNA ; J= ha, Manish ; sureshkumarp@ami.com; KARPAGAVINAYAGAM, MANIC= KAVASAKAM ; Bobroff, Zachary Subject: [edk2-devel] [edk2-platforms] [PATCH V2] WhitleyOpenBoardPkg : Sup= port for Junction City Platform Support for JunctionCity Platform - Add JunctionCity UBA's (Except GpioTable.c, IioBifurInit.c), all other files in UBA folder are just name replacement (replaced TypeWilson= City with TypeJunctionCity) - Disabled Intel ME IDE-R devices, KT devices to avoid BIOS POST time - Modified GetPlatformInfo() to check build time PcdBoardId and decide the= board detection logic Notes : V2 : - Moved Junction UBA folder from WhitleyOpenBoardPkg\Uba\UbaMain to WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity - Modified WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.c Ge= tPlatformInfo() to check build time PcdBoardId and decide the board detection logic which avoid maintaining the JunctionCity PEIM Copy - Include WhitleyOpenBoardPkg\PlatformPkg.dsc in JunctionCity PlatformPkg.= dsc to avoid a lot of duplicate code - Fix typo errors and unwanted statements in ReadMe.md - Fix coding style errors. Cc: Nate DeSimone Cc: Isaac Oram Cc: Harikrishna Doppalapudi Cc: Manish Jha Cc: Sureshkumar Ponnusamy Cc: Manickavasakam Karpagavinayagam Cc: Zachary Bobroff Signed-off-by: Manickavasakam Karpagavinayagam --- Platform/Intel/Readme.md = | 14 + Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc = | 276 +-- Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLi= b/IpmiPlatformHookLib.c | 47 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLi= b/IpmiPlatformHookLib.inf | 32 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib= /PeiPlatformHooklib.c | 95 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib= /PeiPlatformHooklib.inf | 35 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc = | 83 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf = | 824 +++++++++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/I= ioCfgUpdateDxe/IioCfgUpdateDxe.c | 100 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/I= ioCfgUpdateDxe/IioCfgUpdateDxe.h | 119 ++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/I= ioCfgUpdateDxe/IioCfgUpdateDxe.inf | 48 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/S= lotDataUpdateDxe/SlotDataUpdateDxe.c | 116 ++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/S= lotDataUpdateDxe/SlotDataUpdateDxe.h | 58 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/S= lotDataUpdateDxe/SlotDataUpdateDxe.inf | 48 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/U= sbOcUpdateDxe/UsbOcUpdateDxe.c | 128 ++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/U= sbOcUpdateDxe/UsbOcUpdateDxe.h | 27 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/U= sbOcUpdateDxe/UsbOcUpdateDxe.inf | 45 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/A= cpiTablePcds.c | 54 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/G= pioTable.c | 296 +++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/I= ioBifurInit.c | 242 +++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/K= tiEparam.c | 69 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/P= cdData.c | 275 +++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/P= chEarlyUpdate.c | 93 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/P= eiBoardInit.h | 78 + Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/P= eiBoardInitLib.c | 157 ++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/P= eiBoardInitLib.inf | 167 ++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/S= lotTable.c | 172 ++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/S= oftStrapFixup.c | 121 ++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Pei/U= sbOC.c | 127 ++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py = | 127 ++ Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg = | 37 + Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.= c | 1535 ++++++++-------- Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.= inf | 129 +- Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec = | 1793 +++++++++--------- Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc = | 1924 ++++++++++---------- Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c = | 205 ++- Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf = | 142 +- Platform/Intel/build.cfg = | 139 +- Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h = | 214 +-- 39 files changed, 7042 insertions(+), 3149 deletions(-) diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 965009ce21..6fe8e076f3 100644 --- a/Platform/Intel/Readme.md +++ b/Platform/Intel/Readme.md @@ -101,6 +101,8 @@ A UEFI firmware implementation using MinPlatformPkg is = constructed using the fol | Machine Name | Supported Chipsets = | BoardPkg | Board Name | ----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| | TiogaPass | Purley = | PurleyOpenBoardPkg | BoardTiogaPass | +----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| +| JunctionCity | IceLake-SP (Xeon Scalable) = | WhitleyOpenBoardPkg | JunctionCity | =20 =20 #### Simics @@ -289,6 +291,10 @@ return back to the minimum platform caller. | | |------WhitleyOpenBoardPkg | | | |------UpXtreme | | | |---build_config.cfg: UpXtreme = specific build + | | | settings = environment variables. + | | |------WhitleyOpenBoardPkg + | | | |------JunctionCity + | | | |---build_config.cfg: JunctionC= ity specific build | | | settings = environment variables. | | | |------WhiskeylakeURvp | | | |---build_config.cfg: Whiskeyla= keURvp specific build @@ -392,6 +398,14 @@ For PurleyOpenBoardPkg (TiogaPass) **WhitleyOpenBoardPkg** 1. This firmware project has been tested booting to UEFI shell with headle= ss serial console =20 +**JunctionCity** +1. This firmware project has been tested booting to UEFI shell +2. Booted to RHEL 8.2, Ubuntu 18.04 using U2 NVME Disk +3. Booted to Windows 2019 using M2 SSD Disk +4. Booted to Ubuntu 18.04,Windows 2019, RHEL 8.3 using SATA HDD +5. Connected PCIE Network card and made sure PCIE card detected in POST an= d in OS +6. Verified TPM offboard chip detection + ### **Package Builds** =20 In some cases, such as BoardModulePkg, a package may provide a set of func= tionality that is included in other diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.= dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc index 99ab0961ca..6256922386 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc @@ -1,137 +1,139 @@ -## @file -# Platform description. -# -# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - - - # - # Generic EDKII Driver - # - MdeModulePkg/Core/Dxe/DxeMain.inf { - - NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf - } - MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { - - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - } - - MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf - MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf - - UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf - MdeModulePkg/Universal/Metronome/Metronome.inf - MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.i= nf - MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - - MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { - - NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf - NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf - NULL|MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLib.inf - } - - - MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf - - MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf - MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { - -!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE - NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf -!endif -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib= .inf -!endif - } - - MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - - #UefiCpuPkg/CpuDxe/CpuDxe.inf - - MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf - - #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - - #MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf - #MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf - #MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf - MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf - MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf - MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf - MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf - - MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - FatPkg/EnhancedFatDxe/Fat.inf - - #MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf - MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf - - MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - - MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.in= f - - MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - - MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - - MdeModulePkg/Application/UiApp/UiApp.inf { - - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf - NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf - NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf - } - MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf { - - PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf - } - - MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf - MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf - - MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouter= Smm.inf - MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf - - #UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf - - UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf - MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferD= xe.inf - - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf - -!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE - SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf - SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf { - - Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR= outerDxe.inf - NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf - NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf - } - SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf - SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf -!endif - +## @file +# Platform description. +# +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + + # + # Generic EDKII Driver + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.i= nf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf + NULL|MdeModulePkg/Library/VarCheckPolicyLib/VarCheckPolicyLib.inf + } + + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf +!endif +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib= .inf +!endif + } + + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + + #UefiCpuPkg/CpuDxe/CpuDxe.inf + + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + + #MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + #MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + #MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + #MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + #MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.in= f + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + + MdeModulePkg/Application/UiApp/UiApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + + MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouter= Smm.inf + MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf + + #UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf + + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferD= xe.inf + + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf { + + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR= outerDxe.inf + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf + } + SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf + SecurityPkg/Tcg/Tcg2Acpi/Tcg2Acpi.inf +!endif + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPl= atformHookLib/IpmiPlatformHookLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Ju= nctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c new file mode 100644 index 0000000000..91ae2d376f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformH= ookLib/IpmiPlatformHookLib.c @@ -0,0 +1,47 @@ +/** @file + This file implements the IPMI Platform hook functions + + Copyright (c) 2021, American Megatrends International LLC.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#define KCS_BASE_ADDRESS_MASK 0xFFF0 +#define NUMBER_OF_BYTES_TO_DECODE 0x10 + +/** + This function sets IO Decode Range in LPC registers + + @param[in] IpmiIoBase - IPMI Base IO address + + @retval EFI_SUCCESS - Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformIpmiIoRangeSet ( + UINT16 IpmiIoBase +) +{ + + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi; + + DynamicSiLibraryPpi =3D NULL; + + DEBUG ((DEBUG_INFO, "PlatformIpmiIoRangeSet IpmiIoBase %x\n", IpmiIoBase= )); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi for gDynamicSiLibraryPpiGui= d failed. Status %r\n", Status)); + ASSERT_EFI_ERROR (Status); + return Status; + } + + DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IpmiIoBase & KCS_BASE_ADDRESS= _MASK), NUMBER_OF_BYTES_TO_DECODE); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPl= atformHookLib/IpmiPlatformHookLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/= JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf new file mode 100644 index 0000000000..699d89b24a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformH= ookLib/IpmiPlatformHookLib.inf @@ -0,0 +1,32 @@ +## @file +# Component description file for IPMI platform hook Library. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2021, American Megatrends International LLC.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IpmiPlatformHookLib + FILE_GUID =3D A770BDB8-331A-4110-8B60-81FC17480B36 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D IpmiPlatformHookLib + +[sources] + IpmiPlatformHookLib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + +[LibraryClasses] + DebugLib + +[Ppis] + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPla= tformHookLib/PeiPlatformHooklib.c b/Platform/Intel/WhitleyOpenBoardPkg/Junc= tionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c new file mode 100644 index 0000000000..6a88df37d1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHo= okLib/PeiPlatformHooklib.c @@ -0,0 +1,95 @@ +/** @file + PEI Library Functions. Initialize GPIOs + + Copyright 1999 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Configure GPIO + + @param[in] None + + @retval None +**/ +VOID +GpioInit ( + VOID +) +{ + PlatformInitGpios (); +} + +/** + Disables ME PCI devices like IDE-R , KT + + @param[in] None + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +DisableMEDevices ( + VOID +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi; + + DynamicSiLibraryPpi =3D NULL; + + DEBUG ((DEBUG_INFO, "DisableMEDevices\n")); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + //Disable IDE-R + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 ( + PID_PSF1, + (R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + R_PCH_P= SFX_PCR_T0_SHDW_PCIEN), + (UINT32)~0, + B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS + ); + + // + //Disable KT + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 ( + PID_PSF1, + (R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + R_PCH_PSF= X_PCR_T0_SHDW_PCIEN), + (UINT32)~0, + B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS + ); + return EFI_SUCCESS; + +} + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + ) +{ + + GpioInit(); + DisableMEDevices (); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPla= tformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Ju= nctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf new file mode 100644 index 0000000000..fb3985c4e0 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHo= okLib/PeiPlatformHooklib.inf @@ -0,0 +1,35 @@ +## @file +# +# @copyright +# Copyright 1999 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiPlatformHookLib + FILE_GUID =3D 6E9351C3-A17A-4ADF-8602-55B07962718F + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PeiPlatformHookLib|PEIM PEI_CORE SEC + +[Sources] + PeiPlatformHooklib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[LibraryClasses] + DebugLib + UbaGpioInitLib + +[Pcd] + +[Ppis] + +[Guids] diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.ds= c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc new file mode 100644 index 0000000000..93e031a06c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc @@ -0,0 +1,83 @@ +## @file +# X64 Platform with 64-bit DXE. +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + PEI_ARCH =3D IA32 + DXE_ARCH =3D X64 + + !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc + +[PcdsFixedAtBuild] + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6 + +[PcdsFeatureFlag] +!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >=3D 5 + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |TRUE + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |TRUE +!else + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |FALSE + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |FALSE +!endif + + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc + !include WhitleyOpenBoardPkg/PlatformPkg.dsc + +[Defines] + BOARD_NAME =3D JunctionCity + PLATFORM_NAME =3D $(BOARD_NAME) + PLATFORM_GUID =3D F5798629-30B2-42EC-A1CA-825FEAA8A22A + FLASH_DEFINITION =3D $(RP_PKG)/$(BOARD_NAME)/PlatformPkg.fdf + +[PcdsFixedAtBuild] + +!if $(TARGET) =3D=3D "RELEASE" + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # E= nable asserts, prints, code, clear memory, and deadloops on asserts. + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # = Built in messages: Error, MTRR, info, load, warn, init + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # = This is set to INT3 (0x2) for Simics source level debugging +!endif + gPlatformTokenSpaceGuid.PcdBoardId|0x25 + +[PcdsFixedAtBuild.X64] + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1900 + gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|9999 + +[PcdsDynamicExHii] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" + +[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM] + PeiPlatformHookLib|$(RP_PKG)/$(BOARD_NAME)/Library/PeiPlatformHookLib/Pe= iPlatformHooklib.inf + +!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable =3D=3D TRUE + IpmiPlatformHookLib| $(RP_PKG)/$(BOARD_NAME)/Library/IpmiPlatformHookLib= /IpmiPlatformHookLib.inf +!endif + +[Components.IA32] + $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf { + + NULL|$(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Pei/PeiBoardInitLi= b.inf + NULL|$(RP_PKG)/Uba/UbaMain/Common/Pei/PeiCommonBoardInitLib.inf + } + +[Components.X64] + $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpd= ateDxe.inf + $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgU= pdateDxe.inf + $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotD= ataUpdateDxe.inf + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fd= f b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf new file mode 100644 index 0000000000..b1058c9baa --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf @@ -0,0 +1,824 @@ +## @file +# FDF file of platform with 64-bit DXE +# This package provides platform specific modules and flash layout informa= tion. +# +# @copyright +# Copyright 2006 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +DEFINE PLATFORM_PKG =3D MinPlatformPkg + +# 0x00000060 =3D (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_F= FS_FILE_HEADER)) +DEFINE FDF_FIRMWARE_HEADER_SIZE =3D 0x00000060 + +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D = 0x90 # FV Header plus FFS header + +DEFINE VPD_HEADER_SIZE =3D 0x00000090 + +!if $(FSP_MODE) =3D=3D 0 + DEFINE FSP_BIN_DIR =3D Api +!else + DEFINE FSP_BIN_DIR =3D Dispatch +!endif + +# +# Note: FlashNv PCD naming conventions are as follows: +# Note: This should be 100% true of all PCD's in the gCpPlatFlashTo= kenSpaceGuid space, and for +# Others should be examined with an effort to work toward thi= s guideline. +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used = in the system, and +# the FlashMap edit tool can be used to change the values here, with= out effecting the code. +# This requires all code to only use the PCD tokens to recover the v= alues. + + +# +# 16MiB Total FLASH Image (visible in memory mapped IO) +# +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D 0xFF000000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D 0x01000000 + +##########################################################################= ###### +# +# FD SECPEI +# +# Contains all the SEC and PEI modules +# +# Layout: (Low address to high address) +# +# FvBsp for board specific components +# FvPostMemory for compressed post memory MinPlatform spec required co= mponents +# FvFspS for compressed post memory silicon initialization components +# FvPostMemorySilicon for silicon components +# FvFspM for pre memory silicon initialization components +# FvPreMemorySilicon for silicon components +# FvFspT for temp RAM silicon initilization components +# FvBspPreMemory for board specific components required to intialize m= emory +# FvAdvancedPreMemory FV for advanced features components +# FvPreMemory for components required by MinPlatform spec and to initi= alize memory +# FvPreMemorySecurity FV for stage 6 required components +# Contains reset vector +# +##########################################################################= ###### + +[FD.SecPei] + BaseAddress =3D 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSec= PeiBase #The base address of the FLASH Device + Size =3D 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSec= PeiSize #The size in bytes of the FLASH Device + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x360 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # At this time, the FSP FV must be aligned at the same address they were= built to, 0xFFD00000 + # This will be corrected in the future. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize =3D 0x0001= 0000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must =3D = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x0001= 0000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must =3D = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x0004= 0000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x0022= 1000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x0000= 6000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize =3D 0x0000= 9000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize -= gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSiz= e - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset =3D 0x00= 000000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSp= aceGuid.PcdFlashFvBspSize + FV =3D FvBsp + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvPostMemorySize + FV =3D FvPostMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspSSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_S.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspMSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_M.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspTSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_T.fd + + # + # Shared FV layout + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + FV =3D FvBspPreMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvPreMemorySize + FV =3D FvPreMemory + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase =3D gCpP= latFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvBspOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSp= aceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgToken= SpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Set duplicate PCD + # These should not need to be changed + # + + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemoryBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemorySize + + # + # For API mode, wrappers have some duplicate PCD as well + # + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspSBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspTBase + +##########################################################################= ###### +# +# FD Main +# +# All DXE modules and other regions +# +# Layout: (Low address to high address) +# +# FvAdvanced for advanced feature components +# Assorted advanced feature FV +# FvSecurity for MinPlatform spec required components needed to boot s= ecurely +# FvOsBoot for MinPlatform spec required components needed to boot OS +# FvLateSilicon for silicon specific components +# FvUefiBoot for MinPlatform spec required components needed to boot t= o UEFI shell +# +##########################################################################= ###### +[FD.Main] + BaseAddress =3D 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFd= MainBase # The base address of the FLASH Device + Size =3D 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFd= MainSize # The size in bytes of the FLASH Device + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x9C0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # These are out of flash layout order because FvAdvanced gets any remain= ing space + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x0004= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x0023= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x0004= C000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.Pcd= FlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x0000= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvOsBootSize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvAdvancedSize + FV =3D FvAdvanced + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvSecuritySize + FV =3D FvSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvOsBootSize + FV =3D FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvUefiBootSize + FV =3D FvUefiBoot + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvOsBootSize + +##########################################################################= ###### +# +# FD BINARY +# +# Contains the OPROM and other binary modules +# +# Layout: (Low address to high address) +# +# FvOpRom containing pre-built components +# FvAcmRegion containing ACM related content +# FV Header + Blank Space (1K) +# Policy block (3K) +# Blank space to align ACM on 64K boundary (60K) +# ACM binary +# FvMicrocode containing microcode update patches +# Unformatted region for PCI Gen 3 Data +# FvVpd containing PCD VPD data +# FvWhea for WHEA data recording +# FvNvStorageVariable for UEFI Variable storage +# FvNvStorageEventLog for NV Store management +# FvNvStorageFtwWorking for Fault Tolerant Write solution +# FvNvStorageFtwSpare for Fault Tolerant Write solution +# +##########################################################################= ###### +[FD.Binary] + BaseAddress =3D 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBin= aryBase + Size =3D 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBin= arySize + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x2E0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize =3D = 0x00100000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize =3D = 0x00050000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D = 0x000D0000 + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize =3D = 0x00010000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize =3D = 0x00030000 + # + # These four items are tightly coupled. + # The spare area size must be >=3D the first three areas. + # + # There isn't really a benefit to a larger spare area unless the FLASH d= evice + # block size is larger than the size specified. + # + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D = 0x0003C000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize =3D = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlash= TokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceG= uid.PcdFlashNvStorageFtwWorkingSize + + # + # Calculate Offsets Once (You should not need to modify this section) + # Each offset is the prior region's offset plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = =3D 0x00000000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = =3D gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlat= formModuleTokenSpaceGuid.PcdFlashFvVpdSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvWheaSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiM= deModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = =3D gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiM= deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically + # + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPk= gTokenSpaceGuid.PcdMicrocodeOffsetInFv + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinP= latformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv + + # + # FV Layout (You should not need to modify this section) + # + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceG= uid.PcdFlashFvOpromSize + FV =3D FvOprom + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSp= aceGuid.PcdFlashFvAcmRegionSize + FV =3D FvAcm + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvMicrocodeSize + FV =3D FvMicrocode + + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSp= aceGuid.PcdFlashFvVpdSize + FV =3D FvVPD + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGu= id.PcdFlashFvWheaSize + FV =3D FvWhea + + # + # Do not modify. + # See comments in size discussion above. These four areas are tightly c= oupled and should be modified with utmost care. + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf + gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatF= lashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as B= ase/Size to be written + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeM= odulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as B= ase/Size to be written + + # + # Calculate base addresses (You should not need to modify this section) + # Each base is the prior region's base plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvOpromOffset + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress =3D = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatf= ormPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE) + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatform= ModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE) + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvWheaSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # ACM details + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize =3D 0x3000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize =3D 0x000400= 00 + + # + # Other duplicate PCD + # + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFla= shFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize =3D gMinPlat= formPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D gCpuUnco= reTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D gCpuUnco= reTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize +##########################################################################= ###### +# +# FD FPGA +# +# Contains the FPGA modules +# +##########################################################################= ###### + +[FD.Fpga] + BaseAddress =3D 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpg= aBase #The base address of the FPGA Device ( 4G - 48M ) + Size =3D 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpg= aSize #The size in bytes of the FPGA Device ( 32M ) + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x2000 + + 0x00000000|0x02000000 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpac= eGuid.PcdFlashFvFpgaBbsSize + FV =3D FvFpga + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvSecurityPreMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 40ab290f-8494-41cf-b302-31b178b4ce0b + + !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +[FV.FvPreMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 6522280D-28F9-4131-ADC4-F40EBFA45864 + + INF UefiCpuPkg/SecCore/SecCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusC= odeRouterPei.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHa= ndlerPei.inf + + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.= inf + + INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf + + INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf + + FILE PEIM =3D ac4b7f1b-e057-47d3-b2b5-1137493c0f38 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f= 1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi + SECTION UI =3D "DynamicSiLibraryPei" + } + + INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/Platform= VariableInitPei.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPla= tformInit.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf + + # + # UBA common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf + + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf + + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + + FILE PEIM =3D ca8efb69-d7dc-4e94-aad6-9fb373649161 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb= 69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi + SECTION UI =3D "SiliconPolicyInitPreAndPostMem" + } + + INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfr= astructurePreMemory.fdf + + INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerTo= SvidMap.inf + + INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf + + !if $(FSP_MODE) =3D=3D 0 + FILE PEIM =3D 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F= 3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi + SECTION UI =3D "CsrPseudoOffsetInitPeim" + } + FILE PEIM =3D 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6C= ACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi + SECTION UI =3D "RegAccessPeim" + } + FILE PEIM =3D C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9= BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi + SECTION UI =3D "SiliconDataInitPeim" + } + INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf + !endif + + FILE FV_IMAGE =3D 40ab290f-8494-41cf-b302-31b178b4ce0b { + SECTION FV_IMAGE =3D FvSecurityPreMemory + } + +[FV.FvAdvancedPreMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 09f25d44-b2ef-4225-8b2e-e0e094b51775 + + !include AdvancedFeaturePkg/Include/PreMemory.fdf + +[FV.FvBspPreMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D e6c65995-8c2d-4119-a52d-7dbf1acb45a1 + + FILE FV_IMAGE =3D 09f25d44-b2ef-4225-8b2e-e0e094b51775 { + SECTION FV_IMAGE =3D FvAdvancedPreMemory + } + +# +# FvPostMemory includes common hardware, common core variable services, lo= ad and invoke DXE etc +# +[FV.FvPostMemoryUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA + +[FV.FvPostMemory] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 3298afc4-c484-47f1-a65a-5917a54b5e8c + + FILE FV_IMAGE =3D B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvPostMemoryUncompressed + } + } + +# +# FvBsp includes board specific components +# +[FV.FvBspUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D e4c65347-fd90-4143-8a41-113e1015fe07 + +[FV.FvBsp] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 9e151cf3-ca90-444f-b33b-a9941cbc772f + + FILE FV_IMAGE =3D e4c65347-fd90-4143-8a41-113e1015fe07 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvBspUncompressed + } + } + +[FV.FvUefiBootUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D C4D3B0E2-FB26-44f8-A05B-E95895FCB960 + + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.= inf + INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDx= e.inf + + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDx= e.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.in= f + #ATA for IDE/AHCI/RAID support + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestD= xe.inf + INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + + FILE DRIVER =3D 85299F8F-F2B9-4487-AF60-231434A5EFF6 { + SECTION PE32 =3D edk2-non-osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpee= dAst2500Gop.efi + } + + +[FV.FvUefiBoot] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D ab9fe87b-1e37-440c-91cc-9aea03ce7bec + + FILE FV_IMAGE =3D C4D3B0E2-FB26-44f8-A05B-E95895FCB960 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvUefiBootUncompressed + } + } + +[FV.FvOsBootUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 + + # + # DXE Phase modules + # + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStat= usCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandl= erRuntimeDxe.inf + + FILE FV_IMAGE =3D B7C9F0CB-15D8-26FC-CA3F-C63947B12831 { + SECTION UI =3D "FvLateSilicon" + SECTION FV_IMAGE =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateS= ilicon.fv + } + + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.in= f + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfr= astructurePostMemory.fdf + + # + # UBA DXE common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf + INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbO= cUpdateDxe.inf + INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/Iio= CfgUpdateDxe.inf + INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/S= lotDataUpdateDxe.inf + INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf + INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + + !if ($(FSP_MODE) =3D=3D 1) + INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf + !else + INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + !endif + + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf + INF UefiCpuPkg/CpuDxe/CpuDxe.inf + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + + FILE FV_IMAGE =3D a0277d07-a725-4823-90f9-6cba00782111 { + SECTION UI =3D "FvLateOpenBoard" + SECTION FV_IMAGE =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateO= penBoard.fv + } + + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime= Dxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.in= f + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf + + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterR= untimeDxe.inf + INF RuleOverride =3D UI MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV. + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + + INF FatPkg/EnhancedFatDxe/Fat.inf + + INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF ShellPkg/Application/Shell/Shell.inf + + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeR= outerSmm.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.i= nf + + INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + + INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf + + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.= inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.in= f + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf + + INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBu= fferDxe.inf + + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecuto= rDxe.inf + + # UEFI USB stack + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + + INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf + INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf + +[FV.FvOsBoot] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D c7488640-5f51-4969-b63b-89fc369e1725 + + FILE FV_IMAGE =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvOsBootUncompressed + } + } + +[FV.FvSecuritySilicon] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D AD262F8D-BDED-4668-A8D4-8BC73516652F + + !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf + +[FV.FvSecurityUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 03E25550-89A5-4ee6-AF60-DB0553D91FD2 + + FILE FV_IMAGE =3D 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvSecuritySilicon + } + } + +[FV.FvSecurity] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 68134833-2ff6-4d22-973b-575d0eae8ffd + + FILE FV_IMAGE =3D 03E25550-89A5-4ee6-AF60-DB0553D91FD2 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvSecurityUncompressed + } + } + +[FV.FvAdvancedUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 70aeaf57-4997-49ce-a4f7-122980745670 + + !include AdvancedFeaturePkg/Include/PostMemory.fdf + +[FV.FvAdvanced] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D f21ee7a1-53a9-453d-aee3-b6a5c25bada5 + + FILE FV_IMAGE =3D 70aeaf57-4997-49ce-a4f7-122980745670 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvAdvancedUncompressed + } + } + +# +# FV for all Microcode Updates. +# +[FV.FvMicrocode] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS =3D FALSE + FvNameGuid =3D D2C29BA7-3809-480F-9C3D-DE389C61425A + +!if $(CPUTARGET) =3D=3D "CPX" + INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/M= icrocodeUpdates.inf +!else + INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/M= icrocodeUpdates.inf +!endif + + +[FV.FvVPD] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS =3D FALSE + FvNameGuid =3D FFC29BA7-3809-480F-9C3D-DE389C61425A + FILE RAW =3D FF7DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-= 850A-24F7A8D38E08.bin + } + +# +# Various Vendor UEFI Drivers (OROMs). +# +[FV.FvOpromUncompressed] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D B6EDE22C-DE30-45fa-BB09-CA202C1654B7 + +[FV.FvOprom] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD + + FILE FV_IMAGE =3D B6EDE22C-DE30-45fa-BB09-CA202C1654B7 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvOpromUncompressed + } + } + +[FV.FvWhea] + BlockSize =3D 0x1000 + NumBlocks =3D 0x30 + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D d6a1cd70-4b33-4994-a6ea-375f2ccc5437 + +# +# FV For ACM Binary. +# +[FV.FvAcm] + BlockSize =3D 0x1000 + NumBlocks =3D 0x50 + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 11668261-8A8D-47ca-9893-052D24435E59 + +[FV.FvFpga] + !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 974650E7-6DFE-4998-A124-CEDEC5C9B47D + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/WhitleyOpenBo= ardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDx= e.c new file mode 100644 index 0000000000..b6b81f188c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c @@ -0,0 +1,100 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "IioCfgUpdateDxe.h" + +EFI_STATUS +UpdateJunctionCityIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeJunctionCityIioConfigTable =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateJunctionCityIioConfig, + IioSlotTable, + sizeof(IioSlotTable) + +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +IioCfgUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeJunctionCity\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid, + &TypeJunctionCityIioConfigTable, + sizeof(TypeJunctionCityIioConfigTable= ) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_1, + &TypeJunctionCityIioConfigTable, + sizeof(TypeJunctionCityIioConfigTable= ) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_2, + &TypeJunctionCityIioConfigTable, + sizeof(TypeJunctionCityIioConfigTable= ) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_3, + &TypeJunctionCityIioConfigTable, + sizeof(TypeJunctionCityIioConfigTable= ) + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/WhitleyOpenBo= ardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDx= e.h new file mode 100644 index 0000000000..53d3a49f9a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h @@ -0,0 +1,119 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIOCFG_UPDATE_DXE_H_ +#define _IIOCFG_UPDATE_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + +static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =3D +{ + // Neon City IIO bifurcation table (Based on Neon City Block Diagram rev= 0.6) + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] =3D { + // Port | Slot | Inter | Power Limit | Power Limit | H= ot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD = | Hidden + // Index | | lock | Scale | Value | P= lug | Port | Addr | Cap | VppPort | VppAddr = | + { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C = , HIDE },//Oculink + { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C = , HIDE },//Oculink + { PORT_1C_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 11= 8 (MRL in J65) + { PORT_3A_INDEX, 2 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , E= NABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 = , NOT_HIDE }, + { PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 = , HIDE }, + { PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 = , HIDE }, + { PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 = , HIDE }, + { SOCKET_1_INDEX + + PORT_0_INDEX , 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 12= 1 (MRL in J287) + { SOCKET_1_INDEX + + PORT_1A_INDEX, 4 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , E= NABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 = , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 = , HIDE }, + { SOCKET_1_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 = , HIDE }, + { SOCKET_1_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 = , HIDE }, + { SOCKET_1_INDEX + + PORT_2A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 = , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x44 = , HIDE }, + { SOCKET_1_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x46 = , HIDE }, + { SOCKET_1_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x46 = , HIDE }, + { SOCKET_1_INDEX + + PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_3C_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port +}; + +#endif //_IIOCFG_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/WhitleyOpen= BoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdate= Dxe.inf new file mode 100644 index 0000000000..13d88a3748 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf @@ -0,0 +1,48 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IioCfgUpdateDxeJunctionCity + FILE_GUID =3D 9E1DECF5-C606-44A2-B99D-5BF4222A174C + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D IioCfgUpdateEntry + +[sources] + IioCfgUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeJunctionCityProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel/WhitleyOp= enBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotData= UpdateDxe.c new file mode 100644 index 0000000000..37e9c6a9e6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c @@ -0,0 +1,116 @@ +/** @file + Slot Data Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SlotDataUpdateDxe.h" + +UINT8 +GetTypeJunctionCityIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled. + // + IOU0Data =3D IIO_BIFURCATE_xxx8xxx8; + return IOU0Data; +} + +UINT8 +GetTypeJunctionCityIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeJunctionCityBroadwayTable= [] =3D { + {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + {Iio_Socket1, Iio_Iou1, Bw5_Addr_2}, + {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + + +PLATFORM_SLOT_UPDATE_TABLE TypeJunctionCitySlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeJunctionCityBroadwayTable, + GetTypeJunctionCityIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeJunctionCitySlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeJunctionCityBroadwayTable, + GetTypeJunctionCityIOU0Setting, + 0, + GetTypeJunctionCityIOU2Setting +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +SlotDataUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeJunctionCity\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeJunctionCitySlotTable, + sizeof(TypeJunctionCitySlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeJunctionCitySlotTable2, + sizeof(TypeJunctionCitySlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel/WhitleyOp= enBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotData= UpdateDxe.h new file mode 100644 index 0000000000..e59e70c9ee --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h @@ -0,0 +1,58 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SLOT_DATA_UPDATE_DXE_H_ +#define _SLOT_DATA_UPDATE_DXE_H_ + + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +#endif //_SLOT_DATA_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Intel/Whitley= OpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDa= taUpdateDxe.inf new file mode 100644 index 0000000000..8f107b9c42 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf @@ -0,0 +1,48 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SlotDataUpdateDxeJunctionCity + FILE_GUID =3D 98750E94-CCCB-45AA-9259-3CF7F8C43C33 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SlotDataUpdateEntry + +[sources] + SlotDataUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeJunctionCityProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/WhitleyOpenBoar= dPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c new file mode 100644 index 0000000000..7522d7b6e2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c @@ -0,0 +1,128 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "UsbOcUpdateDxe.h" + +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeJunctionCityUsb20OverCurrentMappings[PCH_MAX_USB2_= PORTS] =3D { + UsbOverCurrentPinSkip, //Port00: BMC + UsbOverCurrentPinSkip, //Port01: BMC + UsbOverCurrentPin0, //Port02: Rear Panel + UsbOverCurrentPin1, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPinSkip, //Port05: NC + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPin4, //Port07: Type A intern= al + UsbOverCurrentPinSkip, //Port08: NC + UsbOverCurrentPinSkip, //Port09: NC + UsbOverCurrentPin6, //Port10: Front Panel + UsbOverCurrentPinSkip, //Port11: NC + UsbOverCurrentPin6, //Port12: Front Panel + UsbOverCurrentPinSkip, //Port13: NC + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB_OVERCURRENT_PIN TypeJunctionCityUsb30OverCurrentMappings[PCH_MAX_USB3_= PORTS] =3D { + UsbOverCurrentPin6, //Port01: Front Panel + UsbOverCurrentPin6, //Port02: Front Panel + UsbOverCurrentPin0, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPin1, //Port05: Rear Panel + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeJunctionCityUsb20AfeParams[PCH_H_XHCI_MAX_= USB2_PHYSICAL_PORTS] =3D { + {3, 0, 3, 1}, // PP0 + {5, 0, 3, 1}, // PP1 + {3, 0, 3, 1}, // PP2 + {0, 5, 1, 1}, // PP3 + {3, 0, 3, 1}, // PP4 + {3, 0, 3, 1}, // PP5 + {3, 0, 3, 1}, // PP6 + {3, 0, 3, 1}, // PP7 + {2, 2, 1, 0}, // PP8 + {6, 0, 2, 1}, // PP9 + {2, 2, 1, 0}, // PP10 + {6, 0, 2, 1}, // PP11 + {0, 5, 1, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypeJunctionCityPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings =3D &TypeJunctionCityUsb20OverCurrentMapping= s[0]; + *Usb30OverCurrentMappings =3D &TypeJunctionCityUsb30OverCurrentMapping= s[0]; + + *Usb20AfeParams =3D TypeJunctionCityUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeJunctionCityUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeJunctionCityPlatformUsbOcUpdateCallback +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +UsbOcUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:UsbOcUpdate-TypeJunctionCity\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gDxePlatformUbaOcConfigDataGuid, + &TypeJunctionCityUsbOcUpdate, + sizeof(TypeJunctionCityUsbOcUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/WhitleyOpenBoar= dPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h new file mode 100644 index 0000000000..2ba90c7598 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h @@ -0,0 +1,27 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USBOC_UPDATE_DXE_H_ +#define _USBOC_UPDATE_DXE_H_ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + + + +#endif //_USBOC_UPDATE_DXE_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/WhitleyOpenBo= ardPkg/JunctionCity/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.= inf new file mode 100644 index 0000000000..0f8e953e2b --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf @@ -0,0 +1,45 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UsbOcUpdateDxeJunctionCity + FILE_GUID =3D 5149EA77-8FCC-41B4-A8D0-CE652E817FD0 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D UsbOcUpdateEntry + +[sources] + UsbOcUpdateDxe.c + UsbOcUpdateDxe.h + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeJunctionCityProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCit= y/Uba/TypeJunctionCity/Pei/AcpiTablePcds.c new file mode 100644 index 0000000000..f4eedccd77 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/AcpiTablePcds.c @@ -0,0 +1,54 @@ +/** @file + ACPI table pcds update. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include + +EFI_STATUS +TypeJunctionCityPlatformUpdateAcpiTablePcds ( + VOID + ) +{ + CHAR8 AcpiName10nm[] =3D "EPRP10NM"; // USED for identify ACP= I table for 10nm in systmeboard dxe driver + CHAR8 OemTableIdXhci[] =3D "xh_nccrb"; + + UINTN Size; + EFI_STATUS Status; + + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + DEBUG ((DEBUG_INFO, "Uba Callback: PlatformUpdateAcpiTablePcds entered\n= ")); + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + //# + //#ACPI items + //# + Size =3D AsciiStrSize (AcpiName10nm); + Status =3D PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiName10nm); + DEBUG ((DEBUG_INFO, "%a TypeJunctionCity ICX\n", __FUNCTION__)); + ASSERT_EFI_ERROR (Status); + + Size =3D AsciiStrSize (OemTableIdXhci); + Status =3D PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Ub= a/TypeJunctionCity/Pei/GpioTable.c new file mode 100644 index 0000000000..2d1e46b143 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/GpioTable.c @@ -0,0 +1,296 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include + +#include +#include +#include +#include + +// +// Board : Wilson City RP +// +static GPIO_INIT_CONFIG mGpioTableJunctionCity [] =3D + { + {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N //IRQ_ESPI_F= PGA_PCH_ALERT1_N PU not used + {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0 + {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1 + {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2 + {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3 + {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N //PU_LPC_CLK= RUN_N PU not used + {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI + {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10 + {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N //PU_LPC_PME= _N PU not used + {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N //PU_IRQ_PCH= _SCI_WHEA_N PU not used + {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N //TP_PCH_GPP= _A_13 + {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N + {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_15_FM_SUSACK_N //TP_PCH_GPP= _A_15 + {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16 //FM_PCHIE_B= MC_N + {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16 //FM_BMC_PCH= IE_N + {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS //IRQ_BMC_PC= H_SMI_LPC_N +// GPIO_SKL_H_GPP_A19 - Not Owned by BIOS //ME Recovery Jumper FM_ME_R= CVR_N + {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20 //FM_BMC_REA= DY_N + {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21 + {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22 + {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23 + {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0 + {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1 + {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N + {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}}, //PU_SATA_EN +// GPIO_SKL_H_GPP_B4 - Not Owned by BIOS //ME SMB Alert MGPIO IRQ_SML1= _PMBUS_ALERT + {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1 //TP_PCH_GPP= _B_5 + {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2 //TP_PCH_GPP= _B_6 + {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7 + {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8 + {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2 //TP_PCH_GPP= _B_9 + {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N +// GPIO_SKL_H_GPP_B11 - Not Owned by BIOS //ME SMB Alert_EN MGPIO FM_P= MBUS_ALERT_BUF_EN_N + {GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N //FM_GLOBAL_= RST_WARN_N + {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_13_RST_PLTRST_N + {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR + {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N + {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N + {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N + {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT //PU_NO_REBO= OT Spare + {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5 //TP_PCH_GPP= _B19 + {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, G= pioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N + {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21 + {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE //FM_USB_PWR= _EN + {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N +// GPIO_SKL_H_GPP_C0 - Not Owned by BIOS //ME SMBCLK +// GPIO_SKL_H_GPP_C1 - Not Owned by BIOS //ME SMBDATA + {GPIO_SKL_H_GPP_C2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP //IRQ_SMB_AL= ERT_N_TLS_EN_STRP +// GPIO_SKL_H_GPP_C3 - Not Owned by BIOS //ME SML0CLK +// GPIO_SKL_H_GPP_C4 - Not Owned by BIOS //ME SML0DATA + {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N +// GPIO_SKL_H_GPP_C6 - Not Owned by BIOS //ME SML1CLK +// GPIO_SKL_H_GPP_C7 - Not Owned by BIOS //ME SML1DATA + {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N + {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_9_FM_MFG_MODE + {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone}},/= /GPP_C_10_FM_PCH_SATA_RAID_KEY + {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N //FM_BOARD_R= EV_ID0 + {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0 //FM_BOARD_R= EV_ID1 + {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1 //FM_BOARD_R= EV_ID2 + {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N //TP_PCH_GPP= _C_14 + {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0 //TP_PCH_GPP= _C_15 + {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1 //TP_PCH_GPP= _C_16 + {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0 //TP_PCH_GPP= _C_17 + {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1 //TP_PCH_GPP= _C_18 +// GPIO_SKL_H_GPP_C19 - Not Owned by BIOS //SMBus Smbus Mux GPIO reset = GPP_C_19_RST_SMB_HOST_PCH_MUX_N +// GPIO_SKL_H_GPP_C20 - Not Owned by BIOS //ME PROCHOT MGPIO = GPP_C_20_FM_THROTTLE_N + {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N //TP_PCH_GPP= _C_21 + {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N //FM_BMC_PCH= _SCI_LPC_N + {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N + {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, Gpio= DirInInv, GpioOutDefault, GpioIntLevel | GpioIntNmi, GpioResetNormal, Gp= ioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI + {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioPlatformReset,GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N + {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR //TP_PCH_GPP= _D_2 + {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT //TP_PCH_GPP= _D_3 + {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA + {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5 //FM_OCP_MOD= 1_PRSNT_N + {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6 + {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7 + {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL //TP_PCH_GPP= _D_8 + {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9 + {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP= _D_10 + {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11 + {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1 //TP_PCH_GPP= _D_12 + {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL //TP_PCH_GPP= _D_13 + {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA //TP_PCH_GPP= _D_14 + {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0 + {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1 //FM_SLOT1_P= RSNT + {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2 //FM_SLOT2_P= RSNT + {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N //TP_PCH_GPP= _D_18 + {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R + {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20 + {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21 + {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22 + {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23 + {GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N //TP_PCH_GPP= _E_0 + {GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N //TP_PCH_GPP= _E_1 + {GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N //TP_PCH_GPP= _E_2 + {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone,= GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N + {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4 //FM_CPU0_SS= D0_PRSNT_N + {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5 //FM_CPU0_SS= D1_PRSNT_N + {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E_6 //FM_CPU0_SS= D2_PRSNT_N + {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N + {GPIO_SKL_H_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N //FM_CPU0_SS= D3_PRSNT_N + {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N + {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N + {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N + {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N + {GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N //FM_OCP_MOD= 2_PRSNT_N + {GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N //TP_PCH_GPP= _F_1 + {GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N //FM_EDSFF0_= PRSNT0_N + {GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N //FM_EDSFF0_= PRSNT1_N + {GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N //FM_BIOS_US= B_RECOVERY + {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N + {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK //FM_EDSFF1_= PRSNT0_N + {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI //FM_EDSFF1_= PRSNT1_N + {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS //FM_EDSFF2_= PRSNT0_N + {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO //FM_EDSFF2_= PRSNT1_N + {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK + {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD + {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1 + {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0 + {GPIO_SKL_H_GPP_F14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N //TP_PCH_GPP= _F14 + {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N //FM_EDSFF3_= PRSNT0_N + {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N //FM_EDSFF3_= PRSNT1_N + {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N //FM_EDSFF4_= PRSNT0_N + {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N //FM_EDSFF4_= PRSNT1_N + {GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL //FM_EDSFF5_= PRSNT0_N + {GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA //FM_EDSFF5_= PRSNT1_N + {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21 + {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK + {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD + {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0 //FM_BOARD_S= KU_ID0 + {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1 //FM_BOARD_S= KU_ID1 + {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2 //FM_BOARD_S= KU_ID2 + {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3 //FM_BOARD_S= KU_ID3 + {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4 //FM_BOARD_S= KU_ID4 + {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5 //FM_BOARD_S= KU_ID5 + {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6 //FM_MIDPLAN= E_PCH_ID0 + {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7 //FM_MIDPLAN= E_PCH_ID1 + {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0 //FM_PCH_GPP= _G8 + {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1 //FM_PCH_GPP= _G9 + {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2 //FM_PCH_GPP= _G10 + {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3 //FM_PCH_GPP= _G11 + {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_12_GSXDOUT //IRQ_FORCE_= NM_THROTTLE_N + {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1 //TP_PCH_GPP= _G_13 + {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2 //TP_PCH_GPP= _G_14 + {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3 //TP_PCH_GPP= _G_15 + {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4 //TP_PCH_GPP= _G_16 + {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE + {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N + {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N + {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}}, //TP_PCH_GPP= _G_20 + {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N //TP_PCH_GPP= _G_21 + {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP= _G_22 + {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23 + {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2 //FM_CLKREQ_= M2_SSD_A_N + {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N //FM_CLKREQ_= M2_SSD_B_N + {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0 //FM_ROWOL_E= NABLE + {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1 //FM_ROWOL_L= ATCH + {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4 //TP_PCH_GPP= _H_4 + {GPIO_SKL_H_GPP_H5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_5_FM_CLKREQ_M2_1_N //TP_PCH_GPP= _H_5 + {GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N //TP_PCH_GPP= _H_6 + {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3 //TP_PCH_GPP= _H_7 + {GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N //TP_PCH_GPP= _H_8 + {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5 //TP_PCH_GPP= _H_9 +// GPIO_SKL_H_GPP_H10 - Not Owned by BIOS //ME SML2CLK +// GPIO_SKL_H_GPP_H11 - Not Owned by BIOS //ME SML2DATA + {GPIO_SKL_H_GPP_H12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE //IRQ_SML2_A= LERT_N + {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N + {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N + {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N //TP_PCH_GPP= _H_19 + {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL //TP_PCH_GPP= _H_20 + {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N //TP_PCH_GPP= _H_21 + {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL //TP_PCH_GPP= _H_22 + {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23 + {GPIO_SKL_H_GPP_I0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0 + {GPIO_SKL_H_GPP_I1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1 + {GPIO_SKL_H_GPP_I2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2 + {GPIO_SKL_H_GPP_I3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3 + {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I_4 + {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I_5 + {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I_6 + {GPIO_SKL_H_GPP_I7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7 + {GPIO_SKL_H_GPP_I8, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N + {GPIO_SKL_H_GPP_I9, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N + {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10 //FM_BIOS_MR= C_DEBUG_MSG_DIS_N +// GPIO_SKL_H_GPP_I11 - Not Owned by BIOS +// GPIO_SKL_H_GPD0 - Not Owned by BIOS //ME FIVRBREAK + {GPIO_SKL_H_GPD1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_1_PU_ACPRESENT + {GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N //RST_BMC_SR= ST_N + {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N + {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_4_FM_SLPS3_N + {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_5_FM_SLPS4_N + {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_6_FM_SLPA_N + {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_7_TP_GPD_7 + {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK + {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_9_TP_GPD_9_SLP + {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_10_FM_SLPS5_N + {GPIO_SKL_H_GPD11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N + {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0 + {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1 + {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2 + {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3 + {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4 + {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5 + {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6 + {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7 + {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8 + {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9 + {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10 + {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11 + {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12 + {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13 + {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14 + {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15 + {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16 + {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17 + {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18 + {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19 + {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20 + {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21 + {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22 + {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23 + {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH + {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0 + {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1 + {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN + {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV + {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0 + {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1 + {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER + {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN + {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT + {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N +// GPIO_SKL_H_GPP_K11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_L2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0 + {GPIO_SKL_H_GPP_L3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1 + {GPIO_SKL_H_GPP_L4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2 + {GPIO_SKL_H_GPP_L5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3 + {GPIO_SKL_H_GPP_L6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4 + {GPIO_SKL_H_GPP_L7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5 + {GPIO_SKL_H_GPP_L8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6 + {GPIO_SKL_H_GPP_L9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7 + {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK + {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0 + {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1 + {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2 + {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3 + {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4 + {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5 + {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6 + {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7 + {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK +}; + +EFI_STATUS +TypeJunctionCityInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformGpioInitDataGuid, + &mGpioTableJunctionCity, + sizeof(mGpioTableJunctionCity) + ); + Status =3D PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableJunct= ionCity)); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity= /Uba/TypeJunctionCity/Pei/IioBifurInit.c new file mode 100644 index 0000000000..4c376964e2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/IioBifurInit.c @@ -0,0 +1,242 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D 0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 + +static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] =3D +{ + + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_x4x4xxx8, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_xxx8x4x4, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX } +}; +//[-start-210223-Enhance_Dynamic_Type9-modify]// +static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] =3D { + // Port Index | Slot |Interlock |power |Power |Hotpl= ug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |= Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard |ExtnCard |Ex= tnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard= Hotplug|ExtnCard Hotplug|Max Retimer| + // | | |Limit Scale |Limit Value |Cap = | | |Cap |Port |Address |= |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SM= Bus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port= |Vpp Address | | + {SOCKET_0_INDEX + + PORT_1A_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1C_INDEX, 2 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1D_INDEX, 3 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2C_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4A_INDEX, 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5A_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISAB= LE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , = NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_= MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SM= B_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT= _MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_1_INDEX + + PORT_1A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_2A_INDEX, 9 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_2C_INDEX, 10 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4A_INDEX, 11 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4B_INDEX, 12 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4C_INDEX, 13 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5A_INDEX, 14 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 } +}; + +EFI_STATUS +UpdateJunctionCityIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeJunctionCityIioConfigTable =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION_2, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateJunctionCityIioConfig, + IioSlotTable, + sizeof(IioSlotTable) +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeJunctionCityIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX *PlatformIioInfoPtr; + UINTN PlatformIioInfoSize; + + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + // + // This is config for ICX + // + PlatformIioInfoPtr =3D &TypeJunctionCityIioConfigTable; + PlatformIioInfoSize =3D sizeof(TypeJunctionCityIioConfigTable); + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_1, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_2, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_3, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Ub= a/TypeJunctionCity/Pei/KtiEparam.c new file mode 100644 index 0000000000..1ec1424d23 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/KtiEparam.c @@ -0,0 +1,69 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +extern EFI_GUID gPlatformKtiEparamUpdateDataGuid; + +ALL_LANES_EPARAM_LINK_INFO KtiJunctionCityIcxAllLanesEparamTable[] =3D { + // + // SocketID, Freq, Link, TXEQL, CTLEPEAK + // Please propagate changes to WilsonCitySMT and WilsonCityModular UBA K= tiEparam tables + // + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE}, + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2A31383F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK1), 0x2A30393F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK2), 0x2C34373F, ADAPTIVE_CTLE} +}; + +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeJunctionCityIcxKtiEparamUpdate =3D { + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + KtiJunctionCityIcxAllLanesEparamTable, + sizeof (KtiJunctionCityIcxAllLanesEparamTable), + NULL, + 0 +}; + + +EFI_STATUS +TypeJunctionCityInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformKtiEparamUpdateDataGuid, + &TypeJunctionCityIcxKtiEparamUpdate, + sizeof(TypeJunctionCityIcxKtiEparamUpdate= ) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/= TypeJunctionCity/Pei/PcdData.c new file mode 100644 index 0000000000..f833775a73 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/PcdData.c @@ -0,0 +1,275 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_SKL_H_GPP_B20 0x01010014 + +VOID TypeJunctionCityPlatformUpdateVrIdAddress (VOID); + +/** + Update JunctionCity IMON SVID Information + + retval N/A +**/ +VOID +TypeJunctionCityPlatformUpdateImonAddress ( + VOID + ) +{ + VCC_IMON *VccImon =3D NULL; + UINTN Size =3D 0; + + Size =3D sizeof (VCC_IMON); + VccImon =3D (VCC_IMON *) PcdGetPtr (PcdImonAddr); + if (VccImon =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "UpdateImonAddress() - PcdImonAddr =3D=3D NULL\n"= )); + return; + } + + VccImon->VrSvid[0] =3D PcdGet8 (PcdWilsonCitySvidVrP1V8); + VccImon->VrSvid[1] =3D PcdGet8 (PcdWilsonCitySvidVrVccAna); + VccImon->VrSvid[2] =3D IMON_ADDR_LIST_END; // End array with 0xFF + + PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon); +} + +/** + Update WilsonCity VR ID SVID Information + + retval N/A +**/ +VOID +TypeJunctionCityPlatformUpdateVrIdAddress ( + VOID + ) +{ + MEM_SVID_MAP *MemSvidMap =3D NULL; + UINTN Size =3D 0; + + Size =3D sizeof (MEM_SVID_MAP); + MemSvidMap =3D (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap); + if (MemSvidMap =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap =3D=3D NULL= \n")); + return; + } + /* + Map VR ID Address to Memory controller + The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14,= and 0x16. + Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs = (VR ID's 0x10 and 0x12). + Those are typically shared such that MC0/MC2 share the same DDR VR (as= they are on the same side of the CPU) + and MC1/MC3 share the other. Depending on motherboard layout and other= design constraints, this could change + BIT 4 =3D> 0 or 1, SVID BUS\Interface 0 or 1 respectively + BIT 0:3 =3D> SVID ADDRESS + */ + + MemSvidMap->Socket[0].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[0].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[1].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[1].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[2].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[2].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[3].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[3].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[4].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[4].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[5].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[5].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[6].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[6].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[7].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[7].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + + PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap); +} + +EFI_STATUS +TypeJunctionCityPlatformPcdUpdateCallback ( + VOID +) +{ + CHAR8 FamilyName[] =3D "Whitley"; + + CHAR8 BoardName[] =3D "EPRP"; + UINT32 Data32; + UINTN Size; + UINTN PlatformFeatureFlag =3D 0; + + CHAR16 PlatformName[] =3D L"TypeJunctionCity"; + UINTN PlatformNameSize =3D 0; + EFI_STATUS Status; + + //#Integer for BoardID, must match the SKU number and be unique. + Status =3D PcdSet16S (PcdOemSkuBoardID , TypeJuncti= onCity); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet16S (PcdOemSkuBoardFamily , 0x30); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Number of Sockets on Board. + Status =3D PcdSet32S (PcdOemSkuBoardSocketCount, 2); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Max channel and max DIMM + Status =3D PcdSet32S (PcdOemSkuMaxChannel , 8); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetBoolS (PcdOemSkuDimmLayout, TRUE); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //Update Onboard Video Controller PCI Ven_id, Dev_id + Status =3D PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# + //# Misc. + //# + //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF + Status =3D PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //SDP Active Flag + Status =3D PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to ID family + Size =3D AsciiStrSize (FamilyName); + Status =3D PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyNa= me); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to Board Name + Size =3D AsciiStrSize (BoardName); + Status =3D PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardNam= e); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + PlatformNameSize =3D sizeof (PlatformName); + Status =3D PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)Plat= formNameSize); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNam= eSize, PlatformName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# FeaturesBasedOnPlatform + Status =3D PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)P= latformFeatureFlag); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Assert GPIO + Data32 =3D 0; + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# UplinkPortIndex + Status =3D PcdSet8S (PcdOemSkuUplinkPortIndex, 5); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\= n")); + Status =3D TypeJunctionCityPlatformUpdateAcpiTablePcds (); + //# BMC Pcie Port Number + PcdSet8S (PcdOemSkuBmcPciePortNumber, 5); + ASSERT_EFI_ERROR(Status); + + //# Board Type Bit Mask + PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4)= ); + ASSERT_EFI_ERROR(Status); + + //Update IMON Address + TypeJunctionCityPlatformUpdateImonAddress (); + + return Status; +} + +PLATFORM_PCD_UPDATE_TABLE TypeJunctionCityPcdUpdateTable =3D +{ + PLATFORM_PCD_UPDATE_SIGNATURE, + PLATFORM_PCD_UPDATE_VERSION, + TypeJunctionCityPlatformPcdUpdateCallback +}; + +EFI_STATUS +TypeJunctionCityInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPcdConfigDataGuid, + &TypeJunctionCityPcdUpdateTable, + sizeof(TypeJunctionCityPcdUpdateTable) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCi= ty/Uba/TypeJunctionCity/Pei/PchEarlyUpdate.c new file mode 100644 index 0000000000..e8cc05155a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/PchEarlyUpdate.c @@ -0,0 +1,93 @@ +/** @file + Pch Early update. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + +#include + +#include +#include +#include +#include + +EFI_STATUS +TypeJunctionCityPchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + EFI_STATUS Status; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DynamicSiLibraryPpi->GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)Syst= emConfig->LomDisableByGpio); + DynamicSiLibraryPpi->PchDisableGbe (); + + return EFI_SUCCESS; +} + +EFI_STATUS +TypeJunctionCityOemInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + return EFI_SUCCESS; +} + + +PLATFORM_PCH_EARLY_UPDATE_TABLE TypeJunctionCityPchEarlyUpdateTable =3D +{ + PLATFORM_PCH_EARLY_UPDATE_SIGNATURE, + PLATFORM_PCH_EARLY_UPDATE_VERSION, + TypeJunctionCityPchLanConfig, + TypeJunctionCityOemInitLateHook +}; + + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +EFIAPI +TypeJunctionCityPchEarlyUpdate( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &TypeJunctionCityPchEarlyUpdateTable, + sizeof(TypeJunctionCityPchEarlyUpdateTable) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity= /Uba/TypeJunctionCity/Pei/PeiBoardInit.h new file mode 100644 index 0000000000..1c596a30c4 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/PeiBoardInit.h @@ -0,0 +1,78 @@ +/** @file + PeiBoardInit. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_BOARD_INIT_PEIM_H_ +#define _PEI_BOARD_INIT_PEIM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// TypeJunctionCity +EFI_STATUS +TypeJunctionCityPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeJunctionCityPlatformUpdateAcpiTablePcds ( + VOID +); + +EFI_STATUS +TypeJunctionCityInstallClockgenData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeJunctionCityInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeJunctionCityPchEarlyUpdate ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeJunctionCityIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeJunctionCityInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeJunctionCityInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +// TypeJunctionCity +EFI_STATUS +TypeJunctionCityInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) ; + +EFI_STATUS +TypeJunctionCityInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); +#endif // _PEI_BOARD_INIT_PEIM_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionC= ity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.c new file mode 100644 index 0000000000..8cc76a5db3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/PeiBoardInitLib.c @@ -0,0 +1,157 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. + Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +/** + The constructor function for Board Init Libray. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Table initialization successfully. + @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table. +**/ + +#include "PeiBoardInit.h" +#include +#include +#include + +EFI_STATUS +EFIAPI +TypeJunctionCityPeiBoardInitLibConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + UINT8 SocketIndex; + UINT8 ChannelIndex; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + + if (PlatformInfo->BoardId =3D=3D TypeJunctionCity) { + + DEBUG ((DEBUG_INFO, "PEI UBA init BoardId 0x%X: JunctionCity\n", Platf= ormInfo->BoardId)); + + // Socket 0 has SMT DIMM connector, Socket 1 has PTH DIMM connector + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + for (ChannelIndex =3D 0; ChannelIndex < MAX_CH; ChannelIndex++) { + switch (SocketIndex) { + case 0: + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = =3D DimmConnectorSmt; + break; + case 1: + // Fall through since socket 1 is PTH type + default: + // Use the more restrictive type as the default case + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = =3D DimmConnectorPth; + break; + } + } + } + + BuildGuidDataHob ( + &gEfiPlatformInfoGuid, + &(PlatformInfo), + sizeof (EFI_PLATFORM_INFO) + ); + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->InitSku ( + UbaConfigPpi, + PlatformInfo->BoardId, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + + Status =3D TypeJunctionCityInstallGpioData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeJunctionCityInstallPcdData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeJunctionCityInstallSoftStrapData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeJunctionCityPchEarlyUpdate (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeJunctionCityPlatformUpdateUsbOcMappings (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeJunctionCityInstallSlotTableData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeJunctionCityInstallKtiEparamData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + + // + // Set default memory type connector. + // Socket 0: DimmConnectorSmt + // Socket 1: DimmConnectorPth + // + if (SocketIndex % 2 =3D=3D 0) { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketI= ndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnect= orSmt); + } else { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketI= ndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnect= orPth); + } + } + + // + // Initialize InterposerType to InterposerUnknown + // + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; ++SocketIndex) { + PlatformInfo->InterposerType[SocketIndex] =3D InterposerUnknown; + } + + // + // TypeJunctionCityIioPortBifurcationInit will use PlatformInfo->Inte= rposerType for PPO. + // + Status =3D TypeJunctionCityIioPortBifurcationInit (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + } + return Status; +} \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Junctio= nCity/Uba/TypeJunctionCity/Pei/PeiBoardInitLib.inf new file mode 100644 index 0000000000..ee6fdb95ff --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/PeiBoardInitLib.inf @@ -0,0 +1,167 @@ +## @file +# Component information file for BoardInitLib in PEI post memory phase. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation. +# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TypeJunctionCityPeiBoardInitLib + FILE_GUID =3D F92478AE-058E-4E2A-939C-B806D461398E + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL|PEIM + CONSTRUCTOR =3D TypeJunctionCityPeiBoardInitLibConstr= uctor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + HobLib + PeiServicesTablePointerLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + PeiBoardInitLib.c + GpioTable.c + PcdData.c + UsbOC.c + AcpiTablePcds.c + IioBifurInit.c + SlotTable.c + KtiEparam.c + PchEarlyUpdate.c + SoftStrapFixup.c + PeiBoardInit.h + +[FixedPcd] + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily + + gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName + gOemSkuTokenSpaceGuid.PcdOemSkuBoardName + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount + + gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel + gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05 + + gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName + + gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed + gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag + + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE + + gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32 + + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11 + + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + gOemSkuTokenSpaceGuid.PcdOemTableIdXhci + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8 + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna + gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap + + gPlatformTokenSpaceGuid.PcdMemInterposerMap + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioInitDataGuid + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Ub= a/TypeJunctionCity/Pei/SlotTable.c new file mode 100644 index 0000000000..963515ea41 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/SlotTable.c @@ -0,0 +1,172 @@ +/** @file + Slot Table Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +#define PCI_DEVICE_ON_BOARD_TRUE 0 +#define PCI_DEVICE_ON_BOARD_FALSE 1 + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +static UINT8 TypeJunctionCityPchPciSlotImpementedTableData[] =3D { + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 0 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 3 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 4 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 5 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18 + PCI_DEVICE_ON_BOARD_FALSE // Root Port 19 +}; + +UINT8 +GetTypeJunctionCityIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled. + // + IOU0Data =3D IIO_BIFURCATE_xxx8xxx8; + return IOU0Data; +} + +UINT8 +GetTypeJunctionCityIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeJunctionCityBroadwayTable= [] =3D { + {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + {Iio_Socket1, Iio_Iou1, Bw5_Addr_2}, + {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + + +PLATFORM_SLOT_UPDATE_TABLE TypeJunctionCitySlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeJunctionCityBroadwayTable, + GetTypeJunctionCityIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeJunctionCitySlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeJunctionCityBroadwayTable, + GetTypeJunctionCityIOU0Setting, + 0, + GetTypeJunctionCityIOU2Setting +}; + +PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeJunctionCityPchPciSlotI= mplementedTable =3D { + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + TypeJunctionCityPchPciSlotImpementedTableData +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeJunctionCityInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid, + &TypeJunctionCitySlotTable, + sizeof(TypeJunctionCitySlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2, + &TypeJunctionCitySlotTable2, + sizeof(TypeJunctionCitySlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPciSlotImplementedGuid, + &TypeJunctionCityPchPciSlotImplementedTab= le, + sizeof(TypeJunctionCityPchPciSlotImplemen= tedTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCi= ty/Uba/TypeJunctionCity/Pei/SoftStrapFixup.c new file mode 100644 index 0000000000..541961b020 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/SoftStrapFixup.c @@ -0,0 +1,121 @@ +/** @file + Soft Strap update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include + +PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeJunctionCitySoftStrapTable[] =3D +{ +// SoftStrapNumber, LowBit, BitLength, Value + {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary M= ux Select + {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control + {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2) + {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3) + {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select b= etween sSATA Port 2 and PCIe Port 8) + {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_G= P2) + {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_G= P3) + {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled + {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2 + {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3 + {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0 + {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1 + {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2 + {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3 + {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4 + {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2 + {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5 + {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6 + {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7 + {19, 26, 1, 0x1 }, // Statically assign PCH PCIe NP8 Uplink to act a= s Downlink or Uplink(PCIEUDS) + {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address + {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address + {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable + {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect + {88, 8, 2, 0x3 }, // Root Port Configuration 0 + {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between S= ATA Port 0 and PCIe Port 12 + {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between S= ATA Port 1 and PCIe Port 13 + {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between S= ATA Port 2 and PCIe Port 14 + {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between S= ATA Port 3 and PCIe Port 15 + {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between S= ATA Port 4 and PCIe Port 16 + {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between S= ATA Port 5 and PCIe Port 17 + {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between S= ATA Port 6 and PCIe Port 18 + {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between S= ATA Port 7 and PCIe Port 19 + {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0= and PCIe Port 12 + {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1= and PCIe Port 13 + {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2= and PCIe Port 14 + {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3= and PCIe Port 15 + {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4= and PCIe Port 16 + {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5= and PCIe Port 17 + {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6= and PCIe Port 18 + {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7= and PCIe Port 19 + {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection + {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled + {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled +// {133, 1, 1, 0x1 }, // Dual I/O Read Enabled +// {133, 2, 1, 0x1 }, // Quad Output Read Enabled +// {133, 3, 1, 0x1 }, // Quad I/O Read Enabled +// {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode +// {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable +// {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency +// {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode + +// +// END OF LIST +// + {0, 0, 0, 0} +}; + +UINT32 +TypeJunctionCitySystemBoardRevIdValue (VOID) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT(GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return 0xFF; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + return PlatformInfo->TypeRevisionId; +} + +VOID +TypeJunctionCityPlatformSpecificUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ) +{ +} + +PLATFORM_PCH_SOFTSTRAP_UPDATE TypeJunctionCitySoftStrapUpdate =3D +{ + PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE, + PLATFORM_SOFT_STRAP_UPDATE_VERSION, + TypeJunctionCitySoftStrapTable, + TypeJunctionCityPlatformSpecificUpdate +}; + +EFI_STATUS +TypeJunctionCityInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &TypeJunctionCitySoftStrapUpdate, + sizeof(TypeJunctionCitySoftStrapUpdate) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJuncti= onCity/Pei/UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/Ty= peJunctionCity/Pei/UsbOC.c new file mode 100644 index 0000000000..eaf59de869 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Uba/TypeJunctionCity/= Pei/UsbOC.c @@ -0,0 +1,127 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + + +#include +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeJunctionCityUsb20OverCurrentMappings[PCH_MAX_USB2_= PORTS] =3D { + UsbOverCurrentPin0, + UsbOverCurrentPin1, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin3, + UsbOverCurrentPin7, + UsbOverCurrentPin7, + UsbOverCurrentPin6, + UsbOverCurrentPin4, + UsbOverCurrentPin6, + UsbOverCurrentPin4, + UsbOverCurrentPin5, + UsbOverCurrentPin4, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB_OVERCURRENT_PIN TypeJunctionCityUsb30OverCurrentMappings[PCH_MAX_USB3_= PORTS] =3D { + UsbOverCurrentPin0, + UsbOverCurrentPin1, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin3, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeJunctionCityUsb20AfeParams[PCH_H_XHCI_MAX_= USB2_PHYSICAL_PORTS] =3D { + {3, 0, 3, 1}, // PP0 + {5, 0, 3, 1}, // PP1 + {3, 0, 3, 1}, // PP2 + {0, 5, 1, 1}, // PP3 + {3, 0, 3, 1}, // PP4 + {3, 0, 3, 1}, // PP5 + {3, 0, 3, 1}, // PP6 + {3, 0, 3, 1}, // PP7 + {2, 2, 1, 0}, // PP8 + {6, 0, 2, 1}, // PP9 + {2, 2, 1, 0}, // PP10 + {6, 0, 2, 1}, // PP11 + {0, 5, 1, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypeJunctionCityPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings =3D &TypeJunctionCityUsb20OverCurrentMapping= s[0]; + *Usb30OverCurrentMappings =3D &TypeJunctionCityUsb30OverCurrentMapping= s[0]; + + *Usb20AfeParams =3D TypeJunctionCityUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeJunctionCityUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeJunctionCityPlatformUsbOcUpdateCallback +}; + +EFI_STATUS +TypeJunctionCityPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + //# + //# USB, see PG 104 in GZP SCH + //# + +// USB2 USB3 Port OC +// +//Port00: PORT5 Back Panel ,OC0# +//Port01: PORT2 Back Panel ,OC0# +//Port02: PORT3 Back Panel ,OC1# +//Port03: PORT0 NOT USED ,NA +//Port04: BMC1.0 ,NA +//Port05: INTERNAL_2X5_A ,OC2# +//Port06: INTERNAL_2X5_A ,OC2# +//Port07: NOT USED ,NA +//Port08: EUSB (AKA SSD) ,NA +//Port09: INTERNAL_TYPEA ,OC6# +//Port10: PORT1 Front Panel ,OC5# +//Port11: NOT USED ,NA +//Port12: BMC2.0 ,NA +//Port13: PORT4 Front Panel ,OC5# + + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPeiPlatformUbaOcConfigDataGuid, + &TypeJunctionCityUsbOcUpdate, + sizeof(TypeJunctionCityUsbOcUpdate) + ); + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py= b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py new file mode 100644 index 0000000000..4125ece197 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py @@ -0,0 +1,127 @@ +# @ build_board.py +# Extensions for building JunctionCity using build_bios.py +# +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2021, American Megatrends International LLC.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +""" +This module serves as a sample implementation of the build extension +scripts +""" + +import os +import sys + +def pre_build_ex(config, functions): + """Additional Pre BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: nothing + """ + print("pre_build_ex") + config["BUILD_DIR_PATH"] =3D os.path.join(config["WORKSPACE"], + 'Build', + config["PLATFORM_BOARD_PACKAGE= "], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + # set BUILD_DIR path + config["BUILD_DIR"] =3D os.path.join('Build', + config["PLATFORM_BOARD_PACKAGE"], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + config["BUILD_X64"] =3D os.path.join(config["BUILD_DIR_PATH"], 'X64') + config["BUILD_IA32"] =3D os.path.join(config["BUILD_DIR_PATH"], 'IA32'= ) + + if not os.path.isdir(config["BUILD_DIR_PATH"]): + try: + os.makedirs(config["BUILD_DIR_PATH"]) + except OSError: + print("Error while creating Build folder") + sys.exit(1) + + #@todo: Replace this with PcdFspModeSelection + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") =3D=3D "TRUE": + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D0" + else: + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D1" + + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") =3D=3D "TRUE": + raise ValueError("FSP API Mode is currently unsupported on Ice Lak= e Xeon Scalable") + return None + +def _merge_files(files, ofile): + with open(ofile, 'wb') as of: + for x in files: + if not os.path.exists(x): + return + + with open(x, 'rb') as f: + of.write(f.read()) + +def build_ex(config, functions): + """Additional BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("build_ex") + fv_path =3D os.path.join(config["BUILD_DIR_PATH"], "FV") + binary_fd =3D os.path.join(fv_path, "BINARY.fd") + main_fd =3D os.path.join(fv_path, "MAIN.fd") + secpei_fd =3D os.path.join(fv_path, "SECPEI.fd") + board_fd =3D config["BOARD"].upper() + final_fd =3D os.path.join(fv_path, "{}.fd".format(board_fd)) + _merge_files((binary_fd, main_fd, secpei_fd), final_fd) + return None + + +def post_build_ex(config, functions): + """Additional Post BIOS build function + + :param config: The environment variables to be used in the post + build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("post_build_ex") + fv_path =3D os.path.join(config["BUILD_DIR_PATH"], "FV") + board_fd =3D config["BOARD"].upper() + final_fd =3D os.path.join(fv_path, "{}.fd".format(board_fd)) + final_ifwi =3D os.path.join(fv_path, "{}.bin".format(board_fd)) + + ifwi_ingredients_path =3D os.path.join(config["WORKSPACE_PLATFORM_BIN"= ], "Ifwi", config["BOARD"]) + flash_descriptor =3D os.path.join(ifwi_ingredients_path, "FlashDescrip= tor.bin") + intel_me =3D os.path.join(ifwi_ingredients_path, "Me.bin") + _merge_files((flash_descriptor, intel_me, final_fd), final_ifwi) + if os.path.isfile(final_fd): + print("IFWI image can be found at {}".format(final_ifwi)) + return None + + +def clean_ex(config, functions): + """Additional clean function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("clean_ex") + return None diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.c= fg b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg new file mode 100644 index 0000000000..602987b922 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg @@ -0,0 +1,37 @@ +# @ build_config.cfg +# This is the JunctionCity board specific build settings +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2021, American Megatrends International LLC.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN =3D edk2-non-osi/Platform/Intel/WhitleyOpenBoardBin= Pkg +EDK_SETUP_OPTION =3D +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D WhitleyOpenBoardPkg +PROJECT =3D WhitleyOpenBoardPkg/JunctionCity +BOARD =3D JunctionCity +FLASH_MAP_FDF =3D WhitleyOpenBoardPkg/FspFlashOffsets.fdf +PROJECT_DSC =3D WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc +BOARD_PKG_PCD_DSC =3D WhitleyOpenBoardPkg/PlatformPkgConfig.dsc +ADDITIONAL_SCRIPTS =3D WhitleyOpenBoardPkg/JunctionCity/build_board.py +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D -D CPUTARGET=3DICX -D RP_PKG=3DWhitleyOpenBoardPkg -D = SILICON_PKG=3DWhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=3D6= 4 -D MAX_THREAD=3D2 -D PLATFORM_PKG=3DMinPlatformPkg +MAX_SOCKET =3D 4 +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D TRUE +FSP_BIN_PKG =3D WhitleyFspBinPkg +FSP_PKG_NAME =3D WhitleyFspPkg +FSP_BINARY_BUILD =3D FALSE +FSP_TEST_RELEASE =3D FALSE +SECURE_BOOT_ENABLE =3D FALSE +BIOS_INFO_GUID =3D 4A4CA1C6-871C-45BB-8801-6910A7AA5807 diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/P= latformInfo.c b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInf= o/PlatformInfo.c index 3652695fba..e638e6f941 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.c @@ -1,761 +1,774 @@ -/** @file - Platform Info PEIM. - - @copyright - Copyright 1999 - 2021 Intel Corporation. - - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include "PlatformInfo.h" -#include -#include -#include - -#include - -#include -#include -#include - -#include - -#define TEMP_BUS_NUMBER (0x3F) - - -STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformInfoPpi =3D { - EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, - &gEfiPlatformInfoGuid, - NULL - }; - -#define BOARD_ID_GPIO_PADS_NUMBER 6 -#define BOARD_REV_ID_GPIO_PADS_NUMBER 3 - -// -// These pads shall not be board specific as these are used for Board ID a= nd Rev ID detection -// Therefore can not be moved to UBA and are common for all Purley boards -// -GPIO_PAD mBoardId [BOARD_ID_GPIO_PADS_NUMBER] =3D { - // BoardId pads - PADCFG register for GPIO G12 - // WARNING: The pad number must be obtained from board schematics - GPIO_SKL_H_GPP_G12, - GPIO_SKL_H_GPP_G13, - GPIO_SKL_H_GPP_G14, - GPIO_SKL_H_GPP_G15, - GPIO_SKL_H_GPP_G16, - GPIO_SKL_H_GPP_B19 -}; - -GPIO_PAD mBoardRevId [BOARD_REV_ID_GPIO_PADS_NUMBER] =3D { - // Board RevId pads - Start from pad C12 - // WARNING: This should be obtained from board schematics - GPIO_SKL_H_GPP_C12, - GPIO_SKL_H_GPP_C13, - GPIO_SKL_H_GPP_B9 -}; - -GPIO_CONFIG mBoardAndRevIdConfig =3D { - // Board and Revision ID pads configuration required for proper reading = the values - GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntD= efault, - GpioPlatformReset, GpioTermDefault, GpioLockDefault, GpioRxRaw1Default -}; - - -VOID -GpioConfigForBoardId ( - VOID - ) -{ - UINT8 i; - EFI_STATUS Status; - GPIO_CONFIG PadConfig; - DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; - - PadConfig.PadMode =3D mBoardAndRevIdConfig.PadMode; - PadConfig.HostSoftPadOwn =3D mBoardAndRevIdConfig.HostSoftPadOwn; - PadConfig.Direction =3D mBoardAndRevIdConfig.Direction; - PadConfig.OutputState =3D mBoardAndRevIdConfig.OutputState; - PadConfig.InterruptConfig =3D mBoardAndRevIdConfig.InterruptConfig; - PadConfig.PowerConfig =3D mBoardAndRevIdConfig.PowerConfig; - PadConfig.ElectricalConfig =3D mBoardAndRevIdConfig.ElectricalConfig; - PadConfig.LockConfig =3D mBoardAndRevIdConfig.LockConfig; - PadConfig.OtherSettings =3D mBoardAndRevIdConfig.OtherSettings; - - Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return; - } - - for (i =3D 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) { - Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (mBoardId[i], &PadCon= fig); - ASSERT_EFI_ERROR (Status); - } -} - - -VOID -GpioConfigForBoardRevId ( - VOID - ) -{ - UINT8 i; - EFI_STATUS Status; - GPIO_CONFIG PadConfig; - DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; - - PadConfig.PadMode =3D mBoardAndRevIdConfig.PadMode; - PadConfig.HostSoftPadOwn =3D mBoardAndRevIdConfig.HostSoftPadOwn; - PadConfig.Direction =3D mBoardAndRevIdConfig.Direction; - PadConfig.OutputState =3D mBoardAndRevIdConfig.OutputState; - PadConfig.InterruptConfig =3D mBoardAndRevIdConfig.InterruptConfig; - PadConfig.PowerConfig =3D mBoardAndRevIdConfig.PowerConfig; - PadConfig.ElectricalConfig =3D mBoardAndRevIdConfig.ElectricalConfig; - PadConfig.LockConfig =3D mBoardAndRevIdConfig.LockConfig; - PadConfig.OtherSettings =3D mBoardAndRevIdConfig.OtherSettings; - - Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return; - } - - for (i =3D 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++) { - Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (mBoardRevId[i], &Pad= Config); - ASSERT_EFI_ERROR (Status); - } -} - -/** - - Reads GPIO pins to get Board ID value - - @retval Status - Success if GPIO's are read properly - -**/ -EFI_STATUS -GpioGetBoardId ( - OUT UINT32 *BoardId - ) -{ - EFI_STATUS Status =3D EFI_DEVICE_ERROR; - UINT32 Data32; - UINT8 i; - UINT32 BdId; - DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; - - if (BoardId =3D=3D NULL) { - return EFI_UNSUPPORTED; - } - - Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - BdId =3D 0; - - GpioConfigForBoardId (); - - for (i =3D 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) { - Status =3D DynamicSiLibraryPpi->GpioGetInputValue (mBoardId[i], &Data3= 2); - if (EFI_ERROR(Status)) { - break; - } - if (Data32) { - BdId =3D BdId | (1 << i); - } - } - if (Status !=3D EFI_SUCCESS) { - return Status; - } - *BoardId =3D BdId; - return EFI_SUCCESS; -} - -/** - - Reads GPIO pins to get Board Revision ID value - - @retval Status - Success if GPIO's are read properly - -**/ -EFI_STATUS -GpioGetBoardRevId ( - OUT UINT32 *BoardRevId - ) -{ - EFI_STATUS Status =3D EFI_DEVICE_ERROR; - UINT32 Data32; - UINT8 i; - UINT32 RevId; - DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; - - if (BoardRevId =3D=3D NULL) { - return EFI_UNSUPPORTED; - } - - Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - RevId =3D 0; - - GpioConfigForBoardRevId (); - - for (i =3D 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++){ - Status =3D DynamicSiLibraryPpi->GpioGetInputValue (mBoardRevId[i], &D= ata32); - if (EFI_ERROR(Status)) { - break; - } - if (Data32) { - RevId =3D RevId | (1 << i); - } - } - if (Status !=3D EFI_SUCCESS) { - return Status; - } - *BoardRevId =3D RevId; - return EFI_SUCCESS; - -} - -/** - - Returns the Model ID of the CPU. - Model ID =3D EAX[7:4] - -**/ -VOID -GetCpuInfo ( - UINT32 *CpuType, - UINT8 *CpuStepping - ) - -{ - UINT32 RegEax=3D0; - - AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); - - *CpuStepping =3D (UINT8) (RegEax & 0x0F); - *CpuType =3D (UINT32) (RegEax >> 4); -} - - -/** - - GC_TODO: add routine description - - @param BAR - GC_TODO: add arg description - @param PeiServices - GC_TODO: add arg description - - @retval None - -**/ -VOID -InitGSX( - UINT32 *BAR, - IN EFI_PEI_SERVICES **PeiServices -) -{ -} - -/** - - GC_TODO: add routine description - - @param Data - GC_TODO: add arg description - @param PeiServices - GC_TODO: add arg description - - @retval EFI_SUCCESS - GC_TODO: add retval description - @retval EFI_UNSUPPORTED - GC_TODO: add retval description - -**/ -EFI_STATUS -GsxRead( - UINT32 *Data, - IN EFI_PEI_SERVICES **PeiServices -) -{ - return EFI_UNSUPPORTED; -} - -/** - - GC_TODO: add routine description - - @param Data - GC_TODO: add arg description - @param PeiServices - GC_TODO: add arg description - - @retval None - -**/ -VOID -GetGsxBoardID( - BOARD_ID *Data, - IN EFI_PEI_SERVICES **PeiServices -) -{ - - EFI_STATUS Status; - UINT32 GSXIN[2]; - UINT32 RetryCount; - - RetryCount =3D 0; - GSXIN[0] =3D 0; - GSXIN[1] =3D 0; - - do { - Status =3D GsxRead(GSXIN, PeiServices); - - if(Status){ - // if EFI_SUCCESS !=3D Success then retry one more time - RetryCount ++; - }else{ - // if EFI_SUCCESS read Board ID and exit - RetryCount =3D 0xFFFFFFFF; - } - - if (GSXIN[0] & BIT0) { - Data->BoardID.BoardID0 =3D 1; - } - - if (GSXIN[0] & BIT1) { - Data->BoardID.BoardID1 =3D 1; - } - - if (GSXIN[0] & BIT2) { - Data->BoardID.BoardID2 =3D 1; - } - - if (GSXIN[0] & BIT3) { - Data->BoardID.BoardID3 =3D 1; - } - - if (GSXIN[0] & BIT4) { - Data->BoardID.BoardID4 =3D 1; - } - - if (GSXIN[0] & BIT5) { - Data->BoardID.BoardRev0 =3D 1; - } - - if (GSXIN[0] & BIT6) { - Data->BoardID.BoardRev1 =3D 1; - } - - } while(RetryCount < 1); - - if(Status){ - // - // Unhable to read GSX HW error Hang the system - // - DEBUG ((EFI_D_ERROR, "ERROR: GSX HW is unavailable, SYSTEM HANG\n")); - CpuDeadLoop (); - } -} - -/** - Get Platform Type by read Platform Data Region in SPI flash. - SPI Descriptor Mode Routines for Accessing Platform Info from Platform= Data Region (PDR) - - @param PeiServices - General purpose services available to every PEI= M. - @param PlatformInfoHob - Platform Type is returned in PlatformInfoHob-= >BoardId - - @retval Status EFI_SUCCESS - PDR read success - @retval Status EFI_INCOMPATIBLE_VERSION - PDR read but it is not valid= Platform Type - -**/ -EFI_STATUS -PdrGetPlatformInfo ( - IN CONST EFI_PEI_SERVICES **PeiServices, - OUT EFI_PLATFORM_INFO *PlatformInfoHob - ) -{ - EFI_STATUS Status; - PCH_SPI_PROTOCOL *SpiPpi; - UINTN Size; - - // - // Locate the SPI PPI Interface - // - Status =3D (*PeiServices)->LocatePpi ( - PeiServices, - &gPchSpiPpiGuid, - 0, - NULL, - &SpiPpi - ); - - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - // - // Read the PIT (Platform Info Table) from the SPI Flash Platform Data R= egion - // - Size =3D sizeof (EFI_PLATFORM_INFO); - Status =3D SpiPpi->FlashRead ( - SpiPpi, - FlashRegionPlatformData, - PDR_REGION_START_OFFSET, - (UINT32) Size, - (UINT8 *) PlatformInfoHob - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - if ((PlatformInfoHob->BoardId >=3D TypePlatformMin) && (PlatformInfoHob-= >BoardId <=3D TypePlatformMax)) { - // - // Valid Platform Identified - // - DEBUG ((DEBUG_INFO, "Platform Info from PDR: Type =3D %x\n",PlatformIn= foHob->BoardId)); - } else { - // - // Reading PIT from SPI PDR Failed or a unknown platform identified - // - DEBUG ((EFI_D_ERROR, "PIT from SPI PDR reports Platform ID as %x. This= is unknown ID. Assuming Greencity Platform!\n", PlatformInfoHob->BoardId))= ; - PlatformInfoHob->BoardId =3D TypePlatformUnknown; - Status =3D EFI_INCOMPATIBLE_VERSION; - } - return Status; -} - -VOID -GatherQATInfo(OUT EFI_PLATFORM_INFO *PlatformInfoHob) -/** - - GC_TODO: add routine description - - @param None - - @ret None -**/ -{ - EFI_STATUS Status; - GPIO_CONFIG PadConfig; - DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; - - // Gpio programming to QAT board detection - PadConfig.PadMode =3D GpioPadModeGpio; - PadConfig.HostSoftPadOwn =3D GpioHostOwnDefault; - PadConfig.Direction =3D GpioDirIn; - PadConfig.OutputState =3D GpioOutLow; - PadConfig.InterruptConfig =3D GpioIntDis; - PadConfig.PowerConfig =3D GpioResetPwrGood; - PadConfig.ElectricalConfig =3D GpioTermNone; - PadConfig.LockConfig =3D GpioPadConfigLock; - PadConfig.OtherSettings =3D 00; - - Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return; - } - - Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B3, &Pa= dConfig); - Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B3, &P= latformInfoHob->QATDis); - Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B4, &Pa= dConfig); - Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B4, &P= latformInfoHob->QATSel); -} - -EFI_STATUS -GetPlatformInfo ( - IN CONST EFI_PEI_SERVICES **PeiServices, - OUT EFI_PLATFORM_INFO *PlatformInfoHob - ) -/** - - GC_TODO: add routine description - - @param PeiServices - GC_TODO: add arg description - @param PlatformInfoHob - GC_TODO: add arg description - - @retval EFI_UNSUPPORTED - GC_TODO: add retval description - @retval EFI_SUCCESS - GC_TODO: add retval description - -**/ -{ - - - UINT32 BoardId; - UINT32 BoardRev; - EFI_PEI_PCI_CFG2_PPI *PciCfgPpi; - EFI_STATUS Status; - - PciCfgPpi =3D (**PeiServices).PciCfg; - ASSERT (PciCfgPpi !=3D NULL); - - PlatformInfoHob->BoardId =3D TypeNeonCityEPRP; - DEBUG ((DEBUG_INFO, "Use GPIO to read Board ID\n")); - - Status =3D GpioGetBoardId (&BoardId); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n")); - return Status; - } - Status =3D GpioGetBoardRevId (&BoardRev); - if (EFI_ERROR(Status)) { - DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n")); - return Status; - } - PlatformInfoHob->TypeRevisionId =3D BoardRev; - - switch (BoardId) { - case 0x00: // for Simics - PlatformInfoHob->BoardId =3D TypeWilsonCityRP; - break; - case 0x01: - PlatformInfoHob->BoardId =3D TypeWilsonCityRP; - DEBUG ((DEBUG_INFO, "Board ID =3D TypeWilsonCityRP\n")); - break; - case 0x12: - PlatformInfoHob->BoardId =3D TypeWilsonCityRP; - DEBUG((DEBUG_INFO, "Board ID =3D TypeWilsonCityRP\n")); - break; - case 0x15: - PlatformInfoHob->BoardId =3D TypeWilsonCitySMT; - DEBUG((DEBUG_INFO, "Board ID =3D TypeWilsonCitySMT\n")); - break; - case 0x17: - case 0x18: - PlatformInfoHob->BoardId =3D TypeCooperCityRP; - DEBUG((DEBUG_INFO, "Board ID =3D TypeCooperCityRP\n")); - break; - default: - PlatformInfoHob->BoardId =3D TypePlatformDefault; - DEBUG ((DEBUG_INFO, "Board ID =3D %2X Default set to TypePlatformDef= ault\n",BoardId)); - break; - } - - GatherQATInfo(PlatformInfoHob); - - DEBUG ((DEBUG_INFO, "Board Rev.: %d\n", BoardRev)); - return EFI_SUCCESS; -} - -/** - - This function initializes the board related flag to indicates if - PCH and Lan-On-Motherboard (LOM) devices is supported. - -**/ -VOID -GetPchLanSupportInfo( - IN EFI_PLATFORM_INFO *PlatformInfoHob - ) -{ - PlatformInfoHob->PchData.LomLanSupported =3D 0; -} - -/** - - GC_TODO: add routine description - - @param PeiVariable - GC_TODO: add arg description - @param PlatformInfoHob - GC_TODO: add arg description - - @retval EFI_SUCCESS - GC_TODO: add retval description - -**/ -EFI_STATUS -EFIAPI -GetIioCommonRcPlatformSetupPolicy( - OUT EFI_PLATFORM_INFO *PlatformInfoHob - ) - { - UINT8 IsocEn; - - CopyMem (&IsocEn, (UINT8 *)PcdGetPtr(PcdSocketCommonRcConfig) + OFFSET_O= F(SOCKET_COMMONRC_CONFIGURATION, IsocEn), sizeof(UINT8)); - - PlatformInfoHob->SysData.IsocEn =3D IsocEn; // ISOC enabled - - return EFI_SUCCESS; -} -/** - - GC_TODO: add routine description - - @param PeiVariable - GC_TODO: add arg description - @param PlatformInfoHob - GC_TODO: add arg description - - @retval EFI_SUCCESS - GC_TODO: add retval description - -**/ -EFI_STATUS -EFIAPI -GetIioPlatformSetupPolicy( - OUT EFI_PLATFORM_INFO *PlatformInfoHob - ) -{ - return EFI_SUCCESS; -} - - -/** - Platform Type detection. Because the PEI globle variable - is in the flash, it could not change directly.So use - 2 PPIs to distinguish the platform type. - - @param FfsHeader - Pointer to Firmware File System file header. - @param PeiServices - General purpose services available to every PEIM. - - @retval EFI_SUCCESS - Memory initialization completed successfully. - @retval Others - All other error conditions encountered result in= an ASSERT. - -**/ -EFI_STATUS -EFIAPI -PlatformInfoInit ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - EFI_PEI_PCI_CFG2_PPI *PciCfgPpi; - EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable; - EFI_PLATFORM_INFO PlatformInfoHob; - EFI_PLATFORM_INFO tempPlatformInfoHob; - UINT8 ChipId; - UINT32 Delay; - UINT32 CpuType; - UINT8 CpuStepping; - DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; - - PciCfgPpi =3D (**PeiServices).PciCfg; - if (PciCfgPpi =3D=3D NULL) { - DEBUG ((EFI_D_ERROR, "\nError! PlatformInfoInit() - PeiServices is a N= ULL Pointer!!!\n")); - ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); - return EFI_INVALID_PARAMETER; - } - - // - // Locate Variable PPI - // - Status =3D PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NU= LL, &PeiVariable); - - (*PeiServices)->SetMem (&PlatformInfoHob, sizeof (PlatformInfoHob), 0); - - Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - // - // -------------------------------------------------- - // - // Detect the iBMC SIO for CV/CRB Platforms - // 0x2E/0x2F decoding has been enabled in MonoStatusCode PEIM. - // - IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_UNLOCK); - for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); - IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_CHIP_ID_REG); - for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); - ChipId =3D IoRead8 (PILOTIV_SIO_DATA_PORT); - for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); - IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_LOCK); - for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); - - if (EFI_ERROR (Status)) - { - DEBUG((EFI_D_ERROR, "LocatePpi Error in PlatformInfo.c !\n")); - } - - Status =3D GetIioPlatformSetupPolicy (&PlatformInfoHob); - ASSERT_EFI_ERROR (Status); - Status =3D GetIioCommonRcPlatformSetupPolicy (&PlatformInfoHob); - ASSERT_EFI_ERROR (Status); - - // - // Update PCH Type - // - PlatformInfoHob.PchType =3D DynamicSiLibraryPpi->GetPchSeries (); - PlatformInfoHob.PchSku =3D DynamicSiLibraryPpi->GetPchLpcDeviceId (); - PlatformInfoHob.PchRevision =3D (UINT8) DynamicSiLibraryPpi->PchStepping= (); - PlatformInfoHob.MaxNumOfPchs =3D 1; - Status =3D EFI_SUCCESS; - - if(!EFI_ERROR(Status)) { - Status =3D GetPlatformInfo (PeiServices, &PlatformInfoHob); - if(EFI_ERROR (Status)) { - Status =3D PdrGetPlatformInfo (PeiServices, &tempPlatformInfoHob); - PlatformInfoHob.BoardId =3D tempPlatformInfoHob.BoardId; - PlatformInfoHob.TypeRevisionId =3D tempPlatformInfoHob.TypeRevisio= nId; - if (EFI_ERROR(Status)) { - PlatformInfoHob.BoardId =3D TypePlatformUnknown; - } - } - } else { - PlatformInfoHob.BoardId =3D TypePlatformUnknown; - } - - // - // Update IIO Type - // - PlatformInfoHob.IioRevision =3D 0; - - - // - // Get Subtractive decode enable bit from descriptor - // - - if (DynamicSiLibraryPpi->PchIsGbeRegionValid () =3D=3D FALSE) { - PlatformInfoHob.PchData.GbeRegionInvalid =3D 1; - } else { - PlatformInfoHob.PchData.GbeRegionInvalid =3D 0; - } - GetPchLanSupportInfo (&PlatformInfoHob); - PlatformInfoHob.PchData.GbePciePortNum =3D 0xFF; - PlatformInfoHob.PchData.GbePciePortNum =3D (UINT8) DynamicSiLibraryPpi->= PchGetGbePortNumber (); - PlatformInfoHob.PchData.GbeEnabled =3D DynamicSiLibraryPpi->PchIsGbePre= sent (); - PlatformInfoHob.PchData.PchStepping =3D (UINT8) DynamicSiLibraryPpi->Pch= Stepping (); - - PlatformInfoHob.SysData.SysSioExist =3D (UINT8)IsSioExist(); - - GetCpuInfo (&CpuType, &CpuStepping); - PlatformInfoHob.CpuType =3D CpuType; - PlatformInfoHob.CpuStepping =3D CpuStepping; - - // - // Set default memory topology to DaisyChainTopology. This should be mod= ified in UBA board - // specific file. - // - (*PeiServices)->SetMem (&PlatformInfoHob.MemoryTopology, sizeof (Platfor= mInfoHob.MemoryTopology), DaisyChainTopology); - - // - // Set default memory type connector to DimmConnectorPth. This should be= modified in UBA board - // specific file. - // - (*PeiServices)->SetMem (&PlatformInfoHob.MemoryConnectorType, sizeof (Pl= atformInfoHob.MemoryConnectorType), DimmConnectorPth); - - // - // Build HOB for setup memory information - // - BuildGuidDataHob ( - &gEfiPlatformInfoGuid, - &(PlatformInfoHob), - sizeof (EFI_PLATFORM_INFO) - ); - - Status =3D (**PeiServices).InstallPpi (PeiServices, &mPlatformInfoPpi); - ASSERT_EFI_ERROR (Status); - - // - // Save PlatformInfoHob.BoardId in CMOS - // - IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_LO); - IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)PlatformInfoHob.BoardId); - - IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_HI); - IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)((PlatformInfoHob.PcieRiser2T= ype << 4) + (PlatformInfoHob.PcieRiser1Type))); - - return EFI_SUCCESS; -} +/** @file + Platform Info PEIM. + + @copyright + Copyright 1999 - 2021 Intel Corporation. + Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PlatformInfo.h" +#include +#include +#include + +#include + +#include +#include +#include + +#include + +#define TEMP_BUS_NUMBER (0x3F) + + +STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformInfoPpi =3D { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPlatformInfoGuid, + NULL + }; + +#define BOARD_ID_GPIO_PADS_NUMBER 6 +#define BOARD_REV_ID_GPIO_PADS_NUMBER 3 + +// +// These pads shall not be board specific as these are used for Board ID a= nd Rev ID detection +// Therefore can not be moved to UBA and are common for all Purley boards +// +GPIO_PAD mBoardId [BOARD_ID_GPIO_PADS_NUMBER] =3D { + // BoardId pads - PADCFG register for GPIO G12 + // WARNING: The pad number must be obtained from board schematics + GPIO_SKL_H_GPP_G12, + GPIO_SKL_H_GPP_G13, + GPIO_SKL_H_GPP_G14, + GPIO_SKL_H_GPP_G15, + GPIO_SKL_H_GPP_G16, + GPIO_SKL_H_GPP_B19 +}; + +GPIO_PAD mBoardRevId [BOARD_REV_ID_GPIO_PADS_NUMBER] =3D { + // Board RevId pads - Start from pad C12 + // WARNING: This should be obtained from board schematics + GPIO_SKL_H_GPP_C12, + GPIO_SKL_H_GPP_C13, + GPIO_SKL_H_GPP_B9 +}; + +GPIO_CONFIG mBoardAndRevIdConfig =3D { + // Board and Revision ID pads configuration required for proper reading = the values + GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntD= efault, + GpioPlatformReset, GpioTermDefault, GpioLockDefault, GpioRxRaw1Default +}; + + +VOID +GpioConfigForBoardId ( + VOID + ) +{ + UINT8 i; + EFI_STATUS Status; + GPIO_CONFIG PadConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + PadConfig.PadMode =3D mBoardAndRevIdConfig.PadMode; + PadConfig.HostSoftPadOwn =3D mBoardAndRevIdConfig.HostSoftPadOwn; + PadConfig.Direction =3D mBoardAndRevIdConfig.Direction; + PadConfig.OutputState =3D mBoardAndRevIdConfig.OutputState; + PadConfig.InterruptConfig =3D mBoardAndRevIdConfig.InterruptConfig; + PadConfig.PowerConfig =3D mBoardAndRevIdConfig.PowerConfig; + PadConfig.ElectricalConfig =3D mBoardAndRevIdConfig.ElectricalConfig; + PadConfig.LockConfig =3D mBoardAndRevIdConfig.LockConfig; + PadConfig.OtherSettings =3D mBoardAndRevIdConfig.OtherSettings; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + for (i =3D 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) { + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (mBoardId[i], &PadCon= fig); + ASSERT_EFI_ERROR (Status); + } +} + + +VOID +GpioConfigForBoardRevId ( + VOID + ) +{ + UINT8 i; + EFI_STATUS Status; + GPIO_CONFIG PadConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + PadConfig.PadMode =3D mBoardAndRevIdConfig.PadMode; + PadConfig.HostSoftPadOwn =3D mBoardAndRevIdConfig.HostSoftPadOwn; + PadConfig.Direction =3D mBoardAndRevIdConfig.Direction; + PadConfig.OutputState =3D mBoardAndRevIdConfig.OutputState; + PadConfig.InterruptConfig =3D mBoardAndRevIdConfig.InterruptConfig; + PadConfig.PowerConfig =3D mBoardAndRevIdConfig.PowerConfig; + PadConfig.ElectricalConfig =3D mBoardAndRevIdConfig.ElectricalConfig; + PadConfig.LockConfig =3D mBoardAndRevIdConfig.LockConfig; + PadConfig.OtherSettings =3D mBoardAndRevIdConfig.OtherSettings; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + for (i =3D 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++) { + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (mBoardRevId[i], &Pad= Config); + ASSERT_EFI_ERROR (Status); + } +} + +/** + + Reads GPIO pins to get Board ID value + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetBoardId ( + OUT UINT32 *BoardId + ) +{ + EFI_STATUS Status =3D EFI_DEVICE_ERROR; + UINT32 Data32; + UINT8 i; + UINT32 BdId; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + if (BoardId =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + BdId =3D 0; + + GpioConfigForBoardId (); + + for (i =3D 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) { + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (mBoardId[i], &Data3= 2); + if (EFI_ERROR(Status)) { + break; + } + if (Data32) { + BdId =3D BdId | (1 << i); + } + } + if (Status !=3D EFI_SUCCESS) { + return Status; + } + *BoardId =3D BdId; + return EFI_SUCCESS; +} + +/** + + Reads GPIO pins to get Board Revision ID value + + @retval Status - Success if GPIO's are read properly + +**/ +EFI_STATUS +GpioGetBoardRevId ( + OUT UINT32 *BoardRevId + ) +{ + EFI_STATUS Status =3D EFI_DEVICE_ERROR; + UINT32 Data32; + UINT8 i; + UINT32 RevId; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + if (BoardRevId =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + RevId =3D 0; + + GpioConfigForBoardRevId (); + + for (i =3D 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++){ + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (mBoardRevId[i], &D= ata32); + if (EFI_ERROR(Status)) { + break; + } + if (Data32) { + RevId =3D RevId | (1 << i); + } + } + if (Status !=3D EFI_SUCCESS) { + return Status; + } + *BoardRevId =3D RevId; + return EFI_SUCCESS; + +} + +/** + + Returns the Model ID of the CPU. + Model ID =3D EAX[7:4] + +**/ +VOID +GetCpuInfo ( + UINT32 *CpuType, + UINT8 *CpuStepping + ) + +{ + UINT32 RegEax=3D0; + + AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); + + *CpuStepping =3D (UINT8) (RegEax & 0x0F); + *CpuType =3D (UINT32) (RegEax >> 4); +} + + +/** + + GC_TODO: add routine description + + @param BAR - GC_TODO: add arg description + @param PeiServices - GC_TODO: add arg description + + @retval None + +**/ +VOID +InitGSX( + UINT32 *BAR, + IN EFI_PEI_SERVICES **PeiServices +) +{ +} + +/** + + GC_TODO: add routine description + + @param Data - GC_TODO: add arg description + @param PeiServices - GC_TODO: add arg description + + @retval EFI_SUCCESS - GC_TODO: add retval description + @retval EFI_UNSUPPORTED - GC_TODO: add retval description + +**/ +EFI_STATUS +GsxRead( + UINT32 *Data, + IN EFI_PEI_SERVICES **PeiServices +) +{ + return EFI_UNSUPPORTED; +} + +/** + + GC_TODO: add routine description + + @param Data - GC_TODO: add arg description + @param PeiServices - GC_TODO: add arg description + + @retval None + +**/ +VOID +GetGsxBoardID( + BOARD_ID *Data, + IN EFI_PEI_SERVICES **PeiServices +) +{ + + EFI_STATUS Status; + UINT32 GSXIN[2]; + UINT32 RetryCount; + + RetryCount =3D 0; + GSXIN[0] =3D 0; + GSXIN[1] =3D 0; + + do { + Status =3D GsxRead(GSXIN, PeiServices); + + if(Status){ + // if EFI_SUCCESS !=3D Success then retry one more time + RetryCount ++; + }else{ + // if EFI_SUCCESS read Board ID and exit + RetryCount =3D 0xFFFFFFFF; + } + + if (GSXIN[0] & BIT0) { + Data->BoardID.BoardID0 =3D 1; + } + + if (GSXIN[0] & BIT1) { + Data->BoardID.BoardID1 =3D 1; + } + + if (GSXIN[0] & BIT2) { + Data->BoardID.BoardID2 =3D 1; + } + + if (GSXIN[0] & BIT3) { + Data->BoardID.BoardID3 =3D 1; + } + + if (GSXIN[0] & BIT4) { + Data->BoardID.BoardID4 =3D 1; + } + + if (GSXIN[0] & BIT5) { + Data->BoardID.BoardRev0 =3D 1; + } + + if (GSXIN[0] & BIT6) { + Data->BoardID.BoardRev1 =3D 1; + } + + } while(RetryCount < 1); + + if(Status){ + // + // Unhable to read GSX HW error Hang the system + // + DEBUG ((EFI_D_ERROR, "ERROR: GSX HW is unavailable, SYSTEM HANG\n")); + CpuDeadLoop (); + } +} + +/** + Get Platform Type by read Platform Data Region in SPI flash. + SPI Descriptor Mode Routines for Accessing Platform Info from Platform= Data Region (PDR) + + @param PeiServices - General purpose services available to every PEI= M. + @param PlatformInfoHob - Platform Type is returned in PlatformInfoHob-= >BoardId + + @retval Status EFI_SUCCESS - PDR read success + @retval Status EFI_INCOMPATIBLE_VERSION - PDR read but it is not valid= Platform Type + +**/ +EFI_STATUS +PdrGetPlatformInfo ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_PLATFORM_INFO *PlatformInfoHob + ) +{ + EFI_STATUS Status; + PCH_SPI_PROTOCOL *SpiPpi; + UINTN Size; + + // + // Locate the SPI PPI Interface + // + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gPchSpiPpiGuid, + 0, + NULL, + &SpiPpi + ); + + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Read the PIT (Platform Info Table) from the SPI Flash Platform Data R= egion + // + Size =3D sizeof (EFI_PLATFORM_INFO); + Status =3D SpiPpi->FlashRead ( + SpiPpi, + FlashRegionPlatformData, + PDR_REGION_START_OFFSET, + (UINT32) Size, + (UINT8 *) PlatformInfoHob + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if ((PlatformInfoHob->BoardId >=3D TypePlatformMin) && (PlatformInfoHob-= >BoardId <=3D TypePlatformMax)) { + // + // Valid Platform Identified + // + DEBUG ((DEBUG_INFO, "Platform Info from PDR: Type =3D %x\n",PlatformIn= foHob->BoardId)); + } else { + // + // Reading PIT from SPI PDR Failed or a unknown platform identified + // + DEBUG ((EFI_D_ERROR, "PIT from SPI PDR reports Platform ID as %x. This= is unknown ID. Assuming Greencity Platform!\n", PlatformInfoHob->BoardId))= ; + PlatformInfoHob->BoardId =3D TypePlatformUnknown; + Status =3D EFI_INCOMPATIBLE_VERSION; + } + return Status; +} + +VOID +GatherQATInfo(OUT EFI_PLATFORM_INFO *PlatformInfoHob) +/** + + GC_TODO: add routine description + + @param None + + @ret None +**/ +{ + EFI_STATUS Status; + GPIO_CONFIG PadConfig; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + // Gpio programming to QAT board detection + PadConfig.PadMode =3D GpioPadModeGpio; + PadConfig.HostSoftPadOwn =3D GpioHostOwnDefault; + PadConfig.Direction =3D GpioDirIn; + PadConfig.OutputState =3D GpioOutLow; + PadConfig.InterruptConfig =3D GpioIntDis; + PadConfig.PowerConfig =3D GpioResetPwrGood; + PadConfig.ElectricalConfig =3D GpioTermNone; + PadConfig.LockConfig =3D GpioPadConfigLock; + PadConfig.OtherSettings =3D 00; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B3, &Pa= dConfig); + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B3, &P= latformInfoHob->QATDis); + Status =3D DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B4, &Pa= dConfig); + Status =3D DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B4, &P= latformInfoHob->QATSel); +} + +EFI_STATUS +GetPlatformInfo ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_PLATFORM_INFO *PlatformInfoHob + ) +/** + + GC_TODO: add routine description + + @param PeiServices - GC_TODO: add arg description + @param PlatformInfoHob - GC_TODO: add arg description + + @retval EFI_UNSUPPORTED - GC_TODO: add retval description + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +{ + + + UINT32 BoardId; + UINT32 BoardRev; + EFI_PEI_PCI_CFG2_PPI *PciCfgPpi; + EFI_STATUS Status; + + PciCfgPpi =3D (**PeiServices).PciCfg; + ASSERT (PciCfgPpi !=3D NULL); + + PlatformInfoHob->BoardId =3D TypeNeonCityEPRP; + + // + //Check if BoardId is fixed during build time. + // + BoardId =3D FixedPcdGet8 (PcdBoardId); + if (BoardId !=3D 0) { + PlatformInfoHob->BoardId =3D (UINT8)BoardId; + PlatformInfoHob->TypeRevisionId =3D FixedPcdGet8 (PcdBoardRevId); + DEBUG((DEBUG_INFO, "Board ID =3D %2x Board Rev =3D %x \n", PlatformIn= foHob->BoardId, PlatformInfoHob->TypeRevisionId)); + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "Use GPIO to read Board ID\n")); + + Status =3D GpioGetBoardId (&BoardId); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n")); + return Status; + } + Status =3D GpioGetBoardRevId (&BoardRev); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n")); + return Status; + } + PlatformInfoHob->TypeRevisionId =3D BoardRev; + + switch (BoardId) { + case 0x00: // for Simics + PlatformInfoHob->BoardId =3D TypeWilsonCityRP; + break; + case 0x01: + PlatformInfoHob->BoardId =3D TypeWilsonCityRP; + DEBUG ((DEBUG_INFO, "Board ID =3D TypeWilsonCityRP\n")); + break; + case 0x12: + PlatformInfoHob->BoardId =3D TypeWilsonCityRP; + DEBUG((DEBUG_INFO, "Board ID =3D TypeWilsonCityRP\n")); + break; + case 0x15: + PlatformInfoHob->BoardId =3D TypeWilsonCitySMT; + DEBUG((DEBUG_INFO, "Board ID =3D TypeWilsonCitySMT\n")); + break; + case 0x17: + case 0x18: + PlatformInfoHob->BoardId =3D TypeCooperCityRP; + DEBUG((DEBUG_INFO, "Board ID =3D TypeCooperCityRP\n")); + break; + default: + PlatformInfoHob->BoardId =3D TypePlatformDefault; + DEBUG ((DEBUG_INFO, "Board ID =3D %2X Default set to TypePlatformDef= ault\n",BoardId)); + break; + } + + GatherQATInfo(PlatformInfoHob); + + DEBUG ((DEBUG_INFO, "Board Rev.: %d\n", BoardRev)); + return EFI_SUCCESS; +} + +/** + + This function initializes the board related flag to indicates if + PCH and Lan-On-Motherboard (LOM) devices is supported. + +**/ +VOID +GetPchLanSupportInfo( + IN EFI_PLATFORM_INFO *PlatformInfoHob + ) +{ + PlatformInfoHob->PchData.LomLanSupported =3D 0; +} + +/** + + GC_TODO: add routine description + + @param PeiVariable - GC_TODO: add arg description + @param PlatformInfoHob - GC_TODO: add arg description + + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +EFI_STATUS +EFIAPI +GetIioCommonRcPlatformSetupPolicy( + OUT EFI_PLATFORM_INFO *PlatformInfoHob + ) + { + UINT8 IsocEn; + + CopyMem (&IsocEn, (UINT8 *)PcdGetPtr(PcdSocketCommonRcConfig) + OFFSET_O= F(SOCKET_COMMONRC_CONFIGURATION, IsocEn), sizeof(UINT8)); + + PlatformInfoHob->SysData.IsocEn =3D IsocEn; // ISOC enabled + + return EFI_SUCCESS; +} +/** + + GC_TODO: add routine description + + @param PeiVariable - GC_TODO: add arg description + @param PlatformInfoHob - GC_TODO: add arg description + + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +EFI_STATUS +EFIAPI +GetIioPlatformSetupPolicy( + OUT EFI_PLATFORM_INFO *PlatformInfoHob + ) +{ + return EFI_SUCCESS; +} + + +/** + Platform Type detection. Because the PEI globle variable + is in the flash, it could not change directly.So use + 2 PPIs to distinguish the platform type. + + @param FfsHeader - Pointer to Firmware File System file header. + @param PeiServices - General purpose services available to every PEIM. + + @retval EFI_SUCCESS - Memory initialization completed successfully. + @retval Others - All other error conditions encountered result in= an ASSERT. + +**/ +EFI_STATUS +EFIAPI +PlatformInfoInit ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_PCI_CFG2_PPI *PciCfgPpi; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable; + EFI_PLATFORM_INFO PlatformInfoHob; + EFI_PLATFORM_INFO tempPlatformInfoHob; + UINT8 ChipId; + UINT32 Delay; + UINT32 CpuType; + UINT8 CpuStepping; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + + PciCfgPpi =3D (**PeiServices).PciCfg; + if (PciCfgPpi =3D=3D NULL) { + DEBUG ((EFI_D_ERROR, "\nError! PlatformInfoInit() - PeiServices is a N= ULL Pointer!!!\n")); + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + return EFI_INVALID_PARAMETER; + } + + // + // Locate Variable PPI + // + Status =3D PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NU= LL, &PeiVariable); + + (*PeiServices)->SetMem (&PlatformInfoHob, sizeof (PlatformInfoHob), 0); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // -------------------------------------------------- + // + // Detect the iBMC SIO for CV/CRB Platforms + // 0x2E/0x2F decoding has been enabled in MonoStatusCode PEIM. + // + IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_UNLOCK); + for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); + IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_CHIP_ID_REG); + for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); + ChipId =3D IoRead8 (PILOTIV_SIO_DATA_PORT); + for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); + IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_LOCK); + for (Delay =3D 0; Delay < 40; Delay++) IoRead8 (0x61); + + if (EFI_ERROR (Status)) + { + DEBUG((EFI_D_ERROR, "LocatePpi Error in PlatformInfo.c !\n")); + } + + Status =3D GetIioPlatformSetupPolicy (&PlatformInfoHob); + ASSERT_EFI_ERROR (Status); + Status =3D GetIioCommonRcPlatformSetupPolicy (&PlatformInfoHob); + ASSERT_EFI_ERROR (Status); + + // + // Update PCH Type + // + PlatformInfoHob.PchType =3D DynamicSiLibraryPpi->GetPchSeries (); + PlatformInfoHob.PchSku =3D DynamicSiLibraryPpi->GetPchLpcDeviceId (); + PlatformInfoHob.PchRevision =3D (UINT8) DynamicSiLibraryPpi->PchStepping= (); + PlatformInfoHob.MaxNumOfPchs =3D 1; + Status =3D EFI_SUCCESS; + + if(!EFI_ERROR(Status)) { + Status =3D GetPlatformInfo (PeiServices, &PlatformInfoHob); + if(EFI_ERROR (Status)) { + Status =3D PdrGetPlatformInfo (PeiServices, &tempPlatformInfoHob); + PlatformInfoHob.BoardId =3D tempPlatformInfoHob.BoardId; + PlatformInfoHob.TypeRevisionId =3D tempPlatformInfoHob.TypeRevisio= nId; + if (EFI_ERROR(Status)) { + PlatformInfoHob.BoardId =3D TypePlatformUnknown; + } + } + } else { + PlatformInfoHob.BoardId =3D TypePlatformUnknown; + } + + // + // Update IIO Type + // + PlatformInfoHob.IioRevision =3D 0; + + + // + // Get Subtractive decode enable bit from descriptor + // + + if (DynamicSiLibraryPpi->PchIsGbeRegionValid () =3D=3D FALSE) { + PlatformInfoHob.PchData.GbeRegionInvalid =3D 1; + } else { + PlatformInfoHob.PchData.GbeRegionInvalid =3D 0; + } + GetPchLanSupportInfo (&PlatformInfoHob); + PlatformInfoHob.PchData.GbePciePortNum =3D 0xFF; + PlatformInfoHob.PchData.GbePciePortNum =3D (UINT8) DynamicSiLibraryPpi->= PchGetGbePortNumber (); + PlatformInfoHob.PchData.GbeEnabled =3D DynamicSiLibraryPpi->PchIsGbePre= sent (); + PlatformInfoHob.PchData.PchStepping =3D (UINT8) DynamicSiLibraryPpi->Pch= Stepping (); + + PlatformInfoHob.SysData.SysSioExist =3D (UINT8)IsSioExist(); + + GetCpuInfo (&CpuType, &CpuStepping); + PlatformInfoHob.CpuType =3D CpuType; + PlatformInfoHob.CpuStepping =3D CpuStepping; + + // + // Set default memory topology to DaisyChainTopology. This should be mod= ified in UBA board + // specific file. + // + (*PeiServices)->SetMem (&PlatformInfoHob.MemoryTopology, sizeof (Platfor= mInfoHob.MemoryTopology), DaisyChainTopology); + + // + // Set default memory type connector to DimmConnectorPth. This should be= modified in UBA board + // specific file. + // + (*PeiServices)->SetMem (&PlatformInfoHob.MemoryConnectorType, sizeof (Pl= atformInfoHob.MemoryConnectorType), DimmConnectorPth); + + // + // Build HOB for setup memory information + // + BuildGuidDataHob ( + &gEfiPlatformInfoGuid, + &(PlatformInfoHob), + sizeof (EFI_PLATFORM_INFO) + ); + + Status =3D (**PeiServices).InstallPpi (PeiServices, &mPlatformInfoPpi); + ASSERT_EFI_ERROR (Status); + + // + // Save PlatformInfoHob.BoardId in CMOS + // + IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_LO); + IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)PlatformInfoHob.BoardId); + + IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_HI); + IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)((PlatformInfoHob.PcieRiser2T= ype << 4) + (PlatformInfoHob.PcieRiser1Type))); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/P= latformInfo.inf b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformI= nfo/PlatformInfo.inf index 69d926004d..2eb2d5ab0e 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.inf +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.inf @@ -1,63 +1,66 @@ -## @file -# PlatformInfo PEIM -# -# @copyright -# Copyright 2009 - 2021 Intel Corporation.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PlatformInfo - FILE_GUID =3D 34CC6167-7AE7-403e-8AB2-23837F398A30 - MODULE_TYPE =3D PEIM - VERSION_STRING =3D 1.0 - ENTRY_POINT =3D PlatformInfoInit - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 -# - -[Sources] - PlatformInfo.c - PlatformInfo.h - -[Packages] - MdePkg/MdePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - UefiCpuPkg/UefiCpuPkg.dec - -[LibraryClasses] - PeimEntryPoint - PcdLib - DebugLib - HobLib - IoLib - PlatformHooksLib - PeiServicesLib - -[Pcd] - gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig - -[Guids] - gEfiPlatformInfoGuid - gEfiSetupVariableGuid - -[Ppis] - gPchSpiPpiGuid - gEfiPeiReadOnlyVariable2PpiGuid - gDynamicSiLibraryPpiGuid ## CONSUMES - -[Depex] - gPchSpiPpiGuid AND - gEfiPeiReadOnlyVariable2PpiGuid AND - gDynamicSiLibraryPpiGuid - - - +## @file +# PlatformInfo PEIM +# +# @copyright +# Copyright 2009 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformInfo + FILE_GUID =3D 34CC6167-7AE7-403e-8AB2-23837F398A30 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformInfoInit + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + PlatformInfo.c + PlatformInfo.h + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + PeimEntryPoint + PcdLib + DebugLib + HobLib + IoLib + PlatformHooksLib + PeiServicesLib + +[Pcd] + gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig + gPlatformTokenSpaceGuid.PcdBoardId + gPlatformTokenSpaceGuid.PcdBoardRevId + +[Guids] + gEfiPlatformInfoGuid + gEfiSetupVariableGuid + +[Ppis] + gPchSpiPpiGuid + gEfiPeiReadOnlyVariable2PpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Depex] + gPchSpiPpiGuid AND + gEfiPeiReadOnlyVariable2PpiGuid AND + gDynamicSiLibraryPpiGuid + + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/= Intel/WhitleyOpenBoardPkg/PlatformPkg.dec index 363d4e4059..303baa07cb 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec @@ -1,892 +1,901 @@ -## @file -# Platform Package -# Cross Platform Modules for Tiano -# -# @copyright -# Copyright 2008 - 2021 Intel Corporation.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -## - -[Defines] - DEC_SPECIFICATION =3D 0x00010005 - PACKAGE_NAME =3D PlatformPkg - PACKAGE_GUID =3D 9A29FD32-8C72-4b25-A7C4-767F7A2838EB - PACKAGE_VERSION =3D 0.91 - -[Includes] - Include - Include/Protocol - -#TODO: Move these generated temp files into include. - Uba/BoardInit/Dxe - -[Guids] - gBiosInfoGuid =3D { 0x1b453c67, 0x= cb1a, 0x46ec, { 0x86, 0x4b, 0xe2, 0x24, 0xa6, 0xb7, 0xfe, 0xe8 } } - gClvBootTimeTestExecution =3D { 0x3ff7d152, 0x= ef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } } - gUbaCurrentConfigHobGuid =3D { 0xe4b2025b, 0x= c7db, 0x4e5d, { 0xa6, 0x5e, 0x2b, 0x25, 0x7e, 0xb1, 0x5, 0x8e } } - - gCommonSystemConfigurationGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } } - gEfiSetupVariableGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } } - gEfiSetupVariableDefaultGuid =3D { 0x8d247131, 0x= 385e, 0x491f, { 0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3, 0xa6 } } - gEfiGlobalVariableControlGuid =3D { 0x99a96812, 0x= 4730, 0x4290, { 0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9, 0x3b } } - gMainPkgListGuid =3D { 0x6205c3a4, 0x= 1149, 0x491a, { 0xa6, 0xd6, 0x1e, 0x72, 0x3b, 0x87, 0x83, 0xb1 } } - gAdvancedPkgListGuid =3D { 0xc09c81cb, 0x= 31e9, 0x4de6, { 0xa9, 0xf9, 0x17, 0xa1, 0x44, 0x35, 0x42, 0x45 } } - gTpmPkgListGuid =3D { 0x7da45aa9, 0x= 6dbf, 0x4f1b, { 0xa4, 0x3e, 0x32, 0x87, 0xcb, 0xe5, 0x13, 0x51 } } - gSecurityPkgListGuid =3D { 0x3a885aae, 0x= 3e30, 0x42b9, { 0xa9, 0x76, 0x2f, 0x1f, 0x13, 0xbd, 0x70, 0x15 } } - gBootOptionsPkgListGuid =3D { 0x62197ef0, 0x= 7b7e, 0x11e2, { 0xb9, 0x2a, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 } } - gEfiOcDataGuid =3D { 0x4af92599, 0x= 8e76, 0x4bb4, { 0xbf, 0xd2, 0xf5, 0xa6, 0x6e, 0x30, 0x41, 0xd4 } } - gEfiDprRegsProgrammedGuid =3D { 0x4b844201, 0x= 6fe9, 0x41d1, { 0xb4, 0x6f, 0xdf, 0xfc, 0x34, 0xe4, 0x92, 0xa2 } } - gPlatformModuleTokenSpaceGuid =3D { 0x69d13bf0, 0x= af91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } } - gCpPlatFlashTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } - gPchSetupVariableGuid =3D { 0x4570b7f1, 0x= ade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } } - -# -# UBA_START -# - #OEM SKU - gOemSkuTokenSpaceGuid =3D { 0x9e37d253, 0x= abf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } } - gPlatformKtiEparamUpdateDataGuid =3D { 0x7bc065cf, 0x= afe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } } - gSmbiosTablesTokenSpaceGuid =3D { 0x5e80ad48, 0x= f240, 0x4fe9, { 0x87, 0xef, 0x4b, 0x46, 0xf4, 0xde, 0x78, 0xa0 } } - gPlatformGpioInitDataGuid =3D { 0x9282563e, 0x= ae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } } -# -# UBA_END -# - gReserveMemFlagVariableGuid =3D { 0xb87aa73f, 0x= dcb3, 0x4533, { 0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, 0x40 } } - gEfiOpaSocketMapHobGuid =3D { 0x829d41d2, 0x= 6ca5, 0x485b, { 0xa1, 0xa2, 0xd1, 0xb7, 0x96, 0x27, 0xab, 0xcd } } - gEfiPlatformTxtPolicyDataGuid =3D { 0xa353290b, 0x= 867d, 0x4cd3, { 0xa8, 0x1b, 0x4b, 0x7e, 0x5e, 0x10, 0x0e, 0x16 } } - gEfiSmmPeiSmramMemoryReserveGuid =3D { 0x6dadf1d1, 0x= d4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } } - gSystemBoardInfoConfigDataGuid =3D { 0x68B046F7, 0x= 15A0, 0x4778, { 0xBE, 0xA3, 0x9B, 0xA2, 0xDB, 0xD1, 0x3B, 0x82 } } - - # Fce multi mode support - gPlatformVariableHobGuid =3D { 0x71e6d4bc, 0x= 4837, 0x45f1, { 0xa2, 0xd7, 0x3f, 0x93, 0x08, 0xb1, 0x7e, 0xd7 } } - gDefaultDataFileGuid =3D { 0x1ae42876, 0x= 008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 } } - - gCpPlatIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } - gEfiIpmiFormatFruGuid =3D { 0x3531fdc6, 0x= eae, 0x4cd2, { 0xb0, 0xa6, 0x5f, 0x48, 0xa0, 0xdf, 0xe3, 0x8 } } - gServerCommonIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } - - gServerMgmtPkgListGuid =3D { 0x35dcfcd1, 0x= c14e, 0x45e9, { 0xbe, 0xd3, 0xbb, 0x1, 0x64, 0xf8, 0x80, 0x7b } } - - - ## Include/Guid/CpPlatPkgTokenSpace.h - gCpPlatTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } - gEfiSetupEnterGuid =3D { 0x71202EEE, 0x= 5F53, 0x40d9, { 0xAB, 0x3D, 0x9E, 0x0C, 0x26, 0xD9, 0x66, 0x57 } } - gEfiSetupExitGuid =3D { 0xD6E335EC, 0x= 0336, 0x4CB1, { 0x87, 0xA2, 0xDA, 0x87, 0xD7, 0xE9, 0x99, 0x40 }} - - gPlatformTokenSpaceGuid =3D { 0x07dfa0d2, 0x= 2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } } - -[Ppis] -# -# UBA_START -# - gEfiPeiPlatformTypeWolfPassPpiGuid =3D { 0xd2a92001, 0x= 22ad, 0x43b9, { 0xbe, 0xbc, 0x1b, 0x15, 0x21, 0x00, 0xd8, 0xcc } } - gEfiPeiPlatformTypeNeonCityEPRPPpiGuid =3D { 0xa2e5609e, 0x= 8c2d, 0x42e6, { 0xa2, 0xfc, 0x12, 0xbc, 0x74, 0xbd, 0x43, 0x7f } } - gEfiPeiPlatformTypeTennesseePassPpiGuid =3D { 0xf7b87a79, 0x= a640, 0x4aa5, { 0x8c, 0x1e, 0x45, 0x3f, 0xb2, 0x6e, 0xf3, 0x76 } } - gEfiPeiPlatformTypeNeonCityEPECBPpiGuid =3D { 0x21877e2f, 0x= f86e, 0x4e8a, { 0x9c, 0x9b, 0xd7, 0xb1, 0x52, 0xdd, 0x40, 0xd8 } } - gEfiPeiPlatformTypeOpalCitySTHIPpiGuid =3D { 0xa07b3bdf, 0x= b78a, 0x41ee, { 0xa2, 0x76, 0x55, 0xc2, 0x25, 0xa0, 0x7b, 0x0b } } - gEfiPeiPlatformTypePurleyLBGEPDVPPpiGuid =3D { 0x3c234470, 0x= 69d3, 0x42e1, { 0xb3, 0x23, 0xc8, 0x09, 0x30, 0x0f, 0x39, 0x25 } } - gEfiPeiPlatformTypeCrescentCityPpiGuid =3D { 0x4ad920ef, 0x= 4d6f, 0x4915, { 0x98, 0x2a, 0xdc, 0x16, 0x67, 0x71, 0x31, 0xd5 } } - gEfiPeiPlatformTypeHedtEVPpiGuid =3D { 0x41781f4f, 0x= a3cd, 0x4750, { 0x8a, 0x2c, 0x21, 0x92, 0xb4, 0xdf, 0xe5, 0x2b } } - gEfiPeiPlatformTypeHedtCRBPpiGuid =3D { 0x9bb6e29a, 0x= 2272, 0x426a, { 0xab, 0x77, 0x9b, 0x7f, 0xe5, 0xef, 0xea, 0x84 } } - gEfiPeiPlatformTypeLightningRidgeEXRPPpiGuid =3D { 0xaf2417f4, 0x= 7b7e, 0x4c2e, { 0x94, 0xbb, 0x7a, 0x33, 0x89, 0xa1, 0x57, 0xca } } - gEfiPeiPlatformTypeLightningRidgeEXECB1PpiGuid =3D { 0xf70a4116, 0x= fdf6, 0x45fb, { 0x93, 0xcd, 0x84, 0xcd, 0xdd, 0x73, 0xdf, 0xd4 } } - gEfiPeiPlatformTypeLightningRidgeEXECB2PpiGuid =3D { 0x0c04b0ff, 0x= 227d, 0x479a, { 0x93, 0x5a, 0xf6, 0xe5, 0xa8, 0xb5, 0x19, 0x8c } } - gEfiPeiPlatformTypeLightningRidgeEXECB3PpiGuid =3D { 0x94c0203b, 0x= 54c9, 0x416e, { 0xa6, 0xe0, 0x47, 0xe8, 0xd4, 0x78, 0x69, 0x01 } } - gEfiPeiPlatformTypeLightningRidgeEXECB4PpiGuid =3D { 0x4284a11c, 0x= 18c1, 0x4c10, { 0xb2, 0xd9, 0x58, 0x6a, 0x01, 0x60, 0xa5, 0x23 } } - gEfiPeiPlatformTypeLightningRidgeEX8S1NPpiGuid =3D { 0x4f51c243, 0x= 7cee, 0x4144, { 0x8e, 0xed, 0x23, 0x4a, 0xc2, 0xda, 0xbd, 0x53 } } - gEfiPeiPlatformTypeLightningRidgeEX8S2NPpiGuid =3D { 0x5d9516d3, 0x= bc49, 0x4337, { 0x9f, 0xc7, 0x29, 0xdf, 0x35, 0x26, 0xec, 0x87 } } - gEfiPeiPlatformTypeKyanitePpiGuid =3D { 0xb23ce2c1, 0x= 16a0, 0x4f69, { 0x98, 0x0a, 0x95, 0xc7, 0x72, 0x16, 0xf9, 0xa2 } } - gEfiPeiPlatformTypeNeonCityFPGAPpiGuid =3D { 0x48e796bd, 0x= 4ed3, 0x4755, { 0xa8, 0xca, 0x4c, 0xf4, 0x37, 0x25, 0x82, 0x41 } } - gEfiPeiPlatformTypeOpalCityFPGAPpiGuid =3D { 0xe5434b26, 0x= aedf, 0x43de, { 0x89, 0x35, 0xd1, 0xc4, 0x85, 0xa9, 0x12, 0xb9 } } - gEfiPeiPlatformTypeWilsonCityRPPpiGuid =3D { 0x0629aff2, 0x= 4e23, 0x45c6, { 0x90, 0xc5, 0xb3, 0x21, 0x7b, 0x00, 0x09, 0x23 } } - gEfiPeiPlatformTypeWilsonCityModularPpiGuid =3D { 0x3170ea7b, 0x= 6784, 0x4366, { 0xb4, 0xc6, 0xfe, 0x69, 0x9f, 0x69, 0x42, 0x21 } } - gEfiPlatformTypeIsoscelesPeakPpiGuid =3D { 0xfc7b089f, 0x= 5395, 0x40c0, { 0x9e, 0xfb, 0xca, 0x90, 0x59, 0xe2, 0x7f, 0xea } } - - gPeiIpmiTransportPpiGuid =3D { 0x7bf5fecc, 0x= c5b5, 0x4b25, { 0x81, 0x1b, 0xb4, 0xb5, 0xb, 0x28, 0x79, 0xf7 } } - -# -# UBA_END -# - - gBoardInitGuid =3D { 0xecc07551, 0x= d64c, 0x4c07, { 0xab, 0x95, 0x94, 0x5, 0x66, 0xed, 0x31, 0xf1 } } - gUbaConfigDatabasePpiGuid =3D { 0xc1176733, 0x= 159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73, 0x10 } } - - gPeiSpiSoftStrapsPpiGuid =3D { 0x7F19E716, 0x= 419C, 0x4E79, { 0x8E, 0x37, 0xC2, 0xBD, 0x84, 0xEB, 0x65, 0x28 } } - gUpdatePcdGuid =3D { 0xa08e4c6b, 0x= ff28, 0x4fff, { 0x93, 0x56, 0x78, 0x36, 0x26, 0xc3, 0xe0, 0x38 } } - gPlatformVariableInitPpiGuid =3D { 0x9b1b911b, 0x= 4259, 0x4539, { 0xaf, 0x86, 0xe5, 0xf3, 0x61, 0xca, 0x09, 0x02 } } - gUpdateBootModePpiGuid =3D { 0x927186a0, 0x= a13e, 0x4b53, { 0xad, 0x41, 0xad, 0xd1, 0x65, 0x6f, 0x62, 0x62 } } - - gEfiPeiExStatusCodeHandlerPpiGuid =3D { 0x4e942617, 0x= bbca, 0x4726, { 0x77, 0xb9, 0x49, 0x68, 0x85, 0xf9, 0xc4, 0xf4 } } - - -[Protocols] - gEfiPlatformTypeProtocolGuid =3D { 0x171e9398, 0x= 269c, 0x4081, { 0x90, 0x99, 0x38, 0x44, 0xe2, 0x60, 0x46, 0x6c } } - gUbaConfigDatabaseProtocolGuid =3D { 0xe03e0d46, 0x= 5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77, 0xe2 } } -# -# UBA_START -# - gEfiPlatformTypeNeonCityEPRPProtocolGuid =3D { 0xc0cd2d36, 0x= a81b, 0x450d, { 0xa5, 0x02, 0x37, 0x67, 0xdf, 0xa2, 0x98, 0x26 } } - gEfiPlatformTypeHedtCRBProtocolGuid =3D { 0x2c824f87, 0x= 0f2c, 0x45d7, { 0x81, 0xa6, 0x4f, 0x39, 0xe0, 0x42, 0xbd, 0xdf } } - gEfiPlatformTypeLightningRidgeEXRPProtocolGuid =3D { 0x1b4ae0f8, 0x= ed1f, 0x4fd1, { 0x9b, 0x18, 0xb0, 0x82, 0x29, 0x0f, 0x86, 0xf5 } } - gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid =3D { 0x45b59855, 0x= 500c, 0x443b, { 0xb5, 0x04, 0x9a, 0xb4, 0xca, 0x29, 0xbc, 0x68 } } - gEfiPlatformTypeWilsonCityRPProtocolGuid =3D { 0x8430776f, 0x= bd75, 0x4fc8, { 0xa5, 0x4f, 0x7f, 0x6b, 0xf6, 0x18, 0x9c, 0x13 } } - gEfiPlatformTypeIsoscelesPeakProtocolGuid =3D { 0xcff3f211, 0x= 5d51, 0x4f87, { 0x94, 0xb0, 0x9b, 0x94, 0xf8, 0x4e, 0x8a, 0x48 } } - gEfiPlatformTypeWilsonCityModularProtocolGuid =3D { 0x28e862f4, 0x= a4ed, 0x4acb, { 0x9a, 0x35, 0x36, 0xd0, 0x90, 0x2d, 0xf7, 0x82 } } - - gEfiPlatformTypeWilsonCitySMTProtocolGuid =3D { 0xEE55562D, 0x= 4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } } - gEfiPlatformTypeCooperCityRPProtocolGuid =3D { 0x45c302e1, 0x= 4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } } - -# -# UBA_END -# - - gEfiPciIovPlatformProtocolGuid =3D { 0xf3a4b484, 0x= 9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } } - gEfiWindowsInt10Workaround =3D { 0x387f555, 0x2= 0a8, 0x4fc2, { 0xbb, 0x94, 0xcd, 0x30, 0xda, 0x1b, 0x40, 0x08 } } - gEfiVMDDriverProtocolGuid =3D { 0x5a676ae9, 0x= db23, 0x4a68, { 0xa2, 0x4d, 0xaa, 0x5f, 0xec, 0xd5, 0x74, 0x86 } } - gEfiHfiPcieGen3ProtocolGuid =3D { 0x7b59316e, 0x= e9df, 0x435f, { 0x98, 0xcd, 0x57, 0x26, 0x64, 0x5b, 0xe8, 0x63 } } - gEfiLegacyBiosProtocolGuid =3D { 0xdb9a1e3d, 0x= 45cb, 0x4abb, { 0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d } } - - gEfiIpmiSolStatusProtocolGuid =3D { 0xe790848e, 0x= b6ab, 0x44ab, { 0x84, 0x91, 0xdc, 0xa5, 0xc, 0x39, 0x7, 0xc6 } } - gEfiIpmiTransportProtocolGuid =3D { 0x6bb945e8, 0x= 3743, 0x433e, { 0xb9, 0xe, 0x29, 0xb3, 0xd, 0x5d, 0xc6, 0x30 } } - gSmmIpmiTransportProtocolGuid =3D { 0x8bb070f1, 0x= a8f3, 0x471d, { 0x86, 0x16, 0x77, 0x4b, 0xa3, 0xf4, 0x30, 0xa0 } } - gEfiIpmiBootGuid =3D { 0x5c9b75ec, 0x= 8ec7, 0x45f2, { 0x8f, 0x8f, 0xc1, 0xd8, 0x8f, 0x3b, 0x93, 0x45 } } - gEfiGenericIpmiDriverInstalledGuid =3D { 0x7cdad61a, 0x= 3df8, 0x4425, { 0x96, 0x8c, 0x66, 0x28, 0xc8, 0x35, 0xff, 0xce } } - - gDmaRemapProtocolGuid =3D { 0x4e873773, 0x839= 1, 0x4e47, { 0xb7, 0xf4, 0xca, 0xfb, 0xdc, 0xc4, 0xb2, 0x04 } } - -[PcdsFixedAtBuild] - -#SKX_TODO: add a new GUID, and replace the 'gPlatformTokenSpaceGuid' used = here to it, or move these values to the SocketPkg where the GUID is defined -# Using a GUID defined in another .DEC file is a violation of the= UEFI packaging standards. - - gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E - gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F - gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase|0x00000000|UINT32|0x300000= 1A - gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize|0x00000000|UINT32|0x300000= 1B - gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize|0x00000000|UINT32|0x300= 0001C - gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase|0x00000000|UINT32|0x300= 0001D - gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize|0x00000000|UINT32|0x3000= 001E - gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase|0x00000000|UINT32|0x3000= 001F - gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize|0x00000000|UINT32|0x30000= 020 - gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase|0x00000000|UINT32|0x30000= 021 - gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|0x0000000|UINT32|0x3000= 0027 - - gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize|0x0000000|UINT32|0x30000= 001 - gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|0x0000000|UINT32|0x300= 00004 - gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|0x000000= 0|UINT32|0x30000006 - gPlatformModuleTokenSpaceGuid.PcdFlashFreeSpaceOffset|0x0000000|UINT32|0= x30000008 - - gPlatformTokenSpaceGuid.PcdSupportLegacyStack|TRUE|BOOLEAN|0x30000030 - gPlatformTokenSpaceGuid.PcdMaxOptionRomNumber|0x4|UINT8|0x30000031 - - gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032 - - # Choose the default serial debug message level when CMOS is bad; in the= later BIOS phase, the setup default is applied - # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max - gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033 - gPlatformTokenSpaceGuid.PcdWilsonPointSvidVrP1V8|0x05|UINT8|0x30000000 = #BIT4 =3D> SVID BUS 0, BIT3-BIT0 =3D> VR ADDRESS - gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8|0x15|UINT8|0x30000002 - gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna|0x16|UINT8|0x30000003 - - # PCD for failsafe variable ffs in other FV rather than bb1 - # by default, FCE will insert into SECPEI, and you don't need to set the= se two PCD if bb1(secpei)is used - gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize|0|UINT32|0x30000034 - gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase|0|UINT32|0x30000035 - - gPlatformTokenSpaceGuid.PcdSetupVariableGuid|{ 0x43,0xd6,0x87,0xec,0xa4,= 0xeb, 0xb5,0x4b, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9}|VOID*|0x30= 000036 - - # - # These need to move to MinPlatformPkg.dec - # - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize|0|UINT32|0xF000= 00A9 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase|0|UINT32|0xF000= 00AA - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|0|UINT32|0xF0= 0000AB - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize|0|UINT32|0xF00000AC - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase|0|UINT32|0xF00000AD - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|0|UINT32|0xF00000AE - - #IIO configuration data for socket 3 will be used for sockets 4..7 - gPlatformTokenSpaceGuid.PcdSocketCopy|FALSE|BOOLEAN|0xF00000AF - - gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionSize|0x01000000|UINT32|0xF00= 000B0 - gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionBase|0xFF900000|UINT32|0xF00= 000B1 - - #If True, extend PCR7 when VT-d disabled. - gPlatformTokenSpaceGuid.PcdConditionallyExtendPcr7|FALSE|BOOLEAN|0xE0000= 045 - -[PcdsFixedAtBuild, PcdsPatchableInModule] - gPlatformTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x0= 5, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x400= 00004 - ## Specify memory size with page number for a pre-allocated reserved mem= ory to be used - # by PEI in S3 phase. The default size 32K. When changing the value mak= e sure the memory size - # is large enough to meet PEI requirement in the S3 phase. - # @Prompt Reserved S3 Boot ACPI Memory Size - gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|= 0x90010039 - gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012 - gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013 - gPlatformModuleTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015 - gPlatformModuleTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016 - gPlatformModuleTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0= x90000017 - gPlatformModuleTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000= 018 - - - gPlatformModuleTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021 - gPlatformModuleTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022 - gPlatformModuleTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023 - gPlatformModuleTokenSpaceGuid.PcdHpetTimerBlockId|0x8086A201|UINT32|0x90= 000024 - - gPlatformModuleTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x900= 00025 - gPlatformModuleTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900000= 26 - gPlatformModuleTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027 - gPlatformModuleTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x90= 00000B - gPlatformModuleTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x90000= 00D - gPlatformModuleTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014 - gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006 - -[PcdsDynamicEx] - -# -# PAL -# - gPlatformTokenSpaceGuid.PcdOemSkuPcieSlotOpromBitMap|0xFF|UINT32|0x00000= 008 - -#SKX_TODO: gPlatformTokenSpaceGuid are not correct GUIDs to use here, use = local GUID... - gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|FALSE|BOOLEAN|0x= 00000048 - - ## This value is used to save memory address of MRC data structure. - gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041 - gPlatformTokenSpaceGuid.PcdHalfWidth|FALSE|BOOLEAN|0x30000042 - -# -# IMR0 programming values -# - gPlatformTokenSpaceGuid.PcdImr0Enable|FALSE|BOOLEAN|0xA5000000 - gPlatformTokenSpaceGuid.PcdImr0Base|0x0|UINT64|0xA5000001 - gPlatformTokenSpaceGuid.PcdImr0Mask|0x0|UINT64|0xA5000002 - gPlatformTokenSpaceGuid.PcdImr0Rac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000003 - gPlatformTokenSpaceGuid.PcdImr0Wac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000004 - -# -# IMR3 programming values -# - gPlatformTokenSpaceGuid.PcdImr3Enable|FALSE|BOOLEAN|0xA5000022 - -# -# Server common Hot Key binding -# - # EFI Scan codes - # SCAN_F2 0x000C - # SCAN_F6 0x0010 - # SCAN_F7 0x0011 - gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x00|UINT16|0x00000009 - gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x00|UINT16|0x0000000A - - - gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, = 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x= 0000000B - -#Indicate whether to perform LT Config lock -# The PCD can be set to false when there is the debug request -# TRUE - Force the LT config lock -# FALSE - Allow the LT config unlock for debug - gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE|BOOLEAN|0x30000= 00e - -#Indicate whether LTSX enabled -# TRUE - Intel (R) TXT feature enabled on the platform -# FALSE - Disable Intel(R) TXT feature on the platform - gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x30= 00000f - - # - # SMBIOS Type 0 - BIOS Information - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVendor|"TBD"|VOID*|0x5B00= 0000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVersion|"TBD"|VOID*|0x5B0= 00001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosReleaseDate|"TBD"|VOID*|0= x5B000002 - - # - # SMBIOS Type 1 - System Information - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemManufacturer|"TBD"|VOID= *|0x5B010000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemProductName|"TBD"|VOID*= |0x5B010001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemVersion|"TBD"|VOID*|0x5= B010002 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSerialNumber|"TBD"|VOID= *|0x5B010003 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSkuNumber|"TBD"|VOID*|0= x5B010004 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemFamily|"TBD"|VOID*|0x5B= 010005 - - # - # SMBIOS Type 2 - Base Board (or Module) Information - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardManufacturer|"TBD"|V= OID*|0x5B020000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardProductName|"TBD"|VO= ID*|0x5B020001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardVersion|"TBD"|VOID*|= 0x5B020002 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardSerialNumber|"TBD"|V= OID*|0x5B020003 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardAssetTag|"TBD"|VOID*= |0x5B020004 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardLocationInChassis|"T= BD"|VOID*|0x5B020005 - - # - # SMBIOS Type 3 - System Enclosure or Chassis Information - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisManufacturer|"TBD"|VOI= D*|0x5B030000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisVersion|"TBD"|VOID*|0x= 5B030001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSerialNumber|"TBD"|VOI= D*|0x5B030002 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisAssetTag|"TBD"|VOID*|0= x5B030003 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSkuNumber|"TBD"|VOID*|= 0x5B030004 - - # - # SMBIOS Type 11 - OEM Strings - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesOemString1|"TBD"|VOID*|0x5B0B= 0001 - - # - # SMBIOS Type 12 - System Configuration Options - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSysConfigOption1|"TBD"|VOID*|= 0x5B0C0001 - - # - # SMBIOS Type 14 - Group Associations - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTableType|0xDD|UINT8|0x5B0D0001 - - # - # SMBIOS Type 17 - Memory Device - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesMemorySerialNumberFormat|0x00= |UINT8|0x5B110000 - - # - # SMBIOS Type 27 - Cooling Device - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesCoolingDeviceDescription|"TBD= "|VOID*|0x5B1B0000 - - # - # SMBIOS Type 28 - Temperature Probe - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesTemperatureProbeDescription|"= TBD"|VOID*|0x5B1C0000 - - # - # SMBIOS Type 34 - Management Device - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceDescription|"= TBD"|VOID*|0x5B220000 - - # - # SMBIOS Type 35 - Management Device Component - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceComponentDesc= ription|"TBD"|VOID*|0x5B230000 - - # - # SMBIOS Type 39 - System Power Supply - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyLocation|"TB= D"|VOID*|0x5B270000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyDeviceName|"= TBD"|VOID*|0x5B270001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyManufacturer= |"TBD"|VOID*|0x5B270002 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplySerialNumber= |"TBD"|VOID*|0x5B270003 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyAssetTagNumb= er|"TBD"|VOID*|0x5B270004 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyModelPartNum= ber|"TBD"|VOID*|0x5B270005 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyRevisionLeve= l|"TBD"|VOID*|0x5B270006 - -[PcdsFeatureFlag] - gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00= 000020 - - ## - ## High Speed UART - ## - gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE|BOOLEAN|0x000= 0002C - -[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] - ## MemoryCheck value for checking memory before boot OS. - # To save the boot performance, the default MemoryCheck is set to 0. - gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|0|UINT8|0x40000005 - - - ## following PCDs should remove if CORE accept the fix - gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x0|UINT32|4 - - ## Vendor ID and Device ID of device producing onboard video - gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0|UINT16|0x00000013 - gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0|UINT16|0x00000014 - gPlatformModuleTokenSpaceGuid.PcdPlatformMemoryCheckLevel|0|UINT32|0x300= 00009 - ## This PCD is to control which device is the potential trusted console = input device.

- # For example:
- # USB Short Form: UsbHID(0xFFFF,0xFFFF,0x1,0x1)
- # //Header VendorId ProductId Class SubClass P= rotocol
- # {0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0= x01,
- # //Header
- # 0x7F, 0xFF, 0x04, 0x00}
- gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x03, 0x= 0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04,= 0x00}|VOID*|0x300000A - - ## This PCD is to control which device is the potential trusted console = output device.

- # For example:
- # Integrated Graphic: PciRoot(0x0)/Pci(0x2,0x0)
- # //Header HID UID
- # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00= , 0x00,
- # //Header Func Dev
- # 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, - # //Header
- # 0x7F, 0xFF, 0x04, 0x00}
- gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0= x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01= , 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000C - - - gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16= |0x00010035 - gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16= |0x00010036 - gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x1804|UINT= 16|0x0001037 - gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0x0000|UINT= 16|0x00010038 - gPlatformModuleTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x1850|UINT1= 6|0x00010039 - gPlatformModuleTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x1808|UINT16|0= x0001003A - gPlatformModuleTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x1880|UINT16|0x00= 01003B - gPlatformModuleTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x00= 01003C - -# -# UBA_START -# -[PcdsDynamicEx] - -# -#Board Definitions -# -#Integer for BoardID, must match the SKU number and be unique. - gOemSkuTokenSpaceGuid.PcdOemSkuBoardID|0x0|UINT16|0x00000000 -#Integer for BoardFamily, must be unique - gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily|0x0|UINT16|0x00000001 -# Zero terminated unicode string to ID family - gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName|L"DEFAULT = "|VOID*|0x0000002 -# Zero terminated unicode string to Board Name - gOemSkuTokenSpaceGuid.PcdOemSkuBoardName|L"DEFAULT = "|VOID*|0x00000003 -# Number of Sockets on Board. - gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount|0x0|UINT32|0x00000004 - -# Number of DIMM slots per channel for each Socket - gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel|0x0|UINT32|0x00000005 - gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel|0x0|UINT32|0x00000006 - gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout|FALSE|BOOLEAN|0x00000007 - gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008 - - gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009 -# Form factor is MemoryFormFactorDimm by default -# MemoryFormFactorOther =3D 0x01 -# MemoryFormFactorUnknown =3D 0x02 -# MemoryFormFactorSimm =3D 0x03 -# MemoryFormFactorSip =3D 0x04 -# MemoryFormFactorChip =3D 0x05 -# MemoryFormFactorDip =3D 0x06 -# MemoryFormFactorZip =3D 0x07 -# MemoryFormFactorProprietaryCard =3D 0x08 -# MemoryFormFactorDimm =3D 0x09 -# MemoryFormFactorTsop =3D 0x0A -# MemoryFormFactorRowOfChips =3D 0x0B -# MemoryFormFactorRimm =3D 0x0C -# MemoryFormFactorSodimm =3D 0x0D -# MemoryFormFactorSrimm =3D 0x0E -# MemoryFormFactorFbDimm =3D 0x0F -# MemoryFormFactorDie =3D 0x10 - gOemSkuTokenSpaceGuid.PcdOemSkuMemDevFormFactor|0x09|UINT8|0x10000010 - -# -# USB -# -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00|0x0|UINT16|0x000000= 10 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01|0x0|UINT16|0x000000= 11 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02|0x0|UINT16|0x000000= 12 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03|0x0|UINT16|0x000000= 13 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04|0x0|UINT16|0x000000= 14 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05|0x0|UINT16|0x000000= 15 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06|0x0|UINT16|0x000000= 16 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07|0x0|UINT16|0x000000= 17 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08|0x0|UINT16|0x000000= 18 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09|0x0|UINT16|0x000000= 19 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10|0x0|UINT16|0x000000= 1A -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11|0x0|UINT16|0x000000= 1B -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12|0x0|UINT16|0x000000= 1C -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13|0x0|UINT16|0x000000= 1D - -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00|0x0|UINT16|0x0000002= 0 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01|0x0|UINT16|0x0000002= 1 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02|0x0|UINT16|0x0000002= 2 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03|0x0|UINT16|0x0000002= 3 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04|0x0|UINT16|0x0000002= 4 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05|0x0|UINT16|0x0000002= 5 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06|0x0|UINT16|0x0000002= 6 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07|0x0|UINT16|0x0000002= 7 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08|0x0|UINT16|0x0000002= 8 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09|0x0|UINT16|0x0000002= 9 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10|0x0|UINT16|0x0000002= A -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11|0x0|UINT16|0x0000002= B -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12|0x0|UINT16|0x0000002= C -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13|0x0|UINT16|0x0000002= D - -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00|0x0|UINT16|0x00000= 100 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01|0x0|UINT16|0x00000= 101 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02|0x0|UINT16|0x00000= 102 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03|0x0|UINT16|0x00000= 103 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04|0x0|UINT16|0x00000= 104 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05|0x0|UINT16|0x00000= 105 - -# -# ACPI items -# -# Acpi Name, MUST be 8 chars long - gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName|"DEFAULT "|VOID*|0x000000= 30 - gOemSkuTokenSpaceGuid.PcdOemTableIdXhci|"DEFAULT "|VOID*|0x000000= 31 -# -# Misc. -# - - gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag|0x0|UINT8|0x00000039 - gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed|0x0|UINT16|0x00000040 - -# -# GPIO -# - - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL|0xFF3DB93D|UINT32|0x000= 00050 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL|0x0382F03F|UINT32|0x00= 000051 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL|0xFFFFF30F|UINT32|0x00= 000052 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL|0x91E3EFFF|UINT32|0x0000= 0053 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL|0xFFFD0FF3|UINT32|0x000= 00054 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL|0xFFFFFDF0|UINT32|0x000= 00055 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL|0x661C1000|UINT32|0x0000005= 6 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL|0x0002F004|UINT32|0x000000= 57 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL|0x0000020D|UINT32|0x000000= 58 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL|0x00000000|UINT32|0x0000005= 9 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL|0x00000000|UINT32|0x00000= 05a - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE|0x00000000|UINT32|0x0000= 005c - -# -# SATA registers -# - - gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32|0x99990000|UINT32|0x0000005b - -# -# Clock generator settings -# - - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00|0xFF|UINT8|0x00000060 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01|0x9E|UINT8|0x00000061 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02|0x3F|UINT8|0x00000062 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03|0x00|UINT8|0x00000063 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04|0x00|UINT8|0x00000064 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05|0x0F|UINT8|0x00000065 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06|0x08|UINT8|0x00000066 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07|0x11|UINT8|0x00000067 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08|0x0A|UINT8|0x00000068 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09|0x17|UINT8|0x00000069 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10|0xFF|UINT8|0x0000006a - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11|0xFE|UINT8|0x0000006b - gOemSkuTokenSpaceGuid.PcdOemSkuClockGeneratorAddress|0xD2|UINT8|0x000000= 6c - - gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName|L"DEFAULT = "|VOID*|0x00000201 - gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize|0x0|UINT32|0x00000202 - gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag|0x0|UINT32|0x00000203 - -# -# If PcdOemSkuAssertPostGPIO value is 0xFFFFFFFF, current platform don't s= et related GPIO. -# - gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO|0x01010014|UINT32|0x000002= 04 - gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue|0x0|UINT32|0x00000205 - - gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber|0xFF|UINT8|0x00000206 - gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207 -# -# UBA_END -# - - gCpPlatIpmiTokenSpaceGuid.PcdIpmiIoBaseAddress|0xCA2|UINT16|0x10000022 - gCpPlatIpmiTokenSpaceGuid.PcdIpmiSmmIoBaseAddress|0xCA4|UINT16|0x1000002= 3 - gCpPlatIpmiTokenSpaceGuid.PcdSioMailboxBaseAddress|0x600|UINT32|0x100000= 21 - gCpPlatIpmiTokenSpaceGuid.PcdFRB2EnabledFlag|TRUE|BOOLEAN|0x10000030 - gCpPlatIpmiTokenSpaceGuid.PcdIpmiBmcReadyDelayTimer|0|UINT8|0x00000208 - - -## This PCD replaces the original one gEfiIntelFrameworkModulePkgTokenSpac= eGuid.PcdBootState - gPlatformModuleTokenSpaceGuid.PcdBootState|TRUE|BOOLEAN|0x300000AC - gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000208 - -[PcdsDynamicEx] - gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|FALSE|BOOLEAN|0x10000026 - gCpPlatTokenSpaceGuid.PcdUefiOptimizedBootEx|FALSE|BOOLEAN|0x10000024 - -[PcdsFixedAtBuild] -# -# Flash map related PCD. -# -# Note: most values here are overridden in the .fdf file -# -# -# Note: FlashNv PCD naming conventions are as follows: -# -# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec -# PcdFlash*Size is a hex count of the length of the FD or FV -# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' -# -# Also all values will have a PCD assigned so that they can be used = in the system, and -# the FlashMap edit tool can be used to change the values here, with= out effecting the code. -# This requires all code to only use the PCD tokens to recover the v= alues. -# - - - -# PCD's that are for the whole SPI part - - -#Block size of SPI -gCpPlatFlashTokenSpaceGuid.PcdFlashBlockSize |0x00010= 000 |UINT32|0x50000102 - - -#AJW rename this to be more in keeping with the function -gCpPlatFlashTokenSpaceGuid.PcdFlashAreaBase |0xfff00= 000 |UINT32|0x50000105 - - - -# for PeiSec FD - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize |0x00100= 000 |UINT32|0x50000221 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase |0x00000= 000 |UINT32|0x50000222 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase |0x00000= 000 |UINT32|0x50000260 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize |0x00040= 000 |UINT32|0x50000261 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase |0x00000= 000 |UINT32|0x50000211 -gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize |0x00100= 000 |UINT32|0x50000212 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize |0x001000= 00 |UINT32|0x50000233 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase |0x000000= 00 |UINT32|0x50000234 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset |0x000000= 00 |UINT32|0x50000235 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize |0x00100= 000 |UINT32|0x50000241 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase |0x00000= 000 |UINT32|0x50000242 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize |0x00100= 000 |UINT32|0x50000251 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase |0x00000= 000 |UINT32|0x50000252 - - -# for Main FD - - -gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase |0xfff0= 0000 |UINT32|0x50000300 -gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize |0x0040= 0000 |UINT32|0x50000301 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainSize |0x0020= 0000 |UINT32|0x50000311 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainBase |0xFF82= 0000 |UINT32|0x50000312 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize |0x0020= 0000 |UINT32|0x50000341 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase |0xFF82= 0000 |UINT32|0x50000342 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset |0xFF82= 0000 |UINT32|0x50000343 - - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize |0x0020= 0000 |UINT32|0x50000351 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase |0xFF82= 0000 |UINT32|0x50000352 - -## This PCD specifies the size of the physical device containing the BIOS,= SMBIOS will use it. - -gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionBase |0xFF80= 0000 |UINT32|0x50000001 -gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionSize |0x0000= 0000 |UINT32|0x50000002 - -[PcdsFeatureFlag.common] - -## -## Those PCDs are used to control build process. -## - - # - # SV Tools - # - gPlatformFeatureTokenSpaceGuid.PcdXmlCliEnable|TRUE|BOOLEAN|0xE0000000 - gPlatformFeatureTokenSpaceGuid.PcdSvBiosEnable|TRUE|BOOLEAN|0xE000002E - # - # - # - -[PcdsDynamicEx] - ### Sample implementation...No real data. Use this PCD to override a pla= tform with Interposer ### - gPlatformTokenSpaceGuid.PcdMemInterposerMap|{0}|INTERPOSER_MAP|0x8000001= 5 { - - Guid/PlatformInfo.h - - WhitleyOpenBoardPkg/PlatformPkg.dec - } - # Interposer A MC 0 mapped to original MC1 - # Enum values for Interposer - # Interposer A =3D> 1 - # Interposer B =3D> 2 - # Interposer Unknown =3D> 0 - gPlatformTokenSpaceGuid.PcdMemInterposerMap.Interposer[1].MappedMcId[0] = |1 - -### Sample implementation...No real data. Use this PCD to override a platf= orm with Interposer ### - -[Guids] - gStructPcdTokenSpaceGuid =3D {0x3f1406f4, 0x2b, 0x487a, {0x8b, 0x69, 0x7= 4, 0x29, 0x1b, 0x36, 0x16, 0xf4}} - -[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] -gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig|{0}|EMULATION_DFX_CONFIGURA= TION|0XFCD0000C{ - - Include/Guid/EmulationDfxVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec -} -gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|{0}|FPGA_SOCKET_CONFIGURATION= |0XFCD00010{ - - Include/Guid/FpgaSocketVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec -} -gStructPcdTokenSpaceGuid.PcdIeRcConfiguration|{0}|IE_RC_CONFIGURATION|0XFC= D00004{ - - Include/Guid/IeRcVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdMeRcConfiguration|{0}|ME_RC_CONFIGURATION|0XFC= D0000B{ - - Include/Guid/MeRcVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig|{0}|MEM_BOOT_HEALTH_CONFIG= |0XFCD00002{ - - Include/Guid/MemBootHealthGuid.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdPchSetup|{0}|PCH_SETUP|0XFCD00007{ - - Include/PchSetupVariableLbg.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSetup|{0}|SYSTEM_CONFIGURATION|0XFCD0000F{ - - Include/Guid/SetupVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|{0}|SOCKET_COMMONRC_CONFI= GURATION|0XFCD00001{ - - Include/Guid/SocketCommonRcVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketIioConfig|{0}|SOCKET_IIO_CONFIGURATION|0= XFCD00006{ - - Include/Guid/SocketIioVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|{0}|SOCKET_MEMORY_CONFIGURA= TION|0XFCD0000D{ - - Include/Guid/SocketMemoryVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|{0}|SOCKET_MP_LINK_CONFIGUR= ATION|0XFCD00008{ - - Include/Guid/SocketMpLinkVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|{0}|SOCKET_POWERMA= NAGEMENT_CONFIGURATION|0XFCD00005{ - - Include/Guid/SocketPowermanagementVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|{0}|SOCKET_PROCESSOR= CORE_CONFIGURATION|0XFCD00003{ - - Include/Guid/SocketProcessorCoreVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSvConfiguration|{0}|SV_CONFIGURATION|0XFCD0000= 9{ - - Include/Guid/SetupVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION|{0}|TCG2_CONFIGURATION|0XFC= D0000A{ - - Include/Tcg2ConfigNvData.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - SecurityPkg/SecurityPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec -} -gStructPcdTokenSpaceGuid.PcdTCG2_VERSION|{0}|TCG2_VERSION|0XFCD0000E{ - - Include/Tcg2ConfigNvData.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - SecurityPkg/SecurityPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec -} -[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] - gOemSkuTokenSpaceGuid.PcdTurboPowerLimitLock|0x01|UINT8|0x00000209 - gOemSkuTokenSpaceGuid.PcdNumberOfCoresToDisable|0x0|UINT16|0x0000020A - -[LibraryClasses] - ServerManagementTimeStampLib|Include/Library/ServerManagementTimeStampLi= b.inf +## @file +# Platform Package +# Cross Platform Modules for Tiano +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D PlatformPkg + PACKAGE_GUID =3D 9A29FD32-8C72-4b25-A7C4-767F7A2838EB + PACKAGE_VERSION =3D 0.91 + +[Includes] + Include + Include/Protocol + +#TODO: Move these generated temp files into include. + Uba/BoardInit/Dxe + +[Guids] + gBiosInfoGuid =3D { 0x1b453c67, 0x= cb1a, 0x46ec, { 0x86, 0x4b, 0xe2, 0x24, 0xa6, 0xb7, 0xfe, 0xe8 } } + gClvBootTimeTestExecution =3D { 0x3ff7d152, 0x= ef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } } + gUbaCurrentConfigHobGuid =3D { 0xe4b2025b, 0x= c7db, 0x4e5d, { 0xa6, 0x5e, 0x2b, 0x25, 0x7e, 0xb1, 0x5, 0x8e } } + + gCommonSystemConfigurationGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } } + gEfiSetupVariableGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } } + gEfiSetupVariableDefaultGuid =3D { 0x8d247131, 0x= 385e, 0x491f, { 0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3, 0xa6 } } + gEfiGlobalVariableControlGuid =3D { 0x99a96812, 0x= 4730, 0x4290, { 0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9, 0x3b } } + gMainPkgListGuid =3D { 0x6205c3a4, 0x= 1149, 0x491a, { 0xa6, 0xd6, 0x1e, 0x72, 0x3b, 0x87, 0x83, 0xb1 } } + gAdvancedPkgListGuid =3D { 0xc09c81cb, 0x= 31e9, 0x4de6, { 0xa9, 0xf9, 0x17, 0xa1, 0x44, 0x35, 0x42, 0x45 } } + gTpmPkgListGuid =3D { 0x7da45aa9, 0x= 6dbf, 0x4f1b, { 0xa4, 0x3e, 0x32, 0x87, 0xcb, 0xe5, 0x13, 0x51 } } + gSecurityPkgListGuid =3D { 0x3a885aae, 0x= 3e30, 0x42b9, { 0xa9, 0x76, 0x2f, 0x1f, 0x13, 0xbd, 0x70, 0x15 } } + gBootOptionsPkgListGuid =3D { 0x62197ef0, 0x= 7b7e, 0x11e2, { 0xb9, 0x2a, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 } } + gEfiOcDataGuid =3D { 0x4af92599, 0x= 8e76, 0x4bb4, { 0xbf, 0xd2, 0xf5, 0xa6, 0x6e, 0x30, 0x41, 0xd4 } } + gEfiDprRegsProgrammedGuid =3D { 0x4b844201, 0x= 6fe9, 0x41d1, { 0xb4, 0x6f, 0xdf, 0xfc, 0x34, 0xe4, 0x92, 0xa2 } } + gPlatformModuleTokenSpaceGuid =3D { 0x69d13bf0, 0x= af91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } } + gCpPlatFlashTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } + gPchSetupVariableGuid =3D { 0x4570b7f1, 0x= ade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } } + +# +# UBA_START +# + #OEM SKU + gOemSkuTokenSpaceGuid =3D { 0x9e37d253, 0x= abf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } } + gPlatformKtiEparamUpdateDataGuid =3D { 0x7bc065cf, 0x= afe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } } + gSmbiosTablesTokenSpaceGuid =3D { 0x5e80ad48, 0x= f240, 0x4fe9, { 0x87, 0xef, 0x4b, 0x46, 0xf4, 0xde, 0x78, 0xa0 } } + gPlatformGpioInitDataGuid =3D { 0x9282563e, 0x= ae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } } +# +# UBA_END +# + gReserveMemFlagVariableGuid =3D { 0xb87aa73f, 0x= dcb3, 0x4533, { 0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, 0x40 } } + gEfiOpaSocketMapHobGuid =3D { 0x829d41d2, 0x= 6ca5, 0x485b, { 0xa1, 0xa2, 0xd1, 0xb7, 0x96, 0x27, 0xab, 0xcd } } + gEfiPlatformTxtPolicyDataGuid =3D { 0xa353290b, 0x= 867d, 0x4cd3, { 0xa8, 0x1b, 0x4b, 0x7e, 0x5e, 0x10, 0x0e, 0x16 } } + gEfiSmmPeiSmramMemoryReserveGuid =3D { 0x6dadf1d1, 0x= d4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } } + gSystemBoardInfoConfigDataGuid =3D { 0x68B046F7, 0x= 15A0, 0x4778, { 0xBE, 0xA3, 0x9B, 0xA2, 0xDB, 0xD1, 0x3B, 0x82 } } + + # Fce multi mode support + gPlatformVariableHobGuid =3D { 0x71e6d4bc, 0x= 4837, 0x45f1, { 0xa2, 0xd7, 0x3f, 0x93, 0x08, 0xb1, 0x7e, 0xd7 } } + gDefaultDataFileGuid =3D { 0x1ae42876, 0x= 008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 } } + + gCpPlatIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } + gEfiIpmiFormatFruGuid =3D { 0x3531fdc6, 0x= eae, 0x4cd2, { 0xb0, 0xa6, 0x5f, 0x48, 0xa0, 0xdf, 0xe3, 0x8 } } + gServerCommonIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } + + gServerMgmtPkgListGuid =3D { 0x35dcfcd1, 0x= c14e, 0x45e9, { 0xbe, 0xd3, 0xbb, 0x1, 0x64, 0xf8, 0x80, 0x7b } } + + + ## Include/Guid/CpPlatPkgTokenSpace.h + gCpPlatTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } + gEfiSetupEnterGuid =3D { 0x71202EEE, 0x= 5F53, 0x40d9, { 0xAB, 0x3D, 0x9E, 0x0C, 0x26, 0xD9, 0x66, 0x57 } } + gEfiSetupExitGuid =3D { 0xD6E335EC, 0x= 0336, 0x4CB1, { 0x87, 0xA2, 0xDA, 0x87, 0xD7, 0xE9, 0x99, 0x40 }} + + gPlatformTokenSpaceGuid =3D { 0x07dfa0d2, 0x= 2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } } + +[Ppis] +# +# UBA_START +# + gEfiPeiPlatformTypeWolfPassPpiGuid =3D { 0xd2a92001, 0x= 22ad, 0x43b9, { 0xbe, 0xbc, 0x1b, 0x15, 0x21, 0x00, 0xd8, 0xcc } } + gEfiPeiPlatformTypeNeonCityEPRPPpiGuid =3D { 0xa2e5609e, 0x= 8c2d, 0x42e6, { 0xa2, 0xfc, 0x12, 0xbc, 0x74, 0xbd, 0x43, 0x7f } } + gEfiPeiPlatformTypeTennesseePassPpiGuid =3D { 0xf7b87a79, 0x= a640, 0x4aa5, { 0x8c, 0x1e, 0x45, 0x3f, 0xb2, 0x6e, 0xf3, 0x76 } } + gEfiPeiPlatformTypeNeonCityEPECBPpiGuid =3D { 0x21877e2f, 0x= f86e, 0x4e8a, { 0x9c, 0x9b, 0xd7, 0xb1, 0x52, 0xdd, 0x40, 0xd8 } } + gEfiPeiPlatformTypeOpalCitySTHIPpiGuid =3D { 0xa07b3bdf, 0x= b78a, 0x41ee, { 0xa2, 0x76, 0x55, 0xc2, 0x25, 0xa0, 0x7b, 0x0b } } + gEfiPeiPlatformTypePurleyLBGEPDVPPpiGuid =3D { 0x3c234470, 0x= 69d3, 0x42e1, { 0xb3, 0x23, 0xc8, 0x09, 0x30, 0x0f, 0x39, 0x25 } } + gEfiPeiPlatformTypeCrescentCityPpiGuid =3D { 0x4ad920ef, 0x= 4d6f, 0x4915, { 0x98, 0x2a, 0xdc, 0x16, 0x67, 0x71, 0x31, 0xd5 } } + gEfiPeiPlatformTypeHedtEVPpiGuid =3D { 0x41781f4f, 0x= a3cd, 0x4750, { 0x8a, 0x2c, 0x21, 0x92, 0xb4, 0xdf, 0xe5, 0x2b } } + gEfiPeiPlatformTypeHedtCRBPpiGuid =3D { 0x9bb6e29a, 0x= 2272, 0x426a, { 0xab, 0x77, 0x9b, 0x7f, 0xe5, 0xef, 0xea, 0x84 } } + gEfiPeiPlatformTypeLightningRidgeEXRPPpiGuid =3D { 0xaf2417f4, 0x= 7b7e, 0x4c2e, { 0x94, 0xbb, 0x7a, 0x33, 0x89, 0xa1, 0x57, 0xca } } + gEfiPeiPlatformTypeLightningRidgeEXECB1PpiGuid =3D { 0xf70a4116, 0x= fdf6, 0x45fb, { 0x93, 0xcd, 0x84, 0xcd, 0xdd, 0x73, 0xdf, 0xd4 } } + gEfiPeiPlatformTypeLightningRidgeEXECB2PpiGuid =3D { 0x0c04b0ff, 0x= 227d, 0x479a, { 0x93, 0x5a, 0xf6, 0xe5, 0xa8, 0xb5, 0x19, 0x8c } } + gEfiPeiPlatformTypeLightningRidgeEXECB3PpiGuid =3D { 0x94c0203b, 0x= 54c9, 0x416e, { 0xa6, 0xe0, 0x47, 0xe8, 0xd4, 0x78, 0x69, 0x01 } } + gEfiPeiPlatformTypeLightningRidgeEXECB4PpiGuid =3D { 0x4284a11c, 0x= 18c1, 0x4c10, { 0xb2, 0xd9, 0x58, 0x6a, 0x01, 0x60, 0xa5, 0x23 } } + gEfiPeiPlatformTypeLightningRidgeEX8S1NPpiGuid =3D { 0x4f51c243, 0x= 7cee, 0x4144, { 0x8e, 0xed, 0x23, 0x4a, 0xc2, 0xda, 0xbd, 0x53 } } + gEfiPeiPlatformTypeLightningRidgeEX8S2NPpiGuid =3D { 0x5d9516d3, 0x= bc49, 0x4337, { 0x9f, 0xc7, 0x29, 0xdf, 0x35, 0x26, 0xec, 0x87 } } + gEfiPeiPlatformTypeKyanitePpiGuid =3D { 0xb23ce2c1, 0x= 16a0, 0x4f69, { 0x98, 0x0a, 0x95, 0xc7, 0x72, 0x16, 0xf9, 0xa2 } } + gEfiPeiPlatformTypeNeonCityFPGAPpiGuid =3D { 0x48e796bd, 0x= 4ed3, 0x4755, { 0xa8, 0xca, 0x4c, 0xf4, 0x37, 0x25, 0x82, 0x41 } } + gEfiPeiPlatformTypeOpalCityFPGAPpiGuid =3D { 0xe5434b26, 0x= aedf, 0x43de, { 0x89, 0x35, 0xd1, 0xc4, 0x85, 0xa9, 0x12, 0xb9 } } + gEfiPeiPlatformTypeWilsonCityRPPpiGuid =3D { 0x0629aff2, 0x= 4e23, 0x45c6, { 0x90, 0xc5, 0xb3, 0x21, 0x7b, 0x00, 0x09, 0x23 } } + gEfiPeiPlatformTypeWilsonCityModularPpiGuid =3D { 0x3170ea7b, 0x= 6784, 0x4366, { 0xb4, 0xc6, 0xfe, 0x69, 0x9f, 0x69, 0x42, 0x21 } } + gEfiPlatformTypeIsoscelesPeakPpiGuid =3D { 0xfc7b089f, 0x= 5395, 0x40c0, { 0x9e, 0xfb, 0xca, 0x90, 0x59, 0xe2, 0x7f, 0xea } } + + gPeiIpmiTransportPpiGuid =3D { 0x7bf5fecc, 0x= c5b5, 0x4b25, { 0x81, 0x1b, 0xb4, 0xb5, 0xb, 0x28, 0x79, 0xf7 } } + +# +# UBA_END +# + + gBoardInitGuid =3D { 0xecc07551, 0x= d64c, 0x4c07, { 0xab, 0x95, 0x94, 0x5, 0x66, 0xed, 0x31, 0xf1 } } + gUbaConfigDatabasePpiGuid =3D { 0xc1176733, 0x= 159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73, 0x10 } } + + gPeiSpiSoftStrapsPpiGuid =3D { 0x7F19E716, 0x= 419C, 0x4E79, { 0x8E, 0x37, 0xC2, 0xBD, 0x84, 0xEB, 0x65, 0x28 } } + gUpdatePcdGuid =3D { 0xa08e4c6b, 0x= ff28, 0x4fff, { 0x93, 0x56, 0x78, 0x36, 0x26, 0xc3, 0xe0, 0x38 } } + gPlatformVariableInitPpiGuid =3D { 0x9b1b911b, 0x= 4259, 0x4539, { 0xaf, 0x86, 0xe5, 0xf3, 0x61, 0xca, 0x09, 0x02 } } + gUpdateBootModePpiGuid =3D { 0x927186a0, 0x= a13e, 0x4b53, { 0xad, 0x41, 0xad, 0xd1, 0x65, 0x6f, 0x62, 0x62 } } + + gEfiPeiExStatusCodeHandlerPpiGuid =3D { 0x4e942617, 0x= bbca, 0x4726, { 0x77, 0xb9, 0x49, 0x68, 0x85, 0xf9, 0xc4, 0xf4 } } + + +[Protocols] + gEfiPlatformTypeProtocolGuid =3D { 0x171e9398, 0x= 269c, 0x4081, { 0x90, 0x99, 0x38, 0x44, 0xe2, 0x60, 0x46, 0x6c } } + gUbaConfigDatabaseProtocolGuid =3D { 0xe03e0d46, 0x= 5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77, 0xe2 } } +# +# UBA_START +# + gEfiPlatformTypeNeonCityEPRPProtocolGuid =3D { 0xc0cd2d36, 0x= a81b, 0x450d, { 0xa5, 0x02, 0x37, 0x67, 0xdf, 0xa2, 0x98, 0x26 } } + gEfiPlatformTypeHedtCRBProtocolGuid =3D { 0x2c824f87, 0x= 0f2c, 0x45d7, { 0x81, 0xa6, 0x4f, 0x39, 0xe0, 0x42, 0xbd, 0xdf } } + gEfiPlatformTypeLightningRidgeEXRPProtocolGuid =3D { 0x1b4ae0f8, 0x= ed1f, 0x4fd1, { 0x9b, 0x18, 0xb0, 0x82, 0x29, 0x0f, 0x86, 0xf5 } } + gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid =3D { 0x45b59855, 0x= 500c, 0x443b, { 0xb5, 0x04, 0x9a, 0xb4, 0xca, 0x29, 0xbc, 0x68 } } + gEfiPlatformTypeWilsonCityRPProtocolGuid =3D { 0x8430776f, 0x= bd75, 0x4fc8, { 0xa5, 0x4f, 0x7f, 0x6b, 0xf6, 0x18, 0x9c, 0x13 } } + gEfiPlatformTypeIsoscelesPeakProtocolGuid =3D { 0xcff3f211, 0x= 5d51, 0x4f87, { 0x94, 0xb0, 0x9b, 0x94, 0xf8, 0x4e, 0x8a, 0x48 } } + gEfiPlatformTypeWilsonCityModularProtocolGuid =3D { 0x28e862f4, 0x= a4ed, 0x4acb, { 0x9a, 0x35, 0x36, 0xd0, 0x90, 0x2d, 0xf7, 0x82 } } + + gEfiPlatformTypeWilsonCitySMTProtocolGuid =3D { 0xEE55562D, 0x= 4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } } + gEfiPlatformTypeCooperCityRPProtocolGuid =3D { 0x45c302e1, 0x= 4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } } + gEfiPlatformTypeJunctionCityProtocolGuid =3D { 0xB1C2B1C9, 0x= B606, 0x4B62, { 0x9D, 0x78, 0xCB, 0xD6, 0x0F, 0xF9, 0x0D, 0x0C } } + +# +# UBA_END +# + + gEfiPciIovPlatformProtocolGuid =3D { 0xf3a4b484, 0x= 9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } } + gEfiWindowsInt10Workaround =3D { 0x387f555, 0x2= 0a8, 0x4fc2, { 0xbb, 0x94, 0xcd, 0x30, 0xda, 0x1b, 0x40, 0x08 } } + gEfiVMDDriverProtocolGuid =3D { 0x5a676ae9, 0x= db23, 0x4a68, { 0xa2, 0x4d, 0xaa, 0x5f, 0xec, 0xd5, 0x74, 0x86 } } + gEfiHfiPcieGen3ProtocolGuid =3D { 0x7b59316e, 0x= e9df, 0x435f, { 0x98, 0xcd, 0x57, 0x26, 0x64, 0x5b, 0xe8, 0x63 } } + gEfiLegacyBiosProtocolGuid =3D { 0xdb9a1e3d, 0x= 45cb, 0x4abb, { 0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d } } + + gEfiIpmiSolStatusProtocolGuid =3D { 0xe790848e, 0x= b6ab, 0x44ab, { 0x84, 0x91, 0xdc, 0xa5, 0xc, 0x39, 0x7, 0xc6 } } + gEfiIpmiTransportProtocolGuid =3D { 0x6bb945e8, 0x= 3743, 0x433e, { 0xb9, 0xe, 0x29, 0xb3, 0xd, 0x5d, 0xc6, 0x30 } } + gSmmIpmiTransportProtocolGuid =3D { 0x8bb070f1, 0x= a8f3, 0x471d, { 0x86, 0x16, 0x77, 0x4b, 0xa3, 0xf4, 0x30, 0xa0 } } + gEfiIpmiBootGuid =3D { 0x5c9b75ec, 0x= 8ec7, 0x45f2, { 0x8f, 0x8f, 0xc1, 0xd8, 0x8f, 0x3b, 0x93, 0x45 } } + gEfiGenericIpmiDriverInstalledGuid =3D { 0x7cdad61a, 0x= 3df8, 0x4425, { 0x96, 0x8c, 0x66, 0x28, 0xc8, 0x35, 0xff, 0xce } } + + gDmaRemapProtocolGuid =3D { 0x4e873773, 0x839= 1, 0x4e47, { 0xb7, 0xf4, 0xca, 0xfb, 0xdc, 0xc4, 0xb2, 0x04 } } + +[PcdsFixedAtBuild] + +#SKX_TODO: add a new GUID, and replace the 'gPlatformTokenSpaceGuid' used = here to it, or move these values to the SocketPkg where the GUID is defined +# Using a GUID defined in another .DEC file is a violation of the= UEFI packaging standards. + + gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E + gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F + gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase|0x00000000|UINT32|0x300000= 1A + gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize|0x00000000|UINT32|0x300000= 1B + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize|0x00000000|UINT32|0x300= 0001C + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase|0x00000000|UINT32|0x300= 0001D + gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize|0x00000000|UINT32|0x3000= 001E + gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase|0x00000000|UINT32|0x3000= 001F + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize|0x00000000|UINT32|0x30000= 020 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase|0x00000000|UINT32|0x30000= 021 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|0x0000000|UINT32|0x3000= 0027 + + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize|0x0000000|UINT32|0x30000= 001 + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|0x0000000|UINT32|0x300= 00004 + gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|0x000000= 0|UINT32|0x30000006 + gPlatformModuleTokenSpaceGuid.PcdFlashFreeSpaceOffset|0x0000000|UINT32|0= x30000008 + + gPlatformTokenSpaceGuid.PcdSupportLegacyStack|TRUE|BOOLEAN|0x30000030 + gPlatformTokenSpaceGuid.PcdMaxOptionRomNumber|0x4|UINT8|0x30000031 + + gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032 + + # Choose the default serial debug message level when CMOS is bad; in the= later BIOS phase, the setup default is applied + # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max + gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033 + gPlatformTokenSpaceGuid.PcdWilsonPointSvidVrP1V8|0x05|UINT8|0x30000000 = #BIT4 =3D> SVID BUS 0, BIT3-BIT0 =3D> VR ADDRESS + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8|0x15|UINT8|0x30000002 + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna|0x16|UINT8|0x30000003 + + # PCD for failsafe variable ffs in other FV rather than bb1 + # by default, FCE will insert into SECPEI, and you don't need to set the= se two PCD if bb1(secpei)is used + gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize|0|UINT32|0x30000034 + gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase|0|UINT32|0x30000035 + + gPlatformTokenSpaceGuid.PcdSetupVariableGuid|{ 0x43,0xd6,0x87,0xec,0xa4,= 0xeb, 0xb5,0x4b, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9}|VOID*|0x30= 000036 + + # + # These need to move to MinPlatformPkg.dec + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize|0|UINT32|0xF000= 00A9 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase|0|UINT32|0xF000= 00AA + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|0|UINT32|0xF0= 0000AB + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize|0|UINT32|0xF00000AC + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase|0|UINT32|0xF00000AD + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|0|UINT32|0xF00000AE + + #IIO configuration data for socket 3 will be used for sockets 4..7 + gPlatformTokenSpaceGuid.PcdSocketCopy|FALSE|BOOLEAN|0xF00000AF + + gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionSize|0x01000000|UINT32|0xF00= 000B0 + gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionBase|0xFF900000|UINT32|0xF00= 000B1 + + #If True, extend PCR7 when VT-d disabled. + gPlatformTokenSpaceGuid.PcdConditionallyExtendPcr7|FALSE|BOOLEAN|0xE0000= 045 + + #If 0 BoardId detection is done using GPIO. Otherwise Board id will be f= orced to value set by this PCD + #Non zero value should match the values defined in PlatformInfoTypes.h + gPlatformTokenSpaceGuid.PcdBoardId|0|UINT8|0xE0000046 + + # BoardRevion Id value. Valid only if PcdBoardId is not equal to 0 + gPlatformTokenSpaceGuid.PcdBoardRevId|0|UINT8|0xE0000047 + +[PcdsFixedAtBuild, PcdsPatchableInModule] + gPlatformTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x0= 5, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x400= 00004 + ## Specify memory size with page number for a pre-allocated reserved mem= ory to be used + # by PEI in S3 phase. The default size 32K. When changing the value mak= e sure the memory size + # is large enough to meet PEI requirement in the S3 phase. + # @Prompt Reserved S3 Boot ACPI Memory Size + gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|= 0x90010039 + gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012 + gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0= x90000017 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000= 018 + + + gPlatformModuleTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021 + gPlatformModuleTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022 + gPlatformModuleTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023 + gPlatformModuleTokenSpaceGuid.PcdHpetTimerBlockId|0x8086A201|UINT32|0x90= 000024 + + gPlatformModuleTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x900= 00025 + gPlatformModuleTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900000= 26 + gPlatformModuleTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027 + gPlatformModuleTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x90= 00000B + gPlatformModuleTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x90000= 00D + gPlatformModuleTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014 + gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006 + +[PcdsDynamicEx] + +# +# PAL +# + gPlatformTokenSpaceGuid.PcdOemSkuPcieSlotOpromBitMap|0xFF|UINT32|0x00000= 008 + +#SKX_TODO: gPlatformTokenSpaceGuid are not correct GUIDs to use here, use = local GUID... + gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|FALSE|BOOLEAN|0x= 00000048 + + ## This value is used to save memory address of MRC data structure. + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041 + gPlatformTokenSpaceGuid.PcdHalfWidth|FALSE|BOOLEAN|0x30000042 + +# +# IMR0 programming values +# + gPlatformTokenSpaceGuid.PcdImr0Enable|FALSE|BOOLEAN|0xA5000000 + gPlatformTokenSpaceGuid.PcdImr0Base|0x0|UINT64|0xA5000001 + gPlatformTokenSpaceGuid.PcdImr0Mask|0x0|UINT64|0xA5000002 + gPlatformTokenSpaceGuid.PcdImr0Rac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000003 + gPlatformTokenSpaceGuid.PcdImr0Wac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000004 + +# +# IMR3 programming values +# + gPlatformTokenSpaceGuid.PcdImr3Enable|FALSE|BOOLEAN|0xA5000022 + +# +# Server common Hot Key binding +# + # EFI Scan codes + # SCAN_F2 0x000C + # SCAN_F6 0x0010 + # SCAN_F7 0x0011 + gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x00|UINT16|0x00000009 + gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x00|UINT16|0x0000000A + + + gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, = 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x= 0000000B + +#Indicate whether to perform LT Config lock +# The PCD can be set to false when there is the debug request +# TRUE - Force the LT config lock +# FALSE - Allow the LT config unlock for debug + gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE|BOOLEAN|0x30000= 00e + +#Indicate whether LTSX enabled +# TRUE - Intel (R) TXT feature enabled on the platform +# FALSE - Disable Intel(R) TXT feature on the platform + gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x30= 00000f + + # + # SMBIOS Type 0 - BIOS Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVendor|"TBD"|VOID*|0x5B00= 0000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVersion|"TBD"|VOID*|0x5B0= 00001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosReleaseDate|"TBD"|VOID*|0= x5B000002 + + # + # SMBIOS Type 1 - System Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemManufacturer|"TBD"|VOID= *|0x5B010000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemProductName|"TBD"|VOID*= |0x5B010001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemVersion|"TBD"|VOID*|0x5= B010002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSerialNumber|"TBD"|VOID= *|0x5B010003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSkuNumber|"TBD"|VOID*|0= x5B010004 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemFamily|"TBD"|VOID*|0x5B= 010005 + + # + # SMBIOS Type 2 - Base Board (or Module) Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardManufacturer|"TBD"|V= OID*|0x5B020000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardProductName|"TBD"|VO= ID*|0x5B020001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardVersion|"TBD"|VOID*|= 0x5B020002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardSerialNumber|"TBD"|V= OID*|0x5B020003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardAssetTag|"TBD"|VOID*= |0x5B020004 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardLocationInChassis|"T= BD"|VOID*|0x5B020005 + + # + # SMBIOS Type 3 - System Enclosure or Chassis Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisManufacturer|"TBD"|VOI= D*|0x5B030000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisVersion|"TBD"|VOID*|0x= 5B030001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSerialNumber|"TBD"|VOI= D*|0x5B030002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisAssetTag|"TBD"|VOID*|0= x5B030003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSkuNumber|"TBD"|VOID*|= 0x5B030004 + + # + # SMBIOS Type 11 - OEM Strings + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesOemString1|"TBD"|VOID*|0x5B0B= 0001 + + # + # SMBIOS Type 12 - System Configuration Options + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSysConfigOption1|"TBD"|VOID*|= 0x5B0C0001 + + # + # SMBIOS Type 14 - Group Associations + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTableType|0xDD|UINT8|0x5B0D0001 + + # + # SMBIOS Type 17 - Memory Device + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesMemorySerialNumberFormat|0x00= |UINT8|0x5B110000 + + # + # SMBIOS Type 27 - Cooling Device + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesCoolingDeviceDescription|"TBD= "|VOID*|0x5B1B0000 + + # + # SMBIOS Type 28 - Temperature Probe + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesTemperatureProbeDescription|"= TBD"|VOID*|0x5B1C0000 + + # + # SMBIOS Type 34 - Management Device + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceDescription|"= TBD"|VOID*|0x5B220000 + + # + # SMBIOS Type 35 - Management Device Component + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceComponentDesc= ription|"TBD"|VOID*|0x5B230000 + + # + # SMBIOS Type 39 - System Power Supply + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyLocation|"TB= D"|VOID*|0x5B270000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyDeviceName|"= TBD"|VOID*|0x5B270001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyManufacturer= |"TBD"|VOID*|0x5B270002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplySerialNumber= |"TBD"|VOID*|0x5B270003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyAssetTagNumb= er|"TBD"|VOID*|0x5B270004 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyModelPartNum= ber|"TBD"|VOID*|0x5B270005 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyRevisionLeve= l|"TBD"|VOID*|0x5B270006 + +[PcdsFeatureFlag] + gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00= 000020 + + ## + ## High Speed UART + ## + gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE|BOOLEAN|0x000= 0002C + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] + ## MemoryCheck value for checking memory before boot OS. + # To save the boot performance, the default MemoryCheck is set to 0. + gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|0|UINT8|0x40000005 + + + ## following PCDs should remove if CORE accept the fix + gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x0|UINT32|4 + + ## Vendor ID and Device ID of device producing onboard video + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0|UINT16|0x00000013 + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0|UINT16|0x00000014 + gPlatformModuleTokenSpaceGuid.PcdPlatformMemoryCheckLevel|0|UINT32|0x300= 00009 + ## This PCD is to control which device is the potential trusted console = input device.

+ # For example:
+ # USB Short Form: UsbHID(0xFFFF,0xFFFF,0x1,0x1)
+ # //Header VendorId ProductId Class SubClass P= rotocol
+ # {0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0= x01,
+ # //Header
+ # 0x7F, 0xFF, 0x04, 0x00}
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x03, 0x= 0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04,= 0x00}|VOID*|0x300000A + + ## This PCD is to control which device is the potential trusted console = output device.

+ # For example:
+ # Integrated Graphic: PciRoot(0x0)/Pci(0x2,0x0)
+ # //Header HID UID
+ # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00= , 0x00,
+ # //Header Func Dev
+ # 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, + # //Header
+ # 0x7F, 0xFF, 0x04, 0x00}
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0= x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01= , 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000C + + + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16= |0x00010035 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16= |0x00010036 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x1804|UINT= 16|0x0001037 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0x0000|UINT= 16|0x00010038 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x1850|UINT1= 6|0x00010039 + gPlatformModuleTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x1808|UINT16|0= x0001003A + gPlatformModuleTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x1880|UINT16|0x00= 01003B + gPlatformModuleTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x00= 01003C + +# +# UBA_START +# +[PcdsDynamicEx] + +# +#Board Definitions +# +#Integer for BoardID, must match the SKU number and be unique. + gOemSkuTokenSpaceGuid.PcdOemSkuBoardID|0x0|UINT16|0x00000000 +#Integer for BoardFamily, must be unique + gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily|0x0|UINT16|0x00000001 +# Zero terminated unicode string to ID family + gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName|L"DEFAULT = "|VOID*|0x0000002 +# Zero terminated unicode string to Board Name + gOemSkuTokenSpaceGuid.PcdOemSkuBoardName|L"DEFAULT = "|VOID*|0x00000003 +# Number of Sockets on Board. + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount|0x0|UINT32|0x00000004 + +# Number of DIMM slots per channel for each Socket + gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel|0x0|UINT32|0x00000005 + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel|0x0|UINT32|0x00000006 + gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout|FALSE|BOOLEAN|0x00000007 + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008 + + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009 +# Form factor is MemoryFormFactorDimm by default +# MemoryFormFactorOther =3D 0x01 +# MemoryFormFactorUnknown =3D 0x02 +# MemoryFormFactorSimm =3D 0x03 +# MemoryFormFactorSip =3D 0x04 +# MemoryFormFactorChip =3D 0x05 +# MemoryFormFactorDip =3D 0x06 +# MemoryFormFactorZip =3D 0x07 +# MemoryFormFactorProprietaryCard =3D 0x08 +# MemoryFormFactorDimm =3D 0x09 +# MemoryFormFactorTsop =3D 0x0A +# MemoryFormFactorRowOfChips =3D 0x0B +# MemoryFormFactorRimm =3D 0x0C +# MemoryFormFactorSodimm =3D 0x0D +# MemoryFormFactorSrimm =3D 0x0E +# MemoryFormFactorFbDimm =3D 0x0F +# MemoryFormFactorDie =3D 0x10 + gOemSkuTokenSpaceGuid.PcdOemSkuMemDevFormFactor|0x09|UINT8|0x10000010 + +# +# USB +# +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00|0x0|UINT16|0x000000= 10 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01|0x0|UINT16|0x000000= 11 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02|0x0|UINT16|0x000000= 12 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03|0x0|UINT16|0x000000= 13 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04|0x0|UINT16|0x000000= 14 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05|0x0|UINT16|0x000000= 15 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06|0x0|UINT16|0x000000= 16 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07|0x0|UINT16|0x000000= 17 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08|0x0|UINT16|0x000000= 18 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09|0x0|UINT16|0x000000= 19 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10|0x0|UINT16|0x000000= 1A +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11|0x0|UINT16|0x000000= 1B +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12|0x0|UINT16|0x000000= 1C +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13|0x0|UINT16|0x000000= 1D + +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00|0x0|UINT16|0x0000002= 0 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01|0x0|UINT16|0x0000002= 1 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02|0x0|UINT16|0x0000002= 2 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03|0x0|UINT16|0x0000002= 3 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04|0x0|UINT16|0x0000002= 4 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05|0x0|UINT16|0x0000002= 5 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06|0x0|UINT16|0x0000002= 6 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07|0x0|UINT16|0x0000002= 7 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08|0x0|UINT16|0x0000002= 8 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09|0x0|UINT16|0x0000002= 9 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10|0x0|UINT16|0x0000002= A +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11|0x0|UINT16|0x0000002= B +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12|0x0|UINT16|0x0000002= C +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13|0x0|UINT16|0x0000002= D + +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00|0x0|UINT16|0x00000= 100 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01|0x0|UINT16|0x00000= 101 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02|0x0|UINT16|0x00000= 102 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03|0x0|UINT16|0x00000= 103 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04|0x0|UINT16|0x00000= 104 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05|0x0|UINT16|0x00000= 105 + +# +# ACPI items +# +# Acpi Name, MUST be 8 chars long + gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName|"DEFAULT "|VOID*|0x000000= 30 + gOemSkuTokenSpaceGuid.PcdOemTableIdXhci|"DEFAULT "|VOID*|0x000000= 31 +# +# Misc. +# + + gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag|0x0|UINT8|0x00000039 + gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed|0x0|UINT16|0x00000040 + +# +# GPIO +# + + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL|0xFF3DB93D|UINT32|0x000= 00050 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL|0x0382F03F|UINT32|0x00= 000051 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL|0xFFFFF30F|UINT32|0x00= 000052 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL|0x91E3EFFF|UINT32|0x0000= 0053 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL|0xFFFD0FF3|UINT32|0x000= 00054 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL|0xFFFFFDF0|UINT32|0x000= 00055 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL|0x661C1000|UINT32|0x0000005= 6 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL|0x0002F004|UINT32|0x000000= 57 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL|0x0000020D|UINT32|0x000000= 58 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL|0x00000000|UINT32|0x0000005= 9 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL|0x00000000|UINT32|0x00000= 05a + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE|0x00000000|UINT32|0x0000= 005c + +# +# SATA registers +# + + gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32|0x99990000|UINT32|0x0000005b + +# +# Clock generator settings +# + + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00|0xFF|UINT8|0x00000060 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01|0x9E|UINT8|0x00000061 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02|0x3F|UINT8|0x00000062 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03|0x00|UINT8|0x00000063 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04|0x00|UINT8|0x00000064 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05|0x0F|UINT8|0x00000065 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06|0x08|UINT8|0x00000066 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07|0x11|UINT8|0x00000067 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08|0x0A|UINT8|0x00000068 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09|0x17|UINT8|0x00000069 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10|0xFF|UINT8|0x0000006a + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11|0xFE|UINT8|0x0000006b + gOemSkuTokenSpaceGuid.PcdOemSkuClockGeneratorAddress|0xD2|UINT8|0x000000= 6c + + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName|L"DEFAULT = "|VOID*|0x00000201 + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize|0x0|UINT32|0x00000202 + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag|0x0|UINT32|0x00000203 + +# +# If PcdOemSkuAssertPostGPIO value is 0xFFFFFFFF, current platform don't s= et related GPIO. +# + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO|0x01010014|UINT32|0x000002= 04 + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue|0x0|UINT32|0x00000205 + + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber|0xFF|UINT8|0x00000206 + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207 +# +# UBA_END +# + + gCpPlatIpmiTokenSpaceGuid.PcdIpmiIoBaseAddress|0xCA2|UINT16|0x10000022 + gCpPlatIpmiTokenSpaceGuid.PcdIpmiSmmIoBaseAddress|0xCA4|UINT16|0x1000002= 3 + gCpPlatIpmiTokenSpaceGuid.PcdSioMailboxBaseAddress|0x600|UINT32|0x100000= 21 + gCpPlatIpmiTokenSpaceGuid.PcdFRB2EnabledFlag|TRUE|BOOLEAN|0x10000030 + gCpPlatIpmiTokenSpaceGuid.PcdIpmiBmcReadyDelayTimer|0|UINT8|0x00000208 + + +## This PCD replaces the original one gEfiIntelFrameworkModulePkgTokenSpac= eGuid.PcdBootState + gPlatformModuleTokenSpaceGuid.PcdBootState|TRUE|BOOLEAN|0x300000AC + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000208 + +[PcdsDynamicEx] + gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|FALSE|BOOLEAN|0x10000026 + gCpPlatTokenSpaceGuid.PcdUefiOptimizedBootEx|FALSE|BOOLEAN|0x10000024 + +[PcdsFixedAtBuild] +# +# Flash map related PCD. +# +# Note: most values here are overridden in the .fdf file +# +# +# Note: FlashNv PCD naming conventions are as follows: +# +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used = in the system, and +# the FlashMap edit tool can be used to change the values here, with= out effecting the code. +# This requires all code to only use the PCD tokens to recover the v= alues. +# + + + +# PCD's that are for the whole SPI part + + +#Block size of SPI +gCpPlatFlashTokenSpaceGuid.PcdFlashBlockSize |0x00010= 000 |UINT32|0x50000102 + + +#AJW rename this to be more in keeping with the function +gCpPlatFlashTokenSpaceGuid.PcdFlashAreaBase |0xfff00= 000 |UINT32|0x50000105 + + + +# for PeiSec FD + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize |0x00100= 000 |UINT32|0x50000221 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase |0x00000= 000 |UINT32|0x50000222 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase |0x00000= 000 |UINT32|0x50000260 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize |0x00040= 000 |UINT32|0x50000261 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase |0x00000= 000 |UINT32|0x50000211 +gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize |0x00100= 000 |UINT32|0x50000212 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize |0x001000= 00 |UINT32|0x50000233 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase |0x000000= 00 |UINT32|0x50000234 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset |0x000000= 00 |UINT32|0x50000235 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize |0x00100= 000 |UINT32|0x50000241 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase |0x00000= 000 |UINT32|0x50000242 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize |0x00100= 000 |UINT32|0x50000251 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase |0x00000= 000 |UINT32|0x50000252 + + +# for Main FD + + +gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase |0xfff0= 0000 |UINT32|0x50000300 +gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize |0x0040= 0000 |UINT32|0x50000301 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainSize |0x0020= 0000 |UINT32|0x50000311 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainBase |0xFF82= 0000 |UINT32|0x50000312 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize |0x0020= 0000 |UINT32|0x50000341 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase |0xFF82= 0000 |UINT32|0x50000342 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset |0xFF82= 0000 |UINT32|0x50000343 + + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize |0x0020= 0000 |UINT32|0x50000351 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase |0xFF82= 0000 |UINT32|0x50000352 + +## This PCD specifies the size of the physical device containing the BIOS,= SMBIOS will use it. + +gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionBase |0xFF80= 0000 |UINT32|0x50000001 +gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionSize |0x0000= 0000 |UINT32|0x50000002 + +[PcdsFeatureFlag.common] + +## +## Those PCDs are used to control build process. +## + + # + # SV Tools + # + gPlatformFeatureTokenSpaceGuid.PcdXmlCliEnable|TRUE|BOOLEAN|0xE0000000 + gPlatformFeatureTokenSpaceGuid.PcdSvBiosEnable|TRUE|BOOLEAN|0xE000002E + # + # + # + +[PcdsDynamicEx] + ### Sample implementation...No real data. Use this PCD to override a pla= tform with Interposer ### + gPlatformTokenSpaceGuid.PcdMemInterposerMap|{0}|INTERPOSER_MAP|0x8000001= 5 { + + Guid/PlatformInfo.h + + WhitleyOpenBoardPkg/PlatformPkg.dec + } + # Interposer A MC 0 mapped to original MC1 + # Enum values for Interposer + # Interposer A =3D> 1 + # Interposer B =3D> 2 + # Interposer Unknown =3D> 0 + gPlatformTokenSpaceGuid.PcdMemInterposerMap.Interposer[1].MappedMcId[0] = |1 + +### Sample implementation...No real data. Use this PCD to override a platf= orm with Interposer ### + +[Guids] + gStructPcdTokenSpaceGuid =3D {0x3f1406f4, 0x2b, 0x487a, {0x8b, 0x69, 0x7= 4, 0x29, 0x1b, 0x36, 0x16, 0xf4}} + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] +gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig|{0}|EMULATION_DFX_CONFIGURA= TION|0XFCD0000C{ + + Include/Guid/EmulationDfxVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|{0}|FPGA_SOCKET_CONFIGURATION= |0XFCD00010{ + + Include/Guid/FpgaSocketVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration|{0}|IE_RC_CONFIGURATION|0XFC= D00004{ + + Include/Guid/IeRcVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration|{0}|ME_RC_CONFIGURATION|0XFC= D0000B{ + + Include/Guid/MeRcVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig|{0}|MEM_BOOT_HEALTH_CONFIG= |0XFCD00002{ + + Include/Guid/MemBootHealthGuid.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdPchSetup|{0}|PCH_SETUP|0XFCD00007{ + + Include/PchSetupVariableLbg.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSetup|{0}|SYSTEM_CONFIGURATION|0XFCD0000F{ + + Include/Guid/SetupVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|{0}|SOCKET_COMMONRC_CONFI= GURATION|0XFCD00001{ + + Include/Guid/SocketCommonRcVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketIioConfig|{0}|SOCKET_IIO_CONFIGURATION|0= XFCD00006{ + + Include/Guid/SocketIioVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|{0}|SOCKET_MEMORY_CONFIGURA= TION|0XFCD0000D{ + + Include/Guid/SocketMemoryVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|{0}|SOCKET_MP_LINK_CONFIGUR= ATION|0XFCD00008{ + + Include/Guid/SocketMpLinkVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|{0}|SOCKET_POWERMA= NAGEMENT_CONFIGURATION|0XFCD00005{ + + Include/Guid/SocketPowermanagementVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|{0}|SOCKET_PROCESSOR= CORE_CONFIGURATION|0XFCD00003{ + + Include/Guid/SocketProcessorCoreVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSvConfiguration|{0}|SV_CONFIGURATION|0XFCD0000= 9{ + + Include/Guid/SetupVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION|{0}|TCG2_CONFIGURATION|0XFC= D0000A{ + + Include/Tcg2ConfigNvData.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + SecurityPkg/SecurityPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +gStructPcdTokenSpaceGuid.PcdTCG2_VERSION|{0}|TCG2_VERSION|0XFCD0000E{ + + Include/Tcg2ConfigNvData.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] + gOemSkuTokenSpaceGuid.PcdTurboPowerLimitLock|0x01|UINT8|0x00000209 + gOemSkuTokenSpaceGuid.PcdNumberOfCoresToDisable|0x0|UINT16|0x0000020A + +[LibraryClasses] + ServerManagementTimeStampLib|Include/Library/ServerManagementTimeStampLi= b.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/= Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc index ae3646df7a..5507a044a4 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc @@ -1,954 +1,970 @@ -## @file -# X64 Platform with 64-bit DXE. -# -# @copyright -# Copyright 2008 - 2021 Intel Corporation.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -## - -##########################################################################= ###### -# -# Defines Section - statements that will be processed to create a Makefile= . -# -##########################################################################= ###### -[Defines] - PLATFORM_NAME =3D $(RP_PKG) - PLATFORM_GUID =3D D7EAF54D-C9B9-4075-89F0-71943DBC= FA61 - PLATFORM_VERSION =3D 0.1 - DSC_SPECIFICATION =3D 0x00010005 - OUTPUT_DIRECTORY =3D Build/$(RP_PKG) - SUPPORTED_ARCHITECTURES =3D IA32|X64 - BUILD_TARGETS =3D DEBUG|RELEASE - SKUID_IDENTIFIER =3D DEFAULT - VPD_TOOL_GUID =3D 8C3D856A-9BE6-468E-850A-24F7A8D3= 8E08 - FLASH_DEFINITION =3D $(RP_PKG)/PlatformPkg.fdf - PLATFORM_SI_PACKAGE =3D ClientOneSiliconPkg - DEFINE PLATFORM_SI_BIN_PACKAGE =3D WhitleySiliconBinPkg - PEI_ARCH =3D IA32 - DXE_ARCH =3D X64 - -!if $(CPUTARGET) =3D=3D "CPX" - DEFINE FSP_BIN_PKG =3D CedarIslandFspBinPkg - DEFINE IIO_INSTANCE =3D Skx -!elseif $(CPUTARGET) =3D=3D "ICX" - DEFINE FSP_BIN_PKG =3D WhitleyFspBinPkg - DEFINE IIO_INSTANCE =3D Icx -!else - DEFINE IIO_INSTANCE =3D UnknownCpu -!endif - - # - # Platform On/Off features are defined here - # - !include $(RP_PKG)/PlatformPkgConfig.dsc - - # - # MRC common configuration options defined here - # - !include $(SILICON_PKG)/MrcCommonConfig.dsc - -[Packages] - IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec - - !include $(FSP_BIN_PKG)/DynamicExPcd.dsc - !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc - !include $(RP_PKG)/DynamicExPcd.dsc - - !include $(RP_PKG)/Uba/UbaCommon.dsc - !include $(RP_PKG)/Uba/UbaRpBoards.dsc - - !include $(RP_PKG)/Include/Dsc/EnablePerformanceMonitoringInfrastructure= .dsc - -##########################################################################= ###### -# -# SKU Identification section - list of all SKU IDs supported by this -# Platform. -# -##########################################################################= ###### -[SkuIds] - 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. - -[DefaultStores] - 0|STANDARD - 1|MANUFACTURING - - -##########################################################################= ###### -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -##########################################################################= ###### -[PcdsFeatureFlag] - # - # MinPlatform control flags - # - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit |FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly |FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE - - # don't degrade 64bit MMIO space to 32-bit - gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE - - # Server doesn't support capsule update on Reset. - gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE - gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE - - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE - - gEfiCpRcPkgTokenSpaceGuid.Reserved15|TRUE - -!if ($(CPUTARGET) =3D=3D "ICX") - gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|FALSE -!endif # $(CPUTARGET) =3D=3D "ICX" - - gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE - gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|TRUE - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE - gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE - - ## Uncomment for better boot performance -# gPerfOptTokenSpaceGuid.PcdPreUefiLegacyEnable|FALSE -# gPerfOptTokenSpaceGuid.PcdLocalVideoEnable|FALSE - - gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE - - ## This PCD specified whether ACPI SDT protocol is installed. - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE - - ## This PCD specifies whether FPGA routine will be active - gSocketPkgFpgaGuid.PcdSktFpgaActive|TRUE - -!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D TRUE - gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|FALSE - gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|TRUE -!endif - - ## This PCD specifies whether or not to enable the High Speed UART - gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE - - gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE - -[PcdsFixedAtBuild] - gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption|2 - - ## MinPlatform Boot Stage Selector - # Stage 1 - enable debug (system deadloop after debug init) - # Stage 2 - mem init (system deadloop after mem init) - # Stage 3 - boot to shell only - # Stage 4 - boot to OS - # Stage 5 - boot to OS with security boot enabled - # Stage 6 - boot with advanced features enabled - # - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6 - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # = Enable asserts, prints, code, clear memory, and deadloops on asserts. - gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # = Built in messages: Error, MTRR, info, load, warn, init -!if $(TARGET) =3D=3D "DEBUG" - gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # = This is set to INT3 (0x2) for Simics source level debugging -!endif - - gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 - - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000 - gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE - - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 - gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000 - - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL " - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4449204C45544E= 49 # "INTEL ID" - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x2100000 - gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 - - gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x400000 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 - gCpuPkgTokenSpaceGuid.PcdPlatformType|2 - gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000 - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 - - #PcdCpuMicrocodePatchRegionSize =3D PcdFlashNvStorageMicrocodeSize - (EF= I_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER)) - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x1FFF70 - - # - # This controls the NEM code region cached during SEC - # It usually isn't necessary to match exactly the FV layout in the FDF f= ile. - # It is a performance optimization to have it match the flash region exa= ctly - # as then no extra reads are done to load unused flash into cache. - # - gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0xFFC00000 - gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x00400000 - - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000 - - # - # Mode | FSP_MODE | PcdFspModeSelection - # ------------------|----------|-------------------- - # FSP Dispatch Mode | 1 | 0 - # FSP API Mode | 0 | 1 - # -!if ($(FSP_MODE) =3D=3D 0) - gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000 -!else - gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 -!endif - gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 - - # - # These will be initialized during build - # - - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000 - - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000 - - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000 - - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x00000000 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x00000000 - gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase|0x00000000 - - ## Specifies delay value in microseconds after sending out an INIT IPI. - # @Prompt Configure delay value after send an INIT IPI - gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss - gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 - - gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x2 - - gPlatformTokenSpaceGuid.PcdUboDev|0x08 - gPlatformTokenSpaceGuid.PcdUboFunc|0x02 - gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC - - gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|TRUE - gPlatformTokenSpaceGuid.PcdSupportLegacyStack|FALSE - - ## Defines the ACPI register set base address. - # The invalid 0xFFFF is as its default value. It must be configured to = the real value. - # @Prompt ACPI Timer IO Port Address - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500 - - ## Defines the PCI Bus Number of the PCI device that contains the BAR an= d Enable for ACPI hardware registers. - # @Prompt ACPI Hardware PCI Bus Number - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00 - - ## Defines the PCI Device Number of the PCI device that contains the BAR= and Enable for ACPI hardware registers. - # The invalid 0xFF is as its default value. It must be configured to th= e real value. - # @Prompt ACPI Hardware PCI Device Number - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F - - ## Defines the PCI Function Number of the PCI device that contains the B= AR and Enable for ACPI hardware registers. - # The invalid 0xFF is as its default value. It must be configured to th= e real value. - # @Prompt ACPI Hardware PCI Function Number - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02 - - ## Defines the PCI Register Offset of the PCI device that contains the E= nable for ACPI hardware registers. - # The invalid 0xFFFF is as its default value. It must be configured to = the real value. - # @Prompt ACPI Hardware PCI Register Offset - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044 - - ## Defines the bit mask that must be set to enable the APIC hardware reg= ister BAR. - # @Prompt ACPI Hardware PCI Bar Enable BitMask - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80 - - ## Defines the PCI Register Offset of the PCI device that contains the B= AR for ACPI hardware registers. - # The invalid 0xFFFF is as its default value. It must be configured to = the real value. - # @Prompt ACPI Hardware PCI Bar Register Offset - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040 - - ## Defines the offset to the 32-bit Timer Value register that resides wi= thin the ACPI BAR. - # @Prompt Offset to 32-bit Timer register in ACPI BAR - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 - -!if $(CPUTARGET) =3D=3D "ICX" - # - # ACPI PCD custom override - # - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49 - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013 -!endif - - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) - gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 - - # Enable DDRT scheduler debug features for power on - gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault|TRUE - - # Disable Fast Warm Boot for Whitley Openboard Package - gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault|FALSE - -!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D FALSE - gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|FALSE - gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable|FALSE -!endif - - gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x74 - gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x75 - - # - # PlatformInitPreMem - # - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x100 - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA30 - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x100 - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100 - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x100 - - gEfiCpRcPkgTokenSpaceGuid.PcdReserved15|0 - - !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc - -[PcdsFixedAtBuild.IA32] - # - # FSP Base address PCD will be updated in FDF basing on flash map. - # - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 - -!if ($(FSP_MODE) =3D=3D 0) - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000 - gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0 -!endif - -[PcdsFixedAtBuild.X64] - # Change PcdBootManagerMenuFile to UiApp - ## - - gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } - - gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0xC00000 - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE - - # - # AcpiPlatform - # - gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1 - gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32 - gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09 - gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 - gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24 - - gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04 - gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000 - gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 - gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 - gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000 - gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08 - - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|FALSE - - gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{ 0x02= , 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x0= 1, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, = 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00,= 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01= , 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, = 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, = 0x04, 0x00, 0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, = 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00} - gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{ 0x02= , 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x0= 1, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, = 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00,= 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01= , 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, = 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, = 0x04, 0x00, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, = 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF,= 0x04, 0x00} - gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x0, 0x0, 0x= 1F, 0x0} - gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x01 - -[PcdsPatchableInModule] - # - # These debug options are patcheable so that they can be manipulated dur= ing debug (if memory is updateable) - # - - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 # = Enable status codes for debug, progress, and errors - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 # = Displayed messages: Error, Info, warn - - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 - gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0 - -!if $(PREMEM_PAGE_ALLOC_SUPPORT) =3D=3D FALSE - gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0x130000 -!endif - -[PcdsDynamicExDefault.IA32] -!if ($(FSP_MODE) =3D=3D 0) - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000 -!endif - - -[PcdsDynamicExHii] - gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|L"1GPageTable"|gEfiGene= ricVariableGuid|0x0|TRUE - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|0 # Variable: L"Timeout" - gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|L"MemoryCheck"|gPlatformT= okenSpaceGuid|0x0|0 - gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|L"UefiOptimizedBoot"|gCpPlatT= okenSpaceGuid|0x0|TRUE - gPlatformModuleTokenSpaceGuid.PcdBootState|L"BootState"|gEfiGenericVaria= bleGuid|0x0|TRUE - gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" - gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|L"BootDeviceScra= tchPad"|gEfiGenericVariableGuid|0x0|FALSE - -[PcdsDynamicExDefault] - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000 - gEfiSecurityPkgTokenSpaceGuid.PcdTpmPhysicalPresence|TRUE - gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE - gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE - gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable|FALSE - - gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE - gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE - gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE - - gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE - gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0 - gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0 - gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0 - - #Platform should change it to by code - gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0xAAAA0000 - gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0xAA33AA22 - - gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE - - # - # CPU features related PCDs. - # - gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy - gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle - gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset - - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x01 - - ## Put fTPM guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, = 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } } - ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, = 0x1b, 0x90, 0xcc } } - ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x= 75, 0x8b, 0x73, 0x17 } } - - #TPM2.0# - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28= , 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} - - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|0 - gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1 - gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0 - - gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE - gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE - - gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0x102b - gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0x0522 - - gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x000C - gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x0011 - gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, = 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d } - gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0 - -[PcdsDynamicExDefault.X64] - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 - gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 - - # - # Set video to 1024x768 resolution - # - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768 - -[PcdsDynamicExDefault] - -!if $(CPUTARGET) =3D=3D "CPX" - !include $(RP_PKG)/StructurePcdCpx.dsc -!else - !include $(RP_PKG)/StructurePcd.dsc -!endif - -##########################################################################= ###### -# -# Library Class section - list of all Library Classes needed by this Platf= orm. -# -##########################################################################= ###### - -!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc -!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc -!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc - -[LibraryClasses] - - # - # Simics source level debugging requires the non-null version of PeCoffE= xtraActionLib - # -!if $(TARGET) =3D=3D "DEBUG" - PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf -!else - PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf -!endif - - # - # Basic - # - - PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf - SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf - - # - # Framework - # - S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf - FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf - - SiliconPolicyInitLib|WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/= SiliconPolicyInitLibShim.inf -!if ($(FSP_MODE) =3D=3D 0) - SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconP= olicyUpdateLibFsp.inf -!else - SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconP= olicyUpdateLib.inf -!endif - - SetupLib|WhitleySiliconPkg/Library/SetupLib/SetupLib.inf - - # - # ToDo: Can we use BaseAcpiTimerLib from MinPlatform? - # - TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf - - MultiPlatSupportLib|$(RP_PKG)/Library/MultiPlatSupportLib/MultiPlatSuppo= rtLib.inf - ReadFfsLib|$(RP_PKG)/Library/ReadFfsLib/ReadFfsLib.inf - PlatformSetupVariableSyncLib|$(RP_PKG)/Library/PlatformSetupVariableSync= LibNull/PlatformSetupVariableSyncLibNull.inf - PlatformVariableHookLib |$(RP_PKG)/Library/PlatformVariableHookLibNull/P= latformVariableHookLibNull.inf - - PlatformBootManagerLib|$(PLATFORM_PKG)/Bds/Library/DxePlatformBootManage= rLib/DxePlatformBootManagerLib.inf - SerialPortLib|$(RP_PKG)/Library/SerialPortLib/SerialPortLib.inf - PlatformHooksLib|$(RP_PKG)/Library/PlatformHooksLib/PlatformHooksLib.inf - - CmosAccessLib|BoardModulePkg/Library/CmosAccessLib/CmosAccessLib.inf - PlatformCmosAccessLib|$(RP_PKG)/Library/PlatformCmosAccessLib/PlatformCm= osAccessLib.inf - SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf - TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf - - # - # MinPlatform uses port 80, we don't want to assume HW - # - PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf - - TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull= .inf - Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN= ull.inf - AslUpdateLib|$(PLATFORM_PKG)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLi= b.inf - PciSegmentInfoLib|$(PLATFORM_PKG)/Pci/Library/PciSegmentInfoLibSimple/Pc= iSegmentInfoLibSimple.inf - PlatformOpromPolicyLib|$(RP_PKG)/Library/PlatformOpromPolicyLibNull/Plat= formOpromPolicyLibNull.inf - VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf - -[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses= .Common.PEIM] - FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf - FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf - FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/Fs= pWrapperPlatformLib.inf - FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf - - FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwit= chStackLib.inf - FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf - FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLi= b.inf - -[LibraryClasses.Common.SEC] - # - # SEC phase - # - TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf - - PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapp= erPlatformSecLib.inf - SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/= SecBoardInitLibNull.inf - TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestP= ointCheckLib.inf - VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVaria= bleReadLibNull.inf - -[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM] - # - # ToDo: Can we remove - # - CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuE= xceptionHandlerLib.inf - - MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf - - - PeiPlatformHookLib|$(RP_PKG)/Library/PeiPlatformHookLib/PeiPlatformHookl= ib.inf - PlatformClocksLib|$(RP_PKG)/Library/PlatformClocksLib/Pei/PlatformClocks= Lib.inf - - TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestP= ointCheckLib.inf - TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.in= f - - ReportFvLib|$(RP_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf - -[LibraryClasses.Common.PEIM] - # - # Library instance consumed by MinPlatformPkg PlatformInit modules. - # - ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/Repo= rtCpuHobLib.inf - SetCacheMtrrLib|$(RP_PKG)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf - -[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, Lib= raryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClass= es.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryCla= sses.common.UEFI_APPLICATION] - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf - - Tcg2PhysicalPresenceLib|$(RP_PKG)/Library/Tcg2PhysicalPresenceLibNull/Dx= eTcg2PhysicalPresenceLib.inf - TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/Dxe= TcgPhysicalPresenceLib.inf - - BiosIdLib|BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf - MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf - - TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf - - Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm= .inf - - TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/Test= PointCheckLibNull.inf - TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.in= f - BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.i= nf - BoardBootManagerLib|MinPlatformPkg/Bds/Library/BoardBootManagerLibNull/B= oardBootManagerLibNull.inf - - CompressDxeLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf - -[LibraryClasses.Common.DXE_SMM_DRIVER] - SpiFlashCommonLib|$(RP_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashComm= onLib.inf - TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestP= ointCheckLib.inf - TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.in= f - MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.= inf - BoardAcpiEnableLib|$(RP_PKG)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.= inf - -[LibraryClasses.Common.SMM_CORE] - S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL= ibNull.inf - -[LibraryClasses.Common] - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f - PeiLib|MinPlatformPkg/Library/PeiLib/PeiLib.inf - -[Components.IA32] - UefiCpuPkg/SecCore/SecCore.inf - - !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc - - MdeModulePkg/Universal/PCD/Pei/Pcd.inf { - - # - # Beware of circular dependencies on PCD if you want to use another = DebugLib instance. - # - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf = # Include FSP DynamicEx PCD - NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLat= eSilicon.inf # Include FvLateSilicon DynamicEx PCD - NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLat= eOpenBoard.inf # Include FvLateBoard DynamicEx PCD - } - $(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.in= f - $(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf - $(RP_PKG)/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf - - $(RP_PKG)/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei= .inf - - $(RP_PKG)/Platform/Pei/PlatformInfo/PlatformInfo.inf - $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { - - TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/= TestPointCheckLibNull.inf - BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitPreMemLib.inf - } - $(PLATFORM_PKG)/PlatformInit/ReportFv/ReportFvPei.inf - - $(PLATFORM_PKG)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf= { - - SiliconWorkaroundLib|WhitleySiliconPkg/Library/SiliconWorkaroundLibN= ull/SiliconWorkaroundLibNull.inf - } - $(RP_PKG)/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf - $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { - - TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/= TestPointCheckLibNull.inf - BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf - } - - IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf -!if ($(FSP_MODE) =3D=3D 0) - IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf - $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf -!endif - - $(RP_PKG)/BiosInfo/BiosInfo.inf - - WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf - UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf - - UefiCpuPkg/CpuMpPei/CpuMpPei.inf - - UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf { - - !if $(PERFORMANCE_ENABLE) =3D=3D TRUE - TimerLib|UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerL= ibUefiCpu.inf - !endif - } - -[Components.X64] - !include WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc - - $(RP_PKG)/Platform/Dxe/PlatformType/PlatformType.inf - - MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf - - MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf - MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf - MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf - - MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf - UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf - - ShellPkg/Application/Shell/Shell.inf { - - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf - NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf - NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf - NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf - NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf - NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf - PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf - IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf - - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 - } - - $(RP_PKG)/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf - UefiCpuPkg/CpuDxe/CpuDxe.inf - UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf - - $(RP_PKG)/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf - IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf - - $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf - - $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf - - $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf - - $(PLATFORM_PKG)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf { - - BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitDxeLib.inf - } - $(RP_PKG)/Platform/Dxe/S3NvramSave/S3NvramSave.inf { -!if ($(FSP_MODE) =3D=3D 0) - - *_*_*_CC_FLAGS =3D -D FSP_API_MODE -!endif - } - - $(PLATFORM_PKG)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf - - $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf - $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf - - MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf - MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - BoardModulePkg/LegacySioDxe/LegacySioDxe.inf - BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf - - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - - MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf - - MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf - - # - # SiliconPkg code for Platform Integration are defined here - # -!if $(CPUTARGET) =3D=3D "CPX" - DEFINE CPU_CPX_SUPPORT =3D TRUE -!else - DEFINE CPU_CPX_SUPPORT =3D FALSE -!endif -[PcdsFixedAtBuild] -!if ($(CPU_SKX_ONLY_SUPPORT) =3D=3D TRUE) - gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |FALSE -!endif -[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.UEFI_DRIVER, Libr= aryClasses.common.UEFI_APPLICATION] - ResetSystemLib|MdeModulePkg/Library/DxeResetSystemLib/DxeResetSystemLib.= inf -[LibraryClasses.common.DXE_RUNTIME_DRIVER] - ResetSystemLib|MdeModulePkg/Library/RuntimeResetSystemLib/RuntimeResetSy= stemLib.inf - - -##########################################################################= ######################### -# -# BuildOptions Section - Define the module specific tool chain flags that = should be used as -# the default flags for a module. These flags are a= ppended to any -# standard flags that are defined by the build proc= ess. They can be -# applied for any modules or only those modules wit= h the specific -# module style (EDK or EDKII) specified in [Compone= nts] section. -# -##########################################################################= ######################### -[BuildOptions.Common.EDKII] -# Append build options for EDK and EDKII drivers (=3D is Append, =3D=3D is= Replace) -!if $(CRB_FLAG_ENABLE) =3D=3D TRUE - DEFINE CRB_EDKII_BUILD_OPTIONS =3D -D CRB_FLAG -!else - DEFINE CRB_EDKII_BUILD_OPTIONS =3D -!endif - -!if $(DEBUG_FLAGS_ENABLE) =3D=3D TRUE - DEFINE EDKII_DEBUG_BUILD_OPTIONS =3D -D DEBUG_CODE_BLOCK=3D1 -D PLATFORM= _VARIABLE_ATTRIBUTES=3D0x3 -!else - DEFINE EDKII_DEBUG_BUILD_OPTIONS =3D -D SILENT_MODE -D PLATFORM_VARIABLE= _ATTRIBUTES=3D0x3 -!endif - -!if $(SPARING_SCRATCHPAD_ENABLE) =3D=3D TRUE - DEFINE SPARING_SCRATCHPAD_OPTION =3D -D SPARING_SCRATCHPAD_SUPPORT -!else - DEFINE SPARING_SCRATCHPAD_OPTIONS =3D -!endif - -!if $(SCRATCHPAD_DEBUG) =3D=3D TRUE - DEFINE SCRATCHPAD_DEBUG_OPTION =3D -D SCRATCHPAD_DEBUG -!else - DEFINE SCRATCHPAD_DEBUG_OPTION =3D -!endif - -!if $(PCH_SERVER_BIOS_ENABLE) =3D=3D TRUE - DEFINE PCH_BUILD_OPTION =3D -DPCH_SERVER_BIOS_FLAG=3D1 -!else - DEFINE PCH_BUILD_OPTION =3D -!endif - -!if $(SERVER_BIOS_ENABLE) =3D=3D TRUE - DEFINE SERVER_BUILD_OPTION =3D -DSERVER_BIOS_FLAG=3D1 -!else - DEFINE SERVER_BUILD_OPTION =3D -!endif - -DEFINE SC_PATH =3D -D SC_PATH=3D"Pch/SouthClusterLbg" - -DEFINE ME_PATH =3D -D ME_PATH=3D"Me/MeSps.4" - -DEFINE IE_PATH =3D -D IE_PATH=3D"Ie/v1" - -DEFINE NVDIMM_OPTIONS =3D - -!if $(CPUTARGET) =3D=3D "ICX" - DEFINE CPU_TYPE_OPTIONS =3D -D ICX_HOST -D A0_HOST -D B0_HOST -!elseif $(CPUTARGET) =3D=3D "CPX" - DEFINE CPU_TYPE_OPTIONS =3D -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_H= OST -D B0_HOST -!endif - -DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS =3D -D MAX_SOCKET=3D$(MAX_SOCKET) -D= MAX_CORE=3D$(MAX_CORE) -D MAX_THREAD=3D$(MAX_THREAD) - -DEFINE MRC_OPTIONS =3D -D LRDIMM_SUPPORT -D DDRT_SUPPORT - -!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D FALSE - DEFINE MAX_IMC_CH_OPTIONS =3D -D MAX_IMC=3D4 -D MAX_MC_CH=3D2 -!else - DEFINE MAX_IMC_CH_OPTIONS =3D -D MAX_IMC=3D2 -D MAX_MC_CH=3D3 -!endif - -DEFINE MAX_SAD_RULE_OPTION =3D -D MAX_SAD_RULES=3D24 -D MAX_DRAM_CLUSTERS= =3D1 - -DEFINE LT_BUILD_OPTIONS =3D -D LT_FLAG - -DEFINE FSP_BUILD_OPTIONS =3D -D FSP_DISPATCH_MODE_ENABLE=3D1 - -# -# MAX_KTI_PORTS needs to be updated based on the silicon type -# -!if $(CPUTARGET) =3D=3D "CPX" - DEFINE KTI_OPTIONS =3D -D MAX_KTI_PORTS=3D6 -!else - DEFINE KTI_OPTIONS =3D -D MAX_KTI_PORTS=3D3 -!endif - -DEFINE IIO_STACK_OPTIONS =3D -D MAX_IIO_STACK=3D6 -D MAX_LOGIC_IIO_STACK= =3D8 - -DEFINE PCH_BIOS_BUILD_OPTIONS =3D $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_= BUILD_OPTION) - -DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(CRB_EDKII_BUILD_OPTIONS) $(ED= KII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX= _SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $= (KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) = $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -= D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADD= RESS=3D0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP= _BUILD_OPTIONS) - -DEFINE IE_OPTIONS =3D $(IE_PATH) -DIE_SUPPORT=3D0 - -!if $(LINUX_GCC_BUILD) =3D=3D TRUE - DEFINE EDK2_LINUX_BUILD_OPTIONS =3D -D EDK2_CTE_BUILD -!else - DEFINE EDK2_LINUX_BUILD_OPTIONS =3D -!endif - -DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIO= NS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS) - -DEFINE ME_OPTIONS =3D -DSPS_VERSION=3D4 $(ME_PATH) - -DEFINE ASPEED_ENABLE_BUILD_OPTIONS =3D -D ASPEED_ENABLE -D ESPI_ENABLE - -DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIO= NS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS) - - MSFT:*_*_*_CC_FLAGS=3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819 - GCC:*_*_*_CC_FLAGS=3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_*_VFRPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_*_APP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_*_PP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_*_ASLPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) - *_*_*_ASLCC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) - - -# -# Enable source level debugging for RELEASE build -# -!if $(TARGET) =3D=3D "RELEASE" - DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =3D - DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =3D - DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =3D - - MSFT:*_*_*_ASM_FLAGS =3D $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi - MSFT:*_*_*_CC_FLAGS =3D $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7 - MSFT:*_*_*_DLINK_FLAGS =3D $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /= DEBUG - GCC:*_*_*_ASM_FLAGS =3D $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) - GCC:*_*_*_CC_FLAGS =3D $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) - GCC:*_*_*_DLINK_FLAGS =3D $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) -!endif - -# -# Override ASL Compiler parameters in tools_def.template. -# - MSFT:*_*_*_ASL_PATH =3D=3D $(WORKSPACE)/../FDBin/Tools/IaslCompiler/6.3/= iasl.exe - GCC:*_*_*_ASL_PATH =3D=3D $(WORKSPACE)/../FDBin/Tools/IaslCompiler/6.3/i= asl - *_*_*_ASL_FLAGS =3D=3D -vr -we -oi -# -# Override the VFR compile flags to speed the build time -# - -*_*_*_VFR_FLAGS =3D=3D -n - -# -# add to the build options for DXE/SMM drivers to remove the log message: -# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!= ! -# -[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.D= XE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] - MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 - -[BuildOptions] - GCC:*_GCC5_*_CC_FLAGS =3D -Wno-overflow -Wno-discarded-qualifiers -Wno-u= nused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types= -mabi=3Dms - GCC:*_GCC5_IA32_DLINK_FLAGS =3D -z common-page-size=3D0x20 -z muldefs - GCC:*_GCC5_X64_DLINK_FLAGS =3D -z common-page-size=3D0x20 -z muldefs - MSFT:*_*_*_CC_FLAGS =3D /FAsc +## @file +# X64 Platform with 64-bit DXE. +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D $(RP_PKG) + PLATFORM_GUID =3D D7EAF54D-C9B9-4075-89F0-71943DBC= FA61 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/$(RP_PKG) + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + VPD_TOOL_GUID =3D 8C3D856A-9BE6-468E-850A-24F7A8D3= 8E08 + FLASH_DEFINITION =3D $(RP_PKG)/PlatformPkg.fdf + PLATFORM_SI_PACKAGE =3D ClientOneSiliconPkg + DEFINE PLATFORM_SI_BIN_PACKAGE =3D WhitleySiliconBinPkg + PEI_ARCH =3D IA32 + DXE_ARCH =3D X64 + +!if $(CPUTARGET) =3D=3D "CPX" + DEFINE FSP_BIN_PKG =3D CedarIslandFspBinPkg + DEFINE IIO_INSTANCE =3D Skx +!elseif $(CPUTARGET) =3D=3D "ICX" + DEFINE FSP_BIN_PKG =3D WhitleyFspBinPkg + DEFINE IIO_INSTANCE =3D Icx +!else + DEFINE IIO_INSTANCE =3D UnknownCpu +!endif + + # + # Platform On/Off features are defined here + # + !include $(RP_PKG)/PlatformPkgConfig.dsc + + # + # MRC common configuration options defined here + # + !include $(SILICON_PKG)/MrcCommonConfig.dsc + +[Packages] + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + + !include $(FSP_BIN_PKG)/DynamicExPcd.dsc + !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc + !include $(RP_PKG)/DynamicExPcd.dsc + + !include $(RP_PKG)/Uba/UbaCommon.dsc + !include $(RP_PKG)/Uba/UbaRpBoards.dsc + + !include $(RP_PKG)/Include/Dsc/EnablePerformanceMonitoringInfrastructure= .dsc + +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this +# Platform. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. + +[DefaultStores] + 0|STANDARD + 1|MANUFACTURING + + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFeatureFlag] + # + # MinPlatform control flags + # + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE + + # don't degrade 64bit MMIO space to 32-bit + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE + + # Server doesn't support capsule update on Reset. + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE + + gEfiCpRcPkgTokenSpaceGuid.Reserved15|TRUE + +!if ($(CPUTARGET) =3D=3D "ICX") + gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|FALSE +!endif # $(CPUTARGET) =3D=3D "ICX" + + gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE + gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|TRUE + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE + gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE + + ## Uncomment for better boot performance +# gPerfOptTokenSpaceGuid.PcdPreUefiLegacyEnable|FALSE +# gPerfOptTokenSpaceGuid.PcdLocalVideoEnable|FALSE + + gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE + + ## This PCD specified whether ACPI SDT protocol is installed. + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + ## This PCD specifies whether FPGA routine will be active + gSocketPkgFpgaGuid.PcdSktFpgaActive|TRUE + +!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D TRUE + gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|FALSE + gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|TRUE +!endif + + ## This PCD specifies whether or not to enable the High Speed UART + gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE + +[PcdsFixedAtBuild] + gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption|2 + + ## MinPlatform Boot Stage Selector + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # Stage 6 - boot with advanced features enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6 + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # = Enable asserts, prints, code, clear memory, and deadloops on asserts. + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # = Built in messages: Error, MTRR, info, load, warn, init +!if $(TARGET) =3D=3D "DEBUG" + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # = This is set to INT3 (0x2) for Simics source level debugging +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000 + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL " + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4449204C45544E= 49 # "INTEL ID" + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x2100000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 + + gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x400000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gCpuPkgTokenSpaceGuid.PcdPlatformType|2 + gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 + + #PcdCpuMicrocodePatchRegionSize =3D PcdFlashNvStorageMicrocodeSize - (EF= I_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER)) + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x1FFF70 + + # + # This controls the NEM code region cached during SEC + # It usually isn't necessary to match exactly the FV layout in the FDF f= ile. + # It is a performance optimization to have it match the flash region exa= ctly + # as then no extra reads are done to load unused flash into cache. + # + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0xFFC00000 + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x00400000 + + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000 + + # + # Mode | FSP_MODE | PcdFspModeSelection + # ------------------|----------|-------------------- + # FSP Dispatch Mode | 1 | 0 + # FSP API Mode | 0 | 1 + # +!if ($(FSP_MODE) =3D=3D 0) + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000 +!else + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 +!endif + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 + + # + # These will be initialized during build + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000 + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000 + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000 + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x00000000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x00000000 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase|0x00000000 + + ## Specifies delay value in microseconds after sending out an INIT IPI. + # @Prompt Configure delay value after send an INIT IPI + gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processorss + gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 + + gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x2 + + gPlatformTokenSpaceGuid.PcdUboDev|0x08 + gPlatformTokenSpaceGuid.PcdUboFunc|0x02 + gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC + + gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|TRUE + gPlatformTokenSpaceGuid.PcdSupportLegacyStack|FALSE + + ## Defines the ACPI register set base address. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Timer IO Port Address + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500 + + ## Defines the PCI Bus Number of the PCI device that contains the BAR an= d Enable for ACPI hardware registers. + # @Prompt ACPI Hardware PCI Bus Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00 + + ## Defines the PCI Device Number of the PCI device that contains the BAR= and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to th= e real value. + # @Prompt ACPI Hardware PCI Device Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F + + ## Defines the PCI Function Number of the PCI device that contains the B= AR and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to th= e real value. + # @Prompt ACPI Hardware PCI Function Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02 + + ## Defines the PCI Register Offset of the PCI device that contains the E= nable for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Hardware PCI Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044 + + ## Defines the bit mask that must be set to enable the APIC hardware reg= ister BAR. + # @Prompt ACPI Hardware PCI Bar Enable BitMask + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80 + + ## Defines the PCI Register Offset of the PCI device that contains the B= AR for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Hardware PCI Bar Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040 + + ## Defines the offset to the 32-bit Timer Value register that resides wi= thin the ACPI BAR. + # @Prompt Offset to 32-bit Timer register in ACPI BAR + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 + +!if $(CPUTARGET) =3D=3D "ICX" + # + # ACPI PCD custom override + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013 +!endif + + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + + # Enable DDRT scheduler debug features for power on + gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault|TRUE + + # Disable Fast Warm Boot for Whitley Openboard Package + gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault|FALSE + +!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D FALSE + gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|FALSE + gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable|FALSE +!endif + + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x74 + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x75 + + # + # PlatformInitPreMem + # + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x100 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA30 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x100 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x100 + + gEfiCpRcPkgTokenSpaceGuid.PcdReserved15|0 + + !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc + +[PcdsFixedAtBuild.IA32] + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 + +!if ($(FSP_MODE) =3D=3D 0) + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000 + gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0 +!endif + +[PcdsFixedAtBuild.X64] + # Change PcdBootManagerMenuFile to UiApp + ## + + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0xC00000 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE + + # + # AcpiPlatform + # + gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24 + + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04 + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000 + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000 + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08 + + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|FALSE + + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{ 0x02= , 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x0= 1, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, = 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00,= 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01= , 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, = 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, = 0x04, 0x00, 0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, = 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00} + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{ 0x02= , 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x0= 1, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, = 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00,= 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01= , 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, = 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, = 0x04, 0x00, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, = 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF,= 0x04, 0x00} + gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x0, 0x0, 0x= 1F, 0x0} + gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x01 + +[PcdsPatchableInModule] + # + # These debug options are patcheable so that they can be manipulated dur= ing debug (if memory is updateable) + # + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 # = Enable status codes for debug, progress, and errors + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 # = Displayed messages: Error, Info, warn + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0 + +!if $(PREMEM_PAGE_ALLOC_SUPPORT) =3D=3D FALSE + gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0x130000 +!endif + +[PcdsDynamicExDefault.IA32] +!if ($(FSP_MODE) =3D=3D 0) + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000 +!endif + + +[PcdsDynamicExHii] + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|L"1GPageTable"|gEfiGene= ricVariableGuid|0x0|TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|0 # Variable: L"Timeout" + gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|L"MemoryCheck"|gPlatformT= okenSpaceGuid|0x0|0 + gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|L"UefiOptimizedBoot"|gCpPlatT= okenSpaceGuid|0x0|TRUE + gPlatformModuleTokenSpaceGuid.PcdBootState|L"BootState"|gEfiGenericVaria= bleGuid|0x0|TRUE + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" + gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|L"BootDeviceScra= tchPad"|gEfiGenericVariableGuid|0x0|FALSE + +[PcdsDynamicExDefault] + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmPhysicalPresence|TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE + gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable|FALSE + + gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE + gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE + gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE + + gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0 + gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0 + + #Platform should change it to by code + gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0xAAAA0000 + gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0xAA33AA22 + + gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE + + # + # CPU features related PCDs. + # + gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy + gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle + gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset + + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x01 + + ## Put fTPM guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, = 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } } + ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, = 0x1b, 0x90, 0xcc } } + ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x= 75, 0x8b, 0x73, 0x17 } } + + #TPM2.0# + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28= , 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} + + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|0 + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0 + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|4 + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x600C0 + + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE + gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE + + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0x102b + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0x0522 + + gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x000C + gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x0011 + gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, = 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d } + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0 + +[PcdsDynamicExDefault.X64] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 + + # + # Set video to 1024x768 resolution + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768 + +[PcdsDynamicExDefault] + +!if $(CPUTARGET) =3D=3D "CPX" + !include $(RP_PKG)/StructurePcdCpx.dsc +!else + !include $(RP_PKG)/StructurePcd.dsc +!endif + +[PcdsFeatureFlag] +!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |TRUE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |TRUE +!else + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE +!endif + +[Defines] +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE + DEFINE SECURE_BOOT_ENABLE =3D TRUE +!endif + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc + +[LibraryClasses] + + # + # Simics source level debugging requires the non-null version of PeCoffE= xtraActionLib + # +!if $(TARGET) =3D=3D "DEBUG" + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf +!endif + + # + # Basic + # + + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + # + # Framework + # + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf + + SiliconPolicyInitLib|WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/= SiliconPolicyInitLibShim.inf +!if ($(FSP_MODE) =3D=3D 0) + SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconP= olicyUpdateLibFsp.inf +!else + SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconP= olicyUpdateLib.inf +!endif + + SetupLib|WhitleySiliconPkg/Library/SetupLib/SetupLib.inf + + # + # ToDo: Can we use BaseAcpiTimerLib from MinPlatform? + # + TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf + + MultiPlatSupportLib|$(RP_PKG)/Library/MultiPlatSupportLib/MultiPlatSuppo= rtLib.inf + ReadFfsLib|$(RP_PKG)/Library/ReadFfsLib/ReadFfsLib.inf + PlatformSetupVariableSyncLib|$(RP_PKG)/Library/PlatformSetupVariableSync= LibNull/PlatformSetupVariableSyncLibNull.inf + PlatformVariableHookLib |$(RP_PKG)/Library/PlatformVariableHookLibNull/P= latformVariableHookLibNull.inf + + PlatformBootManagerLib|$(PLATFORM_PKG)/Bds/Library/DxePlatformBootManage= rLib/DxePlatformBootManagerLib.inf + SerialPortLib|$(RP_PKG)/Library/SerialPortLib/SerialPortLib.inf + PlatformHooksLib|$(RP_PKG)/Library/PlatformHooksLib/PlatformHooksLib.inf + + CmosAccessLib|BoardModulePkg/Library/CmosAccessLib/CmosAccessLib.inf + PlatformCmosAccessLib|$(RP_PKG)/Library/PlatformCmosAccessLib/PlatformCm= osAccessLib.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf + TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf + + # + # MinPlatform uses port 80, we don't want to assume HW + # + PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf + + TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull= .inf + Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN= ull.inf + AslUpdateLib|$(PLATFORM_PKG)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLi= b.inf + PciSegmentInfoLib|$(PLATFORM_PKG)/Pci/Library/PciSegmentInfoLibSimple/Pc= iSegmentInfoLibSimple.inf + PlatformOpromPolicyLib|$(RP_PKG)/Library/PlatformOpromPolicyLibNull/Plat= formOpromPolicyLibNull.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + +[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses= .Common.PEIM] + FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf + FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf + FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/Fs= pWrapperPlatformLib.inf + FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf + + FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwit= chStackLib.inf + FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf + FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLi= b.inf + +[LibraryClasses.Common.SEC] + # + # SEC phase + # + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf + + PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapp= erPlatformSecLib.inf + SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/= SecBoardInitLibNull.inf + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestP= ointCheckLib.inf + VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVaria= bleReadLibNull.inf + +[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM] + # + # ToDo: Can we remove + # + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuE= xceptionHandlerLib.inf + + MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf + + + PeiPlatformHookLib|$(RP_PKG)/Library/PeiPlatformHookLib/PeiPlatformHookl= ib.inf + PlatformClocksLib|$(RP_PKG)/Library/PlatformClocksLib/Pei/PlatformClocks= Lib.inf + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestP= ointCheckLib.inf + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.in= f + + ReportFvLib|$(RP_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf + +[LibraryClasses.Common.PEIM] + # + # Library instance consumed by MinPlatformPkg PlatformInit modules. + # + ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/Repo= rtCpuHobLib.inf + SetCacheMtrrLib|$(RP_PKG)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + + ResetSystemLib|MdeModulePkg/Library/PeiResetSystemLib/PeiResetSystemLib.= inf + +[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, Lib= raryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClass= es.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryCla= sses.common.UEFI_APPLICATION] + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + + Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/D= xeTcg2PhysicalPresenceLib.inf + TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/Dxe= TcgPhysicalPresenceLib.inf + + BiosIdLib|BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf + MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf + + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + + Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm= .inf + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/Test= PointCheckLibNull.inf + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.in= f + BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.i= nf + BoardBootManagerLib|MinPlatformPkg/Bds/Library/BoardBootManagerLibNull/B= oardBootManagerLibNull.inf + + CompressDxeLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf + +[LibraryClasses.Common.DXE_SMM_DRIVER] + SpiFlashCommonLib|$(RP_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashComm= onLib.inf + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestP= ointCheckLib.inf + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.in= f + MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.= inf + BoardAcpiEnableLib|$(RP_PKG)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.= inf + Tcg2PhysicalPresenceLib|SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/S= mmTcg2PhysicalPresenceLib.inf + +[LibraryClasses.Common.SMM_CORE] + S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL= ibNull.inf + +[LibraryClasses.Common] + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f + PeiLib|MinPlatformPkg/Library/PeiLib/PeiLib.inf + +[Components.IA32] + UefiCpuPkg/SecCore/SecCore.inf + + !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc + + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + # + # Beware of circular dependencies on PCD if you want to use another = DebugLib instance. + # + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf = # Include FSP DynamicEx PCD + NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLat= eSilicon.inf # Include FvLateSilicon DynamicEx PCD + NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLat= eOpenBoard.inf # Include FvLateBoard DynamicEx PCD + } + $(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.in= f + $(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf + $(RP_PKG)/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf + + $(RP_PKG)/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei= .inf + + $(RP_PKG)/Platform/Pei/PlatformInfo/PlatformInfo.inf + $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/= TestPointCheckLibNull.inf + BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitPreMemLib.inf + } + $(PLATFORM_PKG)/PlatformInit/ReportFv/ReportFvPei.inf + + $(PLATFORM_PKG)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf= { + + SiliconWorkaroundLib|WhitleySiliconPkg/Library/SiliconWorkaroundLibN= ull/SiliconWorkaroundLibNull.inf + } + $(RP_PKG)/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf + $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/= TestPointCheckLibNull.inf + BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf + } + + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +!if ($(FSP_MODE) =3D=3D 0) + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf + $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf +!endif + + $(RP_PKG)/BiosInfo/BiosInfo.inf + + WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + + UefiCpuPkg/CpuMpPei/CpuMpPei.inf + + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf { + + !if $(PERFORMANCE_ENABLE) =3D=3D TRUE + TimerLib|UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerL= ibUefiCpu.inf + !endif + } + +[Components.X64] + !include WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc + + $(RP_PKG)/Platform/Dxe/PlatformType/PlatformType.inf + + MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf + + MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf + + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + + $(RP_PKG)/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf + UefiCpuPkg/CpuDxe/CpuDxe.inf + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + + $(RP_PKG)/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf + IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf + + $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf + + $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf + + $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf + + $(PLATFORM_PKG)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf { + + BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitDxeLib.inf + } + $(RP_PKG)/Platform/Dxe/S3NvramSave/S3NvramSave.inf { +!if ($(FSP_MODE) =3D=3D 0) + + *_*_*_CC_FLAGS =3D -D FSP_API_MODE +!endif + } + + $(PLATFORM_PKG)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + + $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf + $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf + + MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + BoardModulePkg/LegacySioDxe/LegacySioDxe.inf + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf + + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + + # + # SiliconPkg code for Platform Integration are defined here + # +!if $(CPUTARGET) =3D=3D "CPX" + DEFINE CPU_CPX_SUPPORT =3D TRUE +!else + DEFINE CPU_CPX_SUPPORT =3D FALSE +!endif +[PcdsFixedAtBuild] +!if ($(CPU_SKX_ONLY_SUPPORT) =3D=3D TRUE) + gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |FALSE +!endif +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.UEFI_DRIVER, Libr= aryClasses.common.UEFI_APPLICATION] + ResetSystemLib|MdeModulePkg/Library/DxeResetSystemLib/DxeResetSystemLib.= inf +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + ResetSystemLib|MdeModulePkg/Library/RuntimeResetSystemLib/RuntimeResetSy= stemLib.inf + + +##########################################################################= ######################### +# +# BuildOptions Section - Define the module specific tool chain flags that = should be used as +# the default flags for a module. These flags are a= ppended to any +# standard flags that are defined by the build proc= ess. They can be +# applied for any modules or only those modules wit= h the specific +# module style (EDK or EDKII) specified in [Compone= nts] section. +# +##########################################################################= ######################### +[BuildOptions.Common.EDKII] +# Append build options for EDK and EDKII drivers (=3D is Append, =3D=3D is= Replace) +!if $(CRB_FLAG_ENABLE) =3D=3D TRUE + DEFINE CRB_EDKII_BUILD_OPTIONS =3D -D CRB_FLAG +!else + DEFINE CRB_EDKII_BUILD_OPTIONS =3D +!endif + +!if $(DEBUG_FLAGS_ENABLE) =3D=3D TRUE + DEFINE EDKII_DEBUG_BUILD_OPTIONS =3D -D DEBUG_CODE_BLOCK=3D1 -D PLATFORM= _VARIABLE_ATTRIBUTES=3D0x3 +!else + DEFINE EDKII_DEBUG_BUILD_OPTIONS =3D -D SILENT_MODE -D PLATFORM_VARIABLE= _ATTRIBUTES=3D0x3 +!endif + +!if $(SPARING_SCRATCHPAD_ENABLE) =3D=3D TRUE + DEFINE SPARING_SCRATCHPAD_OPTION =3D -D SPARING_SCRATCHPAD_SUPPORT +!else + DEFINE SPARING_SCRATCHPAD_OPTIONS =3D +!endif + +!if $(SCRATCHPAD_DEBUG) =3D=3D TRUE + DEFINE SCRATCHPAD_DEBUG_OPTION =3D -D SCRATCHPAD_DEBUG +!else + DEFINE SCRATCHPAD_DEBUG_OPTION =3D +!endif + +!if $(PCH_SERVER_BIOS_ENABLE) =3D=3D TRUE + DEFINE PCH_BUILD_OPTION =3D -DPCH_SERVER_BIOS_FLAG=3D1 +!else + DEFINE PCH_BUILD_OPTION =3D +!endif + +!if $(SERVER_BIOS_ENABLE) =3D=3D TRUE + DEFINE SERVER_BUILD_OPTION =3D -DSERVER_BIOS_FLAG=3D1 +!else + DEFINE SERVER_BUILD_OPTION =3D +!endif + +DEFINE SC_PATH =3D -D SC_PATH=3D"Pch/SouthClusterLbg" + +DEFINE ME_PATH =3D -D ME_PATH=3D"Me/MeSps.4" + +DEFINE IE_PATH =3D -D IE_PATH=3D"Ie/v1" + +DEFINE NVDIMM_OPTIONS =3D + +!if $(CPUTARGET) =3D=3D "ICX" + DEFINE CPU_TYPE_OPTIONS =3D -D ICX_HOST -D A0_HOST -D B0_HOST +!elseif $(CPUTARGET) =3D=3D "CPX" + DEFINE CPU_TYPE_OPTIONS =3D -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_H= OST -D B0_HOST +!endif + +DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS =3D -D MAX_SOCKET=3D$(MAX_SOCKET) -D= MAX_CORE=3D$(MAX_CORE) -D MAX_THREAD=3D$(MAX_THREAD) + +DEFINE MRC_OPTIONS =3D -D LRDIMM_SUPPORT -D DDRT_SUPPORT + +!if $(CPU_SKX_ONLY_SUPPORT) =3D=3D FALSE + DEFINE MAX_IMC_CH_OPTIONS =3D -D MAX_IMC=3D4 -D MAX_MC_CH=3D2 +!else + DEFINE MAX_IMC_CH_OPTIONS =3D -D MAX_IMC=3D2 -D MAX_MC_CH=3D3 +!endif + +DEFINE MAX_SAD_RULE_OPTION =3D -D MAX_SAD_RULES=3D24 -D MAX_DRAM_CLUSTERS= =3D1 + +DEFINE LT_BUILD_OPTIONS =3D -D LT_FLAG + +DEFINE FSP_BUILD_OPTIONS =3D -D FSP_DISPATCH_MODE_ENABLE=3D1 + +# +# MAX_KTI_PORTS needs to be updated based on the silicon type +# +!if $(CPUTARGET) =3D=3D "CPX" + DEFINE KTI_OPTIONS =3D -D MAX_KTI_PORTS=3D6 +!else + DEFINE KTI_OPTIONS =3D -D MAX_KTI_PORTS=3D3 +!endif + +DEFINE IIO_STACK_OPTIONS =3D -D MAX_IIO_STACK=3D6 -D MAX_LOGIC_IIO_STACK= =3D8 + +DEFINE PCH_BIOS_BUILD_OPTIONS =3D $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_= BUILD_OPTION) + +DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(CRB_EDKII_BUILD_OPTIONS) $(ED= KII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX= _SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $= (KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) = $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -= D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADD= RESS=3D0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP= _BUILD_OPTIONS) + +DEFINE IE_OPTIONS =3D $(IE_PATH) -DIE_SUPPORT=3D0 + +!if $(LINUX_GCC_BUILD) =3D=3D TRUE + DEFINE EDK2_LINUX_BUILD_OPTIONS =3D -D EDK2_CTE_BUILD +!else + DEFINE EDK2_LINUX_BUILD_OPTIONS =3D +!endif + +DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIO= NS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS) + +DEFINE ME_OPTIONS =3D -DSPS_VERSION=3D4 $(ME_PATH) + +DEFINE ASPEED_ENABLE_BUILD_OPTIONS =3D -D ASPEED_ENABLE -D ESPI_ENABLE + +DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIO= NS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS) + + MSFT:*_*_*_CC_FLAGS=3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819 + GCC:*_*_*_CC_FLAGS=3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_VFRPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_APP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_PP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_ASLPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_*_ASLCC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + + +# +# Enable source level debugging for RELEASE build +# +!if $(TARGET) =3D=3D "RELEASE" + DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =3D + DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =3D + DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =3D + + MSFT:*_*_*_ASM_FLAGS =3D $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi + MSFT:*_*_*_CC_FLAGS =3D $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7 + MSFT:*_*_*_DLINK_FLAGS =3D $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /= DEBUG + GCC:*_*_*_ASM_FLAGS =3D $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) + GCC:*_*_*_CC_FLAGS =3D $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) + GCC:*_*_*_DLINK_FLAGS =3D $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) +!endif + +# +# Override ASL Compiler parameters in tools_def.template. +# + *_*_*_ASL_FLAGS =3D=3D -vr -we -oi +# +# Override the VFR compile flags to speed the build time +# + +*_*_*_VFR_FLAGS =3D=3D -n + +# +# add to the build options for DXE/SMM drivers to remove the log message: +# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!= ! +# +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.D= XE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 + +[BuildOptions] + GCC:*_GCC5_*_CC_FLAGS =3D -Wno-overflow -Wno-discarded-qualifiers -Wno-u= nused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types= -mabi=3Dms + GCC:*_GCC5_IA32_DLINK_FLAGS =3D -z common-page-size=3D0x20 -z muldefs + GCC:*_GCC5_X64_DLINK_FLAGS =3D -z common-page-size=3D0x20 -z muldefs + MSFT:*_*_*_CC_FLAGS =3D /FAsc diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInit= Dxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c index 212103f483..498526c856 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c @@ -1,97 +1,108 @@ -/** @file - BOARD INIT DXE Driver. - - @copyright - Copyright 2014 - 2021 Intel Corporation. - - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include "BoardInitDxe.h" -#include - -/** - The Driver Entry Point. - - The function is the driver Entry point. - - @param ImageHandle A handle for the image that is initializing this dr= iver - @param SystemTable A pointer to the EFI system table - - @retval EFI_SUCCESS: Driver initialized successfully - @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d - @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources - -**/ -EFI_STATUS -EFIAPI -BoardInitDxeDriverEntry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable -) -{ - EFI_STATUS Status =3D EFI_SUCCESS; - UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; - UINT32 PlatformType =3D 0; - EFI_HANDLE Handle =3D NULL; - - Status =3D gBS->LocateProtocol ( - &gUbaConfigDatabaseProtocolGuid, - NULL, - &UbaConfigProtocol - ); - if (EFI_ERROR(Status)) { - return Status; - } - - Status =3D UbaConfigProtocol->GetSku( - UbaConfigProtocol, - &PlatformType, - NULL, - NULL - ); - ASSERT_EFI_ERROR (Status); - - DEBUG ((DEBUG_INFO, "Uba init Dxe driver:PlatformType=3D%d\n", PlatformT= ype)); - - //according to the platform type to install different dummy maker. - //later, the PEIM will be loaded by the dependency. - switch(PlatformType) - { - case TypeWilsonCityRP: - Status =3D gBS->InstallProtocolInterface ( - &Handle, - &gEfiPlatformTypeWilsonCityRPProtocolGuid, - EFI_NATIVE_INTERFACE, - NULL - ); - ASSERT_EFI_ERROR (Status); - break; - - case TypeWilsonCitySMT: - Status =3D gBS->InstallProtocolInterface( - &Handle, - &gEfiPlatformTypeWilsonCitySMTProtocolGuid, - EFI_NATIVE_INTERFACE, - NULL - ); - ASSERT_EFI_ERROR(Status); - break; - - case TypeCooperCityRP: - Status =3D gBS->InstallProtocolInterface ( - &Handle, - &gEfiPlatformTypeCooperCityRPProtocolGuid, - EFI_NATIVE_INTERFACE, - NULL - ); - ASSERT_EFI_ERROR (Status); - break; - - default: - // CAN'T GO TO HERE. - ASSERT (FALSE); - } - - return Status; -} +/** @file + BOARD INIT DXE Driver. + + @copyright + Copyright 2014 - 2021 Intel Corporation. + Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitDxe.h" +#include + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +BoardInitDxeDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + UINT32 PlatformType =3D 0; + EFI_HANDLE Handle =3D NULL; + + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->GetSku( + UbaConfigProtocol, + &PlatformType, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Uba init Dxe driver:PlatformType=3D%d\n", PlatformT= ype)); + + //according to the platform type to install different dummy maker. + //later, the PEIM will be loaded by the dependency. + switch(PlatformType) + { + case TypeWilsonCityRP: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeWilsonCityRPProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + + case TypeWilsonCitySMT: + Status =3D gBS->InstallProtocolInterface( + &Handle, + &gEfiPlatformTypeWilsonCitySMTProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR(Status); + break; + + case TypeCooperCityRP: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeCooperCityRPProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + + case TypeJunctionCity: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeJunctionCityProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + + default: + // CAN'T GO TO HERE. + ASSERT (FALSE); + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInit= Dxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe= .inf index 206d95658a..01dc8a9697 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf @@ -1,70 +1,72 @@ -## @file -# Uba init for multi-boards support in DXE phase. -# -# @copyright -# Copyright 2014 - 2021 Intel Corporation. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D BoardInitDxe - FILE_GUID =3D 69E6DD6D-F09E-485f-9627-EB70E9CFC82A - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - - ENTRY_POINT =3D BoardInitDxeDriverEntry - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 -# - -[Sources] - BoardInitDxe.c - BoardInitDxe.h - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - - -[LibraryClasses] - DebugLib - IoLib - HobLib - UefiLib - BaseLib - BaseMemoryLib - MemoryAllocationLib - DebugLib - UefiBootServicesTableLib - UefiRuntimeServicesTableLib - UefiDriverEntryPoint - PrintLib - -[Guids] - -[Protocols] - gUbaConfigDatabaseProtocolGuid #CONSUMER - gEfiPlatformTypeNeonCityEPRPProtocolGuid #PRODUCER - gEfiPlatformTypeHedtCRBProtocolGuid #PRODUCER - gEfiPlatformTypeLightningRidgeEXRPProtocolGuid #PRODUCER - gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid #PRODUCER - gEfiPlatformTypeWilsonCityRPProtocolGuid #PRODUCER - gEfiPlatformTypeWilsonCityModularProtocolGuid #PRODUCER - gEfiPlatformTypeIsoscelesPeakProtocolGuid #PRODUCER - gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER - gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER - -[FixedPcd] - gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount - -[Depex] - gUbaConfigDatabaseProtocolGuid +## @file +# Uba init for multi-boards support in DXE phase. +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation. +# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardInitDxe + FILE_GUID =3D 69E6DD6D-F09E-485f-9627-EB70E9CFC82A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D BoardInitDxeDriverEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + BoardInitDxe.c + BoardInitDxe.h + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + + +[LibraryClasses] + DebugLib + IoLib + HobLib + UefiLib + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiDriverEntryPoint + PrintLib + +[Guids] + +[Protocols] + gUbaConfigDatabaseProtocolGuid #CONSUMER + gEfiPlatformTypeNeonCityEPRPProtocolGuid #PRODUCER + gEfiPlatformTypeHedtCRBProtocolGuid #PRODUCER + gEfiPlatformTypeLightningRidgeEXRPProtocolGuid #PRODUCER + gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid #PRODUCER + gEfiPlatformTypeWilsonCityRPProtocolGuid #PRODUCER + gEfiPlatformTypeWilsonCityModularProtocolGuid #PRODUCER + gEfiPlatformTypeIsoscelesPeakProtocolGuid #PRODUCER + gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER + gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER + gEfiPlatformTypeJunctionCityProtocolGuid #PRODUCER + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Depex] + gUbaConfigDatabaseProtocolGuid diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index 2827334797..9a811fa3d0 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -1,69 +1,70 @@ -# @ build.cfg -# This is the main/default build configuration file -# -# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
-# Copyright (c) 2021, American Megatrends International LLC.
-# SPDX-License-Identifier: BSD-2-Clause-Patent -# - - -[DEFAULT_CONFIG] -WORKSPACE =3D -WORKSPACE_FSP_BIN =3D FSP -EDK_TOOLS_BIN =3D edk2-BaseTools-win32 -EDK_BASETOOLS =3D BaseTools -WORKSPACE_DRIVERS =3D edk2-platforms/Drivers -WORKSPACE_FEATURES =3D edk2-platforms/Features/Intel -WORKSPACE_PLATFORM =3D edk2-platforms/Platform/Intel -WORKSPACE_SILICON =3D edk2-platforms/Silicon/Intel -WORKSPACE_PLATFORM_BIN =3D -WORKSPACE_SILICON_BIN =3D edk2-non-osi/Silicon/Intel -MIN_PACKAGE_TOOLS =3D edk2-platforms/Platform/Intel/MinPlatformPkg/Tools -PACKAGES_PATH =3D -EDK_SETUP_OPTION =3D -BASE_TOOLS_PATH =3D edk2/BaseTools -EDK_TOOLS_PATH =3D edk2/BaseTools -openssl_path =3D -PLATFORM_BOARD_PACKAGE =3D -BIOS_SIZE_OPTION =3D -DBIOS_SIZE_OPTION=3DSIZE_70 -WORKSPACE_CORE =3D edk2 -EFI_SOURCE =3D edk2 -PATHEXT =3D .COM;.EXE;.BAT;.CMD;.VBS;.JS;.WS;.MSC -PROMPT =3D $P$G -PLATFORM_PACKAGE =3D MinPlatformPkg -BOARD =3D -PrepRELEASE =3D DEBUG -SILENT_MODE =3D FALSE -EXT_CONFIG_CLEAR =3D -CapsuleBuild =3D FALSE -EXT_BUILD_FLAGS =3D -CAPSULE_BUILD =3D 0 -TARGET =3D DEBUG -TARGET_SHORT =3D D -PERFORMANCE_BUILD =3D FALSE -FSP_WRAPPER_BUILD =3D FALSE -FSP_BIN_PKG =3D -FSP_PKG_NAME =3D -FSP_BINARY_BUILD =3D FALSE -FSP_TEST_RELEASE =3D FALSE -SECURE_BOOT_ENABLE =3D FALSE -REBUILD_MODE =3D -BUILD_ROM_ONLY =3D -NUMBER_OF_PROCESSORS =3D 0 -BIOS_INFO_GUID =3D - - -[PLATFORMS] -# board_name =3D path_to_board_build_config.cfg -BoardMtOlympus =3D PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg -BoardX58Ich10 =3D SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg -AspireVn7Dash572G =3D KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.= cfg -GalagoPro3 =3D KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg -KabylakeRvp3 =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg -UpXtreme =3D WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg -WhiskeylakeURvp =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.c= fg -CometlakeURvp =3D CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg -TigerlakeURvp =3D TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg -CooperCityRvp =3D WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg -WilsonCityRvp =3D WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg -BoardTiogaPass =3D PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg +# @ build.cfg +# This is the main/default build configuration file +# +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2021, American Megatrends International LLC.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[DEFAULT_CONFIG] +WORKSPACE =3D +WORKSPACE_FSP_BIN =3D FSP +EDK_TOOLS_BIN =3D edk2-BaseTools-win32 +EDK_BASETOOLS =3D BaseTools +WORKSPACE_DRIVERS =3D edk2-platforms/Drivers +WORKSPACE_FEATURES =3D edk2-platforms/Features/Intel +WORKSPACE_PLATFORM =3D edk2-platforms/Platform/Intel +WORKSPACE_SILICON =3D edk2-platforms/Silicon/Intel +WORKSPACE_PLATFORM_BIN =3D +WORKSPACE_SILICON_BIN =3D edk2-non-osi/Silicon/Intel +MIN_PACKAGE_TOOLS =3D edk2-platforms/Platform/Intel/MinPlatformPkg/Tools +PACKAGES_PATH =3D +EDK_SETUP_OPTION =3D +BASE_TOOLS_PATH =3D edk2/BaseTools +EDK_TOOLS_PATH =3D edk2/BaseTools +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D +BIOS_SIZE_OPTION =3D -DBIOS_SIZE_OPTION=3DSIZE_70 +WORKSPACE_CORE =3D edk2 +EFI_SOURCE =3D edk2 +PATHEXT =3D .COM;.EXE;.BAT;.CMD;.VBS;.JS;.WS;.MSC +PROMPT =3D $P$G +PLATFORM_PACKAGE =3D MinPlatformPkg +BOARD =3D +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D FALSE +FSP_BIN_PKG =3D +FSP_PKG_NAME =3D +FSP_BINARY_BUILD =3D FALSE +FSP_TEST_RELEASE =3D FALSE +SECURE_BOOT_ENABLE =3D FALSE +REBUILD_MODE =3D +BUILD_ROM_ONLY =3D +NUMBER_OF_PROCESSORS =3D 0 +BIOS_INFO_GUID =3D + + +[PLATFORMS] +# board_name =3D path_to_board_build_config.cfg +BoardMtOlympus =3D PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg +BoardX58Ich10 =3D SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg +AspireVn7Dash572G =3D KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.= cfg +GalagoPro3 =3D KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg +KabylakeRvp3 =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg +UpXtreme =3D WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg +WhiskeylakeURvp =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.c= fg +CometlakeURvp =3D CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg +TigerlakeURvp =3D TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg +CooperCityRvp =3D WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg +WilsonCityRvp =3D WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg +BoardTiogaPass =3D PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg +JunctionCity =3D WhitleyOpenBoardPkg/JunctionCity/build_config.cfg diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/= Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h index ca91434663..8a8a5c8bc0 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h @@ -1,106 +1,108 @@ -/** @file - - @copyright - Copyright 2020 - 2021 Intel Corporation.
- - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#ifndef _PLATFORM_INFO_TYPES_H_ -#define _PLATFORM_INFO_TYPES_H_ - -// -// DIMM Connector type -// -typedef enum { - DimmConnectorPth =3D 0x00, // Through hole connector - DimmConnectorSmt, // Surface mount connector - DimmConnectorMemoryDown, // Platform soldered DRAMs - DimmConnectorIgnore, // Ignore connector type - DimmConnectorMax -} EFI_MEMORY_DIMM_CONNECTOR_TYPE; - -// -// Platform types - used with EFI_PLATFORM_INFO BoardId -// -typedef enum { - StartOfEfiPlatformTypeEnum =3D 0x00, - //For PPO - TypeNeonCityEPRP, - TypeWolfPass, - TypeTennesseePass, - TypeHedtCRB, - TypeLightningRidgeEXRP, - TypeLightningRidgeEX8S1N, - TypeBarkPeak, - TypeYubaCityRP, - TypeRidgeport, - //End PPO - TypeWilsonCityRP, - TypeWilsonCityModular, - TypeCoyotePass, - TypeIdaville, - TypeMoroCityRP, - TypeBrightonCityRp, - TypeJacobsville, - TypeSnrSvp, - TypeSnrSvpSodimm, - TypeJacobsvilleMDV, - TypeFrostCreekRP, - TypeVictoriaCanyonRP, - TypeArcherCityRP, - TypeNeonCityEPECB, - TypeIsoscelesPeak, - TypeWilsonPointRP, - TypeWilsonPointModular, - TypeBretonSound, - TypeWilsonCityPPV, - TypeCooperCityRP, - TypeWilsonCitySMT, - TypeSnrSvpSodimmB, - TypeArcherCityModular, - TypeArcherCityEVB, - TypeArcherCityXPV, - TypeBigPineKey, - TypeExperWorkStationRP, - EndOfEfiPlatformTypeEnum -} EFI_PLATFORM_TYPE; - -#define TypePlatformUnknown 0xFF -#define TypePlatformMin StartOfEfiPlatformTypeEnum + 1 -#define TypePlatformMax EndOfEfiPlatformTypeEnum - 1 -#define TypePlatformDefault TypeWilsonPointRP - -// -// CPU type: Standard (no MCP), -F, etc -// -typedef enum { - CPU_TYPE_STD, - CPU_TYPE_F, - CPU_TYPE_P, - CPU_TYPE_MAX -} CPU_TYPE; - -#define CPU_TYPE_STD_MASK (1 << CPU_TYPE_STD) -#define CPU_TYPE_F_MASK (1 << CPU_TYPE_F) -#define CPU_TYPE_P_MASK (1 << CPU_TYPE_P) - -typedef enum { - DaisyChainTopology =3D 0x00, - InvSlotsDaisyChainTopology, - TTopology -} EFI_MEMORY_TOPOLOGY_TYPE; - -// -// Values for SocketConfig -// - -#define SOCKET_UNDEFINED 0 -#define SOCKET_4S 1 -#define SOCKET_HEDT 2 -#define SOCKET_1S 3 -#define SOCKET_1SWS 4 -#define SOCKET_8S 5 -#define SOCKET_2S 6 - -#endif // #ifndef _PLATFORM_INFO_TYPES_H_ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_INFO_TYPES_H_ +#define _PLATFORM_INFO_TYPES_H_ + +// +// DIMM Connector type +// +typedef enum { + DimmConnectorPth =3D 0x00, // Through hole connector + DimmConnectorSmt, // Surface mount connector + DimmConnectorMemoryDown, // Platform soldered DRAMs + DimmConnectorIgnore, // Ignore connector type + DimmConnectorMax +} EFI_MEMORY_DIMM_CONNECTOR_TYPE; + +// +// Platform types - used with EFI_PLATFORM_INFO BoardId +// +typedef enum { + StartOfEfiPlatformTypeEnum =3D 0x00, + //For PPO + TypeNeonCityEPRP, + TypeWolfPass, + TypeTennesseePass, + TypeHedtCRB, + TypeLightningRidgeEXRP, + TypeLightningRidgeEX8S1N, + TypeBarkPeak, + TypeYubaCityRP, + TypeRidgeport, + //End PPO + TypeWilsonCityRP, + TypeWilsonCityModular, + TypeCoyotePass, + TypeIdaville, + TypeMoroCityRP, + TypeBrightonCityRp, + TypeJacobsville, + TypeSnrSvp, + TypeSnrSvpSodimm, + TypeJacobsvilleMDV, + TypeFrostCreekRP, + TypeVictoriaCanyonRP, + TypeArcherCityRP, + TypeNeonCityEPECB, + TypeIsoscelesPeak, + TypeWilsonPointRP, + TypeWilsonPointModular, + TypeBretonSound, + TypeWilsonCityPPV, + TypeCooperCityRP, + TypeWilsonCitySMT, + TypeSnrSvpSodimmB, + TypeArcherCityModular, + TypeArcherCityEVB, + TypeArcherCityXPV, + TypeBigPineKey, + TypeExperWorkStationRP, + TypeJunctionCity, + EndOfEfiPlatformTypeEnum +} EFI_PLATFORM_TYPE; + +#define TypePlatformUnknown 0xFF +#define TypePlatformMin StartOfEfiPlatformTypeEnum + 1 +#define TypePlatformMax EndOfEfiPlatformTypeEnum - 1 +#define TypePlatformDefault TypeWilsonPointRP + +// +// CPU type: Standard (no MCP), -F, etc +// +typedef enum { + CPU_TYPE_STD, + CPU_TYPE_F, + CPU_TYPE_P, + CPU_TYPE_MAX +} CPU_TYPE; + +#define CPU_TYPE_STD_MASK (1 << CPU_TYPE_STD) +#define CPU_TYPE_F_MASK (1 << CPU_TYPE_F) +#define CPU_TYPE_P_MASK (1 << CPU_TYPE_P) + +typedef enum { + DaisyChainTopology =3D 0x00, + InvSlotsDaisyChainTopology, + TTopology +} EFI_MEMORY_TOPOLOGY_TYPE; + +// +// Values for SocketConfig +// + +#define SOCKET_UNDEFINED 0 +#define SOCKET_4S 1 +#define SOCKET_HEDT 2 +#define SOCKET_1S 3 +#define SOCKET_1SWS 4 +#define SOCKET_8S 5 +#define SOCKET_2S 6 + +#endif // #ifndef _PLATFORM_INFO_TYPES_H_ -- 2.25.0.windows.1 Please consider the environment before printing this email. The information contained in this message may be confidential and proprieta= ry to American Megatrends (AMI). This communication is intended to be read= only by the individual or entity to whom it is addressed or by their desig= nee. If the reader of this message is not the intended recipient, you are o= n notice that any distribution of this message, in any form, is strictly pr= ohibited. Please promptly notify the sender by reply e-mail or by telephon= e at 770-246-8600, and then delete or destroy all copies of the transmissio= n.