Re: [edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64

["Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>]

Looks good to me. Please get RB by atleast one of the Pkg maintainers. 
With that:
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>

-----Original Message-----
From: Kuo, Ted <ted.kuo@intel.com> 
Sent: Tuesday, January 2, 2024 1:41 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Dong, Eric <eric.dong@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com>; Duggapu, Chinni B <chinni.b.duggapu@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>
Subject: [edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64

https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common files to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
 - PcdFspWrapperBfvforResetVectorInFsp
 - PcdFsptUpdHeaderRevision
 - PcdFsptArchUpdRevision

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
---
 .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h |  25 ++-
 .../Ia32/SecEntry.nasm                        |   4 +-
 .../SecFspWrapperPlatformSecLib.inf           |   9 +-
 ...pWrapperPlatformSecLibResetVectorInFsp.inf | 101 +++++++++
 .../SecGetPerformance.c                       |  11 +-
 .../SecPlatformInformation.c                  |   8 +-
 .../SecRamInitData.c                          |  73 +++++--
 .../X64/PeiCoreEntry.nasm                     | 202 ++++++++++++++++++
 .../X64/SecEntry.nasm                         |  71 ++++++
 .../X64/Stack.nasm                            |  72 +++++++
 .../Ia32 => Include}/Fsp.h                    |   6 +-
 .../Intel/MinPlatformPkg/MinPlatformPkg.dec   |  17 +-
 12 files changed, 565 insertions(+), 34 deletions(-)  create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf
 create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
 create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
 create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
 rename Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32 => Include}/Fsp.h (79%)

diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..24c18f25b8 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
 /** @file -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent  **/@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
  #pragma pack(1) +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1 /** Fsp T Core UPD **/ typedef struct {@@ -34,6 +35,28 @@ typedef struct {
 **/   UINT8                       Reserved[16]; } FSPT_CORE_UPD;+#else+/** Fsp T Core UPD+**/+typedef struct {++/** Offset 0x0040+**/+  EFI_PHYSICAL_ADDRESS        MicrocodeRegionBase;++/** Offset 0x0048+**/+  UINT64                      MicrocodeRegionSize;++/** Offset 0x0050+**/+  EFI_PHYSICAL_ADDRESS        CodeRegionBase;++/** Offset 0x0058+**/+  UINT64                      CodeRegionSize;+} FSPT_CORE_UPD;+#endif  #pragma pack() diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..0b3f343991 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------ ;-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+; Copyright (c) 2019 - 2024, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@  ; ;------------------------------------------------------------------------------ -#include "Fsp.h"+#include <Fsp.h>  SECTION .text diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..6806e000ce 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
 ## @file-#  Provide FSP wrapper platform sec related function.+#  Provide FSP wrapper platform sec related function for IA32. #-#  Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>+#  Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -25,7 +25,7 @@
 # # The following information is for reference only and not required by the build tools. #-#  VALID_ARCHITECTURES           = IA32 X64+#  VALID_ARCHITECTURES           = IA32 #  ################################################################################@@ -47,7 +47,6 @@
   Ia32/SecEntry.nasm   Ia32/PeiCoreEntry.nasm   Ia32/Stack.nasm-  Ia32/Fsp.h  ################################################################################ #@@ -96,3 +95,5 @@
   gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress                  ## CONSUMES   gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection                 ## CONSUMES   gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain       ## CONSUMES+  gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision              ## CONSUMES+  gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision                ## CONSUMESdiff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf
new file mode 100644
index 0000000000..ea062cfad1
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf
@@ -0,0 +1,101 @@
+## @file+#  Provide FSP wrapper platform sec related function for X64.+#+#  Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+#+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+#+##++################################################################################+#+# Defines Section - statements that will be processed to create a Makefile.+#+################################################################################+[Defines]+  INF_VERSION                    = 0x00010005+  BASE_NAME                      = SecFspWrapperPlatformSecLib+  FILE_GUID                      = 94D8AA5C-5BAE-421F-B2C7-DD1A93BB4D3D+  MODULE_TYPE                    = SEC+  VERSION_STRING                 = 1.0+  LIBRARY_CLASS                  = PlatformSecLib+++#+# The following information is for reference only and not required by the build tools.+# This library is only supported in X64 when reset vector is in FSP.+#+#  VALID_ARCHITECTURES           = X64+#++################################################################################+#+# Sources Section - list of files that are required for the build to succeed.+#+################################################################################++[Sources]+  FspWrapperPlatformSecLib.c+  SecRamInitData.c+  SecPlatformInformation.c+  SecGetPerformance.c+  SecTempRamDone.c+  PlatformInit.c+  FsptCoreUpd.h++[Sources.X64]+  X64/SecEntry.nasm+  X64/PeiCoreEntry.nasm+  X64/Stack.nasm++################################################################################+#+# Package Dependency Section - list of Package files that are required for+#                              this module.+#+################################################################################++[Packages]+  MdePkg/MdePkg.dec+  MdeModulePkg/MdeModulePkg.dec+  UefiCpuPkg/UefiCpuPkg.dec+  IntelFsp2Pkg/IntelFsp2Pkg.dec+  IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec+  MinPlatformPkg/MinPlatformPkg.dec++[LibraryClasses]+  LocalApicLib+  SerialPortLib+  FspWrapperPlatformLib+  FspWrapperApiLib+  SecBoardInitLib+  TestPointCheckLib+  PeiServicesTablePointerLib++[Ppis]+  gEfiSecPlatformInformationPpiGuid       ## CONSUMES+  gPeiSecPerformancePpiGuid               ## CONSUMES+  gTopOfTemporaryRamPpiGuid               ## PRODUCES+  gEfiPeiFirmwareVolumeInfoPpiGuid        ## PRODUCES+  gFspTempRamExitPpiGuid                  ## CONSUMES+  gPlatformInitTempRamExitPpiGuid         ## CONSUMES++[Pcd]+  gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize               ## CONSUMES+  gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress                  ## CONSUMES+  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize                  ## CONSUMES+  gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable           ## CONSUMES++[FixedPcd]+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase               ## CONSUMES+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize               ## CONSUMES+  gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv                ## CONSUMES+  gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress            ## CONSUMES+  gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize               ## CONSUMES+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress                  ## CONSUMES+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection                 ## CONSUMES+  gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain       ## CONSUMES+  gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp   ## CONSUMES+  gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision              ## CONSUMES+  gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision                ## CONSUMESdiff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
index ac2deeabec..1699bd9710 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/SecGetPerformance.c
@@ -1,7 +1,7 @@
 /** @file   Sample to provide SecGetPerformance function. -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent  **/@@ -58,6 +58,7 @@ SecGetPerformance (
   if (EFI_ERROR (Status)) {     return EFI_NOT_FOUND;   }+   //   // |--------------| <- TopOfTemporaryRam - BL   // |   List Ptr   |@@ -77,12 +78,12 @@ SecGetPerformance (
   // |  TSC[31:00]  |   // |--------------|   //-  TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);-  TopOfTemporaryRam -= sizeof (UINT32) * 2;-  Count             = *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32));+  TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINTN);+  TopOfTemporaryRam -= sizeof(UINTN) * 2;+  Count             = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));   Size              = Count * sizeof (UINT32); -  Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);+  Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT64));   Performance->ResetEnd = GetTimeInNanoSecond (Ticker);    return EFI_SUCCESS;diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
index 24d55ed838..4cbde95c2d 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/SecPlatformInformation.c
@@ -1,7 +1,7 @@
 /** @file   Provide SecPlatformInformation function. -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent  **/@@ -59,9 +59,9 @@ SecPlatformInformation (
   // This routine copies the BIST information to the buffer pointed by   // PlatformInformationRecord for output.   //-  TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);-  TopOfTemporaryRam -= sizeof (UINT32) * 2;-  Count             = *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)));+  TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINTN);+  TopOfTemporaryRam -= sizeof (UINTN) * 2;+  Count             = *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));   Size              = Count * sizeof (IA32_HANDOFF_STATUS);    if ((*StructureSize) < (UINT64) Size) {diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
index 355d1e6509..49d5302a7b 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/SecRamInitData.c
@@ -1,7 +1,7 @@
 /** @file   Provide TempRamInitParams data. -Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent  **/@@ -12,25 +12,70 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
  typedef struct {   FSP_UPD_HEADER    FspUpdHeader;+#if FixedPcdGet8 (PcdFsptArchUpdRevision) == 1+  FSPT_ARCH_UPD     FsptArchUpd;+#elif FixedPcdGet8 (PcdFsptArchUpdRevision) == 2+  FSPT_ARCH2_UPD    FsptArchUpd;+#endif   FSPT_CORE_UPD     FsptCoreUpd;-} FSPT_UPD_CORE_DATA;+  UINT16            UpdTerminator;+} FSPT_UPD_DATA; -GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {+GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_DATA FsptUpdDataPtr = {   {-    0x4450555F54505346,-    0x00,-    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,-      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00+    0x4450555F54505346,                                           // FSP-T UPD Header Signature - FSPT_UPD+    FixedPcdGet8 (PcdFsptUpdHeaderRevision),                      // FSP-T UPD Header Revision+    {                                                             // Reserved[23]+      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+      0x00, 0x00, 0x00     }   },+#if FixedPcdGet8 (PcdFsptArchUpdRevision) == 1   {-    FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv),-    FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv),-    0,          // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.-    FixedPcdGet32 (PcdFlashCodeCacheSize),-    { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+    0x01,                                                         // FSP-T ARCH UPD Revision+    {                                                             // Reserved[3]+      0x00, 0x00, 0x00+    },+    0x00000020,                                                   // Length of FSP-T ARCH UPD+    0,                                                            // FspDebugHandler+    {                                                             // Reserved1[20]+      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00+    }+  },+#elif FixedPcdGet8 (PcdFsptArchUpdRevision) == 2+  {+    0x02,                                                         // FSP-T ARCH2 UPD Revision+    {                                                             // Reserved[3]+      0x00, 0x00, 0x00+    },+    0x00000020,                                                   // Length of FSP-T ARCH2 UPD+    0,                                                            // FspDebugHandler+    {                                                             // Reserved1[16]+      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,       0x00, 0x00, 0x00, 0x00, 0x00, 0x00     }-  }+  },+#endif+#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1+  {+    FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionBase+    FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionSize+    0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.+    FixedPcdGet32 (PcdFlashCodeCacheSize),                                            // CodeRegionSize+    {                                                                                 // Reserved[16]+      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+      0x00, 0x00, 0x00, 0x00, 0x00, 0x00+    }+  },+#else+  {+    FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionBase+    FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionSize+    0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.+    FixedPcdGet32 (PcdFlashCodeCacheSize)                                             // CodeRegionSize+  },+#endif+  0x55AA };-diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
new file mode 100644
index 0000000000..af3affcf7f
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/X64/PeiCoreEntry.nasm
@@ -0,0 +1,202 @@
+;------------------------------------------------------------------------------+;+; Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+; SPDX-License-Identifier: BSD-2-Clause-Patent+;+; Module Name:+;+;  PeiCoreEntry.nasm+;+; Abstract:+;+;   Find and call SecStartup+;+;------------------------------------------------------------------------------++SECTION .text++extern ASM_PFX(SecStartup)+extern ASM_PFX(PlatformInit)+extern ASM_PFX(PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))++;-----------------------------------------------------------------------------+;  Macro:        PUSHA_64+;+;  Description:  Saves all registers on stack+;+;  Input:        None+;+;  Output:       None+;-----------------------------------------------------------------------------+%macro PUSHA_64   0+  push    r8+  push    r9+  push    r10+  push    r11+  push    r12+  push    r13+  push    r14+  push    r15+  push    rax+  push    rcx+  push    rdx+  push    rbx+  push    rsp+  push    rbp+  push    rsi+  push    rdi+%endmacro++;-----------------------------------------------------------------------------+;  Macro:        POPA_64+;+;  Description:  Restores all registers from stack+;+;  Input:        None+;+;  Output:       None+;-----------------------------------------------------------------------------+%macro POPA_64   0+  pop    rdi+  pop    rsi+  pop    rbp+  pop    rsp+  pop    rbx+  pop    rdx+  pop    rcx+  pop    rax+  pop    r15+  pop    r14+  pop    r13+  pop    r12+  pop    r11+  pop    r10+  pop    r9+  pop    r8+%endmacro++global ASM_PFX(CallPeiCoreEntryPoint)+ASM_PFX(CallPeiCoreEntryPoint):+  ;+  ; Per X64 calling convention, make sure RSP is 16-byte aligned.+  ;+  mov     rax, rsp+  and     rax, 0fh+  sub     rsp, rax++  ;+  ; Platform init+  ;+  PUSHA_64+  sub     rsp, 20h+  call    ASM_PFX(PlatformInit)+  add     rsp, 20h+  POPA_64++  ;+  ; Set stack top pointer+  ;+  mov     rsp, r8++  ;+  ; Push the hob list pointer+  ;+  push    rcx++  ;+  ; RBP holds start of BFV passed from Vtf0. Save it to r10.+  ;+  mov     r10, rbp++  ;+  ; Save the value+  ;   RDX: start of range+  ;   r8: end of range+  ;+  mov     rbp, rsp+  push    rdx+  push    r8+  mov     r14, rdx+  mov     r15, r8++  ;+  ; Push processor count to stack first, then BIST status (AP then BSP)+  ;+  mov     eax, 1+  cpuid+  shr     ebx, 16+  and     ebx, 0000000FFh+  cmp     bl, 1+  jae     PushProcessorCount++  ;+  ; Some processors report 0 logical processors.  Effectively 0 = 1.+  ; So we fix up the processor count+  ;+  inc     ebx++PushProcessorCount:+  sub     rsp, 4+  mov     rdi, rsp+  mov     DWORD [rdi], ebx++  ;+  ; We need to implement a long-term solution for BIST capture.  For now, we just copy BSP BIST+  ; for all processor threads+  ;+  xor     ecx, ecx+  mov     cl, bl+PushBist:+  sub     rsp, 4+  mov     rdi, rsp+  movd    eax, mm0+  mov     DWORD [rdi], eax+  loop    PushBist++  ;+  ; FSP saves the timestamp of the beginning of firmware execution in mm5.+  ; Get the timestamp from mm5 and then push to stack.+  ;+  movq    rax, mm5+  push    rax++  ;+  ; Per X64 calling convention, make sure RSP is 16-byte aligned.+  ;+  mov     rax, rsp+  and     rax, 0fh+  sub     rsp, rax++  ;+  ; Pass entry point of the PEI core+  ;+  mov     rdi, 0FFFFFFE0h+  mov     edi, DWORD [rdi]+  mov     r9, rdi++  ;+  ; Pass BFV into the PEI Core+  ;+  ; Reset Vector and initial SEC core (to initialize Temp Ram) is part of FSP-O.+  ; Default UefiCpuPkg Reset Vector locates FSP-O as BFV. However the actual+  ; SEC core that launches PEI is part of another FV. We need to pass that FV+  ; as BFV to PEI core.+  ;+  mov     r8, ASM_PFX (PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))+  mov     rcx, QWORD[r8]+  mov     r8,  rcx++  ;+  ; Pass stack size into the PEI Core+  ;+  mov     rcx, r15  ; Start of TempRam+  mov     rdx, r14  ; End of TempRam++  sub     rcx, rdx  ; Size of TempRam++  ;+  ; Pass Control into the PEI Core+  ;+  sub     rsp, 20h+  call    ASM_PFX(SecStartup)+diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
new file mode 100644
index 0000000000..de8ba83d52
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/X64/SecEntry.nasm
@@ -0,0 +1,71 @@
+;------------------------------------------------------------------------------+;+; Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+; SPDX-License-Identifier: BSD-2-Clause-Patent+; Module Name:+;+;  SecEntry.nasm+;+; Abstract:+;+;  This is the code that passes control to PEI core.+;+;------------------------------------------------------------------------------++#include <Fsp.h>++SECTION .text++extern   ASM_PFX(CallPeiCoreEntryPoint)+extern   ASM_PFX(FsptUpdDataPtr)+; Pcds+extern   ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))++;----------------------------------------------------------------------------+;+; Procedure:    _ModuleEntryPoint+;+; Input:        None+;+; Output:       None+;+; Destroys:     Assume all registers+;+; Description:+;+;  After TempRamInit done, pass control to PEI core.+;+; Return:       None+;+;  MMX Usage:+;              MM0 = BIST State+;+;----------------------------------------------------------------------------++BITS 64+align 16+global ASM_PFX(_ModuleEntryPoint)+ASM_PFX(_ModuleEntryPoint):+  push    rax+  mov     rax, ASM_PFX(FsptUpdDataPtr)  ; This is dummy code to include TempRamInitParams in SecCore for FSP-O.+#if FixedPcdGet8(PcdFspModeSelection) == 1+  mov     rax, ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))+  sub     edx, dword [rax]              ; TemporaryRam for FSP+#endif+  pop     rax++  mov     r8,  rdx+  mov     rdx, rcx+  xor     ecx, ecx                      ; zero - no Hob List Yet+  mov     rsp, r8++  ;+  ; Per X64 calling convention, make sure RSP is 16-byte aligned.+  ;+  mov     rax, rsp+  and     rax, 0fh+  sub     rsp, rax++  call    ASM_PFX(CallPeiCoreEntryPoint)++  jmp     $diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
new file mode 100644
index 0000000000..21010bf4ef
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/X64/Stack.nasm
@@ -0,0 +1,72 @@
+;------------------------------------------------------------------------------+;+; Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+; SPDX-License-Identifier: BSD-2-Clause-Patent+; Abstract:+;+;   Switch the stack from temporary memory to permanent memory.+;+;------------------------------------------------------------------------------++    SECTION .text++;------------------------------------------------------------------------------+; VOID+; EFIAPI+; SecSwitchStack (+;   UINT32   TemporaryMemoryBase,+;   UINT32   PermanentMemoryBase+;   );+;------------------------------------------------------------------------------+global ASM_PFX(SecSwitchStack)+ASM_PFX(SecSwitchStack):+    ;+    ; Save four register: rax, rbx, rcx, rdx+    ;+    push  rax+    push  rbx+    push  rcx+    push  rdx++    ;+    ; !!CAUTION!! this function address's is pushed into stack after+    ; migration of whole temporary memory, so need save it to permanent+    ; memory at first!+    ;++    mov   rbx, rcx                 ; Save the first parameter+    mov   rcx, rdx                 ; Save the second parameter++    ;+    ; Save this function's return address into permanent memory at first.+    ; Then, Fixup the esp point to permanent memory+    ;+    mov   rax, rsp+    sub   rax, rbx+    add   rax, rcx+    mov   rdx, qword [rsp]         ; copy pushed register's value to permanent memory+    mov   qword [rax], rdx+    mov   rdx, qword [rsp + 8]+    mov   qword [rax + 8], rdx+    mov   rdx, qword [rsp + 16]+    mov   qword [rax + 16], rdx+    mov   rdx, qword [rsp + 24]+    mov   qword [rax + 24], rdx+    mov   rdx, qword [rsp + 32]    ; Update this function's return address into permanent memory+    mov   qword [rax + 32], rdx+    mov   rsp, rax                 ; From now, rsp is pointed to permanent memory++    ;+    ; Fixup the rbp point to permanent memory+    ;+    mov   rax, rbp+    sub   rax, rbx+    add   rax, rcx+    mov   rbp, rax                 ; From now, rbp is pointed to permanent memory++    pop   rdx+    pop   rcx+    pop   rbx+    pop   rax+    ret+diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/MinPlatformPkg/Include/Fsp.h
similarity index 79%
rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
rename to Platform/Intel/MinPlatformPkg/Include/Fsp.h
index 9f6cdcf476..319e1e3372 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
+++ b/Platform/Intel/MinPlatformPkg/Include/Fsp.h
@@ -1,7 +1,7 @@
 /** @file   Fsp related definitions -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent  **/@@ -36,7 +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 // // Fsp Header //-#define FSP_HEADER_IMAGEBASE_OFFSET     0x1C-#define FSP_HEADER_TEMPRAMINIT_OFFSET   0x30+#define FSP_HEADER_IMAGEBASE_OFFSET   0x1C+#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30  #endifdiff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
index a14c6b2db5..12f86585ad 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -6,7 +6,7 @@
 # INF files to generate AutoGen.c and AutoGen.h files # for the build infrastructure. #-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>+# Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR> # Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent@@ -393,6 +393,21 @@
   #   gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE|BOOLEAN|0xF00000A8 +  ## BFV Location for Reset Vector in FSP+  # The default of BFV Location for Reset Vector in FSP is 0x00000000FFFF0000.+  #+  gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp|0x00000000FFFF0000|UINT64|0xF00000A9++  ## FSP-T UPD Header Revision+  # The default of FSP-T UPD Header Revision is 0.+  #+  gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision|0x0|UINT8|0xF00000AA++  ## FSP-T ARCH UPD Revision+  # The default of FSP-T ARCH UPD Revision is 0.+  #+  gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision|0x0|UINT8|0xF00000AC+ [PcdsFeatureFlag]    gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit     |FALSE|BOOLEAN|0xF00000A1-- 
2.40.1.windows.1



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