From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 40375D80CAA for ; Thu, 14 Sep 2023 17:24:11 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=C5aMapbXpNg3bFVilG30VxabYoc9E4Ejf84BTwKbVsQ=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1694712249; v=1; b=lhh8+7BRquAJwmwEyWP5C9g0vPobjFkT63a9EDOzz3LGZgzi3gykBS5OdtfMUgeYCTR8CocO cIfuIIw4e5tk+ZbT5DQuBN+79AYg5IF42EXzUOMofnHPlTWYMBEjyR7oZmF6JUPsEez6nhQFICC ffuf2kDprxGWCcHb6dmn5XK8= X-Received: by 127.0.0.2 with SMTP id 4Hi2YY7687511xoSlbtxt1La; Thu, 14 Sep 2023 10:24:09 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.588.1694712248236150403 for ; Thu, 14 Sep 2023 10:24:09 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10833"; a="382837642" X-IronPort-AV: E=Sophos;i="6.02,146,1688454000"; d="scan'208";a="382837642" X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2023 10:24:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10833"; a="1075473857" X-IronPort-AV: E=Sophos;i="6.02,146,1688454000"; d="scan'208";a="1075473857" X-Received: from orsmsx602.amr.corp.intel.com ([10.22.229.15]) by fmsmga005.fm.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 14 Sep 2023 10:24:07 -0700 X-Received: from orsmsx611.amr.corp.intel.com (10.22.229.24) by ORSMSX602.amr.corp.intel.com (10.22.229.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Thu, 14 Sep 2023 10:24:06 -0700 X-Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx611.amr.corp.intel.com (10.22.229.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32 via Frontend Transport; Thu, 14 Sep 2023 10:24:06 -0700 X-Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.177) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.32; Thu, 14 Sep 2023 10:24:01 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jyCb6amgLE9IKBvb9QEVxpuPEPTxHWwiHnuMOSHN7B5bJKxyW5zLUUqNLEjvDPl75wxs6nNk7c/2PHtKaAJIS76LTcuQh9ig5sW1/w+3pipNFZJ02b4/0YyGv3oXTYTwEXIEsFEXmwLRqb/GxzrBz9BBF3yKh9P/ZGEkNc5N7rsi2XJPoPZuz7e9FMbANMt4XFiSwmu8bd/KBVo2c/IXDFnpFhkUAo0ovstQfFfgDSTXwrda9+Lty5/ZciQZp8K5RS8c6h3ZtyvNrA9rHc7wTGRz6VBXSsY4kalNisULcgbtkuR/8HyJmBoGiaMFlIWAxNuEW1w5Jkcidb0lUUePnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=gT3/QzgiF9ZFT7lamXubSs806ugeSofUGoOsLwe48fM=; b=eP4sIbtG6ASvdrtHPWymvh6mZYn6nmckR38u3ln/AnZW75iLp7mDGfwKS8d+daMspHLaRKhJjWLSoGFKgxrpvmoVFGK+aEQXXUD0srEZBhaNOwusoCDji74s62Z57DC83mlBeaBVCd28TzN13vjY5iFvSfEMLeg8UeYxxN6MXAYeqo45ZvEslJyQAhJ+FHdJKQX8uaHWtLyR9ETDXxeCwaDU6Xc6pz1Ct1+GMz1OYjO3kmvShsflb4rm2ueZ5OGl68IEGcf0QoHy+yNf0sNb7IeqjVyQ5y6QvcoVjG2Hjmf0K3lEClle8SJNHA97vLslmw44ZqMg8ByMLhNFkoexgg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from MW4PR11MB5776.namprd11.prod.outlook.com (2603:10b6:303:183::9) by CO6PR11MB5588.namprd11.prod.outlook.com (2603:10b6:303:13c::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6768.38; Thu, 14 Sep 2023 17:23:59 +0000 X-Received: from MW4PR11MB5776.namprd11.prod.outlook.com ([fe80::2ec0:108e:7afe:f1a4]) by MW4PR11MB5776.namprd11.prod.outlook.com ([fe80::2ec0:108e:7afe:f1a4%5]) with mapi id 15.20.6768.029; Thu, 14 Sep 2023 17:23:58 +0000 From: "Chaganty, Rangasai V" To: "Kasbekar, Saloni" , "devel@edk2.groups.io" CC: "Desimone, Nathaniel L" , "Chuang, Rosen" Subject: Re: [edk2-devel] [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components Thread-Topic: [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components Thread-Index: AQHZ5o+nfu7Kas/d4UiImzNJS3xzMbAak01g Date: Thu, 14 Sep 2023 17:23:58 +0000 Message-ID: References: <3418f591c615697e5678c9bcd872597bfb5d0652.1694643161.git.saloni.kasbekar@intel.com> In-Reply-To: <3418f591c615697e5678c9bcd872597bfb5d0652.1694643161.git.saloni.kasbekar@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW4PR11MB5776:EE_|CO6PR11MB5588:EE_ x-ms-office365-filtering-correlation-id: daa72f37-0173-415e-71ae-08dbb54761aa x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: nbJUVValv+A1+Ly8aLHrLLyapT7CTrFMWg/vJlUpEbkmJpzQ9cEtKDdSnTHGGuAyPyAO56qs2k3C55lFOD4qGSA4z0z6Ai6rh1tc3P9K4Jj8LnYQXkGQudzoFMUdc/v6rn73OPZf0F+UAewEbH1R4JG/N0CsvylLK0wyW/ucJxr+hDgbK3ZpSKe7mnq72JeCzrTcs2K3NqJyQmfkLh7cLdeZTu0J4QkmweOEsKDw/ERo+y0e2YOdvuvxYv3wJoi6fq9V2pplXqTiYB5Eqjhz7eReWjEfvBB+Gxl32ax3/wd/hxY537iHN4V1KLMT+pbrLdfoOeNtfWXOvKdSyzlpH8T82W/LNOHte11850RfdJ6pcBc5+n1+glV5uEtnG+gyHY0LDwZhWYuhhNPvIaADSgfuCjHcGzcbNKbDixrkYBlmib1yF/O50d2G9Y7SBvNmiTDbZ7mLxgsxXdFOLQ99ugojWVitLq2vEurhxFeV89gHXpLyTUNaBi+Rt4yJGGOe1cgEaHnebWK4HQv4Pit//tvIkRKQ2kgFDMT2+gr5DLxiQVV2C0ep4HO12iXn6gMfDuhiAVcm55XLT2AMpXX4h0N91yi1bLTeceH/4+VZgEiSxPBuWFBKhgeL2ty34ql9 x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?WIRo7RNNzyySnJ9j7+vYxIfWDatnUy4GLr1tj+kAmQnW4VLE0iV2VEOYuNXJ?= =?us-ascii?Q?HblZKpfawfu4r9A1C8vmyNfpFxCC275VM54fDlxmeTDR9AX9vZ7D/DDMSupB?= =?us-ascii?Q?UilKG9noK0qQDXfApC+wZ2K32d0BoKGRn1Wn+vablj79c4jp6o0eSKpqJUtx?= =?us-ascii?Q?vIv1M3A2szz+zsS8ulCNZUudJz+bZN5Oj6QJmi9PDj9XvBatIKPeIIlyvLb8?= =?us-ascii?Q?1Vkfws3tJ0Tj/ggsFbYYJnOkm/7Dv1JT2sWmspCay5fgW7UWspayX5Z4iOmh?= =?us-ascii?Q?xCIPraqUeAnl5hYXtExre8mLtYpY5O9nhyvGnMrrxNpMAXNQZzLU65NpZQiS?= =?us-ascii?Q?+zklZbWq15PiDJTmHGGVMLva+UTlksHfKJZvCratenWuDvNx6bt2pRlMBmUj?= =?us-ascii?Q?k3E9tjSHBXzwfFzuHEwEGQCjXGmMYhVgdHxdTiIo8Tq2YDwxmNbNhR8ooiyF?= =?us-ascii?Q?1IKT6afmyihYZjmDJ8YwKSxEqvykPeSVyFf6hcYEZlQkGXQx+ldFiiOk9ehA?= =?us-ascii?Q?zSMYN4k9w7Ju+E+CI6SEQkXgdz5QVdzxTLQocX0ZlEFg5UV3jWHS3S1Joxcn?= =?us-ascii?Q?Y7VFXaZJ+KCv+PleqzlbkdzOy93bthH/Eod/zhYVxa/3uFLSlOcb2UOXvuIs?= =?us-ascii?Q?kA6T9hUXwotkqiSVt5rnVRxktRE1bvBlULDel2hnHXurfizUIoAmt9TtSX4m?= =?us-ascii?Q?VXrrxGinvVPwlBt0+yFsbtxbllrNCXQzMyil1C3Ih/Ne7pWf7ZVGg0XaAfXG?= =?us-ascii?Q?1koNFvz04wsHDUjWNUgm58TqykMaxf3seFNfe1ueLFDcfP55z6W0Id0T/L6T?= =?us-ascii?Q?ZkJ0rVjudMI9XNgXUllINwQZy8GSL/dBnpORkIvPvMePGMp4pGMejXT6V4eT?= =?us-ascii?Q?XrW4ewO55X6tslvvcF9t+M9Ok3i4fBky0QV5PbifMC5ebPEn7I65pEUpD9QB?= =?us-ascii?Q?VTS0UOTJ/L3yd2mpmpIH5ULspwu0JcwzJhvir654MCO16MWSuVRqu0LHfUbp?= =?us-ascii?Q?pVaBKFoD0326EwTCeRt9wJCiwPBcraoCIzyV554gDVusuqb1aOf6tPSitcsU?= =?us-ascii?Q?SSnpUjGQR4M8IpXNsWTbpqVmicHQnuVuCGv1F4TwRTJqNB1ahe948eNRlSLL?= =?us-ascii?Q?k/ghxe+l7Gw5h3MVbKzkoJH4GIFoiDAXJTwnIWY09xw3XbWnSqR87AcwJArD?= =?us-ascii?Q?lEcoWcu62V1JoVpN60JFVO1qsnZh85FluCf6z6zIgfRmWqQ7aPu/qHf9mksI?= =?us-ascii?Q?MiV+kHrLIo+NmDXx3GD7pnO2zD1dP1tHxOTYs3T4YJamEygLBzaaJb9fV00y?= =?us-ascii?Q?t9tCZJMEfv78zLRwlCvUPNVEJ03ex3YyOqo3Nz2faCR6EXg9Lddq9jZ0mqG0?= =?us-ascii?Q?sbM9PhDNqSWsPJjWzcsiqUpALxUFMnZVgedr+DVlez9SNhgOneipdoVQmA7o?= =?us-ascii?Q?E2dpyFsicDFWxCc7c9Skxtf+bdt7j0rizrduII5M1PItexRUAitt7yOIb4qL?= =?us-ascii?Q?pjoBG6nDUahxaPuteivwkEVKVVS60BTx1WPgk/7mTnhoYPull2Xc9y8BiTTN?= =?us-ascii?Q?FjKSrsRaEYZiPIT9S0qIf5RzQ324l5JVR324Y6CphjQOhuvD4sL+9J8RhVP+?= =?us-ascii?Q?Yw=3D=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW4PR11MB5776.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: daa72f37-0173-415e-71ae-08dbb54761aa X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Sep 2023 17:23:58.8922 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GS15cR5MyVivYVSb6fLDDzYnteDgqI6XtSJ73nAqn00w3RTCUmUqZA7Z8TdniVnRp5DH/pC1ZUuTnsoIZflZyroZqMQe8Sj2S7Hz4JMtCeE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR11MB5588 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rangasai.v.chaganty@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 8mEonyHWoS5Hq4b8aGBINiYNx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=lhh8+7BR; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Sai Chaganty -----Original Message----- From: Kasbekar, Saloni =20 Sent: Wednesday, September 13, 2023 3:14 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridg= e, PcieRp components Adds the following modules: - IpBlock/Graphics/Include - IpBlock/Graphics/IncludePrivate - IpBlock/Graphics/Library - IpBlock/Graphics/LibraryPrivate - IpBlock/HostBridge/IncludePrivate - IpBlock/PcieRp/Library Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Include/Ppi/GraphicsPlatformPolicyPpi.h | 76 +++++++++++ .../Library/DxeGraphicsPolicyLib.h | 71 +++++++++++ .../Library/DxeIgdOpRegionInitLib.h | 115 +++++++++++++++++ .../GraphicsInfoLibVer1.c | 52 ++++++++ .../GraphicsInfoLibVer1.inf | 33 +++++ .../DxeGraphicsPolicyLib.c | 116 +++++++++++++++++ .../DxeGraphicsPolicyLib.inf | 36 ++++++ .../DxeIgdOpRegionInit.c | 119 ++++++++++++++++++ .../DxeIgdOpRegionInitLib.inf | 47 +++++++ .../IncludePrivate/HostBridgeDataHob.h | 25 ++++ .../PchPcieRpLibInternal.h | 20 +++ .../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 71 +++++++++++ .../PeiDxeSmmPchPcieRpLibVer2.inf | 37 ++++++ 13 files changed, 818 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Incl= ude/Ppi/GraphicsPlatformPolicyPpi.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Incl= udePrivate/Library/DxeGraphicsPolicyLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Incl= udePrivate/Library/DxeIgdOpRegionInitLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Libr= ary/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Libr= ary/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Libr= aryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Libr= aryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Libr= aryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Libr= aryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/In= cludePrivate/HostBridgeDataHob.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Librar= y/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Librar= y/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Librar= y/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi= /GraphicsPlatformPolicyPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gr= aphics/Include/Ppi/GraphicsPlatformPolicyPpi.h new file mode 100644 index 0000000000..a8f67061a5 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra +++ phicsPlatformPolicyPpi.h @@ -0,0 +1,76 @@ +/** @file + The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PE= I Graphics PEIM. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_ +#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_ + +/** + Globally unique identifier for PEI platform policy PPI. +**/ +#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \ + 0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89,=20 +0x99, 0x5 } \ } + +#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1 + +/** +Pre-declaration of PEI graphics platform policy PPI. +**/ +typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI=20 +PEI_GRAPHICS_PLATFORM_POLICY_PPI; + +/** + Enum defining the different lid status values **/ typedef enum { + LidClosed, + LidOpen, + LidStatusMax +} LID_STATUS; + +/** + This function gets the platform lid status for LFP displays. + + @param[out] CurrentLidStatus Output variable to store the lid status. + + @retval EFI_SUCCESS Correct lid status is returned. + @retval EFI_UNSUPPORTED Platform does not support lid. +**/ +typedef +EFI_STATUS +(EFIAPI *GET_PLATFORM_LID_STATUS) ( + OUT LID_STATUS *CurrentLidStatus + ); + +/** + This function gets the base address of loaded VBT. + + @param[out] VbtAddress Starting address of the VBT is returned in thi= s parameter. + @param[out] VbtSize Size of the VBT is returned in this parameter. + + @retval EFI_SUCCESS If the VBT is loaded and parameters contain va= lid values. + @return Other error codes meaning VBT is not loaded and parameters c= ontain invalid values. +**/ +typedef +EFI_STATUS +(EFIAPI *GET_VBT_DATA) ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize + ); + +/** + This defines the PEI Graphics Platform Policy PPI structure. +**/ +struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI { + UINT32 Revision; ///< Revision of c= urrent implementation. + GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Function Poin= ter for get platform lid status. + GET_VBT_DATA GetVbtData; ///< Function poin= ter for get vbt data. +}; + +extern EFI_GUID gPeiGraphicsPlatformPpiGuid; + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePriv= ate/Library/DxeGraphicsPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBl= ock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h new file mode 100644 index 0000000000..0347d4c94c --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/ +++ Library/DxeGraphicsPolicyLib.h @@ -0,0 +1,71 @@ +/** @file + Header file for the DXE Graphics Policy Init library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_DXE_GRAPHICS_POLICY_LIB_H_ #define _DXE_GRAPHICS_POLICY_LIB_H_ + +#include +#include +#include +#include +#include +#include #include =20 +#include #include #include=20 + + +#define WORD_FIELD_VALID_BIT BIT15 + +extern EFI_GUID gGraphicsDxeConfigGuid; + +/** + This function prints the Graphics DXE phase policy. + + @param[in] SaPolicy - SA DXE Policy protocol **/ VOID=20 +GraphicsDxePolicyPrint ( + IN SA_POLICY_PROTOCOL *SaPolicy + ); + +/** + This function Load default Graphics DXE policy. + + @param[in] ConfigBlockPointer The pointer to add Graphics config bloc= k +**/ +VOID +LoadIgdDxeDefault ( + IN VOID *ConfigBlockPointer + ); + + +/** + Get DXE Graphics config block table total size. + + @retval Size of DXE Graphics config block table +**/ +UINT16 +EFIAPI +GraphicsGetConfigBlockTotalSizeDxe ( + VOID + ); + +/** + GraphicsAddConfigBlocksDxe add all DXE Graphics config block. + + @param[in] ConfigBlockTableAddress The pointer to add SA config block= s + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +GraphicsAddConfigBlocksDxe ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _DXE_GRAPHICs_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePriv= ate/Library/DxeIgdOpRegionInitLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpB= lock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h new file mode 100644 index 0000000000..02e4988b2b --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/ +++ Library/DxeIgdOpRegionInitLib.h @@ -0,0 +1,115 @@ +/** @file + This is part of the implementation of an Intel Graphics drivers=20 +OpRegion / + Software SCI interface between system BIOS, ASL code, and Graphics drive= rs. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_DXE_IGD_OPREGION_INIT_LIB_H_ #define _DXE_IGD_OPREGION_INIT_LIB_H_ + +/// +/// Statements that include other header files. +/// +#include +#include +#include +#include +#include +#include +#include +#include #include =20 +#include #include #include=20 + #include #include=20 + #include #include=20 + /// /// Driver Consumed Protocol=20 +Prototypes /// #include #include=20 + #include /// ///=20 +Driver Produced Protocol Prototypes /// #include=20 + + +#pragma pack(push, 1) +/// +/// +/// OpRegion (Miscellaneous) defines. +/// +/// OpRegion Header defines. +/// +typedef UINT16 STRING_REF; +/// +/// Typedef stuctures +/// +typedef struct { + UINT16 Signature; /// 0xAA55 + UINT8 Size512; + UINT8 Reserved[21]; + UINT16 PcirOffset; + UINT16 VbtOffset; +} INTEL_VBIOS_OPTION_ROM_HEADER; + +typedef struct { + UINT32 Signature; /// "PCIR" + UINT16 VendorId; /// 0x8086 + UINT16 DeviceId; + UINT16 Reserved0; + UINT16 Length; + UINT8 Revision; + UINT8 ClassCode[3]; + UINT16 ImageLength; + UINT16 CodeRevision; + UINT8 CodeType; + UINT8 Indicator; + UINT16 Reserved1; +} INTEL_VBIOS_PCIR_STRUCTURE; + +typedef struct { + UINT8 HeaderSignature[20]; + UINT16 HeaderVersion; + UINT16 HeaderSize; + UINT16 HeaderVbtSize; + UINT8 HeaderVbtCheckSum; + UINT8 HeaderReserved; + UINT32 HeaderOffsetVbtDataBlock; + UINT32 HeaderOffsetAim1; + UINT32 HeaderOffsetAim2; + UINT32 HeaderOffsetAim3; + UINT32 HeaderOffsetAim4; + UINT8 DataHeaderSignature[16]; + UINT16 DataHeaderVersion; + UINT16 DataHeaderSize; + UINT16 DataHeaderDataBlockSize; + UINT8 CoreBlockId; + UINT16 CoreBlockSize; + UINT16 CoreBlockBiosSize; + UINT8 CoreBlockBiosType; + UINT8 CoreBlockReleaseStatus; + UINT8 CoreBlockHWSupported; + UINT8 CoreBlockIntegratedHW; + UINT8 CoreBlockBiosBuild[4]; + UINT8 CoreBlockBiosSignOn[155]; +} VBIOS_VBT_STRUCTURE; +#pragma pack(pop) +/// +/// Driver Private Function definitions /// + +/** + Update Graphics OpRegion after PCI enumeration. + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +UpdateIgdOpRegionEndOfDxe ( + VOID + ); +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/Pei= DxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c b/Silicon/Intel/AlderlakeSilico= nPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.= c new file mode 100644 index 0000000000..9dd9b33a49 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS +++ mmGraphicsInfoLib/GraphicsInfoLibVer1.c @@ -0,0 +1,52 @@ +/** @file + Source file for common Graphics Info Lib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include=20 + #include #include=20 + #include + +/** + GetIgdBusNumber: Get IGD Bus Number + + @retval PCI bus number for IGD +**/ +UINT8 +GetIgdBusNumber ( + VOID + ) +{ + return (UINT8) IGD_BUS_NUM; +} + +/** + GetIgdDevNumber: Get IGD Dev Number + + @retval PCI dev number for IGD +**/ +UINT8 +GetIgdDevNumber ( + VOID + ) +{ + return (UINT8) IGD_DEV_NUM; +} + +/** + GetIgdFunNumber: Get IGD Fun Number + + @retval PCI fun number for IGD +**/ +UINT8 +GetIgdFuncNumber ( + VOID + ) +{ + return (UINT8) IGD_FUN_NUM; +} + + + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/Pei= DxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf b/Silicon/Intel/AlderlakeSili= conPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer= 1.inf new file mode 100644 index 0000000000..ca363ce105 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS +++ mmGraphicsInfoLib/GraphicsInfoLibVer1.inf @@ -0,0 +1,33 @@ +## @file +# Graphics information library. +# +# All function in this library is available for PEI, DXE, and SMM, #=20 +But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmGraphicsInfoLib +FILE_GUID =3D AE4D5DE8-F092-4B2A-8003-F1A4CCBDC3E4 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D GraphicsInfoLib + +[LibraryClasses] +BaseLib +IoLib +DebugLib +BaseMemoryLib +PciSegmentLib +TimerLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + +[Sources] +GraphicsInfoLibVer1.c diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c b/Silicon/Intel/AlderlakeSi= liconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPo= licyLib.c new file mode 100644 index 0000000000..a9344b424d --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/ +++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c @@ -0,0 +1,116 @@ +/** @file + This file provide services for DXE phase Graphics policy default initial= ization. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include + +/** + This function prints the Graphics DXE phase policy. + + @param[in] SaPolicy - SA DXE Policy protocol **/ VOID=20 +GraphicsDxePolicyPrint ( + IN SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + + // + // Get requisite IP Config Blocks which needs to be used here // =20 + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid,=20 + (VOID *)&GraphicsDxeConfig); ASSERT_EFI_ERROR (Status); + + + DEBUG_CODE_BEGIN (); + DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE)=20 + print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, " Revision :=20 + %d\n", GraphicsDxeConfig->Header.Revision)); + ASSERT (GraphicsDxeConfig->Header.Revision =3D=3D=20 + GRAPHICS_DXE_CONFIG_REVISION); DEBUG ((DEBUG_INFO,=20 + "\n------------------------ Graphics Policy (DXE) print END=20 + -----------------\n")); DEBUG_CODE_END (); + + return; +} + + +/** + This function Load default Graphics DXE policy. + + @param[in] ConfigBlockPointer The pointer to add Graphics config bloc= k +**/ +VOID +LoadIgdDxeDefault ( + IN VOID *ConfigBlockPointer + ) +{ + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + + GraphicsDxeConfig =3D ConfigBlockPointer; + + /// + /// Initialize the Graphics configuration + /// + GraphicsDxeConfig->PlatformConfig =3D 1; + GraphicsDxeConfig->AlsEnable =3D 2; + GraphicsDxeConfig->BacklightControlSupport =3D 2; + GraphicsDxeConfig->IgdBlcConfig =3D 2; + GraphicsDxeConfig->GfxTurboIMON =3D 31; + /// + /// Create a static Backlight Brightness Level Duty cycle=20 +Mapping Table + /// Possible 20 entries (example used 11), each 16 bits as follows: + /// [15] =3D Field Valid bit, [14:08] =3D Level in Percentage (0-64h), [= 07:00] =3D Desired duty cycle (0 - FFh). + /// + GraphicsDxeConfig->BCLM[0] =3D (0x0000 + WORD_FIELD_VALID_BIT); ///<=20 +0% + GraphicsDxeConfig->BCLM[1] =3D (0x0A19 + WORD_FIELD_VALID_BIT); ///<=20 +10% + GraphicsDxeConfig->BCLM[2] =3D (0x1433 + WORD_FIELD_VALID_BIT); ///<=20 +20% + GraphicsDxeConfig->BCLM[3] =3D (0x1E4C + WORD_FIELD_VALID_BIT); ///<=20 +30% + GraphicsDxeConfig->BCLM[4] =3D (0x2866 + WORD_FIELD_VALID_BIT); ///<=20 +40% + GraphicsDxeConfig->BCLM[5] =3D (0x327F + WORD_FIELD_VALID_BIT); ///<=20 +50% + GraphicsDxeConfig->BCLM[6] =3D (0x3C99 + WORD_FIELD_VALID_BIT); ///<=20 +60% + GraphicsDxeConfig->BCLM[7] =3D (0x46B2 + WORD_FIELD_VALID_BIT); ///<=20 +70% + GraphicsDxeConfig->BCLM[8] =3D (0x50CC + WORD_FIELD_VALID_BIT); ///<=20 +80% + GraphicsDxeConfig->BCLM[9] =3D (0x5AE5 + WORD_FIELD_VALID_BIT); ///<=20 +90% + GraphicsDxeConfig->BCLM[10] =3D (0x64FF + WORD_FIELD_VALID_BIT); ///<= =20 +100% } + +static COMPONENT_BLOCK_ENTRY mGraphicsDxeIpBlocks =3D { + &gGraphicsDxeConfigGuid, sizeof (GRAPHICS_DXE_CONFIG),=20 +GRAPHICS_DXE_CONFIG_REVISION, LoadIgdDxeDefault}; + + +/** + Get DXE Graphics config block table total size. + + @retval Size of DXE Graphics config block table +**/ +UINT16 +EFIAPI +GraphicsGetConfigBlockTotalSizeDxe ( + VOID + ) +{ + return mGraphicsDxeIpBlocks.Size; +} + +/** + GraphicsAddConfigBlocksDxe add all DXE Graphics config block. + + @param[in] ConfigBlockTableAddress The pointer to add SA config block= s + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +GraphicsAddConfigBlocksDxe ( + IN VOID *ConfigBlockTableAddress + ) +{ + EFI_STATUS Status; + Status =3D AddComponentConfigBlocks (ConfigBlockTableAddress,=20 +&mGraphicsDxeIpBlocks, 1); + return Status; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf b/Silicon/Intel/Alderlake= SiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphics= PolicyLib.inf new file mode 100644 index 0000000000..0fd6aba0bb --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/ +++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf @@ -0,0 +1,36 @@ +## @file +# Component description file for the DXE Graphics Policy Init library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeGraphicsPolicyLib +FILE_GUID =3D C6190599-287E-40F9-9B46-EE112A322EBF +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D DxeGraphicsPolicyLib + +[LibraryClasses] +BaseMemoryLib +UefiRuntimeServicesTableLib +UefiBootServicesTableLib +DebugLib +PostCodeLib +ConfigBlockLib +HobLib +SiConfigBlockLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + +[Sources] +DxeGraphicsPolicyLib.c + +[Guids] +gGraphicsDxeConfigGuid + +[Pcd] diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c b/Silicon/Intel/AlderlakeSil= iconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegio= nInit.c new file mode 100644 index 0000000000..b3c9d28078 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/ +++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c @@ -0,0 +1,119 @@ +/** @file + This is part of the implementation of an Intel Graphics drivers=20 +OpRegion / + Software SCI interface between system BIOS, ASL code, and Graphics drive= rs. + The code in this file will load the driver and initialize the=20 +interface + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include + + + +GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL mIgdOpRegion= ; + + +/** + Update Graphics OpRegion after PCI enumeration. + + @param[in] void - None + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +UpdateIgdOpRegionEndOfDxe ( + VOID +) +{ + EFI_STATUS Status; + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + UINTN Index; + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 Pci; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + + Bus =3D 0; + Device =3D 0; + Function =3D 0; + + DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n")); + + mIgdOpRegion.OpRegion->Header.PCON |=3D BIT8; //Set External Gfx=20 + Adapter field is valid mIgdOpRegion.OpRegion->Header.PCON &=3D (UINT32)= =20 + (~BIT7); //Assume No External Gfx Adapter + + /// + /// Get all PCI IO protocols handles + /// + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + + if (!EFI_ERROR (Status)) { + for (Index =3D 0; Index < HandleCount; Index++) { + /// + /// Get the PCI IO Protocol Interface corresponding to each handle + /// + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo + ); + + if (!EFI_ERROR (Status)) { + /// + /// Read the PCI configuration space + /// + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + 0, + sizeof (Pci) / sizeof (UINT32), + &Pci + ); + + /// + /// Find the display controllers devices + /// + if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) { + Status =3D PciIo->GetLocation ( + PciIo, + &Segment, + &Bus, + &Device, + &Function + ); + + // + // Assumption: Onboard devices will be sits on Bus no 0, while e= xternal devices will be sits on Bus no > 0 + // + if (!EFI_ERROR (Status) && (Bus > 0)) { + //External Gfx Adapter Detected and Available + DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected and = Available\n")); + mIgdOpRegion.OpRegion->Header.PCON |=3D BIT7; + break; + } + } + } + } + } + + /// + /// Free any allocated buffers + /// + if (HandleBuffer !=3D NULL) { + FreePool (HandleBuffer); + } + + /// + /// Return final status + /// + return Status; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf b/Silicon/Intel/Alderla= keSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOp= RegionInitLib.inf new file mode 100644 index 0000000000..e3a56d5563 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/ +++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf @@ -0,0 +1,47 @@ +## @file +# Component description file for the Dxe IGD OpRegion library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeIgdOpRegionInitLib +FILE_GUID =3D 18D47D72-555E-475B-A4E4-AD20C3BD8B15 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_DRIVER +UEFI_SPECIFICATION_VERSION =3D 2.00 +LIBRARY_CLASS =3D DxeIgdOpRegionInitLib + +[LibraryClasses] +UefiLib +UefiRuntimeServicesTableLib +UefiBootServicesTableLib +DebugLib +PostCodeLib +ConfigBlockLib +PciSegmentLib +BaseMemoryLib +MemoryAllocationLib +IoLib +S3BootScriptLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec +IntelSiliconPkg/IntelSiliconPkg.dec + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + +[Sources] +DxeIgdOpRegionInit.c + +[Guids] +gGraphicsDxeConfigGuid ## CONSUMES + +[Protocols] +gIgdOpRegionProtocolGuid ## PRODUCES +gSaPolicyProtocolGuid ## CONSUMES +gEfiPciIoProtocolGuid ## CONSUMES diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePr= ivate/HostBridgeDataHob.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostB= ridge/IncludePrivate/HostBridgeDataHob.h new file mode 100644 index 0000000000..671e821342 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivat +++ e/HostBridgeDataHob.h @@ -0,0 +1,25 @@ +/** @file + The GUID definition for Host Bridge Data Hob + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_HOST_BRIDGE_DATA_HOB_H_ #define _HOST_BRIDGE_DATA_HOB_H_ + +#include + +extern EFI_GUID gHostBridgeDataHobGuid; #pragma pack (push,1) + +/// +/// Host Bridge Data Hob +/// +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID= Hob type structure for gSaDataHobGuid + UINT8 EnableAbove4GBMmio; ///< 0=3D= Disable above 4GB MMIO resource support, 1=3DEnable above 4GB MMIO resource= support + BOOLEAN SkipPamLock; ///< 0=3D= All PAM registers will be locked in System Agent code, 1=3DDo not lock PAM = registers in System Agent code. + UINT8 Rsvd1[2]; ///< Rese= rved for future use +} HOST_BRIDGE_DATA_HOB; +#pragma pack (pop) +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDx= eSmmPchPcieRpLib/PchPcieRpLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg= /IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h new file mode 100644 index 0000000000..e2be00fae7 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm +++ PchPcieRpLib/PchPcieRpLibInternal.h @@ -0,0 +1,20 @@ +/** @file + PCIE root port library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_PCIE_RP_LIB_INTERNAL_H_ +#define _PCH_PCIE_RP_LIB_INTERNAL_H_ + +typedef struct { + UINT8 DevNum; + UINT8 Pid; + UINT8 RpNumBase; +} PCH_PCIE_CONTROLLER_INFO; + +#endif + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDx= eSmmPchPcieRpLib/PchPcieRpLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpB= lock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c new file mode 100644 index 0000000000..0702792597 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm +++ PchPcieRpLib/PchPcieRpLibVer2.c @@ -0,0 +1,71 @@ +/** @file + PCIE root port library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PchPcieRpLibInternal.h" + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_CONTROLLER_INFO=20 +mPchPcieControllerInfo[] =3D { + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1, PID_SPA, 0 }, + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5, PID_SPB, 4 }, + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9, PID_SPC, 8 }, + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13, PID_SPD, 12 }, + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17, PID_SPE, 16 }, // PCH-H=20 +only + { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21, PID_SPF, 20 } // PCH-H=20 +only }; + +/** + Get Pch Pcie Root Port Device and Function Number by Root Port=20 +physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device = number. + @param[out] RpFun Return corresponding root port functio= n number. + + @retval EFI_SUCCESS Root port device and function is retri= eved + @retval EFI_INVALID_PARAMETER RpNumber is invalid +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ) +{ + UINTN Index; + UINTN FuncIndex; + UINT32 PciePcd; + + if (RpNumber >=3D GetPchMaxPciePortNum ()) { + DEBUG ((DEBUG_ERROR, "GetPchPcieRpDevFun invalid RpNumber %x", RpNumbe= r)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Index =3D RpNumber / PCH_PCIE_CONTROLLER_PORTS; FuncIndex =3D RpNumber = -=20 + mPchPcieControllerInfo[Index].RpNumBase; + *RpDev =3D mPchPcieControllerInfo[Index].DevNum; + PciePcd =3D PchPcrRead32 (mPchPcieControllerInfo[Index].Pid,=20 + R_SPX_PCR_PCD); *RpFun =3D (PciePcd >> (FuncIndex *=20 + S_SPX_PCR_PCD_RP_FIELD)) & B_SPX_PCR_PCD_RP1FN; + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDx= eSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf b/Silicon/Intel/AlderlakeSil= iconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibV= er2.inf new file mode 100644 index 0000000000..0acafbfc43 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm +++ PchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf @@ -0,0 +1,37 @@ +## @file +# PCIE root port Library. +# +# All function in this library is available for PEI, DXE, and SMM, #=20 +But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchPcieRpLib +FILE_GUID =3D B522981C-E0C5-4E04-A82A-C61D4F0B2C75 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchPcieRpLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PchInfoLib +PchPcrLib + + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] +PchPcieRpLibVer2.c + -- 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108651): https://edk2.groups.io/g/devel/message/108651 Mute This Topic: https://groups.io/mt/101347728/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-