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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rangasai.v.chaganty@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: A96sNcl7dz9QVfkVztajkEAlx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=MqtpvGET; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Sai Chaganty -----Original Message----- From: Kasbekar, Saloni =20 Sent: Thursday, September 14, 2023 9:46 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, P= pi Includes Adds the following Includes: - Include/Library - Include/Pins - Include/Ppi Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Include/Library/ConfigBlockLib.h | 64 +++ .../Include/Library/EspiLib.h | 34 ++ .../Include/Library/GpioConfig.h | 372 ++++++++++++++++++ .../Include/Library/GpioLib.h | 174 ++++++++ .../Include/Library/GpioNativeLib.h | 135 +++++++ .../Include/Library/GraphicsInfoLib.h | 46 +++ .../Include/Library/MmPciLib.h | 27 ++ .../Include/Library/PchPcieRpLib.h | 41 ++ .../Include/Library/PchPcrLib.h | 221 +++++++++++ .../Library/PeiDxeSmmReserveMmio64SizeLib.h | 21 + .../Include/Library/PeiSiPolicyUpdateLib.h | 154 ++++++++ .../Include/Library/PmcLib.h | 40 ++ .../Include/Library/ResetSystemLib.h | 68 ++++ .../Include/Library/SecPlatformLib.h | 81 ++++ .../Include/Library/SiConfigBlockLib.h | 56 +++ .../Include/Library/SiPolicyLib.h | 39 ++ .../Include/Library/SpiLib.h | 21 + .../Include/Pins/GpioPinsVer2Lp.h | 36 ++ .../Include/Ppi/FspmArchConfigPpi.h | 32 ++ .../Include/Ppi/PeiPreMemSiDefaultPolicy.h | 33 ++ .../Include/Ppi/PeiSiDefaultPolicy.h | 33 ++ .../AlderlakeSiliconPkg/Include/Ppi/Spi.h | 29 ++ .../AlderlakeSiliconPkg/Include/Ppi/Wdt.h | 22 ++ 23 files changed, 1779 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/Confi= gBlockLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiL= ib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioC= onfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioL= ib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioN= ativeLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/Graph= icsInfoLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPci= Lib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPc= ieRpLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPc= rLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDx= eSmmReserveMmio64SizeLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSi= PolicyUpdateLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLi= b.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/Reset= SystemLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPl= atformLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiCon= figBlockLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPol= icyLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLi= b.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPins= Ver2Lp.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchC= onfigPpi.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMem= SiDefaultPolicy.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefa= ultPolicy.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockL= ib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h new file mode 100644 index 0000000000..d9966c76e9 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h @@ -0,0 +1,64 @@ +/** @file + Header file for Config Block Lib implementation + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CONFIG_BLOCK_LIB_H_ +#define _CONFIG_BLOCK_LIB_H_ + +/** + Create config block table + + @param[in] TotalSize - Max size to be allocated f= or the Config Block Table + @param[out] ConfigBlockTableAddress - On return, points to a poi= nter to the beginning of Config Block Table Address + + @retval EFI_INVALID_PARAMETER - Invalid Parameter + @retval EFI_OUT_OF_RESOURCES - Out of resources + @retval EFI_SUCCESS - Successfully created Config Block Table = at ConfigBlockTableAddress +**/ +EFI_STATUS +EFIAPI +CreateConfigBlockTable ( + IN UINT16 TotalSize, + OUT VOID **ConfigBlockTableAddress + ); + +/** + Add config block into config block table structure + + @param[in] ConfigBlockTableAddress - A pointer to the beginning= of Config Block Table Address + @param[out] ConfigBlockAddress - On return, points to a poi= nter to the beginning of Config Block Address + + @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add= new Config Block or + Config Block Offset Table is full and can= not add new Config Block. + @retval EFI_SUCCESS - Successfully added Config Block +**/ +EFI_STATUS +EFIAPI +AddConfigBlock ( + IN VOID *ConfigBlockTableAddress, + OUT VOID **ConfigBlockAddress + ); + +/** + Retrieve a specific Config Block data by GUID + + @param[in] ConfigBlockTableAddress - A pointer to the beginnin= g of Config Block Table Address + @param[in] ConfigBlockGuid - A pointer to the GUID use= s to search specific Config Block + @param[out] ConfigBlockAddress - On return, points to a po= inter to the beginning of Config Block Address + + @retval EFI_NOT_FOUND - Could not find the Config Block + @retval EFI_SUCCESS - Config Block found and return +**/ +EFI_STATUS +EFIAPI +GetConfigBlock ( + IN VOID *ConfigBlockTableAddress, + IN EFI_GUID *ConfigBlockGuid, + OUT VOID **ConfigBlockAddress + ); + +#endif // _CONFIG_BLOCK_LIB_H_ + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h b/= Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h new file mode 100644 index 0000000000..3c37def986 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h @@ -0,0 +1,34 @@ +/** @file + Header file for PchEspiLib. + All function in this library is available for PEI, DXE, and SMM, + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ESPI_LIB_H_ +#define _ESPI_LIB_H_ + +/** + Checks if there's second device connected under CS#1 + + @retval TRUE There's second device + @retval FALSE There's no second device +**/ +BOOLEAN +IsEspiSecondSlaveSupported ( + VOID + ); + +/** + Is eSPI enabled in strap. + + @retval TRUE Espi is enabled in strap + @retval FALSE Espi is disabled in strap +**/ +BOOLEAN +IsEspiEnabled ( + VOID + ); + +#endif // _ESPI_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h= b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h new file mode 100644 index 0000000000..43c0da46d7 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h @@ -0,0 +1,372 @@ +/** @file + Header file for GpioConfig structure used by GPIO library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GPIO_CONFIG_H_ +#define _GPIO_CONFIG_H_ + +#pragma pack(push, 1) + +/// +/// For any GpioPad usage in code use GPIO_PAD type +/// +typedef UINT32 GPIO_PAD; + +/// +/// GpioPad with additional native function information. +/// This type is used to represent signal muxing alternatives. Platform wi= ll provide such value to +/// identify muxing selection for given signal on a specific SOC. +/// Please refer to the board layout +/// +typedef UINT32 GPIO_NATIVE_PAD; + + +/// +/// For any GpioGroup usage in code use GPIO_GROUP type +/// +typedef UINT32 GPIO_GROUP; + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig, Host Software Pad Ownership and OutputStateLock are unn= ecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 5; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion, Out, both In and Out, both In = with inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 6; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). + This setting is applicable only if GPIO is in GpioMode with input enable= d. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 9; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 8; + /** + GPIO Electrical Configuration + This setting controls pads termination. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 9; + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 4; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 9; + + /** + Virtual GPIO eSPI Chip Select configuration + This setting selects between CS0 and CS1. + Refer to definition of VGPIO_CS_CONFIG for supported settings. + **/ + UINT32 VgpioCs : 2; + + UINT32 RsvdBits : 8; ///< Reserved bits for future extensio= n +} GPIO_CONFIG; + + +typedef enum { + GpioHardwareDefault =3D 0x0 ///< Leave setting unmodified +} GPIO_HARDWARE_DEFAULT; + +/** + GPIO Pad Mode + Refer to GPIO documentation on native functions available for certain pa= d. + If GPIO is set to one of NativeX modes then following settings are not a= pplicable + and can be skipped: + - Interrupt related settings + - Host Software Ownership + - Output/Input enabling/disabling + - Output lock +**/ +typedef enum { + GpioPadModeHwDefault =3D 0x0, + GpioPadModeGpio =3D 0x1, + GpioPadModeNative1 =3D 0x3, + GpioPadModeNative2 =3D 0x5, + GpioPadModeNative3 =3D 0x7, + GpioPadModeNative4 =3D 0x9, + GpioPadModeNative5 =3D 0xB, + GpioPadModeNative6 =3D 0xD, + GpioPadModeNative7 =3D 0xF +} GPIO_PAD_MODE; + +/** + Host Software Pad Ownership modes + This setting affects GPIO interrupt status registers. Depending on chose= n ownership + some GPIO Interrupt status register get updated and other masked. + Please refer to EDS for HOSTSW_OWN register description. +**/ +typedef enum { + GpioHostOwnDefault =3D 0x0, ///< Leave ownership value unmodified + /** + Set HOST ownership to ACPI. + Use this setting if pad is not going to be used by GPIO OS driver. + If GPIO is configured to generate SCI/SMI/NMI then this setting must be + used for interrupts to work + **/ + GpioHostOwnAcpi =3D 0x1, + /** + Set HOST ownership to GPIO Driver mode. + Use this setting only if GPIO pad should be controlled by GPIO OS Driver= . + GPIO OS Driver will be able to control the pad if appropriate entry in + ACPI exists (refer to ACPI specification for GpioIo and GpioInt descript= ors) + **/ + GpioHostOwnGpio =3D 0x3 +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault =3D 0x0, ///< Leave pad direction = setting unmodified + GpioDirInOut =3D (0x1 | (0x1 << 3)), ///< Set pad for both out= put and input + GpioDirInInvOut =3D (0x1 | (0x3 << 3)), ///< Set pad for both out= put and input with inversion + GpioDirIn =3D (0x3 | (0x1 << 3)), ///< Set pad for input on= ly + GpioDirInInv =3D (0x3 | (0x3 << 3)), ///< Set pad for input wi= th inversion + GpioDirOut =3D 0x5, ///< Set pad for output o= nly + GpioDirNone =3D 0x7 ///< Disable both output = and input +} GPIO_DIRECTION; + +/** + GPIO Output State + This field is relevant only if output is enabled +**/ +typedef enum { + GpioOutDefault =3D 0x0, ///< Leave output value unmodified + GpioOutLow =3D 0x1, ///< Set output to low + GpioOutHigh =3D 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/** + GPIO interrupt configuration + This setting is applicable only if pad is in GPIO mode and has input ena= bled. + GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/S= CI/SMI/NMI) + and how it is triggered (edge or level). Refer to PADCFG_DW0 register de= scription in + EDS for details on this settings. + Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to G= pioIntBothEdge + to describe an interrupt e.g. GpioIntApic | GpioIntLevel + If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this = pad. + If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this = pad. + Not all GPIO are capable of generating an SMI or NMI interrupt. + When routing GPIO to cause an IOxAPIC interrupt care must be taken, as t= his + interrupt cannot be shared and its IRQn number is not configurable. + Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) + If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt des= criptor + exist then use only trigger type setting (from GpioIntLevel to GpioIntBo= thEdge). + This type of GPIO Driver interrupt doesn't have any additional routing s= etting + required to be set by BIOS. Interrupt is handled by GPIO OS Driver. +**/ + +typedef enum { + GpioIntDefault =3D 0x0, ///< Leave value of interrupt routing= unmodified + GpioIntDis =3D 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI inte= rrupt generation + GpioIntNmi =3D 0x3, ///< Enable NMI interrupt only + GpioIntSmi =3D 0x5, ///< Enable SMI interrupt only + GpioIntSci =3D 0x9, ///< Enable SCI interrupt only + GpioIntApic =3D 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel =3D (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge =3D (0x3 << 5), ///< Set interrupt as edge triggered = (type of edge depends on input inversion) + GpioIntLvlEdgDis =3D (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge =3D (0x7 << 5) ///< Set interrupt as both edge trigg= ered +} GPIO_INT_CONFIG; + +#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CON= FIG for interrupt source +#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CON= FIG for interrupt type + +/** + GPIO Power Configuration + GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) w= hich will + be used to reset certain GPIO settings. + Refer to EDS for settings that are controllable by PadRstCfg. +**/ +typedef enum { + GpioResetDefault =3D 0x00, ///< Leave value of pad reset unmodi= fied + /** + Resume Reset (RSMRST) + GPP: PadRstCfg =3D 00b =3D "Powergood" + GPD: PadRstCfg =3D 11b =3D "Resume Reset" + Pad setting will reset on: + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + **/ + GpioResumeReset =3D 0x01, + /** + Host Deep Reset + PadRstCfg =3D 01b =3D "Deep GPIO Reset" + Pad settings will reset on: + - Warm/Cold/Global reset + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + **/ + GpioHostDeepReset =3D 0x03, + /** + Platform Reset (PLTRST) + PadRstCfg =3D 10b =3D "GPIO Reset" + Pad settings will reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + - G3 + **/ + GpioPlatformReset =3D 0x05, + /** + Deep Sleep Well Reset (DSW_PWROK) + GPP: not applicable + GPD: PadRstCfg =3D 00b =3D "Powergood" + Pad settings will reset on: + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + **/ + GpioDswReset =3D 0x07, + /** + Global reset. Server chipsets only. + PadRstCfg =3D 11b =3D "Global reset" + Pad settings will reset on: + - Global reset + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold reset + - DeepSx transition + **/ + GpioGlobalReset =3D 0x09 +} GPIO_RESET_CONFIG; + +/** + GPIO Electrical Configuration + Configuration options for GPIO termination setting +**/ +typedef enum { + GpioTermDefault =3D 0x0, ///< Leave termination setting unmodi= fied + GpioTermNone =3D 0x1, ///< none + GpioTermWpd5K =3D 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K =3D 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K =3D 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K =3D 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K =3D 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K =3D 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K =3D 0x1B, ///< 1kOhm & 2kOhm weak pull-up + /** + Native function controls pads termination + This setting is applicable only to some native modes. + Please check EDS to determine which native functionality + can control pads termination + **/ + GpioTermNative =3D 0x1F +} GPIO_ELECTRICAL_CONFIG; + +#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for = GPIO_ELECTRICAL_CONFIG for termination value + +/** + GPIO LockConfiguration + Set GPIO configuration lock and output state lock. + GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. + By default GPIO pads will be locked unless GPIO lib is explicitly + informed that certain pad is to be left unlocked. + Lock settings reset is in Powergood domain. Care must be taken when usin= g this setting + as fields it locks may be reset by a different signal and can be control= led + by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library pro= vides + functions which allow to unlock a GPIO pad. If possible each GPIO lib fu= nction will try to unlock + an already locked pad upon request for reconfiguration +**/ +typedef enum { + /** + Perform default action + - if pad is an GPO, lock configuration but leave output unlocked + - if pad is an GPI, lock everything + - if pad is in native, lock everything +**/ + GpioLockDefault =3D 0x0, + GpioPadConfigUnlock =3D 0x3, ///< Leave Pad configuration unlocked + GpioPadConfigLock =3D 0x1, ///< Lock Pad configuration + GpioOutputStateUnlock =3D 0xC, ///< Leave Pad output control unlocked + GpioPadUnlock =3D 0xF, ///< Leave both Pad configuration and = output control unlocked + GpioPadLock =3D 0x5, ///< Lock both Pad configuration and o= utput control + /** + Below statuses are used for + return from GpioGetPadConfig function + **/ + GpioLockTxLockCfgUnLock =3D 0x7, ///< Tx State locked, Pad Configuratio= n unlocked + GpioLockTxUnLockCfgLock =3D 0xD ///< Tx State unlocked, Pad Configurat= ion locked +} GPIO_LOCK_CONFIG; + +#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOC= K_CONFIG for Pad Configuration Lock +#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOC= K_CONFIG for Pad Output Lock + +/** + Other GPIO Configuration + GPIO_OTHER_CONFIG is used for less often settings and for future extensi= ons + Supported settings: + - RX raw override to '1' - allows to override input value to '1' + This setting is applicable only if in input mode (both in GPIO and n= ative usage). + The override takes place at the internal pad state directly from buf= fer and before the RXINV. +**/ +typedef enum { + GpioRxRaw1Default =3D 0x0, ///< Use default input override va= lue + GpioRxRaw1Dis =3D 0x1, ///< Don't override input + GpioRxRaw1En =3D 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +/** + Virtual GPIO eSPI Chip Select configuration + This setting selects between CS0 and CS1. + Supported settings: + - Chipselect CS0 and CS1 +**/ +typedef enum { + VgpioCs0 =3D 0x0, ///< Chipselect CS0 + VgpioCs1 =3D 0x1, ///< Chipselect CS1 +} VGPIO_CS_CONFIG; + +#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_= OTHER_CONFIG for RxRaw1 setting + +#pragma pack(pop) + +#endif //_GPIO_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h b/= Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h new file mode 100644 index 0000000000..d787e13be4 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h @@ -0,0 +1,174 @@ +/** @file + Header file for GpioLib. + All function in this library is available for PEI, DXE, and SMM + + @note: When GPIO pads are owned by ME Firmware, BIOS/host should not + attempt to access these GPIO Pads registers, registers value + returned in this case will be 0xFF. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GPIO_LIB_H_ +#define _GPIO_LIB_H_ + +#include + +typedef struct { + GPIO_PAD GpioPad; + GPIO_CONFIG GpioConfig; +} GPIO_INIT_CONFIG; + +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG = structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware def= ault values. + Separate fields could be set to hardware default if it does not matter, = except + GpioPad and PadMode. + Function will work in most efficient way if pads which belong to the sam= e group are + placed in adjacent records of the table. + Although function can enable pads for Native mode, such programming is d= one + by reference code when enabling related silicon feature. + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfull= y + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +/// +/// Possible values of Pad Ownership +/// If Pad is not under Host ownership then GPIO registers +/// are not accessible by host (e.g. BIOS) and reading them +/// will return 0xFFs. +/// +typedef enum { + GpioPadOwnHost =3D 0x0, + GpioPadOwnCsme =3D 0x1, + GpioPadOwnIsh =3D 0x2, +} GPIO_PAD_OWN; + +/** + This procedure will get Gpio Pad Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ); + +/** + This procedure will check state of Pad Config Lock for pads within one g= roup + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ); + +/** + This procedure will check state of Pad Config Tx Lock for pads within on= e group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ); + +/** + This procedure will clear PadCfgLock for selected pads within one group. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ); + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be l= ocked, + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ); + +/** + This procedure will clear PadCfgLockTx for selected pads within one grou= p. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ); + +#endif // _GPIO_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLi= b.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h new file mode 100644 index 0000000000..971f931442 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h @@ -0,0 +1,135 @@ +/** @file + Header file for GpioLib for native and Si specific usage. + All function in this library is available for PEI, DXE, and SMM, + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GPIO_NATIVE_LIB_H_ +#define _GPIO_NATIVE_LIB_H_ + +#include + +/** + This procedure will get number of pads for certain GPIO group + + @param[in] Group GPIO group number + + @retval Value Pad number for group + If illegal group number then return 0 +**/ +UINT32 +GpioGetPadPerGroup ( + IN GPIO_GROUP Group + ); + +/** + This procedure will get number of groups + + @param[in] none + + @retval Value Group number +**/ +UINT32 +GpioGetNumberOfGroups ( + VOID + ); +/** + This procedure will get lowest group + + @param[in] none + + @retval Value Lowest Group +**/ +GPIO_GROUP +GpioGetLowestGroup ( + VOID + ); + +/** + This procedure will get highest group + + @param[in] none + + @retval Value Highest Group +**/ +GPIO_GROUP +GpioGetHighestGroup ( + VOID + ); + +/** + This procedure will get group + + @param[in] GpioPad Gpio Pad + + @retval Value Group +**/ +GPIO_GROUP +GpioGetGroupFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from GpioPad + + @param[in] GpioPad Gpio Pad + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from group + + @param[in] GpioGroup Gpio Group + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGroup ( + IN GPIO_GROUP GpioGroup + ); + +/** + This procedure will get group from group index (0 based) + + @param[in] GroupIndex Group Index + + @retval GpioGroup Gpio Group +**/ +GPIO_GROUP +GpioGetGroupFromGroupIndex ( + IN UINT32 GroupIndex + ); + +/** + This procedure will get pad number (0 based) from Gpio Pad + + @param[in] GpioPad Gpio Pad + + @retval Value Pad Number +**/ +UINT32 +GpioGetPadNumberFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will return GpioPad from Group and PadNumber + + @param[in] Group GPIO group + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupAndPadNumber ( + IN GPIO_GROUP Group, + IN UINT32 PadNumber + ); + +#endif // _GPIO_NATIVE_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfo= Lib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h new file mode 100644 index 0000000000..bd9a7734b1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h @@ -0,0 +1,46 @@ +/** @file + Header file for Graphics Private Info Lib implementation. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_INFO_LIB_H_ +#define _GRAPHICS_INFO_LIB_H_ + +#include +#include +#include +#include + +/** + GetIgdBusNumber: Get IGD Bus Number + + @retval PCI bus number for IGD +**/ +UINT8 +GetIgdBusNumber ( + VOID + ); + +/** + GetIgdDevNumber: Get IGD Dev Number + + @retval PCI dev number for IGD +**/ +UINT8 +GetIgdDevNumber ( + VOID + ); + +/** + GetIgdFunNumber: Get IGD Fun Number + + @retval PCI fun number for IGD +**/ +UINT8 +GetIgdFuncNumber ( + VOID + ); + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h b= /Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h new file mode 100644 index 0000000000..04249eefdf --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h @@ -0,0 +1,27 @@ +/** @file + Get Pci Express address library implementation. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _MM_PCI_LIB_H_ +#define _MM_PCI_LIB_H_ + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +EFIAPI +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +); + +#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib= .h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h new file mode 100644 index 0000000000..d9ca215d85 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h @@ -0,0 +1,41 @@ +/** @file + Header file for PchPcieRpLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_PCIERP_LIB_H_ +#define _PCH_PCIERP_LIB_H_ + +#include +#include + +/** + Get Pch Pcie Root Port Device and Function Number by Root Port physical = Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device nu= mber. + @param[out] RpFun Return corresponding root port function = number. + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Gets pci segment base address of PCIe root port. + + @param RpIndex Root Port Index (0 based) + @return PCIe port base address. +**/ +UINT64 +PchPcieBase ( + IN UINT32 RpIndex + ); + +#endif // _PCH_PCIERP_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h = b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h new file mode 100644 index 0000000000..19a1a98639 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h @@ -0,0 +1,221 @@ +/** @file + Header file for PchPcrLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_PCR_LIB_H_ +#define _PCH_PCR_LIB_H_ + +#include + +/** + Definition for PCR address + The PCR address is used to the PCR MMIO programming + + SBREG_BAR_20BITADDRESS is configured by SoC + + SBREG_BAR_20BITADDRESS=3D1, the format has included 16b addressing. + +-----------------------------------------------------------------------= ----------------------+ + | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] = | Addr[1:0] | + +----------------+-----------------------+-----------------+------------= ----------------------+ + | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegis= ter[15:2] | + +-----------------------------------------------------------------------= ----------------------+ + + SBREG_BAR_20BITADDRESS=3D0 + +-----------------------------------------------------------------------= ----------------------+ + | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] = | Addr[1:0] | + +----------------+-----------------------+-----------------+------------= ----------------------+ + | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegis= ter[15:2] | + +-----------------------------------------------------------------------= ----------------------+ +**/ +#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (= ((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0= xFFFF)) + +/** + PCH PCR boot script accessing macro + Those macros are only available for DXE phase. +**/ +#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \ + S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), = Count, Buffer); \ + +#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd= ) \ + S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offse= t), DataOr, DataAnd); \ + +#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), B= itMask, BitValue, 1, 1); + +typedef UINT8 PCH_SBI_PID; + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT32 PCR register value. +**/ +UINT32 +PchPcrRead32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ); + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT16 PCR register value. +**/ +UINT16 +PchPcrRead16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ); + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT8 PCR register value +**/ +UINT8 +PchPcrRead8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter= . + + @retval UINT32 Value written to register +**/ +UINT32 +PchPcrWrite32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter= . + + @retval UINT16 Value written to register +**/ +UINT16 +PchPcrWrite16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT16 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter= . + + @retval UINT8 Value written to register +**/ +UINT8 +PchPcrWrite8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT8 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT32 Value written to register + +**/ +UINT32 +PchPcrAndThenOr32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT16 Value written to register + +**/ +UINT16 +PchPcrAndThenOr16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT8 Value written to register + +**/ +UINT8 +PchPcrAndThenOr8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + + +typedef enum { + PchIpDmi =3D 1, + PchIpIclk, +} PCH_IP_PID_ENUM; + + +#endif // _PCH_PCR_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmRes= erveMmio64SizeLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/Pei= DxeSmmReserveMmio64SizeLib.h new file mode 100644 index 0000000000..d27f858892 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmi= o64SizeLib.h @@ -0,0 +1,21 @@ +/** @file + PEI/DXE/SMM library for reserved 64-bit MMIO space. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_ +#define _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_ + +/** + The function return the 64 bit MMIO size to reserve. + + @retval The 64-bit MMIO size +**/ +UINT64 +ReserveMmio64Size ( + VOID + ); + +#endif // _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyU= pdateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyU= pdateLib.h new file mode 100644 index 0000000000..79e7752e4a --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLi= b.h @@ -0,0 +1,154 @@ +/** @file + Header file for PEI SiPolicyUpdate Library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SI_POLICY_UPDATE_LIB_H_ +#define _PEI_SI_POLICY_UPDATE_LIB_H_ + +#include + +/** + This function performs CPU PEI Policy initialization in Post-memory. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicy ( + VOID + ); + +/** + This function performs CPU PEI Policy initialization in PreMem. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyPreMem ( + VOID + ); + + +/** + This function performs SA PEI Policy initialization. + + @retval EFI_SUCCESS The PPI is installed and initialized. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicy ( + VOID + ); + +/** + This function performs SA PEI Policy initialization for PreMem. + + @retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyPreMem ( + VOID + ); + +/** + This function performs PCH PEI Policy initialization. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + VOID + ); + +/** + This function performs PCH PEI Policy initialization. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyPreMem ( + VOID + ); + +/** + Update the ME Policy Library + + @retval EFI_SUCCESS Update complete. + @retval Others Update unsuccessful. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicy ( + VOID + ); + +/** + Update the ME Policy Library + + @retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyPreMem ( + VOID + ); + + + +/** + Update the TBT Policy Library + + @retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +EFIAPI +UpdatePeiTbtPolicy ( + VOID + ); + +/** + Update the ME Server Policy Ppi (pre mem) + + @param[in, out] SiPreMemPolicyPpi PEI Pre Mem Si Policy + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. + @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function +**/ +EFI_STATUS +UpdatePeiMeServerPreMemPolicy ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy + ); + +/** + Update the ME Server Policy Ppi (post mem) + + @param[in, out] SiPolicyPpi PEI Si Policy + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. + @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function +**/ + EFI_STATUS +UpdatePeiMeServerPolicy ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h b/S= ilicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h new file mode 100644 index 0000000000..7d49a14164 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h @@ -0,0 +1,40 @@ +/** @file + Header file for PmcLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PMC_LIB_H_ +#define _PMC_LIB_H_ + +#include + + +typedef struct { + UINT32 Buf0; + UINT32 Buf1; + UINT32 Buf2; + UINT32 Buf3; +} PMC_IPC_COMMAND_BUFFER; + +/** + Get PCH ACPI base address. + + @retval Address Address of PWRM base address. +**/ +UINT16 +PmcGetAcpiBase ( + VOID + ); + +/** + Get PCH PWRM base address. + + @retval Address Address of PWRM base address. +**/ +UINT32 +PmcGetPwrmBase ( + VOID + ); + +#endif // _PMC_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemL= ib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h new file mode 100644 index 0000000000..6146e8610d --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h @@ -0,0 +1,68 @@ +/** @file + System reset Library Services. This library class defines a set of + methods that reset the whole system. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __RESET_SYSTEM_LIB_H__ +#define __RESET_SYSTEM_LIB_H__ + +/** + This function causes a system-wide reset (cold reset), in which + all circuitry within the system returns to its initial state. This type = of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + If this function returns, it means that the system does not support cold= reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ); + +/** + This function causes a system-wide initialization (warm reset), in which= all processors + are set to their initial state. Pending cycles are not corrupted. + + If this function returns, it means that the system does not support warm= reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ); + +/** + This function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + If this function returns, it means that the system does not support shut= down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ); + +/** + This function causes a systemwide reset. The exact type of the reset is + defined by the EFI_GUID that follows the Null-terminated Unicode string = passed + into ResetData. If the platform does not recognize the EFI_GUID in Reset= Data + the platform must pick a supported reset type to perform.The platform ma= y + optionally log the parameters from any non-normal reset that occurs. + + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData The data buffer starts with a Null-terminated str= ing, + followed by the EFI_GUID. +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData + ); + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformL= ib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h new file mode 100644 index 0000000000..7fa23b1a51 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h @@ -0,0 +1,81 @@ +/** @file + Prototype of SEC Platform hook library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SEC_PLATFORM_LIB_H_ +#define _SEC_PLATFORM_LIB_H_ + +#include +#include + +/** + A developer supplied function to perform platform specific operations. + + It's a developer supplied function to perform any operations appropriate= to a + given platform. It's invoked just before passing control to PEI core by = SEC + core. Platform developer may modify the SecCoreData passed to PEI Core. + It returns a platform specific PPI list that platform wishes to pass to = PEI core. + The Generic SEC core module will merge this list to join the final list = passed to + PEI core. + + @param SecCoreData The same parameter as passing to PEI core.= It + could be overridden by this function. + + @return The platform specific PPI list to be passed to PEI core or + NULL if there is no need of such platform specific PPI list. + +**/ +EFI_PEI_PPI_DESCRIPTOR * +EFIAPI +SecPlatformMain ( + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData + ); + + +/** + This interface conveys state information out of the Security (SEC) phase= into PEI. + + @param PeiServices Pointer to the PEI Services Table. + @param StructureSize Pointer to the variable describing siz= e of the input buffer. + @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORM= ATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ); + +/** + This interface conveys performance information out of the Security (SEC)= phase into PEI. + + This service is published by the SEC phase. The SEC phase handoff has an= optional + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the + PEI Foundation. As such, if the platform supports collecting performance= data in SEC, + this information is encapsulated into the data structure abstracted by t= his service. + This information is collected for the boot-strap processor (BSP) on IA-3= 2. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI. + @param[out] Performance The pointer to performance data collected in SE= C phase. + + @retval EFI_SUCCESS The data was successfully returned. +**/ +EFI_STATUS +EFIAPI +SecGetPerformance ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_SEC_PERFORMANCE_PPI *This, + OUT FIRMWARE_SEC_PERFORMANCE *Performance + ); + +#endif + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBloc= kLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib= .h new file mode 100644 index 0000000000..7bb111a932 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h @@ -0,0 +1,56 @@ +/** @file + Prototype of the SiConfigBlockLib library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SI_CONFIG_BLOCK_LIB_H_ +#define _SI_CONFIG_BLOCK_LIB_H_ + + +typedef +VOID +(*LOAD_DEFAULT_FUNCTION) ( + IN VOID *ConfigBlockPointer + ); + +typedef struct { + EFI_GUID *Guid; + UINT16 Size; + UINT8 Revision; + LOAD_DEFAULT_FUNCTION LoadDefault; +} COMPONENT_BLOCK_ENTRY; + +/** + GetComponentConfigBlockTotalSize get config block table total size. + + @param[in] ComponentBlocks Component blocks array + @param[in] TotalBlockCount Number of blocks + + @retval Size of config block table +**/ +UINT16 +EFIAPI +GetComponentConfigBlockTotalSize ( + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, + IN UINT16 TotalBlockCount + ); + +/** + AddComponentConfigBlocks add all config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add config blocks + @param[in] ComponentBlocks Config blocks array + @param[in] TotalBlockCount Number of blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +AddComponentConfigBlocks ( + IN VOID *ConfigBlockTableAddress, + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, + IN UINT16 TotalBlockCount + ); +#endif // _SI_CONFIG_BLOCK_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.= h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h new file mode 100644 index 0000000000..f821ea2fdf --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h @@ -0,0 +1,39 @@ +/** @file + Prototype of the SiPolicyLib library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SI_POLICY_LIB_H_ +#define _SI_POLICY_LIB_H_ + +#include + +/** + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiPreMemInstallPolicyReadyPpi ( + VOID + ); + +/** + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiInstallPolicyReadyPpi ( + VOID + ); +#endif // _SI_POLICY_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h b/S= ilicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h new file mode 100644 index 0000000000..ca56e74e0f --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h @@ -0,0 +1,21 @@ +/** @file + Header file for Spi Library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SPI_LIB_H_ +#define _SPI_LIB_H_ + +/** + This function Initial SPI services + + @retval EFI_STATUS Results of the installation of the SPI services +**/ +EFI_STATUS +EFIAPI +SpiServiceInit ( + VOID + ); + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.= h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h new file mode 100644 index 0000000000..2f58de78f6 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h @@ -0,0 +1,36 @@ +/** @file + GPIO pins for TGL-PCH-LP, + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GPIO_PINS_VER2_LP_H_ +#define _GPIO_PINS_VER2_LP_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// Unique ID used in GpioPad defines +/// +#define GPIO_VER2_LP_CHIPSET_ID 0x9 + +/// +/// TGL LP GPIO pins +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_VER2_LP_GPP_H0 0x09070000 +#define GPIO_VER2_LP_GPP_H1 0x09070001 +#define GPIO_VER2_LP_GPP_D16 0x09080010 +#define GPIO_VER2_LP_GPP_C2 0x090B0002 + +#define GPIO_VER2_LP_GPP_F9 0x090C0009 +#define GPIO_VER2_LP_GPP_F10 0x090C000A +#define GPIO_VER2_LP_GPP_F20 0x090C0014 + +#define GPIO_VER2_LP_GPP_E7 0x090E0007 +#endif // _GPIO_PINS_VER2_LP_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPp= i.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h new file mode 100644 index 0000000000..7ed834b9f5 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h @@ -0,0 +1,32 @@ +/** @file + Header file for FSP-M Arch Config PPI + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FSPM_ARCH_CONFIG_PPI_H_ +#define _FSPM_ARCH_CONFIG_PPI_H_ + +/// +/// Global ID for the FSPM_ARCH_CONFIG_PPI. +/// +#define FSPM_ARCH_CONFIG_GUID \ + { \ + 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a= , 0xbb } \ + } + +/// +/// This PPI provides FSP-M Arch Config PPI. +/// +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + VOID *NvsBufferPtr; + UINT32 BootLoaderTolumSize; + UINT8 Reserved1[4]; +} FSPM_ARCH_CONFIG_PPI; + +extern EFI_GUID gFspmArchConfigPpiGuid; + +#endif // _FSPM_ARCH_CONFIG_PPI_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefau= ltPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefau= ltPolicy.h new file mode 100644 index 0000000000..0713dbd55b --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolic= y.h @@ -0,0 +1,33 @@ +/** @file + This file defines the function to initialize default silicon policy PPI. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ + +// +// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. +// +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAUL= T_POLICY_INIT_PPI; + +/** + Initialize and install default silicon policy PPI +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_PREMEM_POLICY_INIT) ( + VOID + ); + +/// +/// This PPI provides function to install default silicon policy +/// +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI { + PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit= () +}; + +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid; + +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPoli= cy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h new file mode 100644 index 0000000000..83bdbe0f6e --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h @@ -0,0 +1,33 @@ +/** @file + This file defines the function to initialize default silicon policy PPI. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ + +// +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI. +// +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_= PPI; + +/** + Initialize and install default silicon policy PPI +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_POLICY_INIT) ( + VOID + ); + +/// +/// This PPI provides function to install default silicon policy +/// +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI { + PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit() +}; + +extern EFI_GUID gSiDefaultPolicyInitPpiGuid; + +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h b/Silicon/= Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h new file mode 100644 index 0000000000..0faf1e3443 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h @@ -0,0 +1,29 @@ +/** @file + This file defines the PCH SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + @note The APIs in this file are designed to be backward compatible with + previous versions. Any change in behavior of these APIs will result in + newer version of the API. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a PeiSe= rvice pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h b/Silicon/= Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h new file mode 100644 index 0000000000..bd8163fea0 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h @@ -0,0 +1,22 @@ +/** @file + Watchdog Timer PPI + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PEI_WDT_H_ +#define _PEI_WDT_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gWdtPpiGuid; + +/// +/// Reuse WDT_PROTOCOL definition +/// +typedef WDT_PROTOCOL WDT_PPI; + +#endif --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108692): https://edk2.groups.io/g/devel/message/108692 Mute This Topic: https://groups.io/mt/101373950/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-