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devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rangasai.v.chaganty@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: tfnAwxTRvSBYyJpYFCEZQKNTx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=tUCjyYJj; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Sai Chaganty -----Original Message----- From: Kasbekar, Saloni =20 Sent: Thursday, September 14, 2023 9:46 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePr= ivate modules Adds the following modules: - AdlPch/Include - AdlPch/IncludePrivate - AdlPch/Library - AdlPch DSCs - IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Fru/AdlPch/CommonLib.dsc | 29 ++ .../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc | 10 + .../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc | 7 + .../Fru/AdlPch/Include/PchBdfAssignment.h | 81 +++++ .../Fru/AdlPch/Include/PchLimits.h | 47 +++ .../Fru/AdlPch/Include/PchPcieRpInfo.h | 17 ++ .../Fru/AdlPch/Include/PchReservedResources.h | 13 + .../AdlPch/Include/= PchReservedResourcesAdpP.h | 36 +++ .../IncludePrivate/Register/PchPcrRegs.h | 59 ++++ .../IncludePrivate/Register/PchRegsLpcAdl.h | 30 ++ .../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c | 223 ++++++++++++++ .../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 44 +++ .../PeiDxeSmmPchInfoLibAdl.inf | 37 +++ .../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc | 7 + .../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc | 12 + .../IncludePrivate/RegisterAccess.h | 288 ++++++++++++++++++ 16 files changed, 940 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.= dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hBdfAssignment.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hLimits.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hPcieRpInfo.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hReservedResources.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hReservedResourcesAdpP.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePri= vate/Register/PchPcrRegs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePri= vate/Register/PchRegsLpcAdl.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/Pe= iDxeSmmPchInfoLib/PchInfoLibAdl.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/Pe= iDxeSmmPchInfoLib/PchInfoLibPrivate.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/Pe= iDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/Regist= erAccess.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc b/S= ilicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc new file mode 100644 index 0000000000..3f508f83a1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc @@ -0,0 +1,29 @@ +## @file +# Component description file for the AlderLake PCH Common FRU libraries. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + =20 + PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL + ib/PeiDxeSmmPchPcrLib.inf =20 + PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei + DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf + =20 + P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva + te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf + + =20 + EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P + eiDxeSmmEspiLib.inf + + + =20 + PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD + xeSmmPmcLib.inf =20 + PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe + SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf + =20 + SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi + CommonLib/BaseSpiCommonLib.inf =20 + GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P + eiDxeSmmGpioLib.inf =20 + PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS + mmPchDmiLib/PeiDxeSmmPchDmiLib.inf + + =20 + GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD + xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf + =20 + PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPc + hPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf + + + # + # Common FRU Libraries + # + =20 + PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoL + ib/PeiDxeSmmPchInfoLibAdl.inf + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc b/Silicon= /Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc new file mode 100644 index 0000000000..b443611d9a --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc @@ -0,0 +1,10 @@ +## @file +# Component description file for the AlderLake PCH DXE FRU drivers. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + $(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf + + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc b/Sili= con/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc new file mode 100644 index 0000000000..e350b8e643 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc @@ -0,0 +1,7 @@ +# @file +# Component description file for the AlderLake PCH DXE FRU libraries. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + =20 +GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/BaseG +pioHelpersLibNull/BaseGpioHelpersLibNull.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAss= ignment.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssi= gnment.h new file mode 100644 index 0000000000..b8af6d7624 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignm +++ ent.h @@ -0,0 +1,81 @@ +/** @file + Header file for AlderLake PCH devices PCI Bus Device Function map. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_BDF_ASSIGNMENT_H_ #define _PCH_BDF_ASSIGNMENT_H_ + +#define NOT_PRESENT 0xFF + +// +// PCH PCIe Controllers +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27 +#ifdef PCH_ADPP +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT +#else +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 26 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 26 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 26 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 26 +#endif + +// +// USB3 (XHCI) Controller PCI config +// +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + + + + +// +// LPC Controller (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +// +// Primary to Sideband (P2SB) Bridge (D31:F1) // +#define PCI_DEVICE_NUMBER_PCH_P2SB 31 +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1 + + + +// +// SPI Controller (D31:F5) +// +#define PCI_DEVICE_NUMBER_PCH_SPI 31 +#define PCI_FUNCTION_NUMBER_PCH_SPI 5 + + +#endif // _PCH_BDF_ASSIGNMENT_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits= .h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h new file mode 100644 index 0000000000..dad3a9a073 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h @@ -0,0 +1,47 @@ +/** @file + Build time limits of PCH resources. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_LIMITS_H_ #define _PCH_LIMITS_H_ +/* + * Defines povided in this file are indended to be used only where=20 +static value + * is needed. They are set to values which allow to accomodate multiple=20 +projects + * needs. Where runtime usage is possible please used dedicated=20 +functions from + * PchInfoLib to retrieve accurate values */ + + + +// +// PCIe limits +// +#define PCH_MAX_PCIE_ROOT_PORTS 28 +#define PCH_MAX_PCIE_CONTROLLERS 7 + +// +// PCIe clocks limits +// +#define PCH_MAX_PCIE_CLOCKS 18 + +// +// DMI lanes +// +#define PCH_MAX_DMI_LANES 8 + +// +// SerialIo limits +// +#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8 +#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7 +#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2 +#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7 + +// +// Number of eSPI slaves +// +#define PCH_MAX_ESPI_SLAVES 2 + +#endif // _PCH_LIMITS_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRp= Info.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo= .h new file mode 100644 index 0000000000..9276b61e1f --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo +++ .h @@ -0,0 +1,17 @@ +/** @file + Pcie Root Port info header + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_PCIERP_INFO_H_ +#define _PCH_PCIERP_INFO_H_ + +// +// Number of PCIe ports per PCIe controller // +#define PCH_PCIE_CONTROLLER_PORTS 4u + + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReserv= edResources.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchRes= ervedResources.h new file mode 100644 index 0000000000..f4adfab74f --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe +++ sources.h @@ -0,0 +1,13 @@ +/** @file + PCH preserved MMIO resource definitions. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_PRESERVED_RESOURCES_H_ +#define _PCH_PRESERVED_RESOURCES_H_ +#include "PchReservedResourcesAdpP.h" + +#endif // _PCH_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReserv= edResourcesAdpP.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hReservedResourcesAdpP.h new file mode 100644 index 0000000000..69aac29cea --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe +++ sourcesAdpP.h @@ -0,0 +1,36 @@ +/** @file + PCH preserved MMIO resource definitions. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_PRESERVED_RESOURCES_ADP_P_H_ +#define _PCH_PRESERVED_RESOURCES_ADP_P_H_ + +/** + Detailed recommended static allocation + +-----------------------------------------------------------------------= --+ + | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF = | + +-----------------------------------------------------------------------= --+ + | Size | Start | End | Usage = | + | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR = | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = | + | 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode = | + | 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused = | + | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR = | + | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR = | + | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused = | + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR = | + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR = | + | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused = | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = | + =20 ++---------------------------------------------------------------------- +---+ +**/ +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO bas= e address +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO = base address +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO = base address + +#endif // _PCH_PRESERVED_RESOURCES_ADP_P_H_ + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Re= gister/PchPcrRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludeP= rivate/Register/PchPcrRegs.h new file mode 100644 index 0000000000..fe548dae4b --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist +++ er/PchPcrRegs.h @@ -0,0 +1,59 @@ +/** @file + Register names for PCH private chipset register + +Conventions: + + - Register definition format: + =20 + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re + gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI pro= gramming as well. +**/ +#define PID_DMI 0x88 +#define PID_ESPISPI 0x72 +#define PID_SPF 0x85 +#define PID_SPE 0x84 +#define PID_SPD 0x83 +#define PID_SPC 0x82 +#define PID_SPB 0x81 +#define PID_SPA 0x80 +#define PID_GPIOCOM0 0x6E +#define PID_GPIOCOM1 0x6D +#define PID_GPIOCOM2 0x6C +#define PID_GPIOCOM4 0x6A +#define PID_GPIOCOM5 0x69 + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Re= gister/PchRegsLpcAdl.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Inclu= dePrivate/Register/PchRegsLpcAdl.h new file mode 100644 index 0000000000..8b1a01036e --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist +++ er/PchRegsLpcAdl.h @@ -0,0 +1,30 @@ +/** @file + Register names for ADL PCH LPC/eSPI device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_REGS_LPC_ADL_H_ #define _PCH_REGS_LPC_ADL_H_ + +// +// ADL PCH-P/M LPC Device IDs +// +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0 0x5180 ///< LP= C/eSPI Controller +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1 0x5181 ///< LP= C/eSPI Controller P SuperSKU +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2 0x5182 ///< LP= C/eSPI Controller P Premium +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3 0x5183 ///< LP= C/eSPI Controller Placeholder +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4 0x5184 ///< LP= C/eSPI Controller +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5 0x5185 ///< LP= C/eSPI Controller + + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmm= PchInfoLib/PchInfoLibAdl.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/L= ibrary/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c new file mode 100644 index 0000000000..c74d665533 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchI +++ nfoLib/PchInfoLibAdl.c @@ -0,0 +1,223 @@ +/** @file + Pch information library for ADL. + + All function in this library is available for PEI, DXE, and SMM, But=20 + do not support UEFI RUNTIME environment call. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include =20 +#include #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include "PchInfoLibPrivate.h" + + +/** + Return LPC Device Id + + @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID +**/ +UINT16 +PchGetLpcDid ( + VOID + ) +{ + UINT64 LpcBaseAddress; + + LpcBaseAddress =3D LpcPciCfgBase (); + + return PciSegmentRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); +} + +/** + Return Pch Series + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeries ( + VOID + ) +{ + PCH_SERIES PchSer; + static PCH_SERIES PchSeries =3D PCH_UNKNOWN_SERIES; + + if (PchSeries !=3D PCH_UNKNOWN_SERIES) { + return PchSeries; + } + + PchSer =3D PchSeriesFromLpcDid (PchGetLpcDid ()); + + PchSeries =3D PchSer; + + return PchSer; +} + +/** + Return Pch stepping type + + @retval PCH_STEPPING Pch stepping type +**/ +PCH_STEPPING +PchStepping ( + VOID + ) +{ + UINT8 RevId; + UINT64 LpcBaseAddress; + static PCH_STEPPING PchStepping =3D PCH_STEPPING_MAX; + + if (PchStepping !=3D PCH_STEPPING_MAX) { + return PchStepping; + } + + LpcBaseAddress =3D LpcPciCfgBase (); + RevId =3D PciSegmentRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET); + + RevId =3D PchSteppingFromRevId (RevId); + + PchStepping =3D RevId; + + return RevId; +} + +/** + Check if this is PCH P series + + @retval TRUE It's PCH P series + @retval FALSE It's not PCH P series +**/ +BOOLEAN +IsPchP ( + VOID + ) +{ + return (PchSeries () =3D=3D PCH_P); +} + +/** + return support status for P2SB PCR 20-bit addressing + + @retval TRUE + @retval FALSE +**/ +BOOLEAN +IsP2sb20bPcrSupported ( + VOID + ) +{ + return FALSE; +} + +/** + Determine Pch Series based on Device Id + + @param[in] LpcDeviceId Lpc Device Id + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeriesFromLpcDid ( + IN UINT16 LpcDeviceId + ) +{ + return PCH_P; +} + +/** + Determine Pch Stepping based on Revision ID + + @param[in] RevId Pch Revision Id + + @retval PCH_STEPPING Pch Stepping +**/ +PCH_STEPPING +PchSteppingFromRevId ( + IN UINT8 RevId + ) +{ + return RevId; +} + + +/** + Check if this is PCH LP series + + @retval TRUE It's PCH LP series + @retval FALSE It's not PCH LP series +**/ +BOOLEAN +IsPchLp ( + VOID + ) +{ + return (PchSeries () =3D=3D PCH_LP || PchSeries () =3D=3D PCH_P || PchSe= ries () =3D=3D PCH_M || PchSeries () =3D=3D PCH_N ); +} +/** + Get RST mode supported by the silicon + + @retval RST_MODE RST mode supported by silicon +**/ + +GLOBAL_REMOVE_IF_UNREFERENCED +struct PCH_SKU_STRING mSkuStrs[] =3D { + // + // ADL PCH LPC Device IDs + // + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0, "ADL SKU 0"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1, "P Super SKU (SSKU)"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2, "P Premium"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3, "ADL No UFS"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4, "ADL SKU 4"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5, "ADL SKU 5"}, + + {0xFFFF, NULL} +}; + +/** + Get Pch Maximum Pcie Root Port Number + + @retval Pch Maximum Pcie Root Port Number +**/ +UINT8 +GetPchMaxPciePortNum ( + VOID + ) +{ + switch (PchSeries ()) { + case PCH_P: + case PCH_N: + return 12; + case PCH_S: + return 28; + default: + return 0; + } +} + +/** + Get Pch Maximum Serial IO I2C controllers number + + @retval Pch Maximum Serial IO I2C controllers number +**/ +UINT8 +GetPchMaxSerialIoI2cControllersNum ( + VOID + ) +{ + return 8; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmm= PchInfoLib/PchInfoLibPrivate.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlP= ch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h new file mode 100644 index 0000000000..a4bd4d5aa7 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfo= Lib/PchInfoLibPrivate.h @@ -0,0 +1,44 @@ +/** @file + Private header for PCH Info Lib. + + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +/** + Structure for PCH SKU string mapping +**/ +struct PCH_SKU_STRING { + UINT16 Id; + CHAR8 *String; +}; + +extern struct PCH_SKU_STRING mSkuStrs[]; + +/** + Determine Pch Series based on Device Id + + @param[in] LpcDeviceId Lpc Device Id + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeriesFromLpcDid ( + IN UINT16 LpcDeviceId + ); + +/** + Determine Pch Stepping based on Revision ID + + @param[in] RevId Pch Revision Id + + @retval PCH_STEPPING Pch Stepping +**/ +PCH_STEPPING +PchSteppingFromRevId ( + IN UINT8 RevId + ); + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmm= PchInfoLib/PeiDxeSmmPchInfoLibAdl.inf b/Silicon/Intel/AlderlakeSiliconPkg/F= ru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf new file mode 100644 index 0000000000..28a6863aed --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfo= Lib/PeiDxeSmmPchInfoLibAdl.inf @@ -0,0 +1,37 @@ +## @file +# PCH information library for Alderlake PCH. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchInfoLibAdl +FILE_GUID =3D F5B0CBB7-4AFC-4535-A5EC-D9ECEDA24DC5 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchInfoLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PrintLib +PciSegmentLib +PmcPrivateLib +PcdLib + + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] +PchInfoLibAdl.c diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc b/Silicon= /Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc new file mode 100644 index 0000000000..8a923554dd --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc @@ -0,0 +1,7 @@ +## @file +# Component description file for the AlderLake PCH PEI FRU drivers. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc b/Sili= con/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc new file mode 100644 index 0000000000..ebe2bbfda0 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc @@ -0,0 +1,12 @@ +## @file +# Component description file for the AlderLake PCH PEI FRU libraries. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + SpiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.in= f + + GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiGpi= oHelpersLib/PeiGpioHelpersLib.inf + + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAcces= s.h b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h new file mode 100644 index 0000000000..25a0ba49d2 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h @@ -0,0 +1,288 @@ +/** @file + Header file for register access. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _REGISTER_ACCESS_H_ +#define _REGISTER_ACCESS_H_ + +typedef struct _REGISTER_ACCESS REGISTER_ACCESS; + +/** + Reads an 8-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + + @return The 8-bit register value specified by Offset +**/ +typedef +UINT8 +(*REG_READ8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset + ); + +/** + Writes an 8-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] Value Value to write to register + + @return The 8-bit register value written to register +**/ +typedef +UINT8 +(*REG_WRITE8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT8 Value + ); + +/** + Performs an 8-bit or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] OrData Data with which register should be OR-ed + + @return The 8-bit register value written to register +**/ +typedef +UINT8 +(*REG_OR8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT8 OrData + ); + +/** + Performs an 8-bit and on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + + @return The 8-bit register value written to register +**/ +typedef +UINT8 +(*REG_AND8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT8 AndData + ); + +/** + Performs an 8-bit and then or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + @param[in] OrData Data with which register should be OR-ed + + @return The 8-bit register value written to register +**/ +typedef +UINT8 +(*REG_AND_THEN_OR8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + + @return The 16-bit register value specified by Offset +**/ +typedef +UINT16 +(*REG_READ16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset + ); + +/** + Writes a 16-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] Value Value to write to register + + @return The 16-bit register value written to register +**/ +typedef +UINT16 +(*REG_WRITE16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT16 Value + ); + +/** + Performs a 16-bit or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] OrData Data with which register should be OR-ed + + @return The 16-bit register value written to register +**/ +typedef +UINT16 +(*REG_OR16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT16 OrData + ); + +/** + Performs a 16-bit and on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + + @return The 16-bit register value written to register +**/ +typedef +UINT16 +(*REG_AND16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT16 AndData + ); + +/** + Performs a 16-bit and then or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + @param[in] OrData Data with which register should be OR-ed + + @return The 16-bit register value written to register +**/ +typedef +UINT16 +(*REG_AND_THEN_OR16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + + @return The 32-bit register value specified by Offset +**/ +typedef +UINT32 +(*REG_READ32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset + ); + +/** + Writes a 32-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] Value Value to write to register + + @return The 32-bit register value written to register +**/ +typedef +UINT32 +(*REG_WRITE32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT32 Value + ); + +/** + Performs a 32-bit or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] OrData Data with which register should be OR-ed + + @return The 32-bit register value written to register +**/ +typedef +UINT32 +(*REG_OR32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT32 OrData + ); + +/** + Performs a 32-bit and on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + + @return The 32-bit register value written to register +**/ +typedef +UINT32 +(*REG_AND32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT32 AndData + ); + +/** + Performs a 32-bit and then or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + @param[in] OrData Data with which register should be OR-ed + + @return The 32-bit register value written to register +**/ +typedef +UINT32 +(*REG_AND_THEN_OR32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +struct _REGISTER_ACCESS { + REG_READ8 Read8; + REG_WRITE8 Write8; + REG_OR8 Or8; + REG_AND8 And8; + REG_AND_THEN_OR8 AndThenOr8; + + REG_READ16 Read16; + REG_WRITE16 Write16; + REG_OR16 Or16; + REG_AND16 And16; + REG_AND_THEN_OR16 AndThenOr16; + + REG_READ32 Read32; + REG_WRITE32 Write32; + REG_OR32 Or32; + REG_AND32 And32; + REG_AND_THEN_OR32 AndThenOr32; +}; + +#endif --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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