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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rangasai.v.chaganty@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 5IvaVuW93iF25p18YPtPhoAtx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=ck3Yonfm; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Sai Chaganty -----Original Message----- From: Kasbekar, Saloni =20 Sent: Wednesday, September 13, 2023 3:14 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi compon= ents Adds the following modules: - IpBlock/P2sb/IncludePrivate - IpBlock/P2sb/Library - IpBlock/P2sb/LibraryPrivate - IpBlock/PchDmi/IncludePrivate - IpBlock/PchDmi/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Library/P2SbSidebandAccessLib.h | 105 +++++++ .../IncludePrivate/Library/PchSbiAccessLib.h | 58 ++++ .../P2sb/IncludePrivate/P2SbController.h | 32 +++ .../P2sb/IncludePrivate/Register/P2sbRegs.h | 53 ++++ .../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 266 ++++++++++++++++++ .../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf | 35 +++ .../PeiDxeSmmP2SbSidebandAccessLib.c | 208 ++++++++++++++ .../PeiDxeSmmP2SbSidebandAccessLib.inf | 30 ++ .../PchSbiAccessLib.c | 72 +++++ .../PeiDxeSmmPchSbiAccessLib.inf | 35 +++ .../PchDmi/IncludePrivate/Library/PchDmiLib.h | 60 ++++ .../PeiDxeSmmPchDmiLib/PchDmi14.c | 34 +++ .../PeiDxeSmmPchDmiLib/PchDmi14.h | 22 ++ .../PeiDxeSmmPchDmiLib/PchDmiLib.c | 110 ++++++++ .../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 43 +++ 15 files changed, 1163 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludeP= rivate/Library/P2SbSidebandAccessLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludeP= rivate/Library/PchSbiAccessLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludeP= rivate/P2SbController.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludeP= rivate/Register/P2sbRegs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/= PeiDxeSmmPchPcrLib/PchPcrLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/= PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryP= rivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryP= rivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryP= rivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryP= rivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/Includ= ePrivate/Library/PchDmiLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/Librar= yPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/Librar= yPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/Librar= yPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/Librar= yPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/= Library/P2SbSidebandAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock= /P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h new file mode 100644 index 0000000000..e364508eb4 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr +++ ary/P2SbSidebandAccessLib.h @@ -0,0 +1,105 @@ +/** @file + Header for P2SbSidebandAccessLib + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_ +#define _P2SB_SIDEBAND_ACCESS_LIB_H_ + +#include +#include +#include // For PCH_SBI_PID definition + +typedef PCH_SBI_PID P2SB_PID; + +typedef enum { + P2SbMemory =3D 0, + P2SbPciConfig, + P2SbPrivateConfig +} P2SB_REGISTER_SPACE; + +typedef enum { + MemoryRead =3D 0x0, + MemoryWrite =3D 0x1, + PciConfigRead =3D 0x4, + PciConfigWrite =3D 0x5, + PrivateControlRead =3D 0x6, + PrivateControlWrite =3D 0x7, + GpioLockUnlock =3D 0x13 +} P2SB_SBI_OPCODE; + +typedef enum { + SBI_SUCCESSFUL =3D 0, + SBI_UNSUCCESSFUL =3D 1, + SBI_POWERDOWN =3D 2, + SBI_MIXED =3D 3, + SBI_INVALID_RESPONSE +} P2SB_SBI_RESPONSE; + +typedef enum { + P2SbMmioAccess =3D 0, + P2SbMsgAccess +} P2SB_SIDEBAND_ACCESS_METHOD; + +/** + REGISTER_ACCESS for P2SB device to support access to sideband registers. + Be sure to keep first member of this structure as REGISTER_ACCESS to=20 +allow + for correct casting between caller who sees this structure as=20 +REGISTER_ACCESS + and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS. +**/ +typedef struct { + REGISTER_ACCESS Access; + P2SB_SIDEBAND_ACCESS_METHOD AccessMethod; + P2SB_PID P2SbPid; + UINT16 Fid; + P2SB_REGISTER_SPACE RegisterSpace; + BOOLEAN PostedWrites; + P2SB_CONTROLLER *P2SbCtrl; +} P2SB_SIDEBAND_REGISTER_ACCESS; + +/** + Full function for executing P2SB SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the=20 +PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally=20 +hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to=20 + be checked as it would have been SBI_SUCCESS. If the return value is=20 + "EFI_DEVICE_ERROR", then this would provide additional information when = needed. + + @param[in] P2sbBase P2SB PCI config base + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + @retval EFI_TIMEOUT Timeout while waiting for response +**/ +EFI_STATUS +P2SbSbiExecutionEx ( + IN UINT64 P2sbBase, + IN P2SB_PID Pid, + IN UINT64 Offset, + IN P2SB_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/= Library/PchSbiAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/= IncludePrivate/Library/PchSbiAccessLib.h new file mode 100644 index 0000000000..a46d8fb649 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr +++ ary/PchSbiAccessLib.h @@ -0,0 +1,58 @@ +/** @file + Header file for PchSbiAccessLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_SBI_ACCESS_LIB_H_ #define _PCH_SBI_ACCESS_LIB_H_ + +#include +#include + +typedef P2SB_SBI_OPCODE PCH_SBI_OPCODE ; + +typedef P2SB_SBI_RESPONSE PCH_SBI_RESPONSE; + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the=20 +PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally=20 +hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to=20 + be checked as it would have been SBI_SUCCESS. If the return value is=20 + "EFI_DEVICE_ERROR", then this would provide additional information when = needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + @retval EFI_TIMEOUT Timeout while waiting for response +**/ +EFI_STATUS +PchSbiExecutionEx ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +#endif // _PCH_SBI_ACCESS_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/= P2SbController.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePr= ivate/P2SbController.h new file mode 100644 index 0000000000..51c67d4624 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2Sb +++ Controller.h @@ -0,0 +1,32 @@ +/** @file + P2SB controller + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_P2SB_CONTROLLER_H_ #define _P2SB_CONTROLLER_H_ + +/** + P2SB structure + Stores information required to access to registers + like base address, S:B:D:F etc. + and definitions specific to P2SB. +**/ +typedef struct { + /** + P2SB controller PCI config space address + in PCI Segment Library representation. + **/ + UINT64 PciCfgBaseAddr; + /** + P2SB controller MMIO base address + **/ + UINT64 Mmio; + /** + HPET MMIO base address + **/ + UINT64 HpetMmio; +} P2SB_CONTROLLER; + +#endif // _P2SB_CONTROLLER_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/= Register/P2sbRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Includ= ePrivate/Register/P2sbRegs.h new file mode 100644 index 0000000000..ffe35411f7 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Regi +++ ster/P2sbRegs.h @@ -0,0 +1,53 @@ +/** @file + Register names for PCH P2SB device + + Conventions: + + - Register definition format: + =20 + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re + gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_P2SB_REGS_H_ #define _P2SB_REGS_H_ + +// +// Definition for SBI +// +#define R_P2SB_CFG_SBIADDR 0xD0 +#define R_P2SB_CFG_SBIDATA 0xD4 +#define R_P2SB_CFG_SBISTAT 0xD8 +#define B_P2SB_CFG_SBISTAT_OPCODE 0xFF00 +#define B_P2SB_CFG_SBISTAT_POSTED BIT7 +#define B_P2SB_CFG_SBISTAT_RESPONSE 0x0006 +#define N_P2SB_CFG_SBISTAT_RESPONSE 1 +#define B_P2SB_CFG_SBISTAT_INITRDY BIT0 +#define R_P2SB_CFG_SBIRID 0xDA +#define R_P2SB_CFG_SBIEXTADDR 0xDC + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeS= mmPchPcrLib/PchPcrLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Li= brary/PeiDxeSmmPchPcrLib/PchPcrLib.c new file mode 100644 index 0000000000..a5b18613bc --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPc +++ hPcrLib/PchPcrLib.c @@ -0,0 +1,266 @@ +/** @file + PCH PCR library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef MDEPKG_NDEBUG +/** + Checks if the offset is valid for a given memory access width. Offset mu= st align to width size. + + @param[in] Offset Offset of a register + @param[in] Size Size of memory access in bytes + + @retval FALSE Offset is not valid for a given memory access + @retval TRUE Offset is valid +**/ +STATIC +BOOLEAN +PchIsPcrOffsetValid ( + IN UINT32 Offset, + IN UINTN Size + ) +{ + if (!IsP2sb20bPcrSupported ()) { + if (((Offset & (Size - 1)) !=3D 0) || (Offset > 0xFFFF)) { + DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x"= , Offset, Size)); + return FALSE; + } else { + return TRUE; + } + } else { + if (((Offset & (Size - 1)) !=3D 0) || (Offset > 0xFFFFF)) { + DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x"= , Offset, Size)); + return FALSE; + } else { + return TRUE; + } + } +} +#endif + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT32 PCR register value. +**/ +UINT32 +PchPcrRead32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ) +{ +#ifndef MDEPKG_NDEBUG + ASSERT (PchIsPcrOffsetValid (Offset, 4)); #endif + return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); } + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT16 PCR register value. +**/ +UINT16 +PchPcrRead16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ) +{ +#ifndef MDEPKG_NDEBUG + ASSERT (PchIsPcrOffsetValid (Offset, 2)); #endif + return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); } + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT8 PCR register value +**/ +UINT8 +PchPcrRead8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ) +{ + return MmioRead8 (PCH_PCR_ADDRESS (Pid, Offset)); } + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter= . + + @retval UINT32 Value written to register +**/ +UINT32 +PchPcrWrite32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 Data + ) +{ +#ifndef MDEPKG_NDEBUG + ASSERT (PchIsPcrOffsetValid (Offset, 4)); #endif + MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data); + + return Data; + +} + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter= . + + @retval UINT16 Value written to register +**/ +UINT16 +PchPcrWrite16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT16 Data + ) +{ +#ifndef MDEPKG_NDEBUG + ASSERT (PchIsPcrOffsetValid (Offset, 2)); #endif + MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data); + + return Data; +} + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter= . + + @retval UINT8 Value written to register +**/ +UINT8 +PchPcrWrite8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT8 Data + ) +{ + + MmioWrite8 (PCH_PCR_ADDRESS (Pid, Offset), Data); + + return Data; +} + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT32 Value written to register + +**/ +UINT32 +PchPcrAndThenOr32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PchPcrWrite32 (Pid, Offset, (PchPcrRead32 (Pid, Offset) &=20 +AndData) | OrData); } + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT16 Value written to register + +**/ +UINT16 +PchPcrAndThenOr16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PchPcrWrite16 (Pid, Offset, (PchPcrRead16 (Pid, Offset) &=20 +AndData) | OrData); } + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT8 Value written to register + +**/ +UINT8 +PchPcrAndThenOr8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PchPcrWrite8 (Pid, Offset, (PchPcrRead8 (Pid, Offset) &=20 +AndData) | OrData); } diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeS= mmPchPcrLib/PeiDxeSmmPchPcrLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBl= ock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf new file mode 100644 index 0000000000..5e1b4914d8 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPc +++ hPcrLib/PeiDxeSmmPchPcrLib.inf @@ -0,0 +1,35 @@ +## @file +# PCH PCR Library. +# +# All function in this library is available for PEI, DXE, and SMM, #=20 +But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchPcrLib +FILE_GUID =3D 117C8D19-445B-46BF-B624-109F63709375 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchPcrLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PchInfoLib +PchSbiAccessLib +PciSegmentLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] +PchPcrLib.c diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/= PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c b/Silicon/I= ntel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandA= ccessLib/PeiDxeSmmP2SbSidebandAccessLib.c new file mode 100644 index 0000000000..52ec8fd9e1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD +++ xeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c @@ -0,0 +1,208 @@ +/** @file + P2SB sideband access lib + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include +#include +#include +#include +#include +#include +#include #include=20 + #include #include=20 + #include + +#define P2SB_PCR_ADDRESS(MmioBase, Pid, Offset) ((UINTN) MmioBase |=20 +(UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16)=20 +((Offset) & 0xFFFF)) + +/** + Full function for executing P2SB SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the=20 +PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally=20 +hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to=20 + be checked as it would have been SBI_SUCCESS. If the return value is=20 + "EFI_DEVICE_ERROR", then this would provide additional information when = needed. + + @param[in] P2sbBase P2SB PCI config base + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + @retval EFI_TIMEOUT Timeout while waiting for response +**/ +EFI_STATUS +P2SbSbiExecutionEx ( + IN UINT64 P2sbBase, + IN P2SB_PID Pid, + IN UINT64 Offset, + IN P2SB_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + INT32 Timeout; + UINT16 SbiStat; + + // + // Check opcode valid + // + switch (Opcode) { + case MemoryRead: + case MemoryWrite: + case PciConfigRead: + case PciConfigWrite: + case PrivateControlRead: + case PrivateControlWrite: + case GpioLockUnlock: + break; + default: + return EFI_INVALID_PARAMETER; + break; + } + + if (PciSegmentRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF) { + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + /// + /// BWG Section 2.2.1 + /// 1. Poll P2SB PCI offset D8h[0] =3D 0b /// Make sure the previous=20 + opeartion is completed. + /// + Timeout =3D 0xFFFFFFF; + while (Timeout > 0) { + SbiStat =3D PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT); + if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) =3D=3D 0) { + break; + } + Timeout--; + } + if (Timeout =3D=3D 0) { + return EFI_TIMEOUT; + } + // + // Initial Response status + // + *Response =3D SBI_INVALID_RESPONSE; + SbiStat =3D 0; + /// + /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination=20 + Port ID /// + PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIADDR, (UINT32) ((Pid <<=20 + 24) | (UINT16) Offset)); /// /// 3. Write P2SB PCI offset DCh[31:0]=20 + with extended address, which is expected to be 0 in CNL PCH. + /// + PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIEXTADDR, (UINT32)=20 + RShiftU64 (Offset, 16)); /// /// 5. Set P2SB PCI offset D8h[15:8] =3D= =20 + 00000110b for read + /// Set P2SB PCI offset D8h[15:8] =3D 00000111b for write + // + // Set SBISTAT[15:8] to the opcode passed in // Set SBISTAT[7] to=20 + the posted passed in // + PciSegmentAndThenOr16 ( + (P2sbBase + R_P2SB_CFG_SBISTAT), + (UINT16) ~(B_P2SB_CFG_SBISTAT_OPCODE | B_P2SB_CFG_SBISTAT_POSTED), + (UINT16) ((Opcode << 8) | (Posted << 7)) + ); + /// + /// 6. Write P2SB PCI offset DAh[15:0] =3D F000h /// // // Set=20 + RID[15:0] =3D Fbe << 12 | Bar << 8 | Fid // + PciSegmentWrite16 ( + (P2sbBase + R_P2SB_CFG_SBIRID), + (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF)) + ); + + switch (Opcode) { + case MemoryWrite: + case PciConfigWrite: + case PrivateControlWrite: + case GpioLockUnlock: + /// + /// 4. Write P2SB PCI offset D4h[31:0] with the intended data accord= ingly + /// + PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), *Data32); + break; + default: + /// + /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0, + /// because all D0-DFh register range must be touched in CNL PCH + /// for a successful SBI transaction. + /// + PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), 0); + break; + } + /// + /// 7. Set P2SB PCI offset D8h[0] =3D 1b, Poll P2SB PCI offset D8h[0] = =3D=20 +0b + /// + // + // Set SBISTAT[0] =3D 1b, trigger the SBI operation + // + PciSegmentOr16 (P2sbBase + R_P2SB_CFG_SBISTAT, (UINT16)=20 +B_P2SB_CFG_SBISTAT_INITRDY); + // + // Poll SBISTAT[0] =3D 0b, Polling for Busy bit + // + Timeout =3D 0xFFFFFFF; + while (Timeout > 0) { + SbiStat =3D PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT); + if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) =3D=3D 0) { + break; + } + Timeout--; + } + if (Timeout =3D=3D 0) { + // + // If timeout, it's fatal error. + // + return EFI_TIMEOUT; + } else { + /// + /// 8. Check if P2SB PCI offset D8h[2:1] =3D 00b for successful transa= ction + /// + *Response =3D (UINT8) ((SbiStat & B_P2SB_CFG_SBISTAT_RESPONSE) >> N_P2= SB_CFG_SBISTAT_RESPONSE); + if (*Response =3D=3D SBI_SUCCESSFUL) { + switch (Opcode) { + case MemoryRead: + case PciConfigRead: + case PrivateControlRead: + /// + /// 9. Read P2SB PCI offset D4h[31:0] for SBI data + /// + *Data32 =3D PciSegmentRead32 (P2sbBase + R_P2SB_CFG_SBIDATA); + break; + default: + break; + } + return EFI_SUCCESS; + } else if (*Response =3D=3D SBI_POWERDOWN) { + return EFI_NO_RESPONSE; + } else { + return EFI_DEVICE_ERROR; + } + } +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/= PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf b/Silicon= /Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSideban= dAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf new file mode 100644 index 0000000000..9530e56940 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD +++ xeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf @@ -0,0 +1,30 @@ +## @file +# Library for accessing sideband register banks via the P2SB router. +# +# All function in this library is available for PEI, DXE, and SMM, #=20 +But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmP2SbSidebandAccessLib FILE_GUID =3D=20 +425C479D-A489-4382-8C28-59A3521A24FF +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D P2SbSidebandAccessLib + +[LibraryClasses] +BaseLib +IoLib +DebugLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + +[Sources] +PeiDxeSmmP2SbSidebandAccessLib.c diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/= PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c b/Silicon/Intel/AlderlakeSilicon= Pkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c new file mode 100644 index 0000000000..1f7bb82692 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD +++ xeSmmPchSbiAccessLib/PchSbiAccessLib.c @@ -0,0 +1,72 @@ +/** @file + PCH SBI access library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include +#include +#include +#include +#include +#include +#include #include=20 + #include #include=20 + + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the=20 +PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally=20 +hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to=20 + be checked as it would have been SBI_SUCCESS. If the return value is=20 + "EFI_DEVICE_ERROR", then this would provide additional information when = needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + @retval EFI_TIMEOUT Timeout while waiting for response +**/ +EFI_STATUS +PchSbiExecutionEx ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + return P2SbSbiExecutionEx ( + P2sbPciCfgBase (), + Pid, + Offset, + Opcode, + Posted, + Fbe, + Bar, + Fid, + Data32, + Response + ); +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/= PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf b/Silicon/Intel/Alder= lakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeS= mmPchSbiAccessLib.inf new file mode 100644 index 0000000000..a28a90c74b --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD +++ xeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf @@ -0,0 +1,35 @@ +## @file +# PCH SBI access library. +# +# All function in this library is available for PEI, DXE, and SMM, #=20 +But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchSbiAccessLib +FILE_GUID =3D 96ECB0FB-A975-4DC8-B88A-D90C3378CE87 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchSbiAccessLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PchPciBdfLib +P2SbSidebandAccessLib + + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] +PchSbiAccessLib.c diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivat= e/Library/PchDmiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/In= cludePrivate/Library/PchDmiLib.h new file mode 100644 index 0000000000..efbb76f6be --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Li +++ brary/PchDmiLib.h @@ -0,0 +1,60 @@ +/** @file + Header file for PchDmiLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_DMI_LIB_H_ #define _PCH_DMI_LIB_H_ + +/** + This function checks if DMI Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmiLocked ( + VOID + ); + +/** + Get PCH TCO base address. + + @retval Address Address of TCO base address. +**/ +UINT16 +PchDmiGetTcoBase ( + VOID + ); + +/** + Set PCH LPC/eSPI IO decode ranges in DMI + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcIoDecodeRanges ( + IN UINT16 LpcIoDecodeRanges + ); + +/** + Set PCH LPC/eSPI IO enable decoding in DMI + + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcIoEnable ( + IN UINT16 LpcIoEnableDecoding + ); +#endif // _PCH_DMI_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PchDmi14.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock= /PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c new file mode 100644 index 0000000000..9f49790372 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe +++ iDxeSmmPchDmiLib/PchDmi14.c @@ -0,0 +1,34 @@ +/** @file + This file contains functions for PCH DMI SIP14 + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include #include =20 +#include #include =20 +#include #include + +/** + This function checks if DMI SIP14 Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmi14Locked ( + VOID + ) +{ + return ((PchPcrRead32 (PID_DMI, R_PCH_DMI14_PCR_DMIC) &=20 +B_PCH_DMI14_PCR_DMIC_SRL) !=3D 0); } diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PchDmi14.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock= /PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h new file mode 100644 index 0000000000..494caebb4a --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe +++ iDxeSmmPchDmiLib/PchDmi14.h @@ -0,0 +1,22 @@ +/** @file + Internal header file for PCH DMI library for SIP14 + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +__PCH_DMI_14_H__ #define __PCH_DMI_14_H__ + +#include + +/** + This function checks if DMI SIP14 Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmi14Locked ( + VOID + ); + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PchDmiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBloc= k/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c new file mode 100644 index 0000000000..3d5436f1a3 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe +++ iDxeSmmPchDmiLib/PchDmiLib.c @@ -0,0 +1,110 @@ +/** @file + PCH DMI library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include =20 +#include #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + + +#include "PchDmi14.h" + +/** + This function checks if DMI Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmiLocked ( + VOID + ) +{ + return IsPchDmi14Locked (); +} + +/** + Get PCH TCO base address. + + @retval Address Address of TCO base address. +**/ +UINT16 +PchDmiGetTcoBase ( + VOID + ) +{ + // + // Read "TCO Base Address" PCR[DMI] + 2778h[15:5] + // + return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) &=20 +B_PCH_DMI_PCR_TCOBASE_TCOBA); } + +/** + Set PCH LPC/eSPI IO decode ranges in DMI + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcIoDecodeRanges ( + IN UINT16 LpcIoDecodeRanges + ) +{ + // + // This cycle decoding is only allowed to set when DMI is not locked. + // + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same val= ue programmed in LPC/eSPI PCI offset 80h. + // + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, LpcIoDecodeRanges); + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI IO enable decoding in DMI + + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcIoEnable ( + IN UINT16 LpcIoEnableDecoding + ) +{ + // + // This cycle decoding is only allowed to set when DMI is not locked. + // + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same val= ue programmed in LPC/eSPI PCI offset 82h. + // + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, LpcIoEnableDecoding); + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf b/Silicon/Intel/AlderlakeSilico= nPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.in= f new file mode 100644 index 0000000000..4e92117be3 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe +++ iDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for the PeiDxeSmmPchDmiLib # +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchDmiLib +FILE_GUID =3D 067DC1C4-2668-4F06-9921-307514B66B34 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchDmiLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + BaseLib + IoLib + DebugLib + PchInfoLib + PchPcrLib + + +[Packages] + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] + PchDmiLib.c + PchDmi14.c + PchDmi14.h + +[Guids] + gPchDmiConfigGuid ## CONSUMES + gPchDmiPreMemConfigGuid ## CONSUMES + +[Pcd] -- 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108652): https://edk2.groups.io/g/devel/message/108652 Mute This Topic: https://groups.io/mt/101347729/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-