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Mon, 8 Apr 2024 20:57:44 +0000 From: "Nate DeSimone" To: "Duggapu, Chinni B" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" Subject: Re: [edk2-devel] [PATCH v6 1/3] IntelFsp2Pkg: Fsp T new ARCH UPD Support Thread-Topic: [PATCH v6 1/3] IntelFsp2Pkg: Fsp T new ARCH UPD Support Thread-Index: AQHah3uRqy/fnn/oF06t81fQKEFRCbFe32Tw Date: Mon, 8 Apr 2024 20:57:43 +0000 Message-ID: References: <20240405170540.2035-1-chinni.b.duggapu@intel.com> <20240405170540.2035-2-chinni.b.duggapu@intel.com> In-Reply-To: <20240405170540.2035-2-chinni.b.duggapu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW4PR11MB5821:EE_|DS0PR11MB6400:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: HKAekP6YnNy6Upt9blNHs+EmHywCknH4e24GCvCh7XLErFnbWdMjulxpRn3aOKfMXF2O8420CQc5c0zj795wyHbgM7+T+YtjqVjipSRF3YYuFfv1jnT1nfMxKPkfz/pe07aGb/2BaW9hl74K5vQPkJ893dbkAGBgd7HBWZ2UQ5Ie4zbPcErwIQRd5eHfGga/EHVSza3prndnDhWWkLB4ISd9ZScIGx6fJUfFIY2ez7KcJukIkisCTqViWgchOA5LdWdVHpnwPCPBgWeXZqHAge+0FuAsWVbq8dhBY37mgtx1Ay2thriq93ZTl9+e6Jhs27uSJr98QgGJBRmx+js1NJKz8gAvAFuWc3kg3kKDE0ILevAnTr3iPZQSSE4k0gGcEodX+abL2BVcyl7BlpCk5T9utqe5UJZlciAEncHXY2HvHknieELV0APiifge5+XHBXcvMhmY/FxQYghoow3znOxPrvI3yp8YqlvXBDNzE4IA7J59OfgXM31xUZQfi2NKECNf/rIoLDHRYq6sdDNYzR3n+ppdsCWao0j989+bIWRSn1c2dMkb/aiOS+UkHJrPhcGgzsKSxmvOJ6xl6EtLqn34hqnk5HdwBrX0K3WM1PWH4D8yhPtGLogQ9e144YzkPqACfbsrDEMxM7ReBvEtOW46oyqi4RAwd+FSes1G2Zw= x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?TySB1AewVsbwrg5LMhy6YBIFIKFqzph/WAIKWsJUDX3JM+3nKUKa3Bd2JkNU?= =?us-ascii?Q?m+0KHLS1Z5yZPijr+g3JPuvP6wnhbFEpBScod1ph7Ml64eOKrKK5biUrXKpy?= =?us-ascii?Q?oss05bToISZ05MHTx/C4W/qVAa3igCzqrffK9DI1YGN6jkKUr3qezAcDdtb8?= =?us-ascii?Q?+Zm4O6hFkVdsnbrB2EM8KuT+ceLZYWGGfOHlt578QHXPy/MOO5TcCjZwNsz/?= =?us-ascii?Q?YcuKhhd/3cgPlaVeEBhdBCF6RAcBEXUpnSBxYLP96M/Uc0ZFOX3sIDOhN1fl?= =?us-ascii?Q?GmMwgWEO2ddaFLdI2jiF+Ea4eQggkoJE4bCLc8KASpaEb7bDpbBVDKUb60gc?= =?us-ascii?Q?xB1KEELWjpJ0YhpOyrExs/Eo2wSQvbh45/VIW13YA6OWfn6+LOWhr/kudeds?= =?us-ascii?Q?CF3WM18iKK7+zSMNbal5xrFYSma9JSiWiBsALyt8yOVKSfvwctd2OFB9Ympw?= =?us-ascii?Q?j9wL+E9Ho0/OIdGeUenPhMrnYyBj7k3m2yK6aIkWdGiJgY2F4RP2jcuDBFYY?= =?us-ascii?Q?ahEOkxdNrVuaPlMMBxssgSYd2ZqrcqiTWXjVTxPSJR6Ov70kBEfzsbvVKRos?= =?us-ascii?Q?5Orgkkk6bxYUkn9rKhsdxh683xkjb5dBbcuSjPTnmGMG4q9iGn1MdSJxLyyf?= =?us-ascii?Q?iOjVuq/6MX9EMKgRrldaBP0nLBTyhQZML5roQEccBgmWy3aHlne/ksmm7XeX?= =?us-ascii?Q?ilfwZ2CbAy4UGNvd8X2z+1rcE8llK+1DA4P45QACMZg0H/K1A8jpVeJWxqcd?= =?us-ascii?Q?MmJNMgu/3zTZp6vdADumAAINjMLIV+rfOyqD17wusQtnEMhTpFRlOxg/ZMUx?= =?us-ascii?Q?+Oo4e1BJ9pZYO5nQKs9b9hrY8e5z83I1RTKmFJLpL17eQ9J0uouwmrBaV9U4?= =?us-ascii?Q?xENIjHJ0UUgHRGTf8HaRWFePjVYgcOOLu8DoiftZ1dUowhpwKyY569MvVNhN?= =?us-ascii?Q?7u+A0YuhRmqvGvS1bk/0/gXeD6byx0Q2uio1MxJst93At62o1Ir/8+o1Kn8h?= =?us-ascii?Q?Pu/pMNSTmkNk5V7TFux000pijm/nmlyq5u3rvDSVPkmmO25MpMAoRJXBHEfy?= =?us-ascii?Q?4VKB3h9N7oJV7iEyo1WNAwdCThqVcLzixJMjn7QTolANE+8vFMGg+hYJNbdn?= =?us-ascii?Q?i0XlZGl8aA5jNWM5bRh0GIEp7DLS2h0G3ZTZzfE461w2ukxoQSLWQvcs6O/E?= =?us-ascii?Q?Sri9LPSAzwq0BxX+att7dYY9onlxVlAM8etfR5ohcYuaoK9IwNRbpvlPwPh8?= =?us-ascii?Q?qkaalNDKzj63WmoT/kVjG9HvPZOcDyGyRHU7k1OROUk/+0CI7eTnU8wO8sUS?= =?us-ascii?Q?h9A7Z1aryeiPgoMhUIVSFqnocKZ4F4g+Zfl0JvnJka8mAOKfmH38QmhaNOXo?= =?us-ascii?Q?AOAAZrsmXUCRgOEYVH6XFvMyl6QrX2SdMpWFTOhLv+R67Tl0ItRt0hb4MvFk?= =?us-ascii?Q?7JIP5YZy0cvZMS+rQN6r5hHSmUr2EcFSPnNdN5AzOmidxiHbvqWqJ6USPnsH?= =?us-ascii?Q?Jq4/hV3Alx0gKv50HmUtEqGloUja9w6PDWh03PF7u7eBJKTdYWY7NPdZ4WLE?= =?us-ascii?Q?ZdaEqm6D5UckkR3W83nRY7HKClNsXa7jTtmwN6xoVdeoKg21Z0BPseOAWhbM?= =?us-ascii?Q?Ng=3D=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW4PR11MB5821.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d6479d58-9571-4146-f7f9-08dc580e898f X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Apr 2024 20:57:44.0091 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /BrIBcI2gTSPsE9ke3sUGEnHmRlW4mUCZ+b+e3OY0mcNWZFZBfT+QNxuAAfL2vRiLZAg547+wXtVQj9XkbrhWLVMsvO2pjd/Gj7dg8VWY04= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB6400 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Mon, 08 Apr 2024 13:57:47 -0700 Resent-From: nathaniel.l.desimone@intel.com Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 8Nsvex7wjg9Xgl7pH93KB8UYx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=IM8kyYdK; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Chinni, One minor feedback below. With that change... Reviewed-by: Nate DeSimone > -----Original Message----- > From: Duggapu, Chinni B > Sent: Friday, April 5, 2024 10:06 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L ; Chiu, Chasel > ; Duggapu, Chinni B > Subject: [PATCH v6 1/3] IntelFsp2Pkg: Fsp T new ARCH UPD Support >=20 > Changes to support spec changes >=20 > 1. Remove usage of Pcd. > 2. Change code to validate the Temporary Ram size input. > 3. Consume the input saved in YMM Register >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Cc: Chiu Chasel > Cc: Duggapu Chinni B >=20 >=20 > Signed-off-by: Duggapu Chinni B > --- > IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 1 + > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 + > .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 1 - > .../FspSecCore/Ia32/FspApiEntryM.nasm | 1 - > .../FspSecCore/Ia32/FspApiEntryT.nasm | 60 +++++++++++++--- > .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 11 +++ > IntelFsp2Pkg/FspSecCore/SecFsp.c | 9 +++ > IntelFsp2Pkg/FspSecCore/SecFsp.h | 1 + > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 68 +++++++++++++++---- > IntelFsp2Pkg/Include/FspEas/FspApi.h | 12 +++- > IntelFsp2Pkg/Include/Library/FspPlatformLib.h | 13 ++++ > .../Include/SaveRestoreSseAvxNasm.inc | 21 ++++++ > .../BaseFspPlatformLib/FspPlatformMemory.c | 38 +++++++++++ > 13 files changed, 211 insertions(+), 26 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf b/IntelFsp2Pkg/Fsp= SecCore/Fsp24SecCoreM.inf > index cb011f99f9..8cb0e6411f 100644 > --- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf > @@ -60,6 +60,7 @@ > FspSecPlatformLib > CpuLib > FspMultiPhaseLib > + FspPlatformLib > =20 > [Pcd] > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUM= ES > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSe= cCore/FspSecCoreM.inf > index 8029832235..ef19c6ae78 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > @@ -59,6 +59,7 @@ > FspCommonLib > FspSecPlatformLib > CpuLib > + FspPlatformLib > =20 > [Pcd] > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUM= ES > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2= Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm > index 15f8ecea83..5fa5c03569 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm > @@ -11,7 +11,6 @@ > ; Following are fixed PCDs > ; > extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) > -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) > extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) > extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) > =20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/FspApiEntryM.nasm > index 61ab4612a3..861cce4d01 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > @@ -11,7 +11,6 @@ > ; Following are fixed PCDs > ; > extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) > -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) > extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) > extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) > =20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/FspApiEntryT.nasm > index 900126b93b..088bd7ee7f 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > @@ -109,7 +109,8 @@ struc LoadMicrocodeParamsFsp24 > .FsptArchReserved: resb 3 > .FsptArchLength: resd 1 > .FspDebugHandler resq 1 > - .FsptArchUpd: resd 4 > + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison= is >=3D 3 > + .FsptArchUpd: resd 3 > ; } > ; FSPT_CORE_UPD { > .MicrocodeCodeAddr: resq 1 > @@ -267,7 +268,7 @@ ASM_PFX(LoadMicrocodeDefault): > cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 > jb Fsp20UpdHeader > cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 > - je Fsp24UpdHeader > + jae Fsp24UpdHeader > jmp Fsp22UpdHeader > =20 > Fsp20UpdHeader: > @@ -405,7 +406,7 @@ CheckAddress: > cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 > jb Fsp20UpdHeader1 > cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 > - je Fsp24UpdHeader1; > + jae Fsp24UpdHeader1; > jmp Fsp22UpdHeader1 > =20 > Fsp20UpdHeader1: > @@ -497,7 +498,8 @@ ASM_PFX(EstablishStackFsp): > ; Enable FSP STACK > ; > mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] > - add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))] > + LOAD_TEMPORARY_RAM_SIZE ecx > + add esp, ecx > =20 > push DATA_LEN_OF_MCUD ; Size of the data region > push 4455434Dh ; Signature of the data region 'MCUD' > @@ -506,7 +508,7 @@ ASM_PFX(EstablishStackFsp): > cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], = 2 > jb Fsp20UpdHeader2 > cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 > - je Fsp24UpdHeader2 > + jae Fsp24UpdHeader2 > jmp Fsp22UpdHeader2 > =20 > Fsp20UpdHeader2: > @@ -554,12 +556,13 @@ ContinueAfterUpdPush: > ; > ; Set ECX/EDX to the BootLoader temporary memory range > ; > - mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] > - mov edx, ecx > - add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))] > + mov edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] > + LOAD_TEMPORARY_RAM_SIZE ecx > + add edx, ecx > sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))] > + mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] > =20 > - cmp ecx, edx ;If PcdFspReservedBufferSize >=3D PcdTempora= ryRamSize, then error. > + cmp ecx, edx ;If PcdFspReservedBufferSize >=3D TemporaryR= amSize, then error. > jb EstablishStackFspSuccess > mov eax, 80000003h ;EFI_UNSUPPORTED > jmp EstablishStackFspExit > @@ -599,6 +602,45 @@ ASM_PFX(TempRamInitApi): > CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param > SAVE_ECX ; save UPD param to slot 3 in x= mm6 > =20 > + mov edx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > + mov edx, DWORD [edx] > + ; > + ; Read Fsp Arch2 revision > + ; > + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3 > + jb UseTemporaryRamSizePcd > + ; > + ; Read ARCH2 UPD input value. > + ; > + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSi= ze] > + ; > + ; As per spec, if Bootloader pass zero, use Fsp defined Size > + ; > + cmp ebx, 0 > + jz UseTemporaryRamSizePcd > + > + xor eax, eax > + mov ax, WORD [esi + 020h] ; Read ImageAttribute > + test ax, 16 ; check if Bit4 is set > + jnz ConsumeInputConfiguration > + ; > + ; Sometimes user may change input value even if it is not supported > + ; return error if input is Non-Zero and not same as PcdTemporaryRamSiz= e. > + ; > + cmp ebx, edx > + je UseTemporaryRamSizePcd > + mov eax, 080000002h ; RETURN_INVALID_PARAMETER > + jmp TempRamInitExit > +ConsumeInputConfiguration: > + ; > + ; Read ARCH2 UPD value and Save. > + ; > + SAVE_TEMPORARY_RAM_SIZE ebx > + jmp GotTemporaryRamSize > +UseTemporaryRamSizePcd: > + SAVE_TEMPORARY_RAM_SIZE edx > +GotTemporaryRamSize: > + LOAD_ECX > ; > ; Sec Platform Init > ; > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelF= sp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > index 016f943b43..4d6ec1e984 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > @@ -128,6 +128,17 @@ > SXMMN xmm5, 1, eax > %endmacro > =20 > +; > +; XMM5 slot 2 for TemporaryRamSize > +; > +%macro LOAD_TEMPORARY_RAM_SIZE 1 > + LXMMN xmm5, %1, 2 > + %endmacro > + > +%macro SAVE_TEMPORARY_RAM_SIZE 1 > + SXMMN xmm5, 2, %1 > + %endmacro > + > %macro ENABLE_SSE 0 > ; > ; Initialize floating point units > diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/S= ecFsp.c > index 11be1f97ca..281d39a24b 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c > @@ -54,6 +54,7 @@ SecGetPlatformData ( > UINT32 TopOfCar; > UINT32 *StackPtr; > UINT32 DwordSize; > + UINT32 TemporaryRamSize; > =20 > FspPlatformData =3D &FspData->PlatformData; > =20 > @@ -67,12 +68,20 @@ SecGetPlatformData ( > FspPlatformData->MicrocodeRegionSize =3D 0; > FspPlatformData->CodeRegionBase =3D 0; > FspPlatformData->CodeRegionSize =3D 0; > + TemporaryRamSize =3D 0; > =20 > // > // Pointer to the size field > // > TopOfCar =3D PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRa= mSize); > StackPtr =3D (UINT32 *)(TopOfCar - sizeof (UINT32)); > + if ((*(StackPtr - 1) !=3D FSP_MCUD_SIGNATURE) && (FspData->FspInfoHead= er->ImageAttribute & BIT4)) { > + ReadTemporaryRamSize (PcdGet32 (PcdTemporaryRamBase), &TemporaryRamS= ize); > + if (TemporaryRamSize) { > + TopOfCar =3D PcdGet32 (PcdTemporaryRamBase) + TemporaryRamSize; > + StackPtr =3D (UINT32 *)(TopOfCar - sizeof (UINT32)); > + } > + } > =20 > if (*(StackPtr - 1) =3D=3D FSP_MCUD_SIGNATURE) { > while (*StackPtr !=3D 0) { > diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/S= ecFsp.h > index 693af29f20..c05b46c750 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFsp.h > +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h > @@ -17,6 +17,7 @@ > #include > #include > #include > +#include > =20 > #define FSP_MCUD_SIGNATURE SIGNATURE_32 ('M', 'C', 'U', 'D') > #define FSP_PER0_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', '0') > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg= /FspSecCore/X64/FspApiEntryT.nasm > index 698bb063a7..0402d1e893 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > @@ -16,6 +16,7 @@ > extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) > extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) > +extern ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress)) This extern is no longer used in your most recent patch series and can be r= emoved. > =20 > ; > ; Following functions will be provided in PlatformSecLib > @@ -76,7 +77,8 @@ struc LoadMicrocodeParamsFsp24 > .FsptArchReserved: resb 3 > .FsptArchLength: resd 1 > .FspDebugHandler resq 1 > - .FsptArchUpd: resd 4 > + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison = is >=3D 3 > + .FsptArchUpd: resd 3 > ; } > ; FSPT_CORE_UPD { > .MicrocodeCodeAddr: resq 1 > @@ -163,7 +165,7 @@ ASM_PFX(LoadMicrocodeDefault): > cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2 > jb ParamError > cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2 > - jne ParamError > + jb ParamError > =20 > ; UPD structure is compliant with FSP spec 2.4 > mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] > @@ -273,7 +275,7 @@ CheckAddress: > cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2 > jb ParamError > cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2 > - jne ParamError > + jb ParamError > =20 > ; UPD structure is compliant with FSP spec 2.4 > ; Is automatic size detection ? > @@ -337,8 +339,8 @@ ASM_PFX(EstablishStackFsp): > ; > mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) > mov esp, DWORD[rax] > - mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > - add esp, DWORD[rax] > + LOAD_TEMPORARY_RAM_SIZE rax > + add esp, eax > =20 > sub esp, 4 > mov dword[esp], DATA_LEN_OF_MCUD ; Size of the data region > @@ -349,7 +351,7 @@ ASM_PFX(EstablishStackFsp): > cmp byte [rdx + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], = 2 > jb ParamError1 > cmp byte [rdx + LoadMicrocodeParamsFsp24.FsptArchRevision], 2 > - je Fsp24UpdHeader > + jnb Fsp24UpdHeader > =20 > ParamError1: > mov rax, 08000000000000002h > @@ -397,8 +399,8 @@ ContinueAfterUpdPush: > ; > mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) > mov edx, [ecx] > - mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > - add edx, [ecx] > + LOAD_TEMPORARY_RAM_SIZE rcx > + add edx, ecx > mov rcx, ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) > sub edx, [ecx] > mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) > @@ -439,6 +441,14 @@ ASM_PFX(TempRamInitApi): > ; > SAVE_BFV rbp > =20 > + ; > + ; Save timestamp into YMM6 > + ; > + rdtsc > + shl rdx, 32 > + or rax, rdx > + SAVE_TS rax > + > ; > ; Save Input Parameter in YMM10 > ; > @@ -455,14 +465,46 @@ ASM_PFX(TempRamInitApi): > ParamValid: > SAVE_RCX > =20 > + mov rdx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > + mov edx, DWORD [rdx] > ; > - ; Save timestamp into YMM6 > + ; Read Fsp Arch2 revision > ; > - rdtsc > - shl rdx, 32 > - or rax, rdx > - SAVE_TS rax > + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3 > + jb UseTemporaryRamSizePcd > + ; > + ; Read ARCH2 UPD input value. > + ; > + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSi= ze] > + ; > + ; As per spec, if Bootloader pass zero, use Fsp defined Size > + ; > + cmp ebx, 0 > + jz UseTemporaryRamSizePcd > + > + xor rax, rax > + mov ax, WORD [rsi + 020h] ; Read ImageAttribute > + test ax, 16 ; check if Bit4 is set > + jnz ConsumeInputConfiguration > + ; > + ; Sometimes user may change input value even if it is not supported > + ; return error if input is Non-Zero and not same as PcdTemporaryRamSiz= e. > + ; > + cmp ebx, edx > + je UseTemporaryRamSizePcd > + mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER > + jmp TempRamInitExit > +ConsumeInputConfiguration: > + ; > + ; Read ARCH2 UPD value and Save. > + ; Only low-32 bits of rbx/rdx holds the temporary ram size. > + ; > + SAVE_TEMPORARY_RAM_SIZE rbx > + jmp GotTemporaryRamSize > +UseTemporaryRamSizePcd: > + SAVE_TEMPORARY_RAM_SIZE rdx > =20 > +GotTemporaryRamSize: > ; > ; Sec Platform Init > ; > diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/= FspEas/FspApi.h > index 40e063e944..e07aa401e6 100644 > --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h > +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h > @@ -139,7 +139,7 @@ typedef struct { > /// > typedef struct { > /// > - /// Revision of the structure is 2 for this version of the specificati= on. > + /// Revision of the structure is 3 for this version of the specificati= on. > /// > UINT8 Revision; > UINT8 Reserved[3]; > @@ -152,7 +152,15 @@ typedef struct { > /// occurring during FSP execution. > /// > EFI_PHYSICAL_ADDRESS FspDebugHandler; > - UINT8 Reserved1[16]; > + /// > + /// FspTemporaryRamSize is Optional & valid only when > + /// FSP image attribute (BIT4) is set. If Programmed as Zero, Platform > + /// recommended value will be used, otherwise input value will be used > + /// to configure TemporaryRamSize. Refer FSP Integration guide for val= id > + /// TemporaryRamSize range for each platform. > + /// > + UINT32 FspTemporaryRamSize; > + UINT8 Reserved1[12]; > } FSPT_ARCH2_UPD; > =20 > /// > diff --git a/IntelFsp2Pkg/Include/Library/FspPlatformLib.h b/IntelFsp2Pkg= /Include/Library/FspPlatformLib.h > index 081add6529..03eca5e1fc 100644 > --- a/IntelFsp2Pkg/Include/Library/FspPlatformLib.h > +++ b/IntelFsp2Pkg/Include/Library/FspPlatformLib.h > @@ -121,4 +121,17 @@ FspTempRamExitDone2 ( > IN EFI_STATUS Status > ); > =20 > +/** > + Calculate TemporaryRam Size using Base address > + > + @param[in] TemporaryRamBase the address of target memory > + @param[out] TemporaryRamSize the size of target memory > +**/ > +VOID > +EFIAPI > +ReadTemporaryRamSize ( > + IN UINT32 TemporaryRamBase, > + OUT UINT32 *TemporaryRamSize > + ); > + > #endif > diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pk= g/Include/SaveRestoreSseAvxNasm.inc > index 002a5a1412..2168564e6d 100644 > --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > @@ -201,6 +201,27 @@ > movq rcx, xmm5 > %endmacro > =20 > +; > +; Save TemporaryRamSize to YMM10[192:255] > +; arg 1:general purpose register which holds TemporaryRamSize > +; Modified: XMM5 and YMM10[192:255] > +; > +%macro SAVE_TEMPORARY_RAM_SIZE 1 > + LYMMN ymm10, xmm5, 1 > + SXMMN xmm5, 1, %1 > + SYMMN ymm10, 1, xmm5 > + %endmacro > + > +; > +; Restore TemporaryRamSize from YMM10[192:255] > +; arg 1:general purpose register where to save TemporaryRamSize > +; Modified: XMM5 and %1 > +; > +%macro LOAD_TEMPORARY_RAM_SIZE 1 > + LYMMN ymm10, xmm5, 1 > + LXMMN xmm5, %1, 1 > + %endmacro > + > ; > ; YMM7[128:191] for calling stack > ; arg 1:Entry > diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c = b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c > index 2573e4e421..4c5c1f824e 100644 > --- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c > +++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c > @@ -6,6 +6,7 @@ > **/ > =20 > #include > +#include > #include > #include > #include > @@ -119,3 +120,40 @@ FspGetSystemMemorySize ( > Hob.Raw =3D GET_NEXT_HOB (Hob); > } > } > + > +/** > + Calculate TemporaryRam Size using Base address > + > + @param[in] TemporaryRamBase the address of target memory > + @param[out] TemporaryRamSize the size of target memory > +**/ > +VOID > +EFIAPI > +ReadTemporaryRamSize ( > + IN UINT32 TemporaryRamBase, > + OUT UINT32 *TemporaryRamSize > + ) > +{ > + MSR_IA32_MTRRCAP_REGISTER Msr; > + UINT32 MsrNum; > + UINT32 MsrNumEnd; > + > + if (TemporaryRamBase =3D=3D 0) { > + return ; > + } > + > + *TemporaryRamSize =3D 0; > + Msr.Uint64 =3D AsmReadMsr64(MSR_IA32_MTRRCAP); > + MsrNumEnd =3D MSR_IA32_MTRR_PHYSBASE0 + (2 * (Msr.Bits.VCNT)); > + > + for (MsrNum =3D MSR_IA32_MTRR_PHYSBASE0; MsrNum < MsrNumEnd; MsrNum += =3D 2) { > + if ((AsmReadMsr64 (MsrNum+1) & BIT11) !=3D 0 ) { > + if (TemporaryRamBase =3D=3D (AsmReadMsr64 (MsrNum) & 0xFFFFF000)) = { > + *TemporaryRamSize =3D (~(AsmReadMsr64 (MsrNum+1) & 0xFFFFF000) += 1); > + break; > + } > + } > + } > + return; > +} > + > --=20 > 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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