From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 60B427803CE for ; Mon, 11 Mar 2024 20:49:14 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=zP6mAtC6zsRvVH8LH0lf8Z96E1ROBmERul32G2MaIko=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20240206; t=1710190153; v=1; b=X9WD7Ut0m08Cil9GKIFrCxWSKpzBkzhYSmSYmK6NyEnD9WxtIqTopCaASvWFYEpFE/YYFxSr +lyW7RXrVSySKnOCe4s4DYTUmBVo0Qk0gcHVgO6Il7ddUIyTDqunCGnkmcX0lNE/bhZHhAOtd1C mHquWa5PlKtlmYZ7wqMbaa2mK/bzFJ9j0LnMcl5V2OsaxjGXBziRWv32Oa8cndfZSy5jaaI7jUz 7sqGv5AZ5ZPh+bUfcKbkhh58r4kL/zVCv3SWKuBdNrPRa+uJD/MBCvWHbltICYbkCFrhYv7xGWx 98dE5tW6fhxE+1WorqiACJSbqO3mw6m7+R5fa2H380Fuw== X-Received: by 127.0.0.2 with SMTP id pz3gYY7687511xiP7FR0kway; Mon, 11 Mar 2024 13:49:13 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mx.groups.io with SMTP id smtpd.web10.4410.1710190152487419316 for ; Mon, 11 Mar 2024 13:49:12 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,11010"; a="4729999" X-IronPort-AV: E=Sophos;i="6.07,117,1708416000"; d="scan'208";a="4729999" X-Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Mar 2024 13:49:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,117,1708416000"; d="scan'208";a="11202745" X-Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmviesa009.fm.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 11 Mar 2024 13:49:11 -0700 X-Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 11 Mar 2024 13:49:10 -0700 X-Received: from FMSEDG603.ED.cps.intel.com (10.1.192.133) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Mon, 11 Mar 2024 13:49:10 -0700 X-Received: from NAM12-BN8-obe.outbound.protection.outlook.com (104.47.55.168) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Mon, 11 Mar 2024 13:49:10 -0700 X-Received: from MW4PR11MB5821.namprd11.prod.outlook.com (2603:10b6:303:184::5) by SA3PR11MB7609.namprd11.prod.outlook.com (2603:10b6:806:319::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7386.16; Mon, 11 Mar 2024 20:49:07 +0000 X-Received: from MW4PR11MB5821.namprd11.prod.outlook.com ([fe80::2769:a1e8:3236:e5a1]) by MW4PR11MB5821.namprd11.prod.outlook.com ([fe80::2769:a1e8:3236:e5a1%4]) with mapi id 15.20.7386.016; Mon, 11 Mar 2024 20:49:07 +0000 From: "Nate DeSimone" To: "Duggapu, Chinni B" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" Subject: Re: [edk2-devel] [PATCH v4] IntelFsp2Pkg: Fsp 2.x Changes Thread-Topic: [PATCH v4] IntelFsp2Pkg: Fsp 2.x Changes Thread-Index: AQHaaiBqqRLMrqQlGU+R7v20iyLxrLEzFiSg Date: Mon, 11 Mar 2024 20:49:07 +0000 Message-ID: References: <602812ed6f70bd983c30924dc6a3619e7a3bb1b5.1709108958.git.chinni.b.duggapu@intel.com> In-Reply-To: <602812ed6f70bd983c30924dc6a3619e7a3bb1b5.1709108958.git.chinni.b.duggapu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW4PR11MB5821:EE_|SA3PR11MB7609:EE_ x-ms-office365-filtering-correlation-id: 80dab517-33a6-45a7-c650-08dc420cb21b x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: 4fje02d0frQu62C+m9PiSGXUnXG74mC6HjyGctkBlj+h9NReWpe+6fi3OkihceuSQGRVHJTaoEzelubXeMZ/MwdwBr/20K1ADGgrWWiKA2xwSU4JZ7Hbh6Blv3MUCbh6oJZWMixQf+vkN+CttzjfaA8NcoAzAImF0WrFaWvQbMEP1799pF3eqogTC1ZAIxoIKhFH9bHSYs4TnFny9UWnxG9HLZqOFuFL7AAiXcGCJMwp2M6yWLEzhi5ppHvEHR7rOcltIH2uivfCiUZbkao5s/bqIdW6Fmcgtby9rea1MiHBECaJTwy/MtdeprOZloifnfMXjbm5CVEACBc119QbJhLn0eMHR+IFBhoSnuBm5/tqwTCbeARgOd/+nHFuJ9xQeoDYBJXVV4uaqjD4npey0ezS15JPtD1wSYdPdwO0AV/J3rVUL87As6BhgbXca3JBUlUfSlWHzI2V6u5ijJUeqa70Qe/IaRsi9/nIq5UbIpIy0uSFS3qwsFDCAbKPiZzVu5w3lziZYtQSATGZ8u60WrbwB/7y3tM7BWaqB1Xq2ip+MDudHa9bLJarmK8rMLYn3iTKrzxiR1/16vNs6poHB+IaIf6QrfUdB//369CPp4EhhOm0ynEdeM2JfQpogMhae13WtlLAKnbH6JM2aoKgxD5gruL0k7lRhmAvOzWMzsm3dDHD1uuFkiA+VQbihrdMu5U1MowoPHZ9TtNwta/LG37DUaOldiN9xfCi+YW7duA= x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?pPp5/17FZaor1OAUpBTlIOwBE+VMVJP+5B+QmThcvBxfRbiY2Rrw1u3XnWmj?= =?us-ascii?Q?LbWJPRshrEi2tsMH7ihzOi0sEDxVN0UGdlWLRBPqSdydvsDIfBU0claUxZ0D?= =?us-ascii?Q?Ea4VzcMJrN+hXbOPmXzCUEA/TDKTxOytX0HyQliGtN3maghwAsLYOsRDLC/j?= =?us-ascii?Q?y0xzQdM14Gqby12lAcfAb+l7x413x0+Czoe2mpG/v0BRwLkMwovpFXCOLYOO?= =?us-ascii?Q?V8644KXPZkpMCtpdiofujwradMv3t0Kr2/iXao2WJo6QMFZh8KcAwPHsF6oD?= =?us-ascii?Q?4fZZu7mHPCXr/NKf0UDmZzjC0UCSvftYCe5P12m1LOYvBNABTBqIykH5Xmf+?= =?us-ascii?Q?TrTVV1xZ5fykhBbGpP04fZbKrEqoj4xznQlzInrB425zI1krC3EGsbfaXcwz?= =?us-ascii?Q?jIb1cx8tah2lv4Qs+WoYXAXe65FE2Ds66RBv5IXDo/HYhjIoV8RMVj2Y3ZPf?= =?us-ascii?Q?mrP+kGrCxbyM4uXfi94i7ZnJgwiw0mYORFFX8ISx3YMlzoKsKpd4jU1lTZFw?= =?us-ascii?Q?PC2l7wTdiCpcD/EppCjX+tRlc8Ua5CE8z2XFo7trhiwNWeWo7QkXu4bUXpxW?= =?us-ascii?Q?y2JVzPrc4/LquSBI1Er9nez7WebUAx76xO6sepFFO9K91b21vRcwG+lP9Fr5?= =?us-ascii?Q?e3eKX4X+vaZUShtFz57SC8cnM1/DVYyFMp3svlhJAnixYU/3x/Rv7pmNqo2L?= =?us-ascii?Q?nZwQ2CLhFE0/9ha9z3HlL6K44x7iDVECg1Juqi5CyV4CoMrnadqvjViDlOdS?= =?us-ascii?Q?tmMB9h131A4wAaYoNeNF2EilAQ2orf5YR0nsXI9wZ5EC0JqV54sd//LWx8Jb?= =?us-ascii?Q?GM4fdOHqfZuyC9qK0WazHHupSXkyfumSTrQNX0l7OQ96PTPgbW99+XOxC93B?= =?us-ascii?Q?IhtoWwTeJpTHOgrXhpORFdVp3us90tob3IP+FdsMSILPDhNYxKJekz5R6Jgw?= =?us-ascii?Q?ZHAv3B46EGhJ0xZAsXIJqQpNTkZglAFmirVrjskhkvq4uJYWg1/uQoOmHNej?= =?us-ascii?Q?S1sJcWZ8TG3O8duWXWmGyj2ZQKYJW52LSNJgeZPrUgEasAauDXSl738FEmvZ?= =?us-ascii?Q?J0SjgH/QvIx4Qt3LE8RmeuNIjzLqvHAcXUfPd+x96gvtRpgoMaofRheWW1oU?= =?us-ascii?Q?Fdf6GupueTVIujHRfIXdqKlp6PB/v11Y5C7rio2+SswpubvnuE7fHBfAa9NI?= =?us-ascii?Q?1e+EkwR4ezcT9RFfqLQsnGAjNRZxaOAKmCKvZc6YoSe7jZ+QrfXO44pW/FJN?= =?us-ascii?Q?sjXNyzCbIzOf+9wXPcYY6sXjPbYZslGVbAST2njjRasjWeos/HmWopkI9IF4?= =?us-ascii?Q?G/J/KMJQ3GaKHBKEJCDwo+xTemmMODW5GbViOHRu5rouGC6hoKXx2mrVl5hw?= =?us-ascii?Q?EoJRL6S5gEym29FaDF0UaeQUe5qxSNwZbPIa+Lh18iFNbThB9nQfrIu/2epo?= =?us-ascii?Q?bUv4o/j4cDDtLsQ17T6YiEfg6nHKtzRegBRvk2PCyZa2Y7DnYJoli8Q1N/FZ?= =?us-ascii?Q?DAqkrpfGCnH6iRTsFPDOqV57+HXWyIiX0YNqBLWtJqD0cXAYGWAU+Q9Z3+PT?= =?us-ascii?Q?yPVVYqamr1gtgTIHB8CmZ+mhAfIYY0kv8FWlADllSrOX9rxvR3I04yu3Bf4f?= =?us-ascii?Q?QA=3D=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW4PR11MB5821.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 80dab517-33a6-45a7-c650-08dc420cb21b X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2024 20:49:07.4770 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wjL+TrOIu4KERuB804U/XnKV5Il8KN3gnZAicLeGCXAnP0MX78ysQFspITTDPaOndozsN8GAD9dTjsRokaPaMQkZRaVimz0Cw8bF3D/EK9Q= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR11MB7609 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Mon, 11 Mar 2024 13:49:12 -0700 Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: jya56d4IJW3glcV0brD3cKYTx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=X9WD7Ut0; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Chinni, Switching from TopOfCar to SizeOfFspMemory doesn't address my previous feed= back. Please also give this patch a better title. Adding new FSP-T Arch UPD= s or something like that. Look forward to a V5 patch. Thanks, Nate -----Original Message----- From: Duggapu, Chinni B =20 Sent: Wednesday, February 28, 2024 12:30 AM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Desimone, Nathani= el L ; Chiu, Chasel = ; Duggapu, Chinni B Subject: [PATCH v4] IntelFsp2Pkg: Fsp 2.x Changes Changes to support spec changes 1. Remove usage of Pcd. 2. Change code to validate the Temporary Ram size input. 3. Consume the input saved in YMM Register Cc: Sai Chaganty Cc: Nate DeSimone Cc: Chiu Chasel Cc: Duggapu Chinni B Signed-off-by: Duggapu Chinni B --- IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 2 +- IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 2 +- IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 1 + .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 1 - .../FspSecCore/Ia32/FspApiEntryM.nasm | 1 - .../FspSecCore/Ia32/FspApiEntryT.nasm | 70 ++++++++++++++--- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 11 +++ IntelFsp2Pkg/FspSecCore/SecFsp.c | 17 +++- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 4 +- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 78 +++++++++++++++---- IntelFsp2Pkg/Include/FspEas/FspApi.h | 5 +- .../Include/SaveRestoreSseAvxNasm.inc | 21 +++++ IntelFsp2Pkg/IntelFsp2Pkg.dec | 5 ++ .../SecRamInitData.c | 3 +- 14 files changed, 185 insertions(+), 36 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf b/IntelFsp2Pkg/FspSe= cCore/Fsp24SecCoreM.inf index cb011f99f9..cf8cb2eda9 100644 --- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf @@ -63,11 +63,11 @@ =20 [Pcd] gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES =20 [Ppis] gEfiTemporaryRamSupportPpiGuid ## PRODUCES diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreM.inf index 8029832235..717941c33f 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -62,11 +62,11 @@ =20 [Pcd] gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES =20 [Ppis] gEfiTemporaryRamSupportPpiGuid ## PRODUCES diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreT.inf index e5a6eaa164..05c0d5f48b 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf @@ -51,6 +51,7 @@ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES =20 [Ppis] gEfiTemporaryRamSupportPpiGuid ## PRODUCES diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/Fsp24ApiEntryM.nasm index 15f8ecea83..5fa5c03569 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm @@ -11,7 +11,6 @@ ; Following are fixed PCDs ; extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) =20 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryM.nasm index 61ab4612a3..861cce4d01 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -11,7 +11,6 @@ ; Following are fixed PCDs ; extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) =20 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 900126b93b..020599ba89 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -16,6 +16,7 @@ extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) +extern ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress)) =20 ; ; Following functions will be provided in PlatformSecLib @@ -109,7 +110,8 @@ struc LoadMicrocodeParamsFsp24 .FsptArchReserved: resb 3 .FsptArchLength: resd 1 .FspDebugHandler resq 1 - .FsptArchUpd: resd 4 + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison i= s >=3D 3 + .FsptArchUpd: resd 3 ; } ; FSPT_CORE_UPD { .MicrocodeCodeAddr: resq 1 @@ -267,7 +269,7 @@ ASM_PFX(LoadMicrocodeDefault): cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 jb Fsp20UpdHeader cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 - je Fsp24UpdHeader + jae Fsp24UpdHeader jmp Fsp22UpdHeader =20 Fsp20UpdHeader: @@ -405,7 +407,7 @@ CheckAddress: cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 jb Fsp20UpdHeader1 cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 - je Fsp24UpdHeader1; + jae Fsp24UpdHeader1; jmp Fsp22UpdHeader1 =20 Fsp20UpdHeader1: @@ -497,7 +499,15 @@ ASM_PFX(EstablishStackFsp): ; Enable FSP STACK ; mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] - add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))] + LOAD_TEMPORARY_RAM_SIZE ecx + add esp, ecx + ; + ; Save TemporaryRam size in PcdGlobalDataPointerAddress + ; which will be used in FSP-M if required. + ; + mov rax, ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress)) + mov eax, DWORD[rax] + mov DWORD[eax], ecx =20 push DATA_LEN_OF_MCUD ; Size of the data region push 4455434Dh ; Signature of the data region 'MCUD' @@ -506,7 +516,7 @@ ASM_PFX(EstablishStackFsp): cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 jb Fsp20UpdHeader2 cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 - je Fsp24UpdHeader2 + jae Fsp24UpdHeader2 jmp Fsp22UpdHeader2 =20 Fsp20UpdHeader2: @@ -554,12 +564,13 @@ ContinueAfterUpdPush: ; ; Set ECX/EDX to the BootLoader temporary memory range ; - mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] - mov edx, ecx - add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))] + mov edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] + LOAD_TEMPORARY_RAM_SIZE ecx + add edx, ecx sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))] + mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] =20 - cmp ecx, edx ;If PcdFspReservedBufferSize >=3D PcdTemporary= RamSize, then error. + cmp ecx, edx ;If PcdFspReservedBufferSize >=3D TemporaryRam= Size, then error. jb EstablishStackFspSuccess mov eax, 80000003h ;EFI_UNSUPPORTED jmp EstablishStackFspExit @@ -599,6 +610,47 @@ ASM_PFX(TempRamInitApi): CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param SAVE_ECX ; save UPD param to slot 3 in xmm= 6 =20 + mov edx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) + mov edx, DWORD [edx] + ; + ; Read ARCH2 UPD input value. + ; + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize= ] + ; + ; As per spec, if Bootloader pass zero, use Fsp defined Size + ; Irrespective of whether this UPD is supported or not, Fallback + ; to Fsp defined size if input is zero. + ; + cmp ebx, 0 + jz UseTemporaryRamSizePcd + + xor eax, eax + mov ax, WORD [esi + 020h] ; Read ImageAttribute + test ax, 16 ; check if Bit4 is set + jnz ConsumeInputConfiguration + ; + ; Sometimes user may change input value even if it is not supported + ; return error if input is Non-Zero and not same as PcdTemporaryRamSize. + ; + cmp ebx, edx + je UseTemporaryRamSizePcd + mov eax, 080000002h ; RETURN_INVALID_PARAMETER + jmp TempRamInitExit +ConsumeInputConfiguration: + ; + ; Read Fsp Arch2 revision + ; + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3 + jb UseTemporaryRamSizePcd + ; + ; Read ARCH2 UPD value and Save. + ; + SAVE_TEMPORARY_RAM_SIZE ebx + jmp GotTemporaryRamSize +UseTemporaryRamSizePcd: + SAVE_TEMPORARY_RAM_SIZE edx +GotTemporaryRamSize: + LOAD_ECX ; ; Sec Platform Init ; diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp= 2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 016f943b43..4d6ec1e984 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -128,6 +128,17 @@ SXMMN xmm5, 1, eax %endmacro =20 +; +; XMM5 slot 2 for TemporaryRamSize +; +%macro LOAD_TEMPORARY_RAM_SIZE 1 + LXMMN xmm5, %1, 2 + %endmacro + +%macro SAVE_TEMPORARY_RAM_SIZE 1 + SXMMN xmm5, 2, %1 + %endmacro + %macro ENABLE_SSE 0 ; ; Initialize floating point units diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.c index 11be1f97ca..8b41968760 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -47,7 +47,8 @@ FspGetExceptionHandler ( VOID EFIAPI SecGetPlatformData ( - IN OUT FSP_GLOBAL_DATA *FspData + IN OUT FSP_GLOBAL_DATA *FspData, + IN UINT32 TemporaryRamSize ) { FSP_PLAT_DATA *FspPlatformData; @@ -68,10 +69,13 @@ SecGetPlatformData ( FspPlatformData->CodeRegionBase =3D 0; FspPlatformData->CodeRegionSize =3D 0; =20 + if (TemporaryRamSize =3D=3D 0 || TemporaryRamSize =3D=3D 0xFFFFFFFF) { + return; + } // // Pointer to the size field // - TopOfCar =3D PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamS= ize); + TopOfCar =3D PcdGet32 (PcdTemporaryRamBase) + TemporaryRamSize; StackPtr =3D (UINT32 *)(TopOfCar - sizeof (UINT32)); =20 if (*(StackPtr - 1) =3D=3D FSP_MCUD_SIGNATURE) { @@ -123,7 +127,14 @@ FspGlobalDataInit ( VOID *FspmUpdDataPtr; CHAR8 ImageId[9]; UINTN Idx; + UINTN *TopOfCar; =20 + // + // If TempRam is initilized using FspTempRamInitApi (), GlobalDataPointe= r + // will point to the Top of the Car and any Data that FspTempRamInitApi + // wants to Handoff to later stages will be pushed on to the Top of the = car. + // + TopOfCar =3D *(VOID **)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress); // // Set FSP Global Data pointer // @@ -147,7 +158,7 @@ FspGlobalDataInit ( // It may have multiple FVs, so look into the last one for FSP header // PeiFspData->FspInfoHeader =3D (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHea= der (); - SecGetPlatformData (PeiFspData); + SecGetPlatformData (PeiFspData, (UINTN)TopOfCar); =20 // // Set API calling mode diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index 5f59938518..33aaac66c1 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -42,9 +42,7 @@ FspApiCallingCheck ( // // FspMemoryInit check // - if (((UINTN)FspData !=3D MAX_ADDRESS) && ((UINTN)FspData !=3D MAX_UINT= 32)) { - Status =3D EFI_UNSUPPORTED; - } else if (ApiParam =3D=3D NULL) { + if (ApiParam =3D=3D NULL) { Status =3D EFI_SUCCESS; } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) { Status =3D EFI_INVALID_PARAMETER; diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index 698bb063a7..4a1da9f718 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -16,6 +16,7 @@ extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) +extern ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress)) =20 ; ; Following functions will be provided in PlatformSecLib @@ -76,7 +77,8 @@ struc LoadMicrocodeParamsFsp24 .FsptArchReserved: resb 3 .FsptArchLength: resd 1 .FspDebugHandler resq 1 - .FsptArchUpd: resd 4 + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison is= >=3D 3 + .FsptArchUpd: resd 3 ; } ; FSPT_CORE_UPD { .MicrocodeCodeAddr: resq 1 @@ -163,7 +165,7 @@ ASM_PFX(LoadMicrocodeDefault): cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2 jb ParamError cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2 - jne ParamError + jb ParamError =20 ; UPD structure is compliant with FSP spec 2.4 mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] @@ -273,7 +275,7 @@ CheckAddress: cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2 jb ParamError cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2 - jne ParamError + jb ParamError =20 ; UPD structure is compliant with FSP spec 2.4 ; Is automatic size detection ? @@ -337,9 +339,16 @@ ASM_PFX(EstablishStackFsp): ; mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) mov esp, DWORD[rax] - mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) - add esp, DWORD[rax] - + LOAD_TEMPORARY_RAM_SIZE rax + add esp, eax + ; + ; Save top of the TemporaryRam in PcdGlobalDataPointerAddress + ; where the FspTempRamInitAPI information is pushed as part of below cod= e + ; which will be used in other Fsp APIs to retrive the same. + ; + mov rax, ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress)) + mov eax, DWORD[rax] + mov DWORD[eax], esp sub esp, 4 mov dword[esp], DATA_LEN_OF_MCUD ; Size of the data region sub esp, 4 @@ -349,7 +358,7 @@ ASM_PFX(EstablishStackFsp): cmp byte [rdx + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2 jb ParamError1 cmp byte [rdx + LoadMicrocodeParamsFsp24.FsptArchRevision], 2 - je Fsp24UpdHeader + jnb Fsp24UpdHeader =20 ParamError1: mov rax, 08000000000000002h @@ -397,8 +406,8 @@ ContinueAfterUpdPush: ; mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) mov edx, [ecx] - mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) - add edx, [ecx] + LOAD_TEMPORARY_RAM_SIZE rcx + add edx, ecx mov rcx, ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) sub edx, [ecx] mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) @@ -439,6 +448,14 @@ ASM_PFX(TempRamInitApi): ; SAVE_BFV rbp =20 + ; + ; Save timestamp into YMM6 + ; + rdtsc + shl rdx, 32 + or rax, rdx + SAVE_TS rax + ; ; Save Input Parameter in YMM10 ; @@ -455,14 +472,47 @@ ASM_PFX(TempRamInitApi): ParamValid: SAVE_RCX =20 + mov rdx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) + mov edx, DWORD [rdx] ; - ; Save timestamp into YMM6 + ; Read ARCH2 UPD input value. ; - rdtsc - shl rdx, 32 - or rax, rdx - SAVE_TS rax + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize= ] + ; + ; As per spec, if Bootloader pass zero, use Fsp defined Size + ; Irrespective of whether this UPD is supported or not, Fallback + ; to Fsp defined size if input is zero. + ; + cmp ebx, 0 + jz UseTemporaryRamSizePcd + + xor rax, rax + mov ax, WORD [rsi + 020h] ; Read ImageAttribute + test ax, 16 ; check if Bit4 is set + jnz ConsumeInputConfiguration + ; + ; Sometimes user may change input value even if it is not supported + ; return error if input is Non-Zero and not same as PcdTemporaryRamSize. + ; + cmp ebx, edx + je UseTemporaryRamSizePcd + mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER + jmp TempRamInitExit +ConsumeInputConfiguration: + ; + ; Read Fsp Arch2 revision + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3 + jb UseTemporaryRamSizePcd + ; + ; Read ARCH2 UPD value and Save. + ; Only low-32 bits of rbx/rdx holds the temporary ram size. + ; + SAVE_TEMPORARY_RAM_SIZE rbx + jmp GotTemporaryRamSize +UseTemporaryRamSizePcd: + SAVE_TEMPORARY_RAM_SIZE rdx =20 +GotTemporaryRamSize: ; ; Sec Platform Init ; diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index 40e063e944..27d5ec3a3c 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -139,7 +139,7 @@ typedef struct { /// typedef struct { /// - /// Revision of the structure is 2 for this version of the specification= . + /// Revision of the structure is 3 for this version of the specification= . /// UINT8 Revision; UINT8 Reserved[3]; @@ -152,7 +152,8 @@ typedef struct { /// occurring during FSP execution. /// EFI_PHYSICAL_ADDRESS FspDebugHandler; - UINT8 Reserved1[16]; + UINT32 FspTemporaryRamSize; + UINT8 Reserved1[12]; } FSPT_ARCH2_UPD; =20 /// diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index 002a5a1412..2168564e6d 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -201,6 +201,27 @@ movq rcx, xmm5 %endmacro =20 +; +; Save TemporaryRamSize to YMM10[192:255] +; arg 1:general purpose register which holds TemporaryRamSize +; Modified: XMM5 and YMM10[192:255] +; +%macro SAVE_TEMPORARY_RAM_SIZE 1 + LYMMN ymm10, xmm5, 1 + SXMMN xmm5, 1, %1 + SYMMN ymm10, 1, xmm5 + %endmacro + +; +; Restore TemporaryRamSize from YMM10[192:255] +; arg 1:general purpose register where to save TemporaryRamSize +; Modified: XMM5 and %1 +; +%macro LOAD_TEMPORARY_RAM_SIZE 1 + LYMMN ymm10, xmm5, 1 + LXMMN xmm5, %1, 1 + %endmacro + ; ; YMM7[128:191] for calling stack ; arg 1:Entry diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec index d1c3d3ee7b..426d31a13f 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec @@ -85,6 +85,11 @@ gFspEventEndOfFirmwareGuid =3D { 0xbd44f629, 0xeae7, 0x4198, = { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } } =20 [PcdsFixedAtBuild] + # + # As part of FSP-T execution, this will be initialized to TemporaryRamSi= ze that FSP-T used=20 + # for TemporaryRam configuraiton.Once Fsp Global Data is initialed later= in FSP-M, this=20 + # will hold the Global data buffer address. + # gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT= 32|0x00000001 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT= 32|0x10001001 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UINT= 32|0x10001002 diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= SecRamInitData.c b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibS= ample/SecRamInitData.c index fb0d9a8683..316c2fa86a 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c @@ -49,8 +49,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA F= sptUpdDataPtr =3D { }, 0x00000020, 0x00000000, + 0x00000000, { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, --=20 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116656): https://edk2.groups.io/g/devel/message/116656 Mute This Topic: https://groups.io/mt/104620019/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-