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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Oram, Isaac W =20 Sent: Tuesday, October 19, 2021 8:00 PM To: devel@edk2.groups.io Cc: Oram, Isaac W ; Desimone, Nathaniel L ; Chiu, Chasel Subject: [edk2-devel][edk2-platforms][PATCH V1 1/2] WhitleySiliconPkg/Multi= PchPei: Open Source PEIM Eliminate the need for the binary PEIM currenty in use by Whitley. Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram --- Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Library/PchMul= tiPch.h | 34 ++++++++ Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchP= ei.c | 84 ++++++++++++++++++++ Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchP= ei.inf | 40 ++++++++++ 3 files changed, 158 insertions(+) diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Li= brary/PchMultiPch.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/I= nclude/Library/PchMultiPch.h new file mode 100644 index 0000000000..1fe502b7a7 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Librar +++ y/PchMultiPch.h @@ -0,0 +1,34 @@ +/** @file + Prototype of the MultiPch library. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_MULTI_PCH_LIB_H_ +#define _PCH_MULTI_PCH_LIB_H_ + +#include +#include + +#define PCH_IP_INFO_REVISION 1 + +typedef struct _PCH_IP_INFO { + /** + Revision 1: Original version + **/ + UINT8 Revision; + + BOOLEAN Valid[PCH_MAX]; + UINT8 SocketId[PCH_MAX]; + UINT8 Segment[PCH_MAX]; + UINT8 Bus[PCH_MAX]; + UINT64 P2sbBar[PCH_MAX]; + UINT64 TempBar[PCH_MAX]; + UINT64 PmcBar[PCH_MAX]; + UINT64 SpiBar[PCH_MAX]; +} PCH_IP_INFO; + +#endif // _PCH_MULTI_PCH_LIB_H_ diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/P= ei/MultiPchPei.c b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Mult= iPch/Pei/MultiPchPei.c new file mode 100644 index 0000000000..65cee5d031 --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/M +++ ultiPchPei.c @@ -0,0 +1,84 @@ +/** @file + This driver manages the initial phase of Multi PCH + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include #include=20 + + +/// +/// The default PCH PCI segment number +/// +#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0 + +/** + @brief + Multi PCH entry point. + + @param[in] FileHandle PEIM file handle @param[in] PeiServices General=20 + purpose services available to every PEIM + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +MultiPchPeiEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + PCH_IP_INFO *PchInfo; + EFI_PEI_PPI_DESCRIPTOR *PchIpInfoPpiDesc; + + DEBUG ((DEBUG_INFO, "[PCH] MultiPchPeiEntryPoint called.\n")); + + // + // Create PchIpInfo + // + PchInfo =3D (PCH_IP_INFO *) AllocateZeroPool (sizeof (PCH_IP_INFO)); =20 + if (PchInfo =3D=3D NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + PchInfo->Revision =3D PCH_IP_INFO_REVISION; =20 + PchInfo->Valid[PCH_LEGACY_ID] =3D TRUE; PchInfo->Segment[PCH_LEGACY_ID]= =20 + =3D DEFAULT_PCI_SEGMENT_NUMBER_PCH; PchInfo->Bus[PCH_LEGACY_ID] =3D=20 + DEFAULT_PCI_BUS_NUMBER_PCH; PchInfo->P2sbBar[PCH_LEGACY_ID] =3D=20 + PCH_PCR_BASE_ADDRESS; PchInfo->PmcBar[PCH_LEGACY_ID] =3D=20 + PCH_PWRM_BASE_ADDRESS; PchInfo->SpiBar[PCH_LEGACY_ID] =3D=20 + PCH_SPI_BASE_ADDRESS; PchInfo->TempBar[PCH_LEGACY_ID] =3D=20 + PCH_TEMP_BASE_ADDRESS; + + // + // Install PchIpInfoPpi + // + PchIpInfoPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool=20 + (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (PchIpInfoPpiDesc =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PchIpInfoPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI |=20 + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PchIpInfoPpiDesc->Guid =3D &gPchIpInfoPpiGuid; + PchIpInfoPpiDesc->Ppi =3D PchInfo; + + Status =3D PeiServicesInstallPpi (PchIpInfoPpiDesc); if (EFI_ERROR=20 + (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/P= ei/MultiPchPei.inf b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Mu= ltiPch/Pei/MultiPchPei.inf new file mode 100644 index 0000000000..bd15593f2b --- /dev/null +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/M +++ ultiPchPei.inf @@ -0,0 +1,40 @@ +## @file +# This driver manages the initial phase of Multi PCH # # @copyright #=20 +Copyright 2019 - 2021 Intel Corporation.
# #=20 +SPDX-License-Identifier: BSD-2-Clause-Patent ## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D MultiPch + FILE_GUID =3D 0043A734-CB11-4274-B363-E165F958CB5F + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D MultiPchPeiEntryPoint + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + MultiPchPei.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/SiliconPkg.dec + +[LibraryClasses] + BaseLib + PeimEntryPoint + DebugLib + +[Ppis] + gPchIpInfoPpiGuid + +[Depex] + TRUE -- 2.27.0.windows.1