From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web09.10825.1658511809604338918 for ; Fri, 22 Jul 2022 10:43:29 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Q2DqM1A5; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: nathaniel.l.desimone@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658511809; x=1690047809; h=from:to:subject:date:message-id:references:in-reply-to: content-transfer-encoding:mime-version; bh=0CiBVpDbG8SdNctzz/DY8bJntRhVt0SkHPnMPfX0nL4=; b=Q2DqM1A5SgKMpufqPLjeNJfboQ0rDDzi6Fnmca12W7PzkE4UPMi7h91D LVnYQyb0uDGwqhXTScyMKdqyCfLYmQYsvrmXLfuJ5/czWCEXOZ2cAl0pv JQe6PzkvfqhV4JHBfxQn7pJKr9XXrAfj2h21LnV9ziNRR7lorg1jSKb6u ntS1pqNTMh5nVGy0Q32N2lnKo+qJjwIMtjA8qwv9pKBsreFilp2pJVQdm ZJ6ZSAiVhteDaIXX+9AqxP7V6hAtB+HwqJNKOm/PG5eUZvB02/SBJcHmp Ag6JucTC02j8V+hAnaLVKMoBmOMmEfsizqMxHCgT6nhEwI0psENJSbgMu g==; X-IronPort-AV: E=McAfee;i="6400,9594,10416"; a="373677400" X-IronPort-AV: E=Sophos;i="5.93,186,1654585200"; d="scan'208";a="373677400" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2022 10:40:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,186,1654585200"; d="scan'208";a="598923421" Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86]) by orsmga002.jf.intel.com with ESMTP; 22 Jul 2022 10:40:38 -0700 Received: from fmsmsx601.amr.corp.intel.com (10.18.126.81) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Fri, 22 Jul 2022 10:40:38 -0700 Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28 via Frontend Transport; Fri, 22 Jul 2022 10:40:38 -0700 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.173) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2308.27; Fri, 22 Jul 2022 10:40:37 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IzNRA45/Twbm0lW7/okNBfwyYBXLUUaVnmfI/l5wuy5Cw9H8LpZgHGXaXXvo7bI68v6x5ak0LSKlwp4Pc1CjmRbgwWl/H3LHPSm4ukNSkdBFMJHkEMjg3uDUUL/yf1aRHf2DMa/H4xTcgwChnIsIwdbJ83wMQvNFdTdprX55VytaqNdlCH1M8uAlZ2ozWAJIPfW+QO2USA7e7nKpe5l1RoYIjCRvpW4mIKy6STeuosfbaSmTC55NJgmi0cWQqHyOK4hbDHH+aA9Wq0PwHFJtWPt0UTmt16H81+xQAGIRQtT9562c5XolsboJofk1lXymK5vlKXQxs9QJ7SIXUkKioQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dwmFtC02YHcsz2+Hy0jaBWizR1r9SyBkuyZl9wwcdnk=; b=DD7uQdmDrJcqZ/lVQdoywAdSo/bDnX2KNax5rMFl/oUXgG68GXe4S+NFduHlGuf8OVZ5Qf7o6+X0vFczMLrkN7aK4zeMJDc/7TyzsONZfcz+bv0jeq8NB0V1I5LOrd5C039GX1l3RdTfpiLyNX8YLy3JltEAR0Rfqyj0l5/tiQhPHgq+zcXOFbQEbz/qTTEfRjQT3q28VO+o3/rjTWkhLABeUeayF3uXNa1xIZEjqfGagkcArfTgtVCPS/4JMAkixenikduYn2CHu85al0A767N2A3waAWdlN7a3OyUX32kG8MDmjStwZ0VFJ+jzCqpLJdz4bxsUWODhknZ4PNrAKQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from MW4PR11MB5821.namprd11.prod.outlook.com (2603:10b6:303:184::5) by MWHPR11MB1392.namprd11.prod.outlook.com (2603:10b6:300:24::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5458.18; Fri, 22 Jul 2022 17:40:36 +0000 Received: from MW4PR11MB5821.namprd11.prod.outlook.com ([fe80::b4bc:a6b4:5832:5ae0]) by MW4PR11MB5821.namprd11.prod.outlook.com ([fe80::b4bc:a6b4:5832:5ae0%3]) with mapi id 15.20.5458.019; Fri, 22 Jul 2022 17:40:36 +0000 From: "Nate DeSimone" To: "Zeng, Star" , "Chiu, Chasel" , "devel@edk2.groups.io" Subject: Re: [PATCH v3] IntelFsp2Pkg: Add FSPI_ARCH_UPD. Thread-Topic: [PATCH v3] IntelFsp2Pkg: Add FSPI_ARCH_UPD. Thread-Index: AQHYnKmvfeVHtytiRk63FS2aDC9aJK2IJImAgAACnICAAADTAIACguMg Date: Fri, 22 Jul 2022 17:40:36 +0000 Message-ID: References: <20220721022837.4137-1-chasel.chiu@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 58ab531b-7dc0-4596-5ed7-08da6c09491b x-ms-traffictypediagnostic: MWHPR11MB1392:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: doZaiwIvzRieaugFg2izfwW4yknOIWzt9pmCUGTM4fsWbhCUI1w0koo8viy72ap9YbZzO14L/Yey896gRIlbkFIA7QmMPkxyg3GH8Zs2+hd+r0qgwCZ1LJvLb8oQDzkNV201sOQPavxF24ahjCOrWOEn/hi3Cetb6Br1FxdWeCtrjSVMJGlisnVeiu9t0IExiM6/Qmhze7JTsPc5qsY1BPpTNFwpHum5zYp58NzdtYPIlRzfcOEhOLD4WW78F2jKgrFUhqemMo7nguXpOaumHCAX2s79PUbXKPvPENGcgVXyEZPHHl480daLJu+TuK0Q/R8ufj8LvMBGKyzDn4bICVmUBd1KZzMdHcPRoGNcb/0Db1K3bqI8HMEkxx2MsK7uhAP3Mp4LpgdkFCjVJFqoCr8gJWxZ/MDHwfWJKWgi9gEmtrKAXJju/cCwwHNyNQ7UcnAiygUvfUpZiSb6sNG+eiW6JHN/+g2DcuNpB8/S2Pjld4miiG9YVcSC+TonY+/7qlkX6EJ4Y2C4Rgu/cg1b/d9mSb8Vwlb9mhiyZ2/3SNdU8VR+rQK5WcM0FKOQpaTs5FgfMPQGleD3zowdNQxQG1e0Lwtf8Nkue8iNajuC2L0YI4KBE+6xUAQ85liF5JJMKX43PQkJ/31DJSnOUKBKQ84LL+foJRC7ARggSQR2X6AMaHPHtzMkFSfguvXJjVgIkiWQSyqYnVY2H7Z77qOANve5g20gl1iIcWI7ijRbqSuYiBNPXB8BchRHdds+rIesdCXTu78k9eWnmqN4s322lrH5fz+ybp3w2zqVvUjpqIWjX6vlLeLz1N6Ff/6IqYfnoiq5QBGgOWm/iqLYT3ZVRQ== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW4PR11MB5821.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(39860400002)(366004)(376002)(136003)(396003)(346002)(122000001)(38070700005)(478600001)(38100700002)(83380400001)(86362001)(33656002)(82960400001)(966005)(52536014)(8936002)(316002)(19627235002)(5660300002)(66946007)(110136005)(8676002)(66556008)(76116006)(64756008)(71200400001)(66446008)(66476007)(186003)(55016003)(7696005)(6506007)(41300700001)(53546011)(2906002)(9686003)(26005);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?ibdQAhapVc/xTlzJiNj9BQoP5IqpZdCWblnGOPUySQgn/6boGNPtIY7qvAjx?= =?us-ascii?Q?5BGaAbIUfBe8AF/JfgviORZH6/tLDN3ryW2mzoYluEZDNW5kL/CI+3RPdwrY?= =?us-ascii?Q?8mCV/UWODzP1jUwq8M96xpjiSLCwZBtz+8jzuYrS5aSp+ZMAJ8FRh1l+jvjS?= =?us-ascii?Q?yt4I0aX4qEBMh52un+OASKMuM9dnUwKk59qeN2WffxoSmkLfZ7G0X9K6LfFa?= =?us-ascii?Q?X8YDSmGMoM4pA+zLBgh++eOzs9Q1MvUmgTd7bOBOsCg4joz3wlyf3KWNG3/8?= =?us-ascii?Q?ykpgiH3vU4tYkzhcW1m+sXcDiLHY9v/4kp4E1Es6mhpFUO5IJa6E13cJ8j5B?= =?us-ascii?Q?t0CRoQkO9/qsTQMAmKCVxkD/kHBOde953VsKftx6d1REB1iD7arZH0UfjkWW?= =?us-ascii?Q?JiAA6Qdf+eHRZRSITDWVIrqbn0PUr+ur7AVR0CampudddkmCF6ZpjOhdYSKE?= =?us-ascii?Q?LKkuyVjZki2SxUTfMMWgK3igAqF/hMb0yADmt5VGncXRx363aygpUI6Iy4UY?= =?us-ascii?Q?5fGVqDXzTOpXWg0Oc794yTxAtxuxg/3NF1fJqCaDvLEm/1RGz92JnMvDKjpi?= =?us-ascii?Q?Y3KBG8b2HM9KRvSeaqBHRQQJT8cX5MH/WNgulqopqsXsEjZXAdffOgQrKEy6?= =?us-ascii?Q?W8zUFb7plxFnlAX88wpGdo/s/qVLgKeFbW9MM7dzGsyIWpkOzlKevN8QUuqU?= =?us-ascii?Q?n3+J21ZAAuf/239Ljgk7K7EfTRIFnnHoKspkn8O61FPK7WLkZLkHob6wyWgb?= =?us-ascii?Q?809Ura9FgJFwK4ctvNS6d6EggdKN+ZP6V9oSrkrNuBVHqvUQQO93eE9nIbBC?= =?us-ascii?Q?FqYp1UeBbZe+pV/o+nWsSDUDxipBcTCghU5FAPeYvCI0az6E0WvvyoZtc9jB?= =?us-ascii?Q?FVPHrc8JxougYrN8YaXRejt73OvUubx1u8CL88+yQVuhymq15qsEXXRyeyl8?= =?us-ascii?Q?vSSP86tL/lzG2HVGDHHP1B4umB9qJI7VEk9xeEreK70LsGemoVGppqLjnba6?= =?us-ascii?Q?GxxdOjxxghaI7sE4n8WvBh5sYEeIvQ0eFK7pBeanKmScQtucG2aoUzZ2FXJb?= =?us-ascii?Q?mPqxfsjc4gB0gqinS8e/GLkMZOUnL821MY9bHhGo8/r2bIGFxgiKBAmU7mgd?= =?us-ascii?Q?CQiMhJfrOd679WsoduLUMfobOnGef1wfYjRGTafGmoe/XkbCVgOODcmUL17e?= =?us-ascii?Q?DYGNIABdBz+t5zSZtxVg7EaaXczMre+/kScTo7mVUq3rKa0EY8TIdGhxUv9e?= =?us-ascii?Q?TMiMu4V160vPoRx+UTdKwOlOZ4boIxjlXK961ukUYKCWNzEhOegN37yPvaDC?= =?us-ascii?Q?/sy+6dOOwbg52nzZshZFN3logR+0WkrJ3qRwI9B1sqBcbS2jo3xRWnH4tMta?= =?us-ascii?Q?QjxNogeisAbOr0PZtdd9tSMS9tWwn2GithLuqe6cKyKiAJa+NUIJKAPzSmVZ?= =?us-ascii?Q?l2nclBfK6x8L8shDMslcmOHGbyfwQS+YmXuNMNbB5pYz/n6uS00OWK00CWq/?= =?us-ascii?Q?09L8pB/yzGl2jP2GrBx9Yg4OqGcVzfMnq9sa765OvLel9Q2Ypm9melKFZ6C2?= =?us-ascii?Q?HUqfAffkrug/Geko76+sIHpxqCaljs/zKOiT7UJgh8HiZMOcq2MfFy/8RwU/?= =?us-ascii?Q?dw=3D=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW4PR11MB5821.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 58ab531b-7dc0-4596-5ed7-08da6c09491b X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jul 2022 17:40:36.3226 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Vm/i+OERm8Tbbv/gULYuS0/W7pB2q3if4th/tABtSdP/1dufLdvX5SnMG0grVOKCgOr7aP0i52nU9NWYNEObit3y4tqBlif6eKcWKxCINvI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB1392 Return-Path: nathaniel.l.desimone@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Good catch everyone! The spec has been changed to the following: typedef struct { UINT8 Revision; UINT8 Reserved[3]; UINT32 Length; EFI_PHYSICAL_ADDRESS BootloaderSmmFvBaseAddress; UINT64 BootloaderSmmFvLength; EFI_PHYSICAL_ADDRESS BootloaderSmmFvContextData; UINT16 BootloaderSmmFvContextDataLength; UINT8 Reserved1[30]; } FSPI_ARCH_UPD; -----Original Message----- From: Zeng, Star =20 Sent: Wednesday, July 20, 2022 8:19 PM To: Chiu, Chasel ; devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Zeng, Star Subject: RE: [PATCH v3] IntelFsp2Pkg: Add FSPI_ARCH_UPD. The spec looks wrong to me. Thanks, Star -----Original Message----- From: Chiu, Chasel =20 Sent: Thursday, July 21, 2022 11:16 AM To: Zeng, Star ; devel@edk2.groups.io Cc: Desimone, Nathaniel L Subject: RE: [PATCH v3] IntelFsp2Pkg: Add FSPI_ARCH_UPD. Hi Star, this is following current specification. Thanks, Chasel > -----Original Message----- > From: Zeng, Star > Sent: Wednesday, July 20, 2022 8:07 PM > To: Chiu, Chasel ; devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Zeng, Star=20 > > Subject: RE: [PATCH v3] IntelFsp2Pkg: Add FSPI_ARCH_UPD. >=20 > Is the reserved bytes number correct for FSPI_ARCH_UPD alignment? > UINT16 BootloaderSmmFvContextDataLength; > UINT8 Reserved1[24]; >=20 > Thanks, > Star > -----Original Message----- > From: Chiu, Chasel > Sent: Thursday, July 21, 2022 10:29 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L=20 > ; Zeng, Star > Subject: [PATCH v3] IntelFsp2Pkg: Add FSPI_ARCH_UPD. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3993 >=20 > Adding the missing FSPI_ARCH_UPD, FSP_GLOBAL_DATA_VERSION bumpping up,=20 > and some comments for clarification. > Also fixed a bug in SplitFspBin.py for FSP-I support. >=20 > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Chasel Chiu > --- > IntelFsp2Pkg/Include/FspEas/FspApi.h | 71 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- > ----- > IntelFsp2Pkg/Include/FspGlobalData.h | 2 +- > IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 21 +++++++++++++++++++-- > IntelFsp2Pkg/Tools/SplitFspBin.py | 2 +- > 4 files changed, 85 insertions(+), 11 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h > b/IntelFsp2Pkg/Include/FspEas/FspApi.h > index bf46f13f73..3f368574e8 100644 > --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h > +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h > @@ -1,6 +1,6 @@ > /** @file >=20 > Intel FSP API definition from Intel Firmware Support Package=20 > External >=20 > - Architecture Specification v2.0 - v2.2 >=20 > + Architecture Specification v2.0 and above. >=20 >=20 >=20 > Copyright (c) 2014 - 2022, Intel Corporation. All rights=20 > reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > @@ -100,13 +100,14 @@ typedef struct { > /// "XXXXXX_T" for FSP-T >=20 > /// "XXXXXX_M" for FSP-M >=20 > /// "XXXXXX_S" for FSP-S >=20 > + /// "XXXXXX_I" for FSP-I >=20 > /// Where XXXXXX is an unique signature >=20 > /// >=20 > UINT64 Signature; >=20 > /// >=20 > /// Revision of the Data structure. >=20 > - /// For FSP spec 2.0/2.1 value is 1. >=20 > - /// For FSP spec 2.2 value is 2. >=20 > + /// For FSP spec 2.0/2.1, this value is 1 and only FSPM_UPD having > ARCH_UPD. >=20 > + /// For FSP spec 2.2 and above, this value is 2 and ARCH_UPD present= in all > UPD structures. >=20 > /// >=20 > UINT8 Revision; >=20 > UINT8 Reserved[23]; >=20 > @@ -134,7 +135,7 @@ typedef struct { > } FSPT_ARCH_UPD; >=20 >=20 >=20 > /// >=20 > -/// FSPT_ARCH2_UPD Configuration. >=20 > +/// FSPT_ARCH2_UPD Configuration for FSP 2.4 and above. >=20 > /// >=20 > typedef struct { >=20 > /// >=20 > @@ -196,7 +197,7 @@ typedef struct { > } FSPM_ARCH_UPD; >=20 >=20 >=20 > /// >=20 > -/// FSPM_ARCH2_UPD Configuration. >=20 > +/// FSPM_ARCH2_UPD Configuration for FSP 2.4 and above. >=20 > /// >=20 > typedef struct { >=20 > /// >=20 > @@ -209,6 +210,13 @@ typedef struct { > /// >=20 > UINT32 Length; >=20 > /// >=20 > + /// Pointer to the non-volatile storage (NVS) data buffer. >=20 > + /// If it is NULL it indicates the NVS data is not available. >=20 > + /// This value is deprecated starting with v2.4 of the FSP=20 > + specification, >=20 > + /// and will be removed in an upcoming version of the FSP specificatio= n. >=20 > + /// >=20 > + EFI_PHYSICAL_ADDRESS NvsBufferPtr; >=20 > + /// >=20 > /// Pointer to the temporary stack base address to be >=20 > /// consumed inside FspMemoryInit() API. >=20 > /// >=20 > @@ -232,7 +240,7 @@ typedef struct { > /// This value is only valid if Revision is >=3D 2. >=20 > /// >=20 > EFI_PHYSICAL_ADDRESS FspEventHandler; >=20 > - UINT8 Reserved1[24]; >=20 > + UINT8 Reserved1[16]; >=20 > } FSPM_ARCH2_UPD; >=20 >=20 >=20 > /// >=20 > @@ -265,7 +273,7 @@ typedef struct { > } FSPS_ARCH_UPD; >=20 >=20 >=20 > /// >=20 > -/// FSPS_ARCH2_UPD Configuration. >=20 > +/// FSPS_ARCH2_UPD Configuration for FSP 2.4 and above. >=20 > /// >=20 > typedef struct { >=20 > /// >=20 > @@ -285,6 +293,40 @@ typedef struct { > UINT8 Reserved1[16]; >=20 > } FSPS_ARCH2_UPD; >=20 >=20 >=20 > +/// >=20 > +/// FSPI_ARCH_UPD Configuration. >=20 > +/// >=20 > +typedef struct { >=20 > + /// >=20 > + /// Revision of the structure is 1 for this version of the specificati= on. >=20 > + /// >=20 > + UINT8 Revision; >=20 > + UINT8 Reserved[3]; >=20 > + /// >=20 > + /// Length of the structure in bytes. The current value for this field= is 32. >=20 > + /// >=20 > + UINT32 Length; >=20 > + /// >=20 > + /// The physical memory-mapped base address of the bootloader SMM > firmware volume (FV). >=20 > + /// >=20 > + EFI_PHYSICAL_ADDRESS BootloaderSmmFvBaseAddress; >=20 > + /// >=20 > + /// The length in bytes of the bootloader SMM firmware volume (FV). >=20 > + /// >=20 > + UINT64 BootloaderSmmFvLength; >=20 > + /// >=20 > + /// The physical memory-mapped base address of the bootloader SMM=20 > + FV > context data. >=20 > + /// This data is provided to bootloader SMM drivers through a HOB=20 > + by the FSP > MM Foundation. >=20 > + /// >=20 > + EFI_PHYSICAL_ADDRESS BootloaderSmmFvContextData; >=20 > + /// >=20 > + /// The length in bytes of the bootloader SMM FV context data. >=20 > + /// This data is provided to bootloader SMM drivers through a HOB=20 > + by the FSP > MM Foundation. >=20 > + /// >=20 > + UINT16 BootloaderSmmFvContextDataLength; >=20 > + UINT8 Reserved1[24]; >=20 > +} FSPI_ARCH_UPD; >=20 > + >=20 > /// >=20 > /// FSPT_UPD_COMMON Configuration. >=20 > /// >=20 > @@ -393,6 +435,21 @@ typedef struct { > FSPS_ARCH2_UPD FspsArchUpd; >=20 > } FSPS_UPD_COMMON_FSP24; >=20 >=20 >=20 > +/// >=20 > +/// FSPI_UPD_COMMON Configuration. >=20 > +/// >=20 > +typedef struct { >=20 > + /// >=20 > + /// FSP_UPD_HEADER Configuration. >=20 > + /// >=20 > + FSP_UPD_HEADER FspUpdHeader; >=20 > + >=20 > + /// >=20 > + /// FSPI_ARCH_UPD Configuration. >=20 > + /// >=20 > + FSPI_ARCH_UPD FspiArchUpd; >=20 > +} FSPI_UPD_COMMON; >=20 > + >=20 > /// >=20 > /// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE. >=20 > /// >=20 > diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h > b/IntelFsp2Pkg/Include/FspGlobalData.h > index 697b20ed4c..cf94f7b6a5 100644 > --- a/IntelFsp2Pkg/Include/FspGlobalData.h > +++ b/IntelFsp2Pkg/Include/FspGlobalData.h > @@ -12,7 +12,7 @@ >=20 >=20 > #define FSP_IN_API_MODE 0 >=20 > #define FSP_IN_DISPATCH_MODE 1 >=20 > -#define FSP_GLOBAL_DATA_VERSION 1 >=20 > +#define FSP_GLOBAL_DATA_VERSION 0x2 >=20 >=20 >=20 > #pragma pack(1) >=20 >=20 >=20 > diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > index c7fb63168f..5381716d81 100644 > --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > @@ -52,7 +52,7 @@ typedef struct { > UINT8 Reserved1[2]; >=20 > /// >=20 > /// Byte 0x0A: Indicates compliance with a revision of this=20 > specification in the BCD format. >=20 > - /// For revision v2.3 the value will be 0x23. >=20 > + /// For revision v2.4 the value will be 0x24. >=20 > /// >=20 > UINT8 SpecVersion; >=20 > /// >=20 > @@ -93,11 +93,28 @@ typedef struct { > /// Bit 0: Graphics Support - Set to 1 when FSP supports enabling Gr= aphics > Display. >=20 > /// Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the op= tional > Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid=20 > if FSP HeaderRevision is >=3D 4. >=20 > /// Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 6= 4-bit long > mode interfaces. Set to 0 to indicate FSP supports 32-bit mode=20 > interfaces. This bit is only valid if FSP HeaderRevision is >=3D 7. >=20 > - /// Bits 15:3 - Reserved >=20 > + /// Bit 3: FSP Variable Services Support - Set to 1 to indicate FSP = utilizes the > FSP Variable Services defined in Section 9.6 to store non-volatile=20 > data. This bit is only valid if FSP HeaderRevision is >=3D 7. >=20 > + /// Bits 15:4 - Reserved >=20 > /// >=20 > UINT16 ImageAttribute; >=20 > /// >=20 > /// Byte 0x22: Attributes of the FSP Component. >=20 > + /// Bit 0 - Build Type >=20 > + /// 0 - Debug Build >=20 > + /// 1 - Release Build >=20 > + /// Bit 1 - Release Type >=20 > + /// 0 - Test Release >=20 > + /// 1 - Official Release >=20 > + /// Bit 11:2 - Reserved >=20 > + /// Bits 15:12 - Component Type >=20 > + /// 0000 - Reserved >=20 > + /// 0001 - FSP-T >=20 > + /// 0010 - FSP-M >=20 > + /// 0011 - FSP-S >=20 > + /// 0100 - FSP-I (FSP SMM) >=20 > + /// 0101 to 0111 - Reserved >=20 > + /// 1000 - FSP-O >=20 > + /// 1001 to 1111 - Reserved >=20 > /// >=20 > UINT16 ComponentAttribute; >=20 > /// >=20 > diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py > b/IntelFsp2Pkg/Tools/SplitFspBin.py > index 317d9c1fa0..ddabab7d8c 100644 > --- a/IntelFsp2Pkg/Tools/SplitFspBin.py > +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py > @@ -492,7 +492,7 @@ class FspImage: > self.FihOffset =3D fihoff >=20 > self.Offset =3D offset >=20 > self.FvIdxList =3D [] >=20 > - self.Type =3D "XTMSIXXXXOXXXXXXX"[(fih.ComponentAttribute >= > 12) & > 0x0F] >=20 > + self.Type =3D "XTMSIXXXOXXXXXXX"[(fih.ComponentAttribute >>= 12) & > 0x0F] >=20 > self.PatchList =3D patch >=20 > self.PatchList.append(fihoff + 0x1C) >=20 >=20 >=20 > -- > 2.35.0.windows.1