* [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
@ 2024-01-31 2:14 Kuo, Ted
2024-02-01 0:10 ` Nate DeSimone
2024-02-01 0:14 ` Nate DeSimone
0 siblings, 2 replies; 3+ messages in thread
From: Kuo, Ted @ 2024-01-31 2:14 UTC (permalink / raw)
To: devel
Cc: Sai Chaganty, Chasel Chiu, Nate DeSimone, Eric Dong, Ashraf Ali S,
Chinni B Duggapu, Liming Gao
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common files to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperResetVectorInFsp
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++-
.../Ia32/SecEntry.nasm | 4 +-
.../SecFspWrapperPlatformSecLib.inf | 12 +-
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 77 +++++--
.../X64/PeiCoreEntry.nasm | 207 ++++++++++++++++++
.../X64/SecEntry.nasm | 199 +++++++++++++++++
.../X64/Stack.nasm | 72 ++++++
.../Ia32 => Include}/Fsp.h | 6 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 23 +-
11 files changed, 612 insertions(+), 32 deletions(-)
create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32 => Include}/Fsp.h (79%)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..24c18f25b8 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1)
+#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1
/** Fsp T Core UPD
**/
typedef struct {
@@ -34,6 +35,28 @@ typedef struct {
**/
UINT8 Reserved[16];
} FSPT_CORE_UPD;
+#else
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0040
+**/
+ EFI_PHYSICAL_ADDRESS MicrocodeRegionBase;
+
+/** Offset 0x0048
+**/
+ UINT64 MicrocodeRegionSize;
+
+/** Offset 0x0050
+**/
+ EFI_PHYSICAL_ADDRESS CodeRegionBase;
+
+/** Offset 0x0058
+**/
+ UINT64 CodeRegionSize;
+} FSPT_CORE_UPD;
+#endif
#pragma pack()
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..0b3f343991 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019 - 2024, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
; Module Name:
;
@@ -13,7 +13,7 @@
;
;------------------------------------------------------------------------------
-#include "Fsp.h"
+#include <Fsp.h>
SECTION .text
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..e85243c6e3 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
## @file
# Provide FSP wrapper platform sec related function.
#
-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -47,7 +47,11 @@
Ia32/SecEntry.nasm
Ia32/PeiCoreEntry.nasm
Ia32/Stack.nasm
- Ia32/Fsp.h
+
+[Sources.X64]
+ X64/SecEntry.nasm
+ X64/PeiCoreEntry.nasm
+ X64/Stack.nasm
################################################################################
#
@@ -96,3 +100,7 @@
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision ## CONSUMES
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
index ac2deeabec..1699bd9710 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
@@ -1,7 +1,7 @@
/** @file
Sample to provide SecGetPerformance function.
-Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -58,6 +58,7 @@ SecGetPerformance (
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
+
//
// |--------------| <- TopOfTemporaryRam - BL
// | List Ptr |
@@ -77,12 +78,12 @@ SecGetPerformance (
// | TSC[31:00] |
// |--------------|
//
- TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
- TopOfTemporaryRam -= sizeof (UINT32) * 2;
- Count = *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32));
+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINTN);
+ TopOfTemporaryRam -= sizeof(UINTN) * 2;
+ Count = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));
Size = Count * sizeof (UINT32);
- Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);
+ Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT64));
Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
return EFI_SUCCESS;
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
index 24d55ed838..4cbde95c2d 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
@@ -1,7 +1,7 @@
/** @file
Provide SecPlatformInformation function.
-Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -59,9 +59,9 @@ SecPlatformInformation (
// This routine copies the BIST information to the buffer pointed by
// PlatformInformationRecord for output.
//
- TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
- TopOfTemporaryRam -= sizeof (UINT32) * 2;
- Count = *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)));
+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINTN);
+ TopOfTemporaryRam -= sizeof (UINTN) * 2;
+ Count = *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));
Size = Count * sizeof (IA32_HANDOFF_STATUS);
if ((*StructureSize) < (UINT64) Size) {
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
index 355d1e6509..f91c4c1d19 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
@@ -1,7 +1,7 @@
/** @file
Provide TempRamInitParams data.
-Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,27 +10,76 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <FspEas.h>
#include "FsptCoreUpd.h"
+#if defined (MDE_CPU_IA32) && FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 1
+#error "PcdFspWrapperResetVectorInFsp == TRUE only supported for X64 builds"
+#endif
+
typedef struct {
FSP_UPD_HEADER FspUpdHeader;
+#if FixedPcdGet8 (PcdFsptArchUpdRevision) == 1
+ FSPT_ARCH_UPD FsptArchUpd;
+#elif FixedPcdGet8 (PcdFsptArchUpdRevision) == 2
+ FSPT_ARCH2_UPD FsptArchUpd;
+#endif
FSPT_CORE_UPD FsptCoreUpd;
-} FSPT_UPD_CORE_DATA;
+ UINT16 UpdTerminator;
+} FSPT_UPD_DATA;
-GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {
+GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_DATA FsptUpdDataPtr = {
+ {
+ 0x4450555F54505346, // FSP-T UPD Header Signature - FSPT_UPD
+ FixedPcdGet8 (PcdFsptUpdHeaderRevision), // FSP-T UPD Header Revision
+ { // Reserved[23]
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00
+ }
+ },
+#if FixedPcdGet8 (PcdFsptArchUpdRevision) == 1
+ {
+ 0x01, // FSP-T ARCH UPD Revision
+ { // Reserved[3]
+ 0x00, 0x00, 0x00
+ },
+ 0x00000020, // Length of FSP-T ARCH UPD
+ 0, // FspDebugHandler
+ { // Reserved1[20]
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ },
+#elif FixedPcdGet8 (PcdFsptArchUpdRevision) == 2
{
- 0x4450555F54505346,
- 0x00,
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ 0x02, // FSP-T ARCH2 UPD Revision
+ { // Reserved[3]
+ 0x00, 0x00, 0x00
+ },
+ 0x00000020, // Length of FSP-T ARCH2 UPD
+ 0, // FspDebugHandler
+ { // Reserved1[16]
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
},
+#endif
+#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1
{
- FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv),
- FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv),
- 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
- FixedPcdGet32 (PcdFlashCodeCacheSize),
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionBase
+ FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionSize
+ 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
+ FixedPcdGet32 (PcdFlashCodeCacheSize), // CodeRegionSize
+ { // Reserved[16]
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
- }
+ },
+#else
+ {
+ FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionBase
+ FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionSize
+ 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
+ FixedPcdGet32 (PcdFlashCodeCacheSize) // CodeRegionSize
+ },
+#endif
+ 0x55AA
};
-
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
new file mode 100644
index 0000000000..08933c6d37
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
@@ -0,0 +1,207 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; PeiCoreEntry.nasm
+;
+; Abstract:
+;
+; Find and call SecStartup
+;
+;------------------------------------------------------------------------------
+
+SECTION .text
+
+extern ASM_PFX(SecStartup)
+extern ASM_PFX(PlatformInit)
+extern ASM_PFX(PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))
+
+;-----------------------------------------------------------------------------
+; Macro: PUSHA_64
+;
+; Description: Saves all registers on stack
+;
+; Input: None
+;
+; Output: None
+;-----------------------------------------------------------------------------
+%macro PUSHA_64 0
+ push r8
+ push r9
+ push r10
+ push r11
+ push r12
+ push r13
+ push r14
+ push r15
+ push rax
+ push rcx
+ push rdx
+ push rbx
+ push rsp
+ push rbp
+ push rsi
+ push rdi
+%endmacro
+
+;-----------------------------------------------------------------------------
+; Macro: POPA_64
+;
+; Description: Restores all registers from stack
+;
+; Input: None
+;
+; Output: None
+;-----------------------------------------------------------------------------
+%macro POPA_64 0
+ pop rdi
+ pop rsi
+ pop rbp
+ pop rsp
+ pop rbx
+ pop rdx
+ pop rcx
+ pop rax
+ pop r15
+ pop r14
+ pop r13
+ pop r12
+ pop r11
+ pop r10
+ pop r9
+ pop r8
+%endmacro
+
+global ASM_PFX(CallPeiCoreEntryPoint)
+ASM_PFX(CallPeiCoreEntryPoint):
+ ;
+ ; Per X64 calling convention, make sure RSP is 16-byte aligned.
+ ;
+ mov rax, rsp
+ and rax, 0fh
+ sub rsp, rax
+
+ ;
+ ; Platform init
+ ;
+ PUSHA_64
+ sub rsp, 20h
+ call ASM_PFX(PlatformInit)
+ add rsp, 20h
+ POPA_64
+
+ ;
+ ; Set stack top pointer
+ ;
+ mov rsp, r8
+
+ ;
+ ; Push the hob list pointer
+ ;
+ push rcx
+
+ ;
+ ; RBP holds start of BFV passed from Vtf0. Save it to r10.
+ ;
+ mov r10, rbp
+
+ ;
+ ; Save the value
+ ; RDX: start of range
+ ; r8: end of range
+ ;
+ mov rbp, rsp
+ push rdx
+ push r8
+ mov r14, rdx
+ mov r15, r8
+
+ ;
+ ; Push processor count to stack first, then BIST status (AP then BSP)
+ ;
+ mov eax, 1
+ cpuid
+ shr ebx, 16
+ and ebx, 0000000FFh
+ cmp bl, 1
+ jae PushProcessorCount
+
+ ;
+ ; Some processors report 0 logical processors. Effectively 0 = 1.
+ ; So we fix up the processor count
+ ;
+ inc ebx
+
+PushProcessorCount:
+ sub rsp, 4
+ mov rdi, rsp
+ mov DWORD [rdi], ebx
+
+ ;
+ ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
+ ; for all processor threads
+ ;
+ xor ecx, ecx
+ mov cl, bl
+PushBist:
+ sub rsp, 4
+ mov rdi, rsp
+ movd eax, mm0
+ mov DWORD [rdi], eax
+ loop PushBist
+
+ ;
+ ; FSP saves the timestamp of the beginning of firmware execution in mm5.
+ ; Get the timestamp from mm5 and then push to stack.
+ ;
+ movq rax, mm5
+ push rax
+
+ ;
+ ; Per X64 calling convention, make sure RSP is 16-byte aligned.
+ ;
+ mov rax, rsp
+ and rax, 0fh
+ sub rsp, rax
+
+ ;
+ ; Pass entry point of the PEI core
+ ;
+ mov rdi, 0FFFFFFE0h
+ mov edi, DWORD [rdi]
+ mov r9, rdi
+
+ ;
+ ; Pass BFV into the PEI Core
+ ;
+#if FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 1
+ ;
+ ; Reset Vector and initial SEC core (to initialize Temp Ram) is part of FSP-O.
+ ; Default UefiCpuPkg Reset Vector locates FSP-O as BFV. However the actual
+ ; SEC core that launches PEI is part of another FV. We need to pass that FV
+ ; as BFV to PEI core.
+ ;
+ mov r8, ASM_PFX (PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))
+ mov rcx, QWORD[r8]
+ mov r8, rcx
+#else
+ mov r8, r10
+#endif
+
+ ;
+ ; Pass stack size into the PEI Core
+ ;
+ mov rcx, r15 ; Start of TempRam
+ mov rdx, r14 ; End of TempRam
+
+ sub rcx, rdx ; Size of TempRam
+
+ ;
+ ; Pass Control into the PEI Core
+ ;
+ sub rsp, 20h
+ call ASM_PFX(SecStartup)
+
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
new file mode 100644
index 0000000000..2618860366
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
@@ -0,0 +1,199 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Module Name:
+;
+; SecEntry.nasm
+;
+; Abstract:
+;
+; This is the code that passes control to PEI core.
+;
+;------------------------------------------------------------------------------
+
+#include <Fsp.h>
+
+SECTION .text
+
+extern ASM_PFX(CallPeiCoreEntryPoint)
+extern ASM_PFX(FsptUpdDataPtr)
+; Pcds
+extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
+extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
+
+;----------------------------------------------------------------------------
+;
+; Procedure: _ModuleEntryPoint
+;
+; Input: None
+;
+; Output: None
+;
+; Destroys: Assume all registers
+;
+; Description:
+;
+; Call TempRamInit API from FSP binary if reset vector in FSP is not supproted.
+; After TempRamInit done, pass control to PEI core.
+;
+; Return: None
+;
+; MMX Usage:
+; MM0 = BIST State
+;
+;----------------------------------------------------------------------------
+
+BITS 64
+align 16
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+#if FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 1
+ push rax
+ mov rax, ASM_PFX(FsptUpdDataPtr) ; This is dummy code to include TempRamInitParams in SecCore for FSP-O.
+ pop rax
+#else
+ fninit ; clear any pending Floating point exceptions
+ ;
+ ; Store the BIST value in mm0
+ ;
+ movd mm0, eax
+ cli
+
+ ;
+ ; Trigger warm reset if PCIEBAR register is not in reset/default value state
+ ;
+ mov eax, 80000060h ; PCIEX_BAR_REG B0:D0:F0:R60
+ mov dx, 0CF8h
+ out dx, eax
+ mov dx, 0CFCh
+ in eax, dx
+ cmp eax, 0
+ jz NotWarmStart
+
+ ;
+ ; @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
+ ;
+ mov dx, 0CF9h
+ mov al, 06h
+ out dx, al
+ jmp $
+
+NotWarmStart:
+
+ ; Find the fsp info header
+ mov rax, ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
+ mov edi, [eax]
+
+ mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
+ cmp eax, FVH_SIGINATURE_VALID_VALUE
+ jnz FspHeaderNotFound
+
+ xor eax, eax
+ mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
+ cmp ax, 0
+ jnz FspFvExtHeaderExist
+
+ xor eax, eax
+ mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
+ add edi, eax
+ jmp FspCheckFfsHeader
+
+FspFvExtHeaderExist:
+ add edi, eax
+ mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
+ add edi, eax
+
+ ; Round up to 8 byte alignment
+ mov eax, edi
+ and al, 07h
+ jz FspCheckFfsHeader
+
+ and edi, 0FFFFFFF8h
+ add edi, 08h
+
+FspCheckFfsHeader:
+ ; Check the ffs guid
+ mov eax, dword [edi]
+ cmp eax, FSP_HEADER_GUID_DWORD1
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 4]
+ cmp eax, FSP_HEADER_GUID_DWORD2
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 8]
+ cmp eax, FSP_HEADER_GUID_DWORD3
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 0Ch]
+ cmp eax, FSP_HEADER_GUID_DWORD4
+ jnz FspHeaderNotFound
+
+ add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
+
+ ; Check the section type as raw section
+ mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
+ cmp al, 019h
+ jnz FspHeaderNotFound
+
+ add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
+ jmp FspHeaderFound
+
+FspHeaderNotFound:
+ jmp $
+
+FspHeaderFound:
+ ; Get the fsp TempRamInit Api address
+ mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
+ add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
+
+ ; Setup the hardcode stack
+ mov rsp, TempRamInitStack ; move return address to rsp
+ mov rcx, ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams
+
+ ; Call the fsp TempRamInit Api
+ jmp rax
+
+TempRamInitDone:
+ mov rbx, 0800000000000000Eh
+ cmp rax, rbx ; Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
+ je CallSecFspInit ; If microcode not found, don't hang, but continue.
+
+ test rax, rax ; Check if EFI_SUCCESS returned.
+ jnz FspApiFailed
+
+CallSecFspInit:
+#endif
+
+ ; RDX: start of range
+ ; R8: end of range
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ push rax
+ mov rax, ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
+ sub edx, dword [rax] ; TemporaryRam for FSP
+ pop rax
+#endif
+
+ mov r8, rdx
+ mov rdx, rcx
+ xor ecx, ecx ; zero - no Hob List Yet
+ mov rsp, r8
+
+ ;
+ ; Per X64 calling convention, make sure RSP is 16-byte aligned.
+ ;
+ mov rax, rsp
+ and rax, 0fh
+ sub rsp, rax
+
+ call ASM_PFX(CallPeiCoreEntryPoint)
+
+FspApiFailed:
+ jmp $
+
+#if FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 0
+align 10h
+TempRamInitStack:
+ DQ TempRamInitDone
+#endif
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
new file mode 100644
index 0000000000..21010bf4ef
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
@@ -0,0 +1,72 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Abstract:
+;
+; Switch the stack from temporary memory to permanent memory.
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; SecSwitchStack (
+; UINT32 TemporaryMemoryBase,
+; UINT32 PermanentMemoryBase
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SecSwitchStack)
+ASM_PFX(SecSwitchStack):
+ ;
+ ; Save four register: rax, rbx, rcx, rdx
+ ;
+ push rax
+ push rbx
+ push rcx
+ push rdx
+
+ ;
+ ; !!CAUTION!! this function address's is pushed into stack after
+ ; migration of whole temporary memory, so need save it to permanent
+ ; memory at first!
+ ;
+
+ mov rbx, rcx ; Save the first parameter
+ mov rcx, rdx ; Save the second parameter
+
+ ;
+ ; Save this function's return address into permanent memory at first.
+ ; Then, Fixup the esp point to permanent memory
+ ;
+ mov rax, rsp
+ sub rax, rbx
+ add rax, rcx
+ mov rdx, qword [rsp] ; copy pushed register's value to permanent memory
+ mov qword [rax], rdx
+ mov rdx, qword [rsp + 8]
+ mov qword [rax + 8], rdx
+ mov rdx, qword [rsp + 16]
+ mov qword [rax + 16], rdx
+ mov rdx, qword [rsp + 24]
+ mov qword [rax + 24], rdx
+ mov rdx, qword [rsp + 32] ; Update this function's return address into permanent memory
+ mov qword [rax + 32], rdx
+ mov rsp, rax ; From now, rsp is pointed to permanent memory
+
+ ;
+ ; Fixup the rbp point to permanent memory
+ ;
+ mov rax, rbp
+ sub rax, rbx
+ add rax, rcx
+ mov rbp, rax ; From now, rbp is pointed to permanent memory
+
+ pop rdx
+ pop rcx
+ pop rbx
+ pop rax
+ ret
+
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/MinPlatformPkg/Include/Fsp.h
similarity index 79%
rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
rename to Platform/Intel/MinPlatformPkg/Include/Fsp.h
index 9f6cdcf476..319e1e3372 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
+++ b/Platform/Intel/MinPlatformPkg/Include/Fsp.h
@@ -1,7 +1,7 @@
/** @file
Fsp related definitions
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -36,7 +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Fsp Header
//
-#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
-#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
+#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
+#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
#endif
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
index a14c6b2db5..74e1bce87f 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -6,7 +6,7 @@
# INF files to generate AutoGen.c and AutoGen.h files
# for the build infrastructure.
#
-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.<BR>
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -393,6 +393,27 @@
#
gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE|BOOLEAN|0xF00000A8
+ ## Reset Vector in FSP
+ # FALSE: Reset Vector is in FSP Wrapper
+ # TRUE: Reset Vector is in FSP - This is only supported in X64
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp|FALSE|BOOLEAN|0xF00000A9
+
+ ## BFV Location for Reset Vector in FSP
+ # The default of BFV Location for Reset Vector in FSP is 0x00000000FFFF0000.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp|0x00000000FFFF0000|UINT64|0xF00000AA
+
+ ## FSP-T UPD Header Revision
+ # The default of FSP-T UPD Header Revision is 0.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision|0x0|UINT8|0xF00000AB
+
+ ## FSP-T ARCH UPD Revision
+ # The default of FSP-T ARCH UPD Revision is 0.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision|0x0|UINT8|0xF00000AC
+
[PcdsFeatureFlag]
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE|BOOLEAN|0xF00000A1
--
2.40.1.windows.1
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* Re: [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
2024-01-31 2:14 [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64 Kuo, Ted
@ 2024-02-01 0:10 ` Nate DeSimone
2024-02-01 0:14 ` Nate DeSimone
1 sibling, 0 replies; 3+ messages in thread
From: Nate DeSimone @ 2024-02-01 0:10 UTC (permalink / raw)
To: Kuo, Ted, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chiu, Chasel, Dong, Eric, S, Ashraf Ali,
Duggapu, Chinni B, Liming Gao
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> -----Original Message-----
> From: Kuo, Ted <ted.kuo@intel.com>
> Sent: Tuesday, January 30, 2024 6:15 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Dong, Eric <eric.dong@intel.com>; S,
> Ashraf Ali <ashraf.ali.s@intel.com>; Duggapu, Chinni B
> <chinni.b.duggapu@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>
> Subject: [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support
> SecFspWrapperPlatformSecLib in X64
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=4623
> 1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
> 2.Made changes in common files to support both IA32 and X64.
> 3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
> - PcdFspWrapperResetVectorInFsp
> - PcdFspWrapperBfvforResetVectorInFsp
> - PcdFsptUpdHeaderRevision
> - PcdFsptArchUpdRevision
>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Signed-off-by: Ted Kuo <ted.kuo@intel.com>
> ---
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++-
> .../Ia32/SecEntry.nasm | 4 +-
> .../SecFspWrapperPlatformSecLib.inf | 12 +-
> .../SecGetPerformance.c | 11 +-
> .../SecPlatformInformation.c | 8 +-
> .../SecRamInitData.c | 77 +++++--
> .../X64/PeiCoreEntry.nasm | 207 ++++++++++++++++++
> .../X64/SecEntry.nasm | 199 +++++++++++++++++
> .../X64/Stack.nasm | 72 ++++++
> .../Ia32 => Include}/Fsp.h | 6 +-
> .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 23 +-
> 11 files changed, 612 insertions(+), 32 deletions(-) create mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/X64/PeiCoreEntry.nasm
> create mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/X64/SecEntry.nasm
> create mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/X64/Stack.nasm
> rename
> Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32 => Include}/Fsp.h (79%)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/FsptCoreUpd.h
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/FsptCoreUpd.h
> index 7c0f605b92..24c18f25b8 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/FsptCoreUpd.h
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/FsptCoreUpd.h
> @@ -1,6 +1,6 @@
> /** @file -Copyright (c) 2017, Intel Corporation. All rights
> reserved.<BR>+Copyright (c) 2017 - 2024, Intel Corporation. All rights
> reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6
> +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #pragma pack(1) +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1 /** Fsp T
> Core UPD **/ typedef struct {@@ -34,6 +35,28 @@ typedef struct {
> **/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#else+/** Fsp T
> Core UPD+**/+typedef struct {++/** Offset 0x0040+**/+
> EFI_PHYSICAL_ADDRESS MicrocodeRegionBase;++/** Offset 0x0048+**/+
> UINT64 MicrocodeRegionSize;++/** Offset 0x0050+**/+
> EFI_PHYSICAL_ADDRESS CodeRegionBase;++/** Offset 0x0058+**/+
> UINT64 CodeRegionSize;+} FSPT_CORE_UPD;+#endif #pragma
> pack() diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.nasm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/SecEntry.nasm
> index 7f6d771e41..0b3f343991 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.nasm
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/Ia32/SecEntry.nasm
> @@ -1,6 +1,6 @@
> ;------------------------------------------------------------------------------ ;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+; Copyright (c)
> 2019 - 2024, Intel Corporation. All rights reserved.<BR> ; SPDX-License-
> Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@ ; ;------
> ------------------------------------------------------------------------ -#include
> "Fsp.h"+#include <Fsp.h> SECTION .text diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecFspWrapperPlatformSecLib.inf
> index 2e0d67eae4..e85243c6e3 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -1,7 +1,7 @@
> ## @file # Provide FSP wrapper platform sec related function. #-# Copyright
> (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>+# Copyright (c)
> 2017 - 2024, Intel Corporation. All rights reserved.<BR> # # SPDX-License-
> Identifier: BSD-2-Clause-Patent #@@ -47,7 +47,11 @@
> Ia32/SecEntry.nasm Ia32/PeiCoreEntry.nasm Ia32/Stack.nasm-
> Ia32/Fsp.h++[Sources.X64]+ X64/SecEntry.nasm+ X64/PeiCoreEntry.nasm+
> X64/Stack.nasm
> ###################################################################
> ############# #@@ -96,3 +100,7 @@
> gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ##
> CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> ## CONSUMES
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ##
> CONSUMES+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp ##
> CONSUMES+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp ##
> CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision
> ## CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision
> ## CONSUMESdiff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecGetPerformance.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecGetPerformance.c
> index ac2deeabec..1699bd9710 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecGetPerformance.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecGetPerformance.c
> @@ -1,7 +1,7 @@
> /** @file Sample to provide SecGetPerformance function. -Copyright (c)
> 2017 - 2019, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 -
> 2024, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-
> 2-Clause-Patent **/@@ -58,6 +58,7 @@ SecGetPerformance (
> if (EFI_ERROR (Status)) { return EFI_NOT_FOUND; }+ // // |--------------|
> <- TopOfTemporaryRam - BL // | List Ptr |@@ -77,12 +78,12 @@
> SecGetPerformance (
> // | TSC[31:00] | // |--------------| //- TopOfTemporaryRam = (UINTN)
> TopOfTemporaryRamPpi - sizeof (UINT32);- TopOfTemporaryRam -= sizeof
> (UINT32) * 2;- Count = *(UINT32 *)(TopOfTemporaryRam - sizeof
> (UINT32));+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof
> (UINTN);+ TopOfTemporaryRam -= sizeof(UINTN) * 2;+ Count =
> *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32)); Size =
> Count * sizeof (UINT32); - Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof
> (UINT32) - Size - sizeof (UINT32) * 2);+ Ticker = *(UINT64 *) (UINTN)
> (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT64));
> Performance->ResetEnd = GetTimeInNanoSecond (Ticker); return
> EFI_SUCCESS;diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecPlatformInformation.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecPlatformInformation.c
> index 24d55ed838..4cbde95c2d 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecPlatformInformation.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecPlatformInformation.c
> @@ -1,7 +1,7 @@
> /** @file Provide SecPlatformInformation function. -Copyright (c) 2017 -
> 2019, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2024,
> Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-
> Clause-Patent **/@@ -59,9 +59,9 @@ SecPlatformInformation (
> // This routine copies the BIST information to the buffer pointed by //
> PlatformInformationRecord for output. //- TopOfTemporaryRam = (UINTN)
> TopOfTemporaryRamPpi - sizeof (UINT32);- TopOfTemporaryRam -= sizeof
> (UINT32) * 2;- Count = *((UINT32 *)(TopOfTemporaryRam - sizeof
> (UINT32)));+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi -
> sizeof (UINTN);+ TopOfTemporaryRam -= sizeof (UINTN) * 2;+ Count =
> *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32))); Size =
> Count * sizeof (IA32_HANDOFF_STATUS); if ((*StructureSize) < (UINT64)
> Size) {diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecRamInitData.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecRamInitData.c
> index 355d1e6509..f91c4c1d19 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecRamInitData.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecRamInitData.c
> @@ -1,7 +1,7 @@
> /** @file Provide TempRamInitParams data. -Copyright (c) 2017 - 2021,
> Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2024, Intel
> Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-
> Patent **/@@ -10,27 +10,76 @@ SPDX-License-Identifier: BSD-2-Clause-
> Patent
> #include <FspEas.h> #include "FsptCoreUpd.h" +#if defined (MDE_CPU_IA32)
> && FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 1+#error
> "PcdFspWrapperResetVectorInFsp == TRUE only supported for X64
> builds"+#endif+ typedef struct { FSP_UPD_HEADER FspUpdHeader;+#if
> FixedPcdGet8 (PcdFsptArchUpdRevision) == 1+ FSPT_ARCH_UPD
> FsptArchUpd;+#elif FixedPcdGet8 (PcdFsptArchUpdRevision) == 2+
> FSPT_ARCH2_UPD FsptArchUpd;+#endif FSPT_CORE_UPD FsptCoreUpd;-
> } FSPT_UPD_CORE_DATA;+ UINT16 UpdTerminator;+} FSPT_UPD_DATA;
> -GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA
> FsptUpdDataPtr = {+GLOBAL_REMOVE_IF_UNREFERENCED CONST
> FSPT_UPD_DATA FsptUpdDataPtr = {+ {+ 0x4450555F54505346,
> // FSP-T UPD Header Signature - FSPT_UPD+ FixedPcdGet8
> (PcdFsptUpdHeaderRevision), // FSP-T UPD Header Revision+ {
> // Reserved[23]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00,+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+
> 0x00, 0x00, 0x00+ }+ },+#if FixedPcdGet8 (PcdFsptArchUpdRevision) == 1+
> {+ 0x01, // FSP-T ARCH UPD Revision+ {
> // Reserved[3]+ 0x00, 0x00, 0x00+ },+ 0x00000020,
> // Length of FSP-T ARCH UPD+ 0, //
> FspDebugHandler+ { // Reserved1[20]+
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00+ }+ },+#elif FixedPcdGet8
> (PcdFsptArchUpdRevision) == 2 {- 0x4450555F54505346,- 0x00,- {
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00+ 0x02, // FSP-T
> ARCH2 UPD Revision+ { // Reserved[3]+
> 0x00, 0x00, 0x00+ },+ 0x00000020, // Length of
> FSP-T ARCH2 UPD+ 0, // FspDebugHandler+ {
> // Reserved1[16]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00,+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } },+#endif+#if FixedPcdGet8
> (PcdFsptArchUpdRevision) <= 1 {- FixedPcdGet32
> (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv),-
> FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32
> (PcdMicrocodeOffsetInFv),- 0, // Set CodeRegionBase as 0, so that
> caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will
> be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),- { 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ FixedPcdGet32
> (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv), //
> MicrocodeRegionBase+ FixedPcdGet32 (PcdFlashFvMicrocodeSize) -
> FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionSize+ 0, // Set
> CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ?
> LLCSize : CodeRegionSize) will be used.+ FixedPcdGet32
> (PcdFlashCodeCacheSize), // CodeRegionSize+ {
> // Reserved[16]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }- }+ },+#else+ {+
> FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32
> (PcdMicrocodeOffsetInFv), // MicrocodeRegionBase+ FixedPcdGet32
> (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv), //
> MicrocodeRegionSize+ 0, // Set CodeRegionBase as 0, so that caching will be
> 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.+
> FixedPcdGet32 (PcdFlashCodeCacheSize) //
> CodeRegionSize+ },+#endif+ 0x55AA };-diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/X64/PeiCoreEntry.nasm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/X64/PeiCoreEntry.nasm
> new file mode 100644
> index 0000000000..08933c6d37
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/X64/PeiCoreEntry.nasm
> @@ -0,0 +1,207 @@
> +;------------------------------------------------------------------------------+;+;
> Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+; SPDX-License-
> Identifier: BSD-2-Clause-Patent+;+; Module Name:+;+; PeiCoreEntry.nasm+;+;
> Abstract:+;+; Find and call SecStartup+;+;--------------------------------------------
> ----------------------------------++SECTION .text++extern
> ASM_PFX(SecStartup)+extern ASM_PFX(PlatformInit)+extern
> ASM_PFX(PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))++;--------------
> ---------------------------------------------------------------+; Macro:
> PUSHA_64+;+; Description: Saves all registers on stack+;+; Input:
> None+;+; Output: None+;-----------------------------------------------------------
> ------------------+%macro PUSHA_64 0+ push r8+ push r9+ push r10+
> push r11+ push r12+ push r13+ push r14+ push r15+ push rax+
> push rcx+ push rdx+ push rbx+ push rsp+ push rbp+ push rsi+ push
> rdi+%endmacro++;-----------------------------------------------------------------------
> ------+; Macro: POPA_64+;+; Description: Restores all registers from
> stack+;+; Input: None+;+; Output: None+;-----------------------------------
> ------------------------------------------+%macro POPA_64 0+ pop rdi+ pop
> rsi+ pop rbp+ pop rsp+ pop rbx+ pop rdx+ pop rcx+ pop rax+ pop
> r15+ pop r14+ pop r13+ pop r12+ pop r11+ pop r10+ pop r9+ pop
> r8+%endmacro++global
> ASM_PFX(CallPeiCoreEntryPoint)+ASM_PFX(CallPeiCoreEntryPoint):+ ;+ ; Per
> X64 calling convention, make sure RSP is 16-byte aligned.+ ;+ mov rax, rsp+
> and rax, 0fh+ sub rsp, rax++ ;+ ; Platform init+ ;+ PUSHA_64+ sub rsp,
> 20h+ call ASM_PFX(PlatformInit)+ add rsp, 20h+ POPA_64++ ;+ ; Set
> stack top pointer+ ;+ mov rsp, r8++ ;+ ; Push the hob list pointer+ ;+ push
> rcx++ ;+ ; RBP holds start of BFV passed from Vtf0. Save it to r10.+ ;+ mov
> r10, rbp++ ;+ ; Save the value+ ; RDX: start of range+ ; r8: end of range+ ;+
> mov rbp, rsp+ push rdx+ push r8+ mov r14, rdx+ mov r15, r8++ ;+
> ; Push processor count to stack first, then BIST status (AP then BSP)+ ;+ mov
> eax, 1+ cpuid+ shr ebx, 16+ and ebx, 0000000FFh+ cmp bl, 1+ jae
> PushProcessorCount++ ;+ ; Some processors report 0 logical processors.
> Effectively 0 = 1.+ ; So we fix up the processor count+ ;+ inc
> ebx++PushProcessorCount:+ sub rsp, 4+ mov rdi, rsp+ mov DWORD
> [rdi], ebx++ ;+ ; We need to implement a long-term solution for BIST capture.
> For now, we just copy BSP BIST+ ; for all processor threads+ ;+ xor ecx, ecx+
> mov cl, bl+PushBist:+ sub rsp, 4+ mov rdi, rsp+ movd eax, mm0+
> mov DWORD [rdi], eax+ loop PushBist++ ;+ ; FSP saves the timestamp of
> the beginning of firmware execution in mm5.+ ; Get the timestamp from mm5
> and then push to stack.+ ;+ movq rax, mm5+ push rax++ ;+ ; Per X64
> calling convention, make sure RSP is 16-byte aligned.+ ;+ mov rax, rsp+ and
> rax, 0fh+ sub rsp, rax++ ;+ ; Pass entry point of the PEI core+ ;+ mov rdi,
> 0FFFFFFE0h+ mov edi, DWORD [rdi]+ mov r9, rdi++ ;+ ; Pass BFV into the
> PEI Core+ ;+#if FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 1+ ;+ ;
> Reset Vector and initial SEC core (to initialize Temp Ram) is part of FSP-O.+ ;
> Default UefiCpuPkg Reset Vector locates FSP-O as BFV. However the actual+ ;
> SEC core that launches PEI is part of another FV. We need to pass that FV+ ; as
> BFV to PEI core.+ ;+ mov r8, ASM_PFX (PcdGet64
> (PcdFspWrapperBfvforResetVectorInFsp))+ mov rcx, QWORD[r8]+ mov
> r8, rcx+#else+ mov r8, r10+#endif++ ;+ ; Pass stack size into the PEI Core+
> ;+ mov rcx, r15 ; Start of TempRam+ mov rdx, r14 ; End of TempRam++
> sub rcx, rdx ; Size of TempRam++ ;+ ; Pass Control into the PEI Core+ ;+ sub
> rsp, 20h+ call ASM_PFX(SecStartup)+diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/X64/SecEntry.nasm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/X64/SecEntry.nasm
> new file mode 100644
> index 0000000000..2618860366
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/X64/SecEntry.nasm
> @@ -0,0 +1,199 @@
> +;------------------------------------------------------------------------------+;+;
> Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+; SPDX-License-
> Identifier: BSD-2-Clause-Patent+; Module Name:+;+; SecEntry.nasm+;+;
> Abstract:+;+; This is the code that passes control to PEI core.+;+;-----------------
> -------------------------------------------------------------++#include
> <Fsp.h>++SECTION .text++extern ASM_PFX(CallPeiCoreEntryPoint)+extern
> ASM_PFX(FsptUpdDataPtr)+; Pcds+extern ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))+extern ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))++;--------------------------------------------------------------
> --------------+;+; Procedure: _ModuleEntryPoint+;+; Input: None+;+;
> Output: None+;+; Destroys: Assume all registers+;+; Description:+;+; Call
> TempRamInit API from FSP binary if reset vector in FSP is not supproted.+;
> After TempRamInit done, pass control to PEI core.+;+; Return: None+;+;
> MMX Usage:+; MM0 = BIST State+;+;------------------------------------------
> ----------------------------------++BITS 64+align 16+global
> ASM_PFX(_ModuleEntryPoint)+ASM_PFX(_ModuleEntryPoint):+#if
> FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 1+ push rax+ mov
> rax, ASM_PFX(FsptUpdDataPtr) ; This is dummy code to include
> TempRamInitParams in SecCore for FSP-O.+ pop rax+#else+ fninit
> ; clear any pending Floating point exceptions+ ;+ ; Store the BIST value in
> mm0+ ;+ movd mm0, eax+ cli++ ;+ ; Trigger warm reset if PCIEBAR register
> is not in reset/default value state+ ;+ mov eax, 80000060h ;
> PCIEX_BAR_REG B0:D0:F0:R60+ mov dx, 0CF8h+ out dx, eax+ mov dx,
> 0CFCh+ in eax, dx+ cmp eax, 0+ jz NotWarmStart++ ;+ ; @note Issue
> warm reset, since if CPU only reset is issued not all MSRs are restored to their
> defaults+ ;+ mov dx, 0CF9h+ mov al, 06h+ out dx, al+ jmp
> $++NotWarmStart:++ ; Find the fsp info header+ mov rax,
> ASM_PFX(PcdGet32 (PcdFsptBaseAddress))+ mov edi, [eax]++ mov eax,
> dword [edi + FVH_SIGINATURE_OFFSET]+ cmp eax,
> FVH_SIGINATURE_VALID_VALUE+ jnz FspHeaderNotFound++ xor eax,
> eax+ mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]+ cmp ax, 0+
> jnz FspFvExtHeaderExist++ xor eax, eax+ mov ax, word [edi +
> FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header+ add edi, eax+ jmp
> FspCheckFfsHeader++FspFvExtHeaderExist:+ add edi, eax+ mov eax,
> dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header+ add
> edi, eax++ ; Round up to 8 byte alignment+ mov eax, edi+ and al, 07h+ jz
> FspCheckFfsHeader++ and edi, 0FFFFFFF8h+ add edi,
> 08h++FspCheckFfsHeader:+ ; Check the ffs guid+ mov eax, dword [edi]+
> cmp eax, FSP_HEADER_GUID_DWORD1+ jnz FspHeaderNotFound++ mov
> eax, dword [edi + 4]+ cmp eax, FSP_HEADER_GUID_DWORD2+ jnz
> FspHeaderNotFound++ mov eax, dword [edi + 8]+ cmp eax,
> FSP_HEADER_GUID_DWORD3+ jnz FspHeaderNotFound++ mov eax,
> dword [edi + 0Ch]+ cmp eax, FSP_HEADER_GUID_DWORD4+ jnz
> FspHeaderNotFound++ add edi, FFS_HEADER_SIZE_VALUE ; Bypass the
> ffs header++ ; Check the section type as raw section+ mov al, byte [edi +
> SECTION_HEADER_TYPE_OFFSET]+ cmp al, 019h+ jnz
> FspHeaderNotFound++ add edi, RAW_SECTION_HEADER_SIZE_VALUE ;
> Bypass the section header+ jmp FspHeaderFound++FspHeaderNotFound:+
> jmp $++FspHeaderFound:+ ; Get the fsp TempRamInit Api address+ mov
> eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]+ add eax, dword [edi
> + FSP_HEADER_TEMPRAMINIT_OFFSET]++ ; Setup the hardcode stack+ mov
> rsp, TempRamInitStack ; move return address to rsp+ mov rcx,
> ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams++ ; Call the fsp
> TempRamInit Api+ jmp rax++TempRamInitDone:+ mov rbx,
> 0800000000000000Eh+ cmp rax, rbx ; Check if EFI_NOT_FOUND
> returned. Error code for Microcode Update not found.+ je CallSecFspInit
> ; If microcode not found, don't hang, but continue.++ test rax, rax ;
> Check if EFI_SUCCESS returned.+ jnz
> FspApiFailed++CallSecFspInit:+#endif++ ; RDX: start of range+ ; R8: end of
> range+#if FixedPcdGet8(PcdFspModeSelection) == 1+ push rax+ mov rax,
> ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))+ sub edx, dword [rax]
> ; TemporaryRam for FSP+ pop rax+#endif++ mov r8, rdx+ mov rdx, rcx+
> xor ecx, ecx ; zero - no Hob List Yet+ mov rsp, r8++ ;+ ; Per X64
> calling convention, make sure RSP is 16-byte aligned.+ ;+ mov rax, rsp+ and
> rax, 0fh+ sub rsp, rax++ call
> ASM_PFX(CallPeiCoreEntryPoint)++FspApiFailed:+ jmp $++#if
> FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 0+align
> 10h+TempRamInitStack:+ DQ TempRamInitDone+#endifdiff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/X64/Stack.nasm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/X64/Stack.nasm
> new file mode 100644
> index 0000000000..21010bf4ef
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/X64/Stack.nasm
> @@ -0,0 +1,72 @@
> +;------------------------------------------------------------------------------+;+;
> Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+; SPDX-License-
> Identifier: BSD-2-Clause-Patent+; Abstract:+;+; Switch the stack from
> temporary memory to permanent memory.+;+;-------------------------------------
> -----------------------------------------++ SECTION .text++;---------------------------
> ---------------------------------------------------+; VOID+; EFIAPI+; SecSwitchStack
> (+; UINT32 TemporaryMemoryBase,+; UINT32 PermanentMemoryBase+;
> );+;------------------------------------------------------------------------------+global
> ASM_PFX(SecSwitchStack)+ASM_PFX(SecSwitchStack):+ ;+ ; Save four
> register: rax, rbx, rcx, rdx+ ;+ push rax+ push rbx+ push rcx+ push
> rdx++ ;+ ; !!CAUTION!! this function address's is pushed into stack after+ ;
> migration of whole temporary memory, so need save it to permanent+ ;
> memory at first!+ ;++ mov rbx, rcx ; Save the first parameter+
> mov rcx, rdx ; Save the second parameter++ ;+ ; Save this
> function's return address into permanent memory at first.+ ; Then, Fixup the
> esp point to permanent memory+ ;+ mov rax, rsp+ sub rax, rbx+ add
> rax, rcx+ mov rdx, qword [rsp] ; copy pushed register's value to
> permanent memory+ mov qword [rax], rdx+ mov rdx, qword [rsp + 8]+
> mov qword [rax + 8], rdx+ mov rdx, qword [rsp + 16]+ mov qword [rax +
> 16], rdx+ mov rdx, qword [rsp + 24]+ mov qword [rax + 24], rdx+ mov
> rdx, qword [rsp + 32] ; Update this function's return address into permanent
> memory+ mov qword [rax + 32], rdx+ mov rsp, rax ; From now,
> rsp is pointed to permanent memory++ ;+ ; Fixup the rbp point to
> permanent memory+ ;+ mov rax, rbp+ sub rax, rbx+ add rax, rcx+
> mov rbp, rax ; From now, rbp is pointed to permanent memory++
> pop rdx+ pop rcx+ pop rbx+ pop rax+ ret+diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Fsp.h b/Platform/Intel/MinPlatformPkg/Include/Fsp.h
> similarity index 79%
> rename from
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/Ia32/Fsp.h
> rename to Platform/Intel/MinPlatformPkg/Include/Fsp.h
> index 9f6cdcf476..319e1e3372 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Fsp.h
> +++ b/Platform/Intel/MinPlatformPkg/Include/Fsp.h
> @@ -1,7 +1,7 @@
> /** @file Fsp related definitions -Copyright (c) 2017, Intel Corporation. All
> rights reserved.<BR>+Copyright (c) 2017 - 2024, Intel Corporation. All rights
> reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -36,7
> +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> // // Fsp Header //-#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C-
> #define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30+#define
> FSP_HEADER_IMAGEBASE_OFFSET 0x1C+#define
> FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 #endifdiff --git
> a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> index a14c6b2db5..74e1bce87f 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> @@ -6,7 +6,7 @@
> # INF files to generate AutoGen.c and AutoGen.h files # for the build
> infrastructure. #-# Copyright (c) 2017 - 2021, Intel Corporation. All rights
> reserved.<BR>+# Copyright (c) 2017 - 2024, Intel Corporation. All rights
> reserved.<BR> # Copyright (C) 2023 Advanced Micro Devices, Inc. All rights
> reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent@@ -393,6
> +393,27 @@
> #
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
> |BOOLEAN|0xF00000A8 + ## Reset Vector in FSP+ # FALSE: Reset Vector is in
> FSP Wrapper+ # TRUE: Reset Vector is in FSP - This is only supported in X64+
> #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp|FALSE|B
> OOLEAN|0xF00000A9++ ## BFV Location for Reset Vector in FSP+ # The
> default of BFV Location for Reset Vector in FSP is 0x00000000FFFF0000.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp|0x
> 00000000FFFF0000|UINT64|0xF00000AA++ ## FSP-T UPD Header
> Revision+ # The default of FSP-T UPD Header Revision is 0.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision|0x0|UINT8|0x
> F00000AB++ ## FSP-T ARCH UPD Revision+ # The default of FSP-T ARCH UPD
> Revision is 0.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision|0x0|UINT8|0xF0
> 0000AC+ [PcdsFeatureFlag]
> gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit
> |FALSE|BOOLEAN|0xF00000A1--
> 2.40.1.windows.1
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* Re: [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
2024-01-31 2:14 [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64 Kuo, Ted
2024-02-01 0:10 ` Nate DeSimone
@ 2024-02-01 0:14 ` Nate DeSimone
1 sibling, 0 replies; 3+ messages in thread
From: Nate DeSimone @ 2024-02-01 0:14 UTC (permalink / raw)
To: Kuo, Ted, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chiu, Chasel, Dong, Eric, S, Ashraf Ali,
Duggapu, Chinni B, Liming Gao
Pushed as 03a69eb
> -----Original Message-----
> From: Kuo, Ted <ted.kuo@intel.com>
> Sent: Tuesday, January 30, 2024 6:15 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Dong, Eric <eric.dong@intel.com>; S,
> Ashraf Ali <ashraf.ali.s@intel.com>; Duggapu, Chinni B
> <chinni.b.duggapu@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>
> Subject: [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support
> SecFspWrapperPlatformSecLib in X64
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=4623
> 1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
> 2.Made changes in common files to support both IA32 and X64.
> 3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
> - PcdFspWrapperResetVectorInFsp
> - PcdFspWrapperBfvforResetVectorInFsp
> - PcdFsptUpdHeaderRevision
> - PcdFsptArchUpdRevision
>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Signed-off-by: Ted Kuo <ted.kuo@intel.com>
> ---
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++-
> .../Ia32/SecEntry.nasm | 4 +-
> .../SecFspWrapperPlatformSecLib.inf | 12 +-
> .../SecGetPerformance.c | 11 +-
> .../SecPlatformInformation.c | 8 +-
> .../SecRamInitData.c | 77 +++++--
> .../X64/PeiCoreEntry.nasm | 207 ++++++++++++++++++
> .../X64/SecEntry.nasm | 199 +++++++++++++++++
> .../X64/Stack.nasm | 72 ++++++
> .../Ia32 => Include}/Fsp.h | 6 +-
> .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 23 +-
> 11 files changed, 612 insertions(+), 32 deletions(-) create mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/X64/PeiCoreEntry.nasm
> create mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/X64/SecEntry.nasm
> create mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/X64/Stack.nasm
> rename
> Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32 => Include}/Fsp.h (79%)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/FsptCoreUpd.h
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/FsptCoreUpd.h
> index 7c0f605b92..24c18f25b8 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/FsptCoreUpd.h
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/FsptCoreUpd.h
> @@ -1,6 +1,6 @@
> /** @file -Copyright (c) 2017, Intel Corporation. All rights
> reserved.<BR>+Copyright (c) 2017 - 2024, Intel Corporation. All rights
> reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6
> +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #pragma pack(1) +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1 /** Fsp T
> Core UPD **/ typedef struct {@@ -34,6 +35,28 @@ typedef struct {
> **/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#else+/** Fsp T
> Core UPD+**/+typedef struct {++/** Offset 0x0040+**/+
> EFI_PHYSICAL_ADDRESS MicrocodeRegionBase;++/** Offset 0x0048+**/+
> UINT64 MicrocodeRegionSize;++/** Offset 0x0050+**/+
> EFI_PHYSICAL_ADDRESS CodeRegionBase;++/** Offset 0x0058+**/+
> UINT64 CodeRegionSize;+} FSPT_CORE_UPD;+#endif #pragma
> pack() diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.nasm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/SecEntry.nasm
> index 7f6d771e41..0b3f343991 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.nasm
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/Ia32/SecEntry.nasm
> @@ -1,6 +1,6 @@
> ;------------------------------------------------------------------------------ ;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+; Copyright (c)
> 2019 - 2024, Intel Corporation. All rights reserved.<BR> ; SPDX-License-
> Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@ ; ;------
> ------------------------------------------------------------------------ -#include
> "Fsp.h"+#include <Fsp.h> SECTION .text diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecFspWrapperPlatformSecLib.inf
> index 2e0d67eae4..e85243c6e3 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -1,7 +1,7 @@
> ## @file # Provide FSP wrapper platform sec related function. #-# Copyright
> (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>+# Copyright (c)
> 2017 - 2024, Intel Corporation. All rights reserved.<BR> # # SPDX-License-
> Identifier: BSD-2-Clause-Patent #@@ -47,7 +47,11 @@
> Ia32/SecEntry.nasm Ia32/PeiCoreEntry.nasm Ia32/Stack.nasm-
> Ia32/Fsp.h++[Sources.X64]+ X64/SecEntry.nasm+ X64/PeiCoreEntry.nasm+
> X64/Stack.nasm
> ###################################################################
> ############# #@@ -96,3 +100,7 @@
> gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ##
> CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> ## CONSUMES
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ##
> CONSUMES+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp ##
> CONSUMES+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp ##
> CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision
> ## CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision
> ## CONSUMESdiff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecGetPerformance.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecGetPerformance.c
> index ac2deeabec..1699bd9710 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecGetPerformance.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecGetPerformance.c
> @@ -1,7 +1,7 @@
> /** @file Sample to provide SecGetPerformance function. -Copyright (c)
> 2017 - 2019, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 -
> 2024, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-
> 2-Clause-Patent **/@@ -58,6 +58,7 @@ SecGetPerformance (
> if (EFI_ERROR (Status)) { return EFI_NOT_FOUND; }+ // // |--------------|
> <- TopOfTemporaryRam - BL // | List Ptr |@@ -77,12 +78,12 @@
> SecGetPerformance (
> // | TSC[31:00] | // |--------------| //- TopOfTemporaryRam = (UINTN)
> TopOfTemporaryRamPpi - sizeof (UINT32);- TopOfTemporaryRam -= sizeof
> (UINT32) * 2;- Count = *(UINT32 *)(TopOfTemporaryRam - sizeof
> (UINT32));+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof
> (UINTN);+ TopOfTemporaryRam -= sizeof(UINTN) * 2;+ Count =
> *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32)); Size =
> Count * sizeof (UINT32); - Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof
> (UINT32) - Size - sizeof (UINT32) * 2);+ Ticker = *(UINT64 *) (UINTN)
> (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT64));
> Performance->ResetEnd = GetTimeInNanoSecond (Ticker); return
> EFI_SUCCESS;diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecPlatformInformation.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecPlatformInformation.c
> index 24d55ed838..4cbde95c2d 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecPlatformInformation.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecPlatformInformation.c
> @@ -1,7 +1,7 @@
> /** @file Provide SecPlatformInformation function. -Copyright (c) 2017 -
> 2019, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2024,
> Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-
> Clause-Patent **/@@ -59,9 +59,9 @@ SecPlatformInformation (
> // This routine copies the BIST information to the buffer pointed by //
> PlatformInformationRecord for output. //- TopOfTemporaryRam = (UINTN)
> TopOfTemporaryRamPpi - sizeof (UINT32);- TopOfTemporaryRam -= sizeof
> (UINT32) * 2;- Count = *((UINT32 *)(TopOfTemporaryRam - sizeof
> (UINT32)));+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi -
> sizeof (UINTN);+ TopOfTemporaryRam -= sizeof (UINTN) * 2;+ Count =
> *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32))); Size =
> Count * sizeof (IA32_HANDOFF_STATUS); if ((*StructureSize) < (UINT64)
> Size) {diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecRamInitData.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecRamInitData.c
> index 355d1e6509..f91c4c1d19 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecRamInitData.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecRamInitData.c
> @@ -1,7 +1,7 @@
> /** @file Provide TempRamInitParams data. -Copyright (c) 2017 - 2021,
> Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2024, Intel
> Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-
> Patent **/@@ -10,27 +10,76 @@ SPDX-License-Identifier: BSD-2-Clause-
> Patent
> #include <FspEas.h> #include "FsptCoreUpd.h" +#if defined (MDE_CPU_IA32)
> && FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 1+#error
> "PcdFspWrapperResetVectorInFsp == TRUE only supported for X64
> builds"+#endif+ typedef struct { FSP_UPD_HEADER FspUpdHeader;+#if
> FixedPcdGet8 (PcdFsptArchUpdRevision) == 1+ FSPT_ARCH_UPD
> FsptArchUpd;+#elif FixedPcdGet8 (PcdFsptArchUpdRevision) == 2+
> FSPT_ARCH2_UPD FsptArchUpd;+#endif FSPT_CORE_UPD FsptCoreUpd;-
> } FSPT_UPD_CORE_DATA;+ UINT16 UpdTerminator;+} FSPT_UPD_DATA;
> -GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA
> FsptUpdDataPtr = {+GLOBAL_REMOVE_IF_UNREFERENCED CONST
> FSPT_UPD_DATA FsptUpdDataPtr = {+ {+ 0x4450555F54505346,
> // FSP-T UPD Header Signature - FSPT_UPD+ FixedPcdGet8
> (PcdFsptUpdHeaderRevision), // FSP-T UPD Header Revision+ {
> // Reserved[23]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00,+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+
> 0x00, 0x00, 0x00+ }+ },+#if FixedPcdGet8 (PcdFsptArchUpdRevision) == 1+
> {+ 0x01, // FSP-T ARCH UPD Revision+ {
> // Reserved[3]+ 0x00, 0x00, 0x00+ },+ 0x00000020,
> // Length of FSP-T ARCH UPD+ 0, //
> FspDebugHandler+ { // Reserved1[20]+
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00+ }+ },+#elif FixedPcdGet8
> (PcdFsptArchUpdRevision) == 2 {- 0x4450555F54505346,- 0x00,- {
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00+ 0x02, // FSP-T
> ARCH2 UPD Revision+ { // Reserved[3]+
> 0x00, 0x00, 0x00+ },+ 0x00000020, // Length of
> FSP-T ARCH2 UPD+ 0, // FspDebugHandler+ {
> // Reserved1[16]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00,+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } },+#endif+#if FixedPcdGet8
> (PcdFsptArchUpdRevision) <= 1 {- FixedPcdGet32
> (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv),-
> FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32
> (PcdMicrocodeOffsetInFv),- 0, // Set CodeRegionBase as 0, so that
> caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will
> be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),- { 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ FixedPcdGet32
> (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv), //
> MicrocodeRegionBase+ FixedPcdGet32 (PcdFlashFvMicrocodeSize) -
> FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionSize+ 0, // Set
> CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ?
> LLCSize : CodeRegionSize) will be used.+ FixedPcdGet32
> (PcdFlashCodeCacheSize), // CodeRegionSize+ {
> // Reserved[16]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }- }+ },+#else+ {+
> FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32
> (PcdMicrocodeOffsetInFv), // MicrocodeRegionBase+ FixedPcdGet32
> (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv), //
> MicrocodeRegionSize+ 0, // Set CodeRegionBase as 0, so that caching will be
> 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.+
> FixedPcdGet32 (PcdFlashCodeCacheSize) //
> CodeRegionSize+ },+#endif+ 0x55AA };-diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/X64/PeiCoreEntry.nasm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/X64/PeiCoreEntry.nasm
> new file mode 100644
> index 0000000000..08933c6d37
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/X64/PeiCoreEntry.nasm
> @@ -0,0 +1,207 @@
> +;------------------------------------------------------------------------------+;+;
> Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+; SPDX-License-
> Identifier: BSD-2-Clause-Patent+;+; Module Name:+;+; PeiCoreEntry.nasm+;+;
> Abstract:+;+; Find and call SecStartup+;+;--------------------------------------------
> ----------------------------------++SECTION .text++extern
> ASM_PFX(SecStartup)+extern ASM_PFX(PlatformInit)+extern
> ASM_PFX(PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))++;--------------
> ---------------------------------------------------------------+; Macro:
> PUSHA_64+;+; Description: Saves all registers on stack+;+; Input:
> None+;+; Output: None+;-----------------------------------------------------------
> ------------------+%macro PUSHA_64 0+ push r8+ push r9+ push r10+
> push r11+ push r12+ push r13+ push r14+ push r15+ push rax+
> push rcx+ push rdx+ push rbx+ push rsp+ push rbp+ push rsi+ push
> rdi+%endmacro++;-----------------------------------------------------------------------
> ------+; Macro: POPA_64+;+; Description: Restores all registers from
> stack+;+; Input: None+;+; Output: None+;-----------------------------------
> ------------------------------------------+%macro POPA_64 0+ pop rdi+ pop
> rsi+ pop rbp+ pop rsp+ pop rbx+ pop rdx+ pop rcx+ pop rax+ pop
> r15+ pop r14+ pop r13+ pop r12+ pop r11+ pop r10+ pop r9+ pop
> r8+%endmacro++global
> ASM_PFX(CallPeiCoreEntryPoint)+ASM_PFX(CallPeiCoreEntryPoint):+ ;+ ; Per
> X64 calling convention, make sure RSP is 16-byte aligned.+ ;+ mov rax, rsp+
> and rax, 0fh+ sub rsp, rax++ ;+ ; Platform init+ ;+ PUSHA_64+ sub rsp,
> 20h+ call ASM_PFX(PlatformInit)+ add rsp, 20h+ POPA_64++ ;+ ; Set
> stack top pointer+ ;+ mov rsp, r8++ ;+ ; Push the hob list pointer+ ;+ push
> rcx++ ;+ ; RBP holds start of BFV passed from Vtf0. Save it to r10.+ ;+ mov
> r10, rbp++ ;+ ; Save the value+ ; RDX: start of range+ ; r8: end of range+ ;+
> mov rbp, rsp+ push rdx+ push r8+ mov r14, rdx+ mov r15, r8++ ;+
> ; Push processor count to stack first, then BIST status (AP then BSP)+ ;+ mov
> eax, 1+ cpuid+ shr ebx, 16+ and ebx, 0000000FFh+ cmp bl, 1+ jae
> PushProcessorCount++ ;+ ; Some processors report 0 logical processors.
> Effectively 0 = 1.+ ; So we fix up the processor count+ ;+ inc
> ebx++PushProcessorCount:+ sub rsp, 4+ mov rdi, rsp+ mov DWORD
> [rdi], ebx++ ;+ ; We need to implement a long-term solution for BIST capture.
> For now, we just copy BSP BIST+ ; for all processor threads+ ;+ xor ecx, ecx+
> mov cl, bl+PushBist:+ sub rsp, 4+ mov rdi, rsp+ movd eax, mm0+
> mov DWORD [rdi], eax+ loop PushBist++ ;+ ; FSP saves the timestamp of
> the beginning of firmware execution in mm5.+ ; Get the timestamp from mm5
> and then push to stack.+ ;+ movq rax, mm5+ push rax++ ;+ ; Per X64
> calling convention, make sure RSP is 16-byte aligned.+ ;+ mov rax, rsp+ and
> rax, 0fh+ sub rsp, rax++ ;+ ; Pass entry point of the PEI core+ ;+ mov rdi,
> 0FFFFFFE0h+ mov edi, DWORD [rdi]+ mov r9, rdi++ ;+ ; Pass BFV into the
> PEI Core+ ;+#if FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 1+ ;+ ;
> Reset Vector and initial SEC core (to initialize Temp Ram) is part of FSP-O.+ ;
> Default UefiCpuPkg Reset Vector locates FSP-O as BFV. However the actual+ ;
> SEC core that launches PEI is part of another FV. We need to pass that FV+ ; as
> BFV to PEI core.+ ;+ mov r8, ASM_PFX (PcdGet64
> (PcdFspWrapperBfvforResetVectorInFsp))+ mov rcx, QWORD[r8]+ mov
> r8, rcx+#else+ mov r8, r10+#endif++ ;+ ; Pass stack size into the PEI Core+
> ;+ mov rcx, r15 ; Start of TempRam+ mov rdx, r14 ; End of TempRam++
> sub rcx, rdx ; Size of TempRam++ ;+ ; Pass Control into the PEI Core+ ;+ sub
> rsp, 20h+ call ASM_PFX(SecStartup)+diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/X64/SecEntry.nasm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/X64/SecEntry.nasm
> new file mode 100644
> index 0000000000..2618860366
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/X64/SecEntry.nasm
> @@ -0,0 +1,199 @@
> +;------------------------------------------------------------------------------+;+;
> Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+; SPDX-License-
> Identifier: BSD-2-Clause-Patent+; Module Name:+;+; SecEntry.nasm+;+;
> Abstract:+;+; This is the code that passes control to PEI core.+;+;-----------------
> -------------------------------------------------------------++#include
> <Fsp.h>++SECTION .text++extern ASM_PFX(CallPeiCoreEntryPoint)+extern
> ASM_PFX(FsptUpdDataPtr)+; Pcds+extern ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))+extern ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))++;--------------------------------------------------------------
> --------------+;+; Procedure: _ModuleEntryPoint+;+; Input: None+;+;
> Output: None+;+; Destroys: Assume all registers+;+; Description:+;+; Call
> TempRamInit API from FSP binary if reset vector in FSP is not supproted.+;
> After TempRamInit done, pass control to PEI core.+;+; Return: None+;+;
> MMX Usage:+; MM0 = BIST State+;+;------------------------------------------
> ----------------------------------++BITS 64+align 16+global
> ASM_PFX(_ModuleEntryPoint)+ASM_PFX(_ModuleEntryPoint):+#if
> FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 1+ push rax+ mov
> rax, ASM_PFX(FsptUpdDataPtr) ; This is dummy code to include
> TempRamInitParams in SecCore for FSP-O.+ pop rax+#else+ fninit
> ; clear any pending Floating point exceptions+ ;+ ; Store the BIST value in
> mm0+ ;+ movd mm0, eax+ cli++ ;+ ; Trigger warm reset if PCIEBAR register
> is not in reset/default value state+ ;+ mov eax, 80000060h ;
> PCIEX_BAR_REG B0:D0:F0:R60+ mov dx, 0CF8h+ out dx, eax+ mov dx,
> 0CFCh+ in eax, dx+ cmp eax, 0+ jz NotWarmStart++ ;+ ; @note Issue
> warm reset, since if CPU only reset is issued not all MSRs are restored to their
> defaults+ ;+ mov dx, 0CF9h+ mov al, 06h+ out dx, al+ jmp
> $++NotWarmStart:++ ; Find the fsp info header+ mov rax,
> ASM_PFX(PcdGet32 (PcdFsptBaseAddress))+ mov edi, [eax]++ mov eax,
> dword [edi + FVH_SIGINATURE_OFFSET]+ cmp eax,
> FVH_SIGINATURE_VALID_VALUE+ jnz FspHeaderNotFound++ xor eax,
> eax+ mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]+ cmp ax, 0+
> jnz FspFvExtHeaderExist++ xor eax, eax+ mov ax, word [edi +
> FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header+ add edi, eax+ jmp
> FspCheckFfsHeader++FspFvExtHeaderExist:+ add edi, eax+ mov eax,
> dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header+ add
> edi, eax++ ; Round up to 8 byte alignment+ mov eax, edi+ and al, 07h+ jz
> FspCheckFfsHeader++ and edi, 0FFFFFFF8h+ add edi,
> 08h++FspCheckFfsHeader:+ ; Check the ffs guid+ mov eax, dword [edi]+
> cmp eax, FSP_HEADER_GUID_DWORD1+ jnz FspHeaderNotFound++ mov
> eax, dword [edi + 4]+ cmp eax, FSP_HEADER_GUID_DWORD2+ jnz
> FspHeaderNotFound++ mov eax, dword [edi + 8]+ cmp eax,
> FSP_HEADER_GUID_DWORD3+ jnz FspHeaderNotFound++ mov eax,
> dword [edi + 0Ch]+ cmp eax, FSP_HEADER_GUID_DWORD4+ jnz
> FspHeaderNotFound++ add edi, FFS_HEADER_SIZE_VALUE ; Bypass the
> ffs header++ ; Check the section type as raw section+ mov al, byte [edi +
> SECTION_HEADER_TYPE_OFFSET]+ cmp al, 019h+ jnz
> FspHeaderNotFound++ add edi, RAW_SECTION_HEADER_SIZE_VALUE ;
> Bypass the section header+ jmp FspHeaderFound++FspHeaderNotFound:+
> jmp $++FspHeaderFound:+ ; Get the fsp TempRamInit Api address+ mov
> eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]+ add eax, dword [edi
> + FSP_HEADER_TEMPRAMINIT_OFFSET]++ ; Setup the hardcode stack+ mov
> rsp, TempRamInitStack ; move return address to rsp+ mov rcx,
> ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams++ ; Call the fsp
> TempRamInit Api+ jmp rax++TempRamInitDone:+ mov rbx,
> 0800000000000000Eh+ cmp rax, rbx ; Check if EFI_NOT_FOUND
> returned. Error code for Microcode Update not found.+ je CallSecFspInit
> ; If microcode not found, don't hang, but continue.++ test rax, rax ;
> Check if EFI_SUCCESS returned.+ jnz
> FspApiFailed++CallSecFspInit:+#endif++ ; RDX: start of range+ ; R8: end of
> range+#if FixedPcdGet8(PcdFspModeSelection) == 1+ push rax+ mov rax,
> ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))+ sub edx, dword [rax]
> ; TemporaryRam for FSP+ pop rax+#endif++ mov r8, rdx+ mov rdx, rcx+
> xor ecx, ecx ; zero - no Hob List Yet+ mov rsp, r8++ ;+ ; Per X64
> calling convention, make sure RSP is 16-byte aligned.+ ;+ mov rax, rsp+ and
> rax, 0fh+ sub rsp, rax++ call
> ASM_PFX(CallPeiCoreEntryPoint)++FspApiFailed:+ jmp $++#if
> FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) == 0+align
> 10h+TempRamInitStack:+ DQ TempRamInitDone+#endifdiff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/X64/Stack.nasm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/X64/Stack.nasm
> new file mode 100644
> index 0000000000..21010bf4ef
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/X64/Stack.nasm
> @@ -0,0 +1,72 @@
> +;------------------------------------------------------------------------------+;+;
> Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>+; SPDX-License-
> Identifier: BSD-2-Clause-Patent+; Abstract:+;+; Switch the stack from
> temporary memory to permanent memory.+;+;-------------------------------------
> -----------------------------------------++ SECTION .text++;---------------------------
> ---------------------------------------------------+; VOID+; EFIAPI+; SecSwitchStack
> (+; UINT32 TemporaryMemoryBase,+; UINT32 PermanentMemoryBase+;
> );+;------------------------------------------------------------------------------+global
> ASM_PFX(SecSwitchStack)+ASM_PFX(SecSwitchStack):+ ;+ ; Save four
> register: rax, rbx, rcx, rdx+ ;+ push rax+ push rbx+ push rcx+ push
> rdx++ ;+ ; !!CAUTION!! this function address's is pushed into stack after+ ;
> migration of whole temporary memory, so need save it to permanent+ ;
> memory at first!+ ;++ mov rbx, rcx ; Save the first parameter+
> mov rcx, rdx ; Save the second parameter++ ;+ ; Save this
> function's return address into permanent memory at first.+ ; Then, Fixup the
> esp point to permanent memory+ ;+ mov rax, rsp+ sub rax, rbx+ add
> rax, rcx+ mov rdx, qword [rsp] ; copy pushed register's value to
> permanent memory+ mov qword [rax], rdx+ mov rdx, qword [rsp + 8]+
> mov qword [rax + 8], rdx+ mov rdx, qword [rsp + 16]+ mov qword [rax +
> 16], rdx+ mov rdx, qword [rsp + 24]+ mov qword [rax + 24], rdx+ mov
> rdx, qword [rsp + 32] ; Update this function's return address into permanent
> memory+ mov qword [rax + 32], rdx+ mov rsp, rax ; From now,
> rsp is pointed to permanent memory++ ;+ ; Fixup the rbp point to
> permanent memory+ ;+ mov rax, rbp+ sub rax, rbx+ add rax, rcx+
> mov rbp, rax ; From now, rbp is pointed to permanent memory++
> pop rdx+ pop rcx+ pop rbx+ pop rax+ ret+diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Fsp.h b/Platform/Intel/MinPlatformPkg/Include/Fsp.h
> similarity index 79%
> rename from
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/Ia32/Fsp.h
> rename to Platform/Intel/MinPlatformPkg/Include/Fsp.h
> index 9f6cdcf476..319e1e3372 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Fsp.h
> +++ b/Platform/Intel/MinPlatformPkg/Include/Fsp.h
> @@ -1,7 +1,7 @@
> /** @file Fsp related definitions -Copyright (c) 2017, Intel Corporation. All
> rights reserved.<BR>+Copyright (c) 2017 - 2024, Intel Corporation. All rights
> reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -36,7
> +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> // // Fsp Header //-#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C-
> #define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30+#define
> FSP_HEADER_IMAGEBASE_OFFSET 0x1C+#define
> FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 #endifdiff --git
> a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> index a14c6b2db5..74e1bce87f 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> @@ -6,7 +6,7 @@
> # INF files to generate AutoGen.c and AutoGen.h files # for the build
> infrastructure. #-# Copyright (c) 2017 - 2021, Intel Corporation. All rights
> reserved.<BR>+# Copyright (c) 2017 - 2024, Intel Corporation. All rights
> reserved.<BR> # Copyright (C) 2023 Advanced Micro Devices, Inc. All rights
> reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent@@ -393,6
> +393,27 @@
> #
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
> |BOOLEAN|0xF00000A8 + ## Reset Vector in FSP+ # FALSE: Reset Vector is in
> FSP Wrapper+ # TRUE: Reset Vector is in FSP - This is only supported in X64+
> #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp|FALSE|B
> OOLEAN|0xF00000A9++ ## BFV Location for Reset Vector in FSP+ # The
> default of BFV Location for Reset Vector in FSP is 0x00000000FFFF0000.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp|0x
> 00000000FFFF0000|UINT64|0xF00000AA++ ## FSP-T UPD Header
> Revision+ # The default of FSP-T UPD Header Revision is 0.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision|0x0|UINT8|0x
> F00000AB++ ## FSP-T ARCH UPD Revision+ # The default of FSP-T ARCH UPD
> Revision is 0.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision|0x0|UINT8|0xF0
> 0000AC+ [PcdsFeatureFlag]
> gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit
> |FALSE|BOOLEAN|0xF00000A1--
> 2.40.1.windows.1
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2024-01-31 2:14 [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64 Kuo, Ted
2024-02-01 0:10 ` Nate DeSimone
2024-02-01 0:14 ` Nate DeSimone
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