From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.21703.1644376905555213236 for ; Tue, 08 Feb 2022 19:21:45 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=iJMzKKJa; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: nathaniel.l.desimone@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644376905; x=1675912905; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=z+btiKAHrOAxmtxgUKaGPoHywiB2NmiY+MQAR5m32+Q=; b=iJMzKKJa/w50eyr8Cz8jMBnXlhSDXBs/YdIyOLRcoD0PRbfsBYfhaDSe WWBh+cAyFLeB5CKmGCMq13fkLiU1HBb88qgZpiPEpL1tE0y3dJ2Jfe2Wi YM/x1o8PLO190rq4uiojFq2WlTw9nxlU5UBveBBdpbFS6nGoMP4jCeOc9 LCheShRnZT8AQxfRMhYwqFIyoC/PXw0AC3Uq6Q9mZ8onpJTuBtBhMjRpv /Q5WoaengOeE75NRQydvWmp73opdLj2bDL+elCTMYhrzw33BvFBlah+FG wKDnUTckbxk+hTzW42jF4jbnLW0w5mrrYQHUeWQQ/AMXJDkxEC6mr8ie4 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10252"; a="335511942" X-IronPort-AV: E=Sophos;i="5.88,354,1635231600"; d="scan'208";a="335511942" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 19:21:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,354,1635231600"; d="scan'208";a="678325448" Received: from orsmsx602.amr.corp.intel.com ([10.22.229.15]) by fmsmga001.fm.intel.com with ESMTP; 08 Feb 2022 19:21:44 -0800 Received: from orsmsx602.amr.corp.intel.com (10.22.229.15) by ORSMSX602.amr.corp.intel.com (10.22.229.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Tue, 8 Feb 2022 19:21:43 -0800 Received: from ORSEDG601.ED.cps.intel.com (10.7.248.6) by orsmsx602.amr.corp.intel.com (10.22.229.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20 via Frontend Transport; Tue, 8 Feb 2022 19:21:43 -0800 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (104.47.55.168) by edgegateway.intel.com (134.134.137.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2308.20; Tue, 8 Feb 2022 19:21:42 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aJn7odqyylz8BSt1oLdJjlh4tTB46Us59FyN8oIjYjociFZhFcHur36WC0COReO8HQzSC6pXt5tJEfC+qcs0LAVA6pB4qEdvudPOBMcktudq1VCNzfeWYaLRRZ0vC8pLHD+2DadOrNnckn215sRTIpvBKv1yvUhMuNzqtlTKVOjS8+eFGcJbGjT5bveXahGGyMJ9lDfLxwdDYo8eFjLFgu+rczsDIBnq7/FtTZK7XjIW3+GDN6yT8P9QMcGGDKpqUAKUB2NMC+m2qP6Y4WRrQUYZRlfeo1soHKvgOHNiY5Svi/OPJKysS800ot0r47BEx8F0hQj5G/p8muoKJ74l8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bG7aazn+gD7/KN3vO8CKcdA5aQQnddrD3R8Mzkt9Eyw=; b=FbtHyzn8wQW9HnOumwVhviQhqPkTZtGgJKgQlHq5ijL32055IIlMJthpHbqSov5u8atSMYf5uPbxz2gg1ULmuAKklVfG9VHA6ZycL/mYb3palCEghK624agEuEFhsd/Mr+IMNGfeYQ0/3C1/zX9jbN07JkOt5eW1GqFFqxr7XQLIQTLv2HYjmfVzkEy2tpiw9ACs8vqxifrwk8TDow521WJD+TG8JF0kCHY13/F6GgJAG0G6csCLNdF2UfgVBlNOxJDAOceZzzPjozPVNSDySRnrh30xXqRufO3fVJo7lqwsMRKueX3uSo2lAM6B9oOJNHd7OkYA8EVMK8z2aPRM9w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none Received: from MW4PR11MB5821.namprd11.prod.outlook.com (2603:10b6:303:184::5) by DM6PR11MB2668.namprd11.prod.outlook.com (2603:10b6:5:c7::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4975.11; Wed, 9 Feb 2022 03:21:27 +0000 Received: from MW4PR11MB5821.namprd11.prod.outlook.com ([fe80::6920:39b9:e18c:9dc5]) by MW4PR11MB5821.namprd11.prod.outlook.com ([fe80::6920:39b9:e18c:9dc5%7]) with mapi id 15.20.4930.022; Wed, 9 Feb 2022 03:21:27 +0000 From: "Nate DeSimone" To: "Oram, Isaac W" , "devel@edk2.groups.io" CC: "Chiu, Chasel" Subject: Re: [edk2-devel][edk2-platforms][PATCH V1 5/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table Thread-Topic: [edk2-devel][edk2-platforms][PATCH V1 5/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table Thread-Index: AQHYHFVZ+W+U/Hj19Uu2UWGakkoE36yKj4vw Date: Wed, 9 Feb 2022 03:21:27 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.200.16 dlp-product: dlpe-windows authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 546e4d31-5a76-4cb4-907e-08d9eb7b4237 x-ms-traffictypediagnostic: DM6PR11MB2668:EE_ x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:513; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: Hod1GHnC8xlc/HMCvp55WaFvbR5MTxvy0rgzMclzmLKdHrrhASIGxoifXvYud2Rum+uQM3LDvBc6tvXjAMp2wS9ZGGWv/Yk4f2gqt93kOoAC/7iUy5RFrlnW9EKLK7CJP48qDD5ORXXLZsyvtapw3nbqE0R/OU7PxrYybFyAzztRAw329tbW5FLdWLXxM/4LtsRy3AK0yQ2KNeR+UILPjr0to4MOG8HxgaKJBoR5rEusAcM6S0j1mgy836QKAP01PbbJdp1SkM1p7ZdYFoLMcrdkHvZ/ybPd/wtECCkYavs1B99wfSfs6CeDc21FB4uK62osPAfVsW0v+63cXmBMiftGazgNnbMOMSuoZyiuyLUmJ/tPDFQ9Si15Z4W1VxZAQBjTjzlTrsRitsfLkyW8Ud1VpU7551ufdP2AW1nDh4cxgaDpON2PXjCdiD+7QkWELv0qbiwmVM1X21zypSBkBSIAPYL9nzokOtYZb1TzIm215Ak/SG4prEKJ6BCDaw0ffhXFOyx2Kmt01os3EGFDc5CVvDLJ1LcII1O60Zk7S6JDA04QbYw5OKU4LpgbfFNefrh3LBgjuKeXad2gY38zuw2ptAAKJRX5zzDThyVxTcK2gmUcGNS0uNry1mgefSLxf71md2afFex79jKVO4OpMIG7YkIBoNN0bn/1aY8X9Y1FQFIkW45cmxj8oIAvzIOlz6xN8jYRnvdDKuksIznGptkHufbxjJh+Z+t1wxPaf6k= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW4PR11MB5821.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(366004)(7696005)(53546011)(9686003)(508600001)(38070700005)(6506007)(82960400001)(30864003)(5660300002)(2906002)(110136005)(52536014)(122000001)(64756008)(66946007)(76116006)(8676002)(66556008)(33656002)(38100700002)(66476007)(86362001)(19627235002)(8936002)(71200400001)(107886003)(83380400001)(316002)(55016003)(66446008)(26005)(4326008)(186003)(523214004)(559001)(579004);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?tPo3LWSfr76tWXuPwkD6q+ZeIVSn3OtfvnORZs4iVtpOe47sZft3PDH2mMEw?= =?us-ascii?Q?GV6RlIkasuel9xWsiiW21eQKFaV01+T1P06UTZdys4W4z8XoS2dA7/4/hNsp?= =?us-ascii?Q?6GyXkgq10VrPkOrUsRjbJWg6irbO15uTzMXtiJVPGtnWWF5kOiytonjAcZ9L?= =?us-ascii?Q?Q0MC3EDyPYj15LWfKhG0oth/HdqoI/tIIdPIh4cyaH5aJiFwVjKWGh4nhTXk?= =?us-ascii?Q?CC0akfPa0q2fPIGkZrvVTBcALaixymxfebepIP1BJN4Pgyt4CgFtlEF5ts9O?= =?us-ascii?Q?LmZE6KX3iNeAFT9+RidKBdzmazavhWvsjhEoNKPWrtEIuE8g5Ax78Uy81W1F?= =?us-ascii?Q?rIBsoe6Vp6Dh254Bugynd/minMvoePJcshzgAcrGbar54HJ0Qfe5iGMauvDE?= =?us-ascii?Q?LFznf3GSPGWb1TKZwFDbCXqzD8BRrUiuFm3D4uJx/xCRQldQ0uycp15UdCPp?= =?us-ascii?Q?JXXM6umjuwgNs7hPCv7jHBcLnEKfvmKFLIlD/sPMCqwdaZCOEjdQoSCEuZtP?= =?us-ascii?Q?GtS4xLOg3R7bynrcxRuXqXRMdrKaUaNFbTLhxrIJ2m0Qw31dD+TgArnOcM1V?= =?us-ascii?Q?QIDy0+t7hBEcZLoNcDiMbikXK+neNIv1Oi3DRRQwhtwU02UDevx+0y3Gl0CU?= =?us-ascii?Q?z9S/y94W1xU3bGoFBFJr44wNG8cUGf739H2xfiOH5xG7UB+4R26rD23I0dvf?= =?us-ascii?Q?i45CuZ7MZJPXR8OY26Pk2WEb6lPzIMF4p9WVrpYolcqfumWDjpZf+OKsHBQL?= =?us-ascii?Q?C4Pw0HFdvtJedwxIXrDjP0NmtchYuoU+xyUceGhdmeNde4vvO9rP7cURSKnq?= =?us-ascii?Q?aaCZBrz/GGRayIN92QAMc/wHUGUG7+lVhIyzm0FLHHg783uFpxJRP3/oJP/p?= =?us-ascii?Q?YOcKAQi0kU7Qy6ywvbVMEX7VkGl0kMzjRT8cf/UcCLIpS0tUfQ5NWdR0eaqq?= =?us-ascii?Q?CW6qyTwO2CG+GrvMxdiVOWZwenOov84y5fsD8v0GI++ihcb3Y3vRJmwLDZ6S?= =?us-ascii?Q?sgGk4uaHL1sqqn47X9DQoeaZzdRaUa0BzTUUeVo1KfFn0/83i8ccXJQk2YUr?= =?us-ascii?Q?K3fuRPwoxr8PwhYHb+4l/hkeGtFGE1klMV5QJUNVV3bAYF0PaEdjLWkm1U4Y?= =?us-ascii?Q?ySOUMC8kWuDE29IoYSbU6ckJVwR927NVFp21YaF5MGKxNPh4axYRoG8udSZ3?= =?us-ascii?Q?tAOrfAZaohH+7+yPOfgLoxriNAxnFtwY2ASSidNLvkFgtdC7EGH2x7PRUj7a?= =?us-ascii?Q?8/Z/kbtPOanvrZnYniqklQB5jgH20p1uWQRFGVhd1RFpjH+EzgAJylMPY7M8?= =?us-ascii?Q?8mv1AkWOuFokhhonqvASCJBKFgA2QDH9LHz/PJZZQvyelsZtHtP1cklJ8CSY?= =?us-ascii?Q?+cxCG4hS5nhhP8pSAxgvYLV2IdxAcw126bP+sMS4LiDV72iQUKvkxxYIkT1l?= =?us-ascii?Q?EZARaDkPR4HULp/19HVKMANOsNhxDK4D/nDjWVyx9maAaK0k57nfFBXPU1L3?= =?us-ascii?Q?SFKEleqoJkwP6+sypt3TawbZlFG93ADDlA3oeqka44OqyVORZ45yom8RU3op?= =?us-ascii?Q?GF0wt9V+60nK0DyxtbOmssttyU8A2A0/qLtHK/DXeRn+6kQOCOddvukYqeLm?= =?us-ascii?Q?D/mPyEhITR/ofa0nPXLZcrLKhqnK6LORl/NbtNjLNYDxMS3nfk76v3y2Ppak?= =?us-ascii?Q?CdwNlA=3D=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW4PR11MB5821.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 546e4d31-5a76-4cb4-907e-08d9eb7b4237 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Feb 2022 03:21:27.1735 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 905kbf+yxYSqHbcLwoyqggdLRMEw3UiN2cf9Js+w8W26mZh3OGzPIs1T7OU2URjljLaCnVaa9jZhP0vadSXzVWTzXn1oURCznWDmfoHeRoo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB2668 Return-Path: nathaniel.l.desimone@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Oram, Isaac W > Sent: Monday, February 7, 2022 11:03 AM > To: devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Chiu, Chasel > > Subject: [edk2-devel][edk2-platforms][PATCH V1 5/8] > WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table >=20 > DSDT for WilsonCityRvp >=20 > Cc: Nate DeSimone > Cc: Chasel Chiu > Signed-off-by: Isaac Oram > --- >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables > 10nm.inf | 48 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AML > UPD.asl | 20 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosP > arameterRegion.asi | 346 ++ >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Com > monPlatform10nm.asi | 205 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Cpu > MemHp.asi | 730 +++ >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT > .asl | 61 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRP > Platform10nm.asl | 19 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpga > Bus00.asi | 158 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpga > Bus01.asi | 158 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpga > Bus02.asi | 157 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpga > Bus03.asi | 157 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe. > asi | 137 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPci > eEdpcGpe.asi | 16 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPci > eEdpcNotify10nm.asi | 183 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPci > eEdpcOst.asi | 16 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPci > eHotPlugGpeHandler10nm.asl | 1322 +++++ >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRo > otBridge.asi | 328 ++ >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRo > otBridgeIcx.asi | 270 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Moth > er.asi | 164 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Nvdi > mmGpe.asi | 25 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.as > i | 66 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC00 > 10nm.asi | 427 ++ >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC06 > 10nmEjd.asi | 10 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC12 > 10nmEjd.asi | 10 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC18 > 10nmEjd.asi | 10 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchA > pic.asi | 18 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieH > p.asi | 669 +++ >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieH > pDev.asi | 53 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieN > onHpDev.asi | 45 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platf > orm.asl | 91 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platf > ormGpe10nm.asi | 191 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platf > ormPciTree10nm_EPRP.asi | 5388 ++++++++++++++++++++ >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1E > jd.asi | 10 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2E > jd.asi | 10 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3E > jd.asi | 10 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.a > si | 219 + >=20 > Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Unco > re.asi | 163 + > Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc > | 1 + > Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf > | 1 + > 39 files changed, 11912 insertions(+) >=20 > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTabl > es10nm.inf > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTabl > es10nm.inf > new file mode 100644 > index 0000000000..5480040545 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTabl > es10nm.inf > @@ -0,0 +1,48 @@ > +## @file > +# > +# @copyright > +# Copyright 2009 - 2022 Intel Corporation.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PlatformAcpiTable > + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606C= D > + MODULE_TYPE =3D USER_DEFINED > + VERSION_STRING =3D 1.0 > + > +[Sources] > + Fadt/Fadt62.aslc > + Facs/Facs62.aslc > + Dsdt/EPRPPlatform10nm.asl > + Mcfg/Mcfg.aslc > + Hpet/Hpet.aslc > + NFIT/Nfit.aslc > + PCAT/Pcat.aslc > + > + SPCR/Spcr.aslc > + Msct/Msct.aslc > + Wddt/Wddt1.0.aslc > + Bdat/Bdat.aslc > + > + Migt/Migt.aslc > + DBG2/DBG2.aslc > + Spmi/Spmi.aslc > + Pmtt/Pmtt10nm.aslc > + Hmat/Hmat.aslc > + > + Wsmt/Wsmt.aslc > + > +[Packages] > + MdePkg/MdePkg.dec > + WhitleySiliconPkg/CpRcPkg.dec > + WhitleySiliconPkg/SiliconPkg.dec > + WhitleyOpenBoardPkg/PlatformPkg.dec > + > +[FixedPcd] > + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount > + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount > + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount > + gPlatformTokenSpaceGuid.PcdEfiAcpiPm1aEvtBlkAddress > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AM > LUPD.asl > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/A > MLUPD.asl > new file mode 100644 > index 0000000000..3b46dd84df > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/A > MLUPD.asl > @@ -0,0 +1,20 @@ > +/** @file > + ACPI DSDT table > + > + @copyright > + Copyright 2011 - 2014 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +////////////////////////////////////////////////////////////////////////= ///// > ////// > +//Values are set like this to have ASL compiler reserve enough space for > objects > +////////////////////////////////////////////////////////////////////////= ///// > ////// > +// > +// Available Sleep states > +// > +Name(SS1,0) > +Name(SS2,0) > +Name(SS3,1) > +Name(SS4,1) > + > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Bio > sParameterRegion.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Bio > sParameterRegion.asi > new file mode 100644 > index 0000000000..4e49adc10c > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Bio > sParameterRegion.asi > @@ -0,0 +1,346 @@ > +/** @file > + > + @copyright > + Copyright 2016 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // > + // BIOS parameters region left in memory for ASL by POST code, defined= as > BIOS_ACPI_PARAM in GlobalNvsArea.h. > + // > + OperationRegion (PSYS, SystemMemory, 0x30584946, 0x800) // (FIX0 - > Patched by ACPI Platform Driver during POST) > + Field (PSYS, ByteAcc, NoLock, Preserve) { > + // IOAPIC Start > + PLAT , 32, // Platform ID > + > + Offset (0x04), // > + APCE , 1, // PCH IOAPIC Enable > + AP00 , 1, // PC00 IOAPIC Enable S0 > + AP01 , 1, // PC01 IOAPIC Enable > + AP02 , 1, // PC02 IOAPIC Enable > + AP03 , 1, // PC03 IOAPIC Enable > + AP04 , 1, // PC04 IOAPIC Enable > + AP05 , 1, // PC05 IOAPIC Enable > + AP06 , 1, // PC06 IOAPIC Enable S1 > + AP07 , 1, // PC07 IOAPIC Enable > + AP08 , 1, // PC08 IOAPIC Enable > + AP09 , 1, // PC09 IOAPIC Enable > + AP10 , 1, // PC10 IOAPIC Enable > + AP11 , 1, // PC11 IOAPIC Enable > + AP12 , 1, // PC12 IOAPIC Enable S2 > + AP13 , 1, // PC13 IOAPIC Enable > + AP14 , 1, // PC14 IOAPIC Enable > + AP15 , 1, // PC15 IOAPIC Enable > + AP16 , 1, // PC16 IOAPIC Enable > + AP17 , 1, // PC17 IOAPIC Enable > + AP18 , 1, // PC18 IOAPIC Enable S3 > + AP19 , 1, // PC19 IOAPIC Enable > + AP20 , 1, // PC20 IOAPIC Enable > + AP21 , 1, // PC21 IOAPIC Enable > + AP22 , 1, // PC22 IOAPIC Enable > + AP23 , 1, // PC23 IOAPIC Enable > + AP24 , 1, // PC24 IOAPIC Enable S4 > + AP25 , 1, // PC25 IOAPIC Enable > + AP26 , 1, // PC26 IOAPIC Enable > + AP27 , 1, // PC27 IOAPIC Enable > + AP28 , 1, // PC28 IOAPIC Enable > + AP29 , 1, // PC29 IOAPIC Enable > + AP30 , 1, // PC30 IOAPIC Enable S5 > + AP31 , 1, // PC31 IOAPIC Enable > + AP32 , 1, // PC32 IOAPIC Enable > + AP33 , 1, // PC33 IOAPIC Enable > + AP34 , 1, // PC34 IOAPIC Enable > + AP35 , 1, // PC35 IOAPIC Enable > + AP36 , 1, // PC36 IOAPIC Enable S6 > + AP37 , 1, // PC37 IOAPIC Enable > + AP38 , 1, // PC38 IOAPIC Enable > + AP39 , 1, // PC39 IOAPIC Enable > + AP40 , 1, // PC40 IOAPIC Enable > + AP41 , 1, // PC41 IOAPIC Enable > + AP42 , 1, // PC42 IOAPIC Enable S7 > + AP43 , 1, // PC43 IOAPIC Enable > + AP44 , 1, // PC44 IOAPIC Enable > + AP45 , 1, // PC45 IOAPIC Enable > + AP46 , 1, // PC46 IOAPIC Enable > + AP47 , 1, // PC47 IOAPIC Enable > + RESA , 15, > + > + Offset (0x0C), > + SKOV , 1, // Override ApicId socket field > + P119 , 1, // PCH IOAPIC 24_119 enabled > + CPX4 , 1, // 1 =3D CPX4, 0 =3D CPX6 > + RES0 , 5, // Unused > + // IOAPIC End > + > + // Power Managment Start > + Offset (0x0D), > + TPME , 1, // TPM Enable > + CSEN , 1, // C State Enable > + C3EN , 1, // OS C3 Report Enbale > + C6EN , 1, // C6 Enable > + C7EN , 1, // C7 Enable > + MWOS , 1, // MWAIT support Enable > + PSEN , 1, // P State Enable > + EMCA , 1, // EMCA Enable > + Offset (0x0E), > + HWAL , 2, // PSD HW_ALL Enable > + KPRS , 1, // KB present Flag > + MPRS , 1, // Mouse present Flag > + TSEN , 1, // T State Enable Flag > + FGTS , 1, // Fine grained T state Flag > + OSCX , 1, // OS C States > + RESX , 1, // Unused > + // Power Management End > + > + // RAS Start > + Offset (0x0F), > + CPHP , 8, // Bit field for determining CPU hotplug event is ha= ppening, > Update every time CPU Hotpug event is registered as valid > + // Bit0 CPU0 O*L Request > + // Bit1 CPU1 O*L Request > + // Bit2 CPU2 O*L Request > + // Bit3 CPU3 O*L Request > + // Bit4 CPU4 O*L Request > + // Bit5 CPU5 O*L Request > + // Bit6 CPU6 O*L Request > + // Bit7 CPU7 O*L Request > + IIOP , 8, // Bit field for determining IIO hotplug event is ha= ppening, > Update every time IIO Hotpug event is registered as valid > + // Bit0 IIO1 O*L Request > + // Bit1 IIO2 O*L Request > + // Bit2 IIO3 O*L Request > + // Bit3-7 Reserved > + SPB0 , 16, // Stack Present Bitmask in socket0, what stacks are= present > for STA method (Patched by ACPI Platform Driver during POST) > + SPB1 , 16, // Stack Present Bitmask in socket1, what stacks are= present > for STA method (Patched by ACPI Platform Driver during POST) > + SPB2 , 16, // Stack Present Bitmask in socket2, what stacks are= present > for STA method (Patched by ACPI Platform Driver during POST) > + SPB3 , 16, // Stack Present Bitmask in socket3, what stacks are= present > for STA method (Patched by ACPI Platform Driver during POST) > + SPB4 , 16, // Stack Present Bitmask in socket4, what stacks are= present > for STA method (Patched by ACPI Platform Driver during POST) > + SPB5 , 16, // Stack Present Bitmask in socket5, what stacks are= present > for STA method (Patched by ACPI Platform Driver during POST) > + SPB6 , 16, // Stack Present Bitmask in socket6, what stacks are= present > for STA method (Patched by ACPI Platform Driver during POST) > + SPB7 , 16, // Stack Present Bitmask in socket7, what stacks are= present > for STA method (Patched by ACPI Platform Driver during POST) > + PRBM , 32, // Processor Bit mask, what sockets are present for = STA > method, Update every time hotplug event happen and at boot time > (Patched by ACPI Platform Driver during POST) > + CTHC , 8, // CPU Core Thread Count > + P0ID , 32, // Processor 0 APIC ID base > + P1ID , 32, // Processor 1 APIC ID base > + P2ID , 32, // Processor 2 APIC ID base > + P3ID , 32, // Processor 3 APIC ID base > + P4ID , 32, // Processor 4 APIC ID base > + P5ID , 32, // Processor 5 APIC ID base > + P6ID , 32, // Processor 6 APIC ID base > + P7ID , 32, // Processor 7 APIC ID base > + P0BM , 64, // Processor 0 Bit mask, what cores (0-63) are prese= nt for > STA method > + P1BM , 64, // Processor 1 Bit mask, what cores (0-63) are prese= nt for > STA method > + P2BM , 64, // Processor 2 Bit mask, what cores (0-63) are prese= nt for > STA method > + P3BM , 64, // Processor 3 Bit mask, what cores (0-63) are prese= nt for > STA method > + P4BM , 64, // Processor 4 Bit mask, what cores (0-63) are prese= nt for > STA method > + P5BM , 64, // Processor 5 Bit mask, what cores (0-63) are prese= nt for > STA method > + P6BM , 64, // Processor 6 Bit mask, what cores (0-63) are prese= nt for > STA method > + P7BM , 64, // Processor 7 Bit mask, what cores (0-63) are prese= nt for > STA method > + P0BH , 64, // Processor 0 Bit mask, what cores (64-127) are pre= sent for > STA method > + P1BH , 64, // Processor 1 Bit mask, what cores (64-127) are pre= sent for > STA method > + P2BH , 64, // Processor 2 Bit mask, what cores (64-127) are pre= sent for > STA method > + P3BH , 64, // Processor 3 Bit mask, what cores (64-127) are pre= sent for > STA method > + P4BH , 64, // Processor 4 Bit mask, what cores (64-127) are pre= sent for > STA method > + P5BH , 64, // Processor 5 Bit mask, what cores (64-127) are pre= sent for > STA method > + P6BH , 64, // Processor 6 Bit mask, what cores (64-127) are pre= sent for > STA method > + P7BH , 64, // Processor 7 Bit mask, what cores (64-127) are pre= sent for > STA method > + CFMM , 32, // MMCFG Base > + TSSZ , 32, // TSEG Size. > + SMI0 , 32, // Parameter0 used for faked SMI request > + SMI1 , 32, // Parameter1 used for faked SMI request > + SMI2 , 32, // Parameter2 used for faked SMI request > + SMI3 , 32, // Parameter3 used for faked SMI request > + SCI0 , 32, // Parameter0 used for faked SCI request > + SCI1 , 32, // Parameter1 used for faked SCI request > + SCI2 , 32, // Parameter2 used for faked SCI request > + SCI3 , 32, // Parameter3 used for faked SCI request > + MADD , 64, // Migration ActionRegion GAS address. (Migration su= pport > written for 8 CPU socket system. In a 4 socket system, CPU4-7 and MEM8-15 > are invalid.) > + CUU0 , 128, // CPU0 UUID > + CUU1 , 128, // CPU1 UUID > + CUU2 , 128, // CPU2 UUID > + CUU3 , 128, // CPU3 UUID > + CUU4 , 128, // CPU4 UUID > + CUU5 , 128, // CPU5 UUID > + CUU6 , 128, // CPU6 UUID > + CUU7 , 128, // CPU7 UUID > + CPSP , 8, // CPU spare bitmap. 1 =3D=3D IsSpare. > + ME00 , 128, // MEM0 UUID > + ME01 , 128, // MEM1 UUID > + ME10 , 128, // MEM2 UUID > + ME11 , 128, // MEM3 UUID > + ME20 , 128, // MEM4 UUID > + ME21 , 128, // MEM5 UUID > + ME30 , 128, // MEM6 UUID > + ME31 , 128, // MEM7 UUID > + ME40 , 128, // MEM8 UUID > + ME41 , 128, // MEM9 UUID > + ME50 , 128, // MEM10 UUID > + ME51 , 128, // MEM11 UUID > + ME60 , 128, // MEM12 UUID > + ME61 , 128, // MEM13 UUID > + ME70 , 128, // MEM14 UUID > + ME71 , 128, // MEM15 UUID > + LDIR , 64, // L1 Directory Address > + PRID , 32, // Processor ID > + AHPE , 8, // ACPI PCIe hot plug enable. > + WHEN , 8, > + WSCI , 8, > + SERR , 8, // Propogate SERR > + PERR , 8, // Propogate PERR > + // RAS End > + > + // VTD Start > + DHRD , 192, // DHRD > + ATSR , 192, // ATSR > + RHSA , 192, // RHSA > + // VTD End > + > + // SR-IOV WA Start > + WSIC , 8, > + WSIS , 16, > + WSIB , 8, > + WSID , 8, > + WSIF , 8, > + WSTS , 8, > + WHEA , 8, > + // SR-IOV WA End > + > + // BIOS Guard Start > + BGMA , 64, // BIOS Guard Memory Address > + BGMS , 8, // BIOS Guard Memory Size > + BGIO , 16, // BIOS Guard IO Trap Address > + CNBS , 8, // CPU SKU number bit shift > + // BIOS Guard End > + > + // USB3 Start > + XHMD , 8, // copy of setup item PchUsb30Mode > + SBV1 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#1) > + SBV2 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#2) > + // USB3 End > + > + // HWPM Start > + HWEN , 2, // HWPM State Enable option from setup > + RES2 , 1, // Reserved bit > + HWPI , 1, // HWP Interrupt > + RES1 , 4, // Reserved bits > + // HWPM End > + > + // SGX Start > + EPCS , 8, // EPC Status > + ELN0 , 64, // EPC0 Length > + ELN1 , 64, // EPC1 Length > + ELN2 , 64, // EPC2 Length > + ELN3 , 64, // EPC3 Length > + ELN4 , 64, // EPC4 Length > + ELN5 , 64, // EPC5 Length > + ELN6 , 64, // EPC6 Length > + ELN7 , 64, // EPC7 Length > + EBA0 , 64, // EPC0 Base Address > + EBA1 , 64, // EPC1 Base Address > + EBA2 , 64, // EPC2 Base Address > + EBA3 , 64, // EPC3 Base Address > + EBA4 , 64, // EPC4 Base Address > + EBA5 , 64, // EPC5 Base Address > + EBA6 , 64, // EPC6 Base Address > + EBA7 , 64, // EPC7 Base Address > + // SGX End > + > + // PCIe Multi-Seg Start > + // Stack bus base numbers for up to 14 stacks in up to 8 socket. Nam= e is > 'BB', where and are hex. > + BB00, 8, BB01, 8, BB02, 8, BB03, 8, BB04, 8, BB05, 8, BB06, 8, BB07,= 8, BB08, > 8, BB09, 8, BB0A, 8, BB0B, 8, BB0C, 8, BB0D, 8, > + BB10, 8, BB11, 8, BB12, 8, BB13, 8, BB14, 8, BB15, 8, BB16, 8, BB17,= 8, BB18, > 8, BB19, 8, BB1A, 8, BB1B, 8, BB1C, 8, BB1D, 8, > + BB20, 8, BB21, 8, BB22, 8, BB23, 8, BB24, 8, BB25, 8, BB26, 8, BB27,= 8, BB28, > 8, BB29, 8, BB2A, 8, BB2B, 8, BB2C, 8, BB2D, 8, > + BB30, 8, BB31, 8, BB32, 8, BB33, 8, BB34, 8, BB35, 8, BB36, 8, BB37,= 8, BB38, > 8, BB39, 8, BB3A, 8, BB3B, 8, BB3C, 8, BB3D, 8, > + BB40, 8, BB41, 8, BB42, 8, BB43, 8, BB44, 8, BB45, 8, BB46, 8, BB47,= 8, BB48, > 8, BB49, 8, BB4A, 8, BB4B, 8, BB4C, 8, BB4D, 8, > + BB50, 8, BB51, 8, BB52, 8, BB53, 8, BB54, 8, BB55, 8, BB56, 8, BB57,= 8, BB58, > 8, BB59, 8, BB5A, 8, BB5B, 8, BB5C, 8, BB5D, 8, > + BB60, 8, BB61, 8, BB62, 8, BB63, 8, BB64, 8, BB65, 8, BB66, 8, BB67,= 8, BB68, > 8, BB69, 8, BB6A, 8, BB6B, 8, BB6C, 8, BB6D, 8, > + BB70, 8, BB71, 8, BB72, 8, BB73, 8, BB74, 8, BB75, 8, BB76, 8, BB77,= 8, BB78, > 8, BB79, 8, BB7A, 8, BB7B, 8, BB7C, 8, BB7D, 8, > + > + SGEN , 8, // PCIe_MultiSeg_Support enable/disable > + SG00 , 8, // PCI segment ID for socket 0 > + SG01 , 8, // PCI segment ID for socket 1 > + SG02 , 8, // PCI segment ID for socket 2 > + SG03 , 8, // PCI segment ID for socket 3 > + SG04 , 8, // PCI segment ID for socket 4 > + SG05 , 8, // PCI segment ID for socket 5 > + SG06 , 8, // PCI segment ID for socket 6 > + SG07 , 8, // PCI segment ID for socket 7 > + // PCIe Multi-Seg End > + > + // Sub-NUMA Cluster support > + CLOD , 8, // 0 - SNC disabled, 2 - SNC enabled with 2 cluster= s, 4 - SNC > enabled with 4 clusters > + > + // XTU Start > + XTUB , 32, > + XTUS , 32, > + XMBA , 32, > + DDRF , 8, > + RT3S , 8, > + RTP0 , 8, > + RTP3 , 8, > + // XTU End > + > + // FPGA Root Port Bus > + FBB0 , 8, // FPGA Bus Base for Socket 0 > + FBB1 , 8, // FPGA Bus Base for Socket 1 > + FBB2 , 8, // FPGA Bus Base for Socket 2 > + FBB3 , 8, // FPGA Bus Base for Socket 3 > + FBB4 , 8, // FPGA Bus Base for Socket 4 > + FBB5 , 8, // FPGA Bus Base for Socket 5 > + FBB6 , 8, // FPGA Bus Base for Socket 6 > + FBB7 , 8, // FPGA Bus Base for Socket 7 > + > + FBL0 , 8, // FPGA Bus limit for Socket 0 > + FBL1 , 8, // FPGA Bus limit for Socket 1 > + FBL2 , 8, // FPGA Bus limit for Socket 2 > + FBL3 , 8, // FPGA Bus limit for Socket 3 > + FBL4 , 8, // FPGA Bus limit for Socket 4 > + FBL5 , 8, // FPGA Bus limit for Socket 5 > + FBL6 , 8, // FPGA Bus limit for Socket 6 > + FBL7 , 8, // FPGA Bus limit for Socket 7 > + > + // FPGA present bit > + P0FB , 8, // FPGA present in Socket 0 > + P1FB , 8, // FPGA present in Socket 1 > + P2FB , 8, // FPGA present in Socket 2 > + P3FB , 8, // FPGA present in Socket 3 > + P4FB , 8, // FPGA present in Socket 4 > + P5FB , 8, // FPGA present in Socket 5 > + P6FB , 8, // FPGA present in Socket 6 > + P7FB , 8, // FPGA present in Socket 7 > + > + // FPGA Resource Allocation > + FMB0 , 32, > + FMB1 , 32, > + FMB2 , 32, > + FMB3 , 32, > + FMB4 , 32, > + FMB5 , 32, > + FMB6 , 32, > + FMB7 , 32, > + > + FML0 , 32, > + FML1 , 32, > + FML2 , 32, > + FML3 , 32, > + FML4 , 32, > + FML5 , 32, > + FML6 , 32, > + FML7 , 32, > + > + // FPGA KTI present bitmap > + FKPB , 32, > + // FPGA Bus for KTI > + FKB0 , 8, // FPGA Bus Base for Socket 0 KTI Link > + FKB1 , 8, // FPGA Bus Base for Socket 1 KTI Link > + FKB2 , 8, // FPGA Bus Base for Socket 2 KTI Link > + FKB3 , 8, // FPGA Bus Base for Socket 3 KTI Link > + FKB4 , 8, // FPGA Bus Base for Socket 4 KTI Link > + FKB5 , 8, // FPGA Bus Base for Socket 5 KTI Link > + FKB6 , 8, // FPGA Bus Base for Socket 6 KTI Link > + FKB7 , 8, // FPGA Bus Base for Socket 7 KTI Link > + > + PMBA , 16, // ACPI IO Base Address > + DBGM , 8, // Debug Mode Indicator > + IRPC , 8, // IIO PCIe root port PCIe Capability offset > + ATSC , 8, // Flag to indicate if TSC is linked to ART > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Co > mmonPlatform10nm.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Co > mmonPlatform10nm.asi > new file mode 100644 > index 0000000000..28a997b102 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Co > mmonPlatform10nm.asi > @@ -0,0 +1,205 @@ > +/** @file > + > + @copyright > + Copyright 2016 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "MaxSocket.h" > + > + // > + // External declarations > + // HECI-1/HECI-2 are in 10nmServerPlatformPkg\Me\Sps\Acpi\SpsNm.asl > + // > + External(\_SB.PC00.HEC2.HPTS, MethodObj) > + External(\_SB.PC00.HEC2.HWAK, MethodObj) > + > + External(\_SB.OSPC, MethodObj) > + // > + // System Sleep States > + // > + Name (\_S0,Package (){0,0,0,0}) > + Name (\_S3,Package (){5,0,0,0}) // Name changed to \DS3 if disabled = in > Setup > + Name (\_S4,Package (){6,0,0,0}) // Name changed to \DS4 if disabled = in > Setup > + Name (\_S5,Package (){7,0,0,0}) > + > + // > + // Native OS hot plug support, 0->ACPI, 1->OS > + // > + Name (\OSHF, 0) > + > + Name (\HWPS, 0) // CPC capability from platform _OSC > + > + // > + // OS flag > + // > + #include "Os.asi" > + > + // > + // for determing PIC mode > + // > + Name (\PICM,Zero) > + Method (\_PIC, 1, NotSerialized) { > + Store(Arg0,\PICM) > + } > + > + OperationRegion (DBG0, SystemIO, 0x80, 2) > + Field (DBG0, ByteAcc,NoLock,Preserve) { > + IO80, 8, > + IO81, 8 > + } > + > + // > + // Access CMOS range > + // > + OperationRegion (ACMS, SystemIO, 0x72, 2) > + Field ( ACMS, ByteAcc, NoLock, Preserve) { > + INDX, 8, > + DATA, 8 > + } > + > + > + // > + // BIOS parameter BIOS_ACPI_PARAM > + // > + #include "BiosParameterRegion.asi" > + > + // > + // SWGPE_CTRL > + // > + OperationRegion (GPCT, SystemIO, Add (PMBA, 0x42), 1) > + Field (GPCT, ByteAcc, NoLock, Preserve) { > + , 1, > + SGPC , 1, > + } > + > + // > + // GPE0 Enable > + // > + OperationRegion (GPE0, SystemIO, Add (PMBA, 0x9C), 4) > + Field (GPE0, ByteAcc,NoLock,Preserve) { > + ,1, > + GPEH,1, > + ,7, > + PCIE,1, > + ,1, > + PMEE,1, > + ,1, > + PMB0,1, > + ,18, > + } > + > + // > + // GPE0 Status > + // > + OperationRegion (GPES, SystemIO, Add (PMBA, 0x8C), 4) > + Field (GPES, ByteAcc,NoLock,Preserve) { > + ,1, > + GPSH,1, > + SGPS,1, > + ,6, > + PEES,1, > + ,1, > + PMES,1, > + ,1, > + PMEB,1, > + ,18, > + } > + > + // > + // System sleep down > + // > + Method (_PTS, 1, NotSerialized) > + { > + Store (0x72, IO80) // Sync with EfiPostCode.h > + > + // > + // Clear wake event status. > + // > + Store(1,PMES) > + Store(1,PMEB) > + > + // > + // Enable SCI and wake event sources. > + // > + Store(1,GPEH) > + Store(1,PCIE) > + Store(1,PMEE) > + Store(1,PMB0) > + > + // > + // If HECI-2 exist call its prepare-to-sleep handler. > + // The handler checks whether HECI-2 is enabled. > + // > + If (CondRefOf(\_SB.PC00.HEC2.HPTS)) > + { > + \_SB.PC00.HEC2.HPTS() > + } > + > + /// WA for S3 on XHCI > + \_SB.PC00.XHCI.XHCS() > + } > + > + > + // > + // System Wake up > + // > + Method (_WAK, 1, Serialized) > + { > + Store (0x73, IO80) // Sync with EfiPostCode.h > + > + // > + // If HECI-2 exist call its wake-up handler. > + // The handler checks whether HECI-2 is enabled. > + // > + If (CondRefOf(\_SB.PC00.HEC2.HWAK)) > + { > + \_SB.PC00.HEC2.HWAK() > + } > + > + // > + // If waking from S3 > + // > + If (LEqual(Arg0, 3)) { > + } > + > + Return(Package(){0, 0}) > + } > + > + Scope(\_SB) { > + > + // Information on CPU and Memory for hotplug SKUs > + #include "CpuMemHp.asi" > + > + OperationRegion (IOB2, SystemIO, 0xB2, 2) //MKF_SMIPORT > + Field (IOB2, ByteAcc, NoLock, Preserve) { > + SMIC, 8, // SW-SMI ctrl port > + SMIS, 8, // SW-SMI status port > + } > + > + Method(_OSC , 4) { > + Store(Arg3,Local0) > + CreateDWordField(Local0,4,CPBF) > + If(LEqual(Arg0, ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) { > + //Save Platform OSC HWPM capabilities > + If(LEqual(And(CPBF, 0x00000040), 0x00000040)) { > + Store(1,HWPS) > + } > + } > + If (CondRefOf (\_SB.OSPC)) { > + Return (\_SB.OSPC(Arg0, Arg1, Arg2, Arg3)) > + } > + Return (Local0) > + } > + // > + // SGX > + // > + #include "Sgx.asi" > + // > + // Common Hot Plug for PCxx devices > + // > + #include "IioRootBridgeIcx.asi" > + } // end _SB scope > + > + > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Cp > uMemHp.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Cp > uMemHp.asi > new file mode 100644 > index 0000000000..a0824a30c0 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Cp > uMemHp.asi > @@ -0,0 +1,730 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "MaxSocket.h" > + > +#define HECI_CMD_CPUHOTPLUG 1 > +#define HECI_CMD_CPUHOTREMOVE 2 > + > +#define SIZE_LAPIC_STRUC 8 > +#define LAPIC_TYPE 0 > + > +#define SIZE_X2LAPIC_STRUC 16 > +#define X2LAPIC_TYPE 9 > + > +#define MAK_STR(x) #x > + > +// > +// This macro creates method that calculates > +// number of active threads for its socket > +// > +#define CPU_THREADS_NUM(socket) = \ > + Method(THNU, 0) { = \ > + Store(0, Local0) = \ > + Store(P##socket##BM, Local1) = \ > + While (Local1) { = \ > + Add(Local0, And(Local1, 1), Local0) = \ > + ShiftRight(Local1, 1, Local1) = \ > + } = \ > + return (Or(ShiftLeft(socket, 8), Local0)) = \ > + } > + > +// > +//set DevName ProcId field and IO to C##thread > +// > +#define CPU_THREAD_DEV(socket, thread) = \ > + Device(C##thread) { = \ > + Name(_HID, "ACPI0007") = \ > + Method (_UID) { = \ > + Return (\_SB.CUID(0x0##socket, 0x##thread)) = \ > + } = \ > + Method(_PXM) { = \ > + if (LEqual (CLOD, 0)) { = \ > + Return(0x0##socket) = \ > + } else { = \ > + Store(DerefOf(Index(\_SB.APT##socket, 0x##thread)), Local0) = \ > + Store(CNBS, Local1) = \ > + Subtract(Local1, 1, Local1) = \ > + ShiftRight(Local0, Local1, Local0) = \ > + And(Local0, 1, Local0) = \ > + Store(0x##socket, Local1) = \ > + Multiply(Local1, 2, Local1) = \ > + if(LEqual(Local0, 1)) { = \ > + Add(Local1, 1, Local1) = \ > + } = \ > + Return(Local1) = \ > + } = \ > + } = \ > + Method(_STA) { = \ > + if(LEqual(\_SB.CSTA(0x0##socket, 0x##thread), 0x00)) { = \ > + Return(0x00) = \ > + } else { = \ > + If (LGreaterEqual (\_SB.OSYS, 12)) { = \ > + Return(0x0F) = \ > + } Else { = \ > + Return(0x0B) = \ > + } = \ > + } = \ > + } = \ > + Method(_MAT) { = \ > + if(SKOV) { = \ > + Return(\_SB.X2AP(0x0##socket, 0x##thread)) = \ > + } else { = \ > + Return(\_SB.LAPC(0x0##socket, 0x##thread)) = \ > + } = \ > + } = \ > + } > + > +#define CPU_SOCKET_DEV(socket) = \ > + Device(\_SB.SCK##socket) { = \ > + Name (_HID, "ACPI0004") = \ > + Name (_UID, MAK_STR(CPUSCK##socket)) = \ > + Name (LSTA, 0xff) = \ > + Method(_STA) { = \ > + Store(MAK_STR(CPUSCK##socket), CUU##socket) = \ > + Store(\_SB.PSTA(0x0##socket), Local0) = \ > + And(Local0, 0x03, Local1) = \ > + If (LAnd(LNotEqual(LSTA, 0xff), LNotEqual(Local1, LSTA))) { = \ > + If (LEqual(Local1, 0x03)) { = \ > + /*\_SB.PC00.HEC2.HPNF(HECI_CMD_CPUHOTPLUG, socket, THNU) > TODO: Obsolete with _PUR?*/\ > + } Else { = \ > + /*\_SB.PC00.HEC2.HPNF(HECI_CMD_CPUHOTREMOVE, socket, THNU) > TODO: Obsolete with _PUR?*/\ > + } = \ > + } = \ > + Store(Local1, LSTA) = \ > + return(Local0) = \ > + } = \ > + = \ > + CPU_THREADS_NUM(socket) \ > + CPU_THREAD_DEV (socket, 000) \ > + CPU_THREAD_DEV (socket, 001) \ > + CPU_THREAD_DEV (socket, 002) \ > + CPU_THREAD_DEV (socket, 003) \ > + CPU_THREAD_DEV (socket, 004) \ > + CPU_THREAD_DEV (socket, 005) \ > + CPU_THREAD_DEV (socket, 006) \ > + CPU_THREAD_DEV (socket, 007) \ > + CPU_THREAD_DEV (socket, 008) \ > + CPU_THREAD_DEV (socket, 009) \ > + CPU_THREAD_DEV (socket, 00A) \ > + CPU_THREAD_DEV (socket, 00B) \ > + CPU_THREAD_DEV (socket, 00C) \ > + CPU_THREAD_DEV (socket, 00D) \ > + CPU_THREAD_DEV (socket, 00E) \ > + CPU_THREAD_DEV (socket, 00F) \ > + CPU_THREAD_DEV (socket, 010) \ > + CPU_THREAD_DEV (socket, 011) \ > + CPU_THREAD_DEV (socket, 012) \ > + CPU_THREAD_DEV (socket, 013) \ > + CPU_THREAD_DEV (socket, 014) \ > + CPU_THREAD_DEV (socket, 015) \ > + CPU_THREAD_DEV (socket, 016) \ > + CPU_THREAD_DEV (socket, 017) \ > + CPU_THREAD_DEV (socket, 018) \ > + CPU_THREAD_DEV (socket, 019) \ > + CPU_THREAD_DEV (socket, 01A) \ > + CPU_THREAD_DEV (socket, 01B) \ > + CPU_THREAD_DEV (socket, 01C) \ > + CPU_THREAD_DEV (socket, 01D) \ > + CPU_THREAD_DEV (socket, 01E) \ > + CPU_THREAD_DEV (socket, 01F) \ > + CPU_THREAD_DEV (socket, 020) \ > + CPU_THREAD_DEV (socket, 021) \ > + CPU_THREAD_DEV (socket, 022) \ > + CPU_THREAD_DEV (socket, 023) \ > + CPU_THREAD_DEV (socket, 024) \ > + CPU_THREAD_DEV (socket, 025) \ > + CPU_THREAD_DEV (socket, 026) \ > + CPU_THREAD_DEV (socket, 027) \ > + CPU_THREAD_DEV (socket, 028) \ > + CPU_THREAD_DEV (socket, 029) \ > + CPU_THREAD_DEV (socket, 02A) \ > + CPU_THREAD_DEV (socket, 02B) \ > + CPU_THREAD_DEV (socket, 02C) \ > + CPU_THREAD_DEV (socket, 02D) \ > + CPU_THREAD_DEV (socket, 02E) \ > + CPU_THREAD_DEV (socket, 02F) \ > + CPU_THREAD_DEV (socket, 030) \ > + CPU_THREAD_DEV (socket, 031) \ > + CPU_THREAD_DEV (socket, 032) \ > + CPU_THREAD_DEV (socket, 033) \ > + CPU_THREAD_DEV (socket, 034) \ > + CPU_THREAD_DEV (socket, 035) \ > + CPU_THREAD_DEV (socket, 036) \ > + CPU_THREAD_DEV (socket, 037) \ > + CPU_THREAD_DEV (socket, 038) \ > + CPU_THREAD_DEV (socket, 039) \ > + CPU_THREAD_DEV (socket, 03A) \ > + CPU_THREAD_DEV (socket, 03B) \ > + CPU_THREAD_DEV (socket, 03C) \ > + CPU_THREAD_DEV (socket, 03D) \ > + CPU_THREAD_DEV (socket, 03E) \ > + CPU_THREAD_DEV (socket, 03F) \ > + CPU_THREAD_DEV (socket, 040) \ > + CPU_THREAD_DEV (socket, 041) \ > + CPU_THREAD_DEV (socket, 042) \ > + CPU_THREAD_DEV (socket, 043) \ > + CPU_THREAD_DEV (socket, 044) \ > + CPU_THREAD_DEV (socket, 045) \ > + CPU_THREAD_DEV (socket, 046) \ > + CPU_THREAD_DEV (socket, 047) \ > + CPU_THREAD_DEV (socket, 048) \ > + CPU_THREAD_DEV (socket, 049) \ > + CPU_THREAD_DEV (socket, 04A) \ > + CPU_THREAD_DEV (socket, 04B) \ > + CPU_THREAD_DEV (socket, 04C) \ > + CPU_THREAD_DEV (socket, 04D) \ > + CPU_THREAD_DEV (socket, 04E) \ > + CPU_THREAD_DEV (socket, 04F) \ > + CPU_THREAD_DEV (socket, 050) \ > + CPU_THREAD_DEV (socket, 051) \ > + CPU_THREAD_DEV (socket, 052) \ > + CPU_THREAD_DEV (socket, 053) \ > + CPU_THREAD_DEV (socket, 054) \ > + CPU_THREAD_DEV (socket, 055) \ > + CPU_THREAD_DEV (socket, 056) \ > + CPU_THREAD_DEV (socket, 057) \ > + CPU_THREAD_DEV (socket, 058) \ > + CPU_THREAD_DEV (socket, 059) \ > + CPU_THREAD_DEV (socket, 05A) \ > + CPU_THREAD_DEV (socket, 05B) \ > + CPU_THREAD_DEV (socket, 05C) \ > + CPU_THREAD_DEV (socket, 05D) \ > + CPU_THREAD_DEV (socket, 05E) \ > + CPU_THREAD_DEV (socket, 05F) \ > + CPU_THREAD_DEV (socket, 060) \ > + CPU_THREAD_DEV (socket, 061) \ > + CPU_THREAD_DEV (socket, 062) \ > + CPU_THREAD_DEV (socket, 063) \ > + CPU_THREAD_DEV (socket, 064) \ > + CPU_THREAD_DEV (socket, 065) \ > + CPU_THREAD_DEV (socket, 066) \ > + CPU_THREAD_DEV (socket, 067) \ > + CPU_THREAD_DEV (socket, 068) \ > + CPU_THREAD_DEV (socket, 069) \ > + CPU_THREAD_DEV (socket, 06A) \ > + CPU_THREAD_DEV (socket, 06B) \ > + CPU_THREAD_DEV (socket, 06C) \ > + CPU_THREAD_DEV (socket, 06D) \ > + CPU_THREAD_DEV (socket, 06E) \ > + CPU_THREAD_DEV (socket, 06F) \ > + CPU_THREAD_DEV (socket, 070) \ > + CPU_THREAD_DEV (socket, 071) \ > + CPU_THREAD_DEV (socket, 072) \ > + CPU_THREAD_DEV (socket, 073) \ > + CPU_THREAD_DEV (socket, 074) \ > + CPU_THREAD_DEV (socket, 075) \ > + CPU_THREAD_DEV (socket, 076) \ > + CPU_THREAD_DEV (socket, 077) \ > + CPU_THREAD_DEV (socket, 078) \ > + CPU_THREAD_DEV (socket, 079) \ > + CPU_THREAD_DEV (socket, 07A) \ > + CPU_THREAD_DEV (socket, 07B) \ > + CPU_THREAD_DEV (socket, 07C) \ > + CPU_THREAD_DEV (socket, 07D) \ > + CPU_THREAD_DEV (socket, 07E) \ > + CPU_THREAD_DEV (socket, 07F) \ > + } > + > + Scope(\_SB) { > + > + //---------------------------------------------------------------- > + // Method PSTA() > + // Return package state > + // > + // Inputs: Arg0 =3D socket number for which to return the _STA code= . > + //---------------------------------------------------------------- > + Method(PSTA, 1){ // Socket Status > + ShiftRight(PRBM, Arg0, Local6) > + And(Local6, 0x1, Local6) > + if(LEqual(Local6, 0x0)) { > + Return(0x00) > + } else { > + Return(0x0F) > + } > + } // End Method PSTA > + > + //---------------------------------------------------------------- > + // APIC ID Map > + // Extened APIC ID buffer to support MAX 64 core > + //---------------------------------------------------------------- > + Name (APT0, Buffer (128) { > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF > + }) > + > + Name (APT1, Buffer (128) { > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF > + }) > + > + Name (APT2, Buffer (128) { > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF > + }) > + > + Name (APT3, Buffer (128) { > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF > + }) > + > + Name (APT4, Buffer (128) { > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF > + }) > + > + Name (APT5, Buffer (128) { > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF > + }) > + > + Name (APT6, Buffer (128) { > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF > + }) > + > + Name (APT7, Buffer (128) { > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF > + }) > + > + //---------------------------------------------------------------- > + // Method TPID() > + // Convert the socket and thread index to the actual APIC ID > + // > + // Inputs: Arg0 =3D socket index > + // Arg1 =3D thread index > + //---------------------------------------------------------------- > + Method (TPID, 2, NotSerialized) { > + Store (0x00, Local0) > + If (LEqual (Arg0, 0x00)) > + { > + Store (P0ID, Local0) > + Add (Local0, DerefOf(Index(APT0, Arg1)), Local0) > + } > + > + If (LEqual (Arg0, 0x01)) > + { > + Store (P1ID, Local0) > + Add (Local0, DerefOf(Index(APT1, Arg1)), Local0) > + } > + > + If (LEqual (Arg0, 0x02)) > + { > + Store (P2ID, Local0) > + Add (Local0, DerefOf(Index(APT2, Arg1)), Local0) > + } > + > + If (LEqual (Arg0, 0x03)) > + { > + Store (P3ID, Local0) > + Add (Local0, DerefOf(Index(APT3, Arg1)), Local0) > + } > + > + If (LEqual (Arg0, 0x04)) > + { > + Store (P4ID, Local0) > + Add (Local0, DerefOf(Index(APT4, Arg1)), Local0) > + } > + > + If (LEqual (Arg0, 0x05)) > + { > + Store (P5ID, Local0) > + Add (Local0, DerefOf(Index(APT5, Arg1)), Local0) > + } > + > + If (LEqual (Arg0, 0x06)) > + { > + Store (P6ID, Local0) > + Add (Local0, DerefOf(Index(APT6, Arg1)), Local0) > + } > + > + If (LEqual (Arg0, 0x07)) > + { > + Store (P7ID, Local0) > + Add (Local0, DerefOf(Index(APT7, Arg1)), Local0) > + } > + > + Return (Local0) > + } > + > + //---------------------------------------------------------------- > + // Method CSTA() > + // Get current processor state > + // Inputs: Arg0 =3D Socket Number where core belongs > + // Arg1 =3D Thread number for which to return the _STA code > + // (Bit0 - Core Id, BIT1- Thread Id) > + //---------------------------------------------------------------- > + Method(CSTA, 2){ // Core Status > + Store(0, Local0) > + Store(0, Local2) //for Core# > + > + //Get ApicId per thread Index from APT# > + if (LEqual(Arg0, 0x0)) { > + if(LEqual(P0BM, 0x0)) { > + Return(0x00) > + } > + > + Add (Local2, DerefOf(Index(APT0, Arg1)), Local2) > + if (LEqual(Local2, 0xFF)) { > + Return(0x00) > + } > + //Processor Bit mask is changed for core# only > + ShiftRight(Local2, 1, Local2) > + ShiftRight(P0BM, Local2, Local0) > + } > + if (LEqual(Arg0, 0x1)) { > + if(LEqual(P1BM, 0x0)) { > + Return(0x00) > + } > + > + Add (Local2, DerefOf(Index(APT1, Arg1)), Local2) > + if (LEqual(Local2, 0xFF)) { > + Return(0x00) > + } > + //Processor Bit mask is changed for core# only > + ShiftRight(Local2, 1, Local2) > + ShiftRight(P1BM, Local2, Local0) > + } > + if (LEqual(Arg0, 0x2)) { > + if(LEqual(P2BM, 0x0)) { > + Return(0x00) > + } > + > + Add (Local2, DerefOf(Index(APT2, Arg1)), Local2) > + if (LEqual(Local2, 0xFF)) { > + Return(0x00) > + } > + //Processor Bit mask is changed for core# only > + ShiftRight(Local2, 1, Local2) > + ShiftRight(P2BM, Local2, Local0) > + } > + if (LEqual(Arg0, 0x3)) { > + if(LEqual(P3BM, 0x0)) { > + Return(0x00) > + } > + > + Add (Local2, DerefOf(Index(APT3, Arg1)), Local2) > + if (LEqual(Local2, 0xFF)) { > + Return(0x00) > + } > + //Processor Bit mask is changed for core# only > + ShiftRight(Local2, 1, Local2) > + ShiftRight(P3BM, Local2, Local0) > + } > + if (LEqual(Arg0, 0x4)) { > + if(LEqual(P4BM, 0x0)) { > + Return(0x00) > + } > + > + Add (Local2, DerefOf(Index(APT4, Arg1)), Local2) > + if (LEqual(Local2, 0xFF)) { > + Return(0x00) > + } > + //Processor Bit mask is changed for core# only > + ShiftRight(Local2, 1, Local2) > + ShiftRight(P4BM, Local2, Local0) > + } > + if (LEqual(Arg0, 0x5)) { > + if(LEqual(P5BM, 0x0)) { > + Return(0x00) > + } > + > + Add (Local2, DerefOf(Index(APT5, Arg1)), Local2) > + if (LEqual(Local2, 0xFF)) { > + Return(0x00) > + } > + //Processor Bit mask is changed for core# only > + ShiftRight(Local2, 1, Local2) > + ShiftRight(P5BM, Local2, Local0) > + } > + if (LEqual(Arg0, 0x6)) { > + if(LEqual(P6BM, 0x0)) { > + Return(0x00) > + } > + > + Add (Local2, DerefOf(Index(APT6, Arg1)), Local2) > + if (LEqual(Local2, 0xFF)) { > + Return(0x00) > + } > + //Processor Bit mask is changed for core# only > + ShiftRight(Local2, 1, Local2) > + ShiftRight(P6BM, Local2, Local0) > + } > + if (LEqual(Arg0, 0x7)) { > + if(LEqual(P7BM, 0x0)) { > + Return(0x00) > + } > + > + Add (Local2, DerefOf(Index(APT7, Arg1)), Local2) > + if (LEqual(Local2, 0xFF)) { > + Return(0x00) > + } > + //Processor Bit mask is changed for core# only > + ShiftRight(Local2, 1, Local2) > + ShiftRight(P7BM, Local2, Local0) > + } > + > + And(Local0, 0x1, Local0) > + if(LEqual(Local0, 0x0)) { > + Return(0x00) > + } else { > + Return(0x01) > + } > + } // End Method CSTA > + > + //---------------------------------------------------------------- > + // Method CUID() > + // Return MADT ACPI Processor UID, AcpiProcessorId and _UID > + // Should match with AcpiProcessorId in C code > + // > + // Inputs: Arg0 =3D Socket ID > + // Inputs: Arg1 =3D Thread ID > + // Return _UID > + //----------------------------------------------------------------+ > + Method (CUID, 2) { > + Store(ShiftLeft(1, CNBS), Local1) > + Multiply(Arg0, local1, local1) > + Add(local1, Arg1, local1) > + > + Return (Local1) > + } > + > + //---------------------------------------------------------------- > + // Method LAPC() > + // Return the _MAT APIC data structure > + // > + // Inputs: Arg0 =3D Socket ID > + // Inputs: Arg1 =3D Thread ID > + // APID =3D TPID(Arg0, Arg1) > + // PUID =3D Socket ID << CNBS + Thread ID > + //----------------------------------------------------------------+ > + Method(LAPC, 2,Serialized) { > + > + Name(APIC, Buffer(SIZE_LAPIC_STRUC) {} ) // initialize a buffer wi= th > CRST size > + > + CreateByteField (APIC, 0x00, TYPE) // Type > + CreateByteField (APIC, 0x01, LLEN) // Length > + CreateByteField (APIC, 0x02, PUID) // ACPI Processor ID > + CreateByteField (APIC, 0x03, APID) // APIC ID > + CreateDwordField(APIC, 0x04, FLAG) // Flags > + > + Store(LAPIC_TYPE, TYPE) > + Store(SIZE_LAPIC_STRUC, LLEN) > + > + // Update APIC ID > + Store (\_SB.TPID(Arg0, Arg1), APID) > + > + // Update Flag > + if(LEqual(\_SB.CSTA(Arg0, Arg1), 0x00)) { > + Store(0x00, FLAG) > + Store(0xFF, PUID) > + Store(0xFF, APID) > + } else { > + Store(ShiftLeft(1, CNBS), Local1) > + Multiply(Arg0, local1, local1) > + Add(local1, Arg1, local1) > + Store(local1, PUID) > + > + //set Enable flag > + Store(0x01, FLAG) > + } > + > + // calculate PROCID based on APICID using same algorithm in > AcpiPlatformHook.c > + > + Return(APIC) > + } > + > + Method(X2AP, 2,Serialized) { > + > + Name(APIC, Buffer(SIZE_X2LAPIC_STRUC) {} ) // initialize a buffer = with > CRST siz > + > + CreateByteField (APIC, 0x00, TYPE) // Type > + CreateByteField (APIC, 0x01, LLEN) // Length > + CreateWordField (APIC, 0x02, RSVD) // Reserved 2 bytes > + CreateDwordField(APIC, 0x04, APID) // APIC ID > + CreateDwordField(APIC, 0x08, FLAG) // Flags > + CreateDwordField(APIC, 0x0C, PUID) // ACPI Processor UID > + > + Store(X2LAPIC_TYPE, TYPE) > + Store(SIZE_X2LAPIC_STRUC, LLEN) > + Store(0, RSVD) > + > + // Update APIC ID > + Store (\_SB.TPID(Arg0, Arg1), APID) > + > + // Update Flag > + if(LEqual(\_SB.CSTA(Arg0, Arg1), 0x00)) { > + Store(0x00, FLAG) > + Store(0xFFFFFFFF, APID) > + } else { > + //ProcId =3D socket# * MAX_THREADS_PER_SOCKET + thread# > + Store(ShiftLeft(1, CNBS), Local1) > + Multiply(Arg0, local1, local1) > + Add(local1, Arg1, local1) > + Store(local1, PUID) > + > + //set Enable flag > + Store(0x01, FLAG) > + > + } > + > + Return(APIC) > + > + } > + > + CPU_SOCKET_DEV(0) > + > +#if MAX_SOCKET > 1 > + CPU_SOCKET_DEV(1) > +#endif > + > +#if MAX_SOCKET > 2 > + CPU_SOCKET_DEV(2) > +#endif > + > +#if MAX_SOCKET > 3 > + CPU_SOCKET_DEV(3) > +#endif > + > +#if MAX_SOCKET > 4 > + CPU_SOCKET_DEV(4) > +#endif > + > +#if MAX_SOCKET > 5 > + CPU_SOCKET_DEV(5) > +#endif > + > +#if MAX_SOCKET > 6 > + CPU_SOCKET_DEV(6) > +#endif > + > +#if MAX_SOCKET > 7 > + CPU_SOCKET_DEV(7) > +#endif > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DS > DT.asl > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DS > DT.asl > new file mode 100644 > index 0000000000..b3f96f8ddb > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DS > DT.asl > @@ -0,0 +1,61 @@ > +/** @file > + ACPI DSDT table > + > + @copyright > + Copyright 2011 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +// > +// @NOTE: This should be read from hardware to reflect > +// real PCI exress base. Currently we do not have such > +// capability so hardcode is used instead. > +// > +#define PCI_EXPRESS_BASE 0x80000000 > + > +Scope(\_SB.PC00) { > + > + // > + // PCI-specific method's GUID > + // > + Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) > + // > + // PCI's _DSM - an attempt at modular _DSM implementation > + // When writing your own _DSM function that needs to include PCI- > specific methods, do this: > + // > + // Method(_YOUR_DSM,4){ > + // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } > + // ...continue your _DSM by checking different GUIDs... > + // else { return(0) } > + // } > + // > + Method(PCID, 4, Serialized) { > + If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID > + If(LGreaterEqual(Arg1,3)) { = // revision at least 3 > + If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } = // function > 0: list of supported functions > + If(LEqual(Arg2,8)) { Return (1) } = // function 8: Avoiding > Power-On Reset Delay Duplication on Sx Resume > + If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,On= es}) > } // function 9: Specifying Device Readiness Durations > + } > + } > + return (Buffer(1){0}) > + } > + > + Method(PCIC,1,Serialized) { > + If(LEqual(ECR1,1)) { > + If(LEqual(Arg0, PCIG)) { > + return (1) > + } > + } > + return (0) > + } > + > + // > + // Get the PCI express base address. > + // Currently hardcoded. > + // > + Method (GPCB) { > + Return (PCI_EXPRESS_BASE) > + } > +} > + > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EP > RPPlatform10nm.asl > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EP > RPPlatform10nm.asl > new file mode 100644 > index 0000000000..386fbdac59 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EP > RPPlatform10nm.asl > @@ -0,0 +1,19 @@ > +/** @file > + > + @copyright > + Copyright 2016 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +DefinitionBlock ("EPRPPlatform10nm.asl","DSDT",2,"INTEL","EPRP10NM",3) > +{ > + #include "CommonPlatform10nm.asi" > + #include "PlatformPciTree10nm_EPRP.asi" > + #include "AMLUPD.asl" > + #include "DSDT.asl" > + #include "Pch.asl" //This is in another package (PchPkg) > + #include "Platform.asl" > + #include "PlatformGpe10nm.asi" > + #include "IioPcieEdpcNotify10nm.asi" > +} // end of DSDT > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpg > aBus00.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp > gaBus00.asi > new file mode 100644 > index 0000000000..235e60650c > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp > gaBus00.asi > @@ -0,0 +1,158 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2016 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + Name (SUPP, 0) > + Name (CTRL, 0) > + > + Method(_OSC,4) { > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,0,CDW1) > + CreateDWordField(Arg3,4,CDW2) > + If(LGreater(Arg2,2)) { > + CreateDWordField(Arg3,8,CDW3) > + } > + > + > + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + // > + // Save Capabilities DWord2 & 3 > + // > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > + > + // > + // Only allow native hot plug control if OS supports > + // * ASPM > + // * MSI/MSI-X > + // > + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions= not > met? > + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. > + Sleep(1000) > + } > + > + // > + // Never allow SHPC (no SHPC controller in system) > + // > + And(CTRL, 0x1D, CTRL) > + //And (CTRL, 0x1C, CTRL) > + > + If (LNotEqual(Arg1,one)) { // unknown revision > + Or(CDW1,0x08,CDW1) > + } > + > + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked > + Or(CDW1,0x10,CDW1) > + } > + // > + // update DWORD3 in the buffer > + // > + Store(CTRL,CDW3) > + Return(Arg3) > + > + } Else { > + // > + // Just indicate unrecognized UUID > + // Leave it at that > + // > + Or (CDW1,4,CDW1) > + Store (0xEE, IO80) > + Return(Arg3) > + } > + } > + > + Method(_STA){ > + // Check if Virtual FPGA is present > + if(LEqual(P0FB, 0x1)) { > + // Virtual FPGA present and logically online > + Return(0x0F) > + } > + // Virtual FPGA logically offline > + Return(0x00) > + > + } // End Method STA > + > + Name (RBUF, ResourceTemplate () { > + WORDBusNumber( // Bus number resource (0); the bridge pro= duces > bus numbers for its subsequent buses > + ResourceProducer, // bit 0 of general flags is 1 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, // PosDecode > + 0x0000, // Granularity > + 0x0000, // Min > + 0x0000, // Max > + 0x0000, // Translation > + 0x0001, // Range Length =3D Max-Min+1 > + , > + , > + FBUS > + ) > + > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIX7 - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIX7 - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IX7 - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIX7 - > Patched by ACPI Platform Driver during POST) > + , > + , > + FPGM // DescriptorName populated so iASL output= s offset for > it in a .h file > + ) > + > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIXZ - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIXZ - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IXZ - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIXZ - > Patched by ACPI Platform Driver during POST) > + , > + , > + FIXZ // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + }) > + > + Method(_CRS, 0x0, NotSerialized) { > + /// > + /// Patch 32b memory > + /// > + CreateDwordField(^RBUF, ^FPGM._MIN, FMN1) > + CreateDwordField(^RBUF, ^FPGM._MAX, FMX1) > + CreateDwordField(^RBUF, ^FPGM._LEN, FLN1) > + Store(FMB0, FMN1) > + Store(FML0, FMX1) > + Subtract (FMX1, FMN1, FLN1) > + Add (FLN1, 1, FLN1) > + > + /// > + /// Patch _BBN > + /// > + If(LGreater(FBL0, FBB0)) { > + CreateWordField(^RBUF, ^FBUS._MIN, BMIN) > + CreateWordField(^RBUF, ^FBUS._MAX, BMAX) > + CreateWordField(^RBUF, ^FBUS._LEN, BLEN) > + Store(FBB0, BMIN) > + Store(FBL0, BMAX) > + Subtract (BMAX, BMIN, BLEN) > + Add (BLEN, 1, BLEN) > + } > + Return (RBUF) > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpg > aBus01.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp > gaBus01.asi > new file mode 100644 > index 0000000000..cecf469c9d > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp > gaBus01.asi > @@ -0,0 +1,158 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2016 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + Name (SUPP, 0) > + Name (CTRL, 0) > + > + Method(_OSC,4) { > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,0,CDW1) > + CreateDWordField(Arg3,4,CDW2) > + If(LGreater(Arg2,2)) { > + CreateDWordField(Arg3,8,CDW3) > + } > + > + > + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + // > + // Save Capabilities DWord2 & 3 > + // > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > + > + // > + // Only allow native hot plug control if OS supports > + // * ASPM > + // * MSI/MSI-X > + // > + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions= not > met? > + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. > + Sleep(1000) > + } > + > + // > + // Never allow SHPC (no SHPC controller in system) > + // > + And(CTRL, 0x1D, CTRL) > + //And (CTRL, 0x1C, CTRL) > + > + If (LNotEqual(Arg1,one)) { // unknown revision > + Or(CDW1,0x08,CDW1) > + } > + > + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked > + Or(CDW1,0x10,CDW1) > + } > + // > + // update DWORD3 in the buffer > + // > + Store(CTRL,CDW3) > + Return(Arg3) > + > + } Else { > + // > + // Just indicate unrecognized UUID > + // Leave it at that > + // > + Or (CDW1,4,CDW1) > + Store (0xEE, IO80) > + Return(Arg3) > + } > + } > + > + Method(_STA){ > + // Check if Virtual FPGA is present > + if(LEqual(P1FB, 0x1)) { > + // Virtual FPGA present and logically online > + Return(0x0F) > + } > + // Virtual FPGA logically offline > + Return(0x00) > + > + } // End Method STA > + > + Name (RBUF, ResourceTemplate () { > + WORDBusNumber( // Bus number resource (0); the bridge pro= duces > bus numbers for its subsequent buses > + ResourceProducer, // bit 0 of general flags is 1 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, // PosDecode > + 0x0000, // Granularity > + 0x0000, // Min > + 0x0000, // Max > + 0x0000, // Translation > + 0x0001, // Range Length =3D Max-Min+1 > + , > + , > + FBUS > + ) > + > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIX7 - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIX7 - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IX7 - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIX7 - > Patched by ACPI Platform Driver during POST) > + , > + , > + FPGM // DescriptorName populated so iASL output= s offset for > it in a .h file > + ) > + > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIXZ - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIXZ - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IXZ - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIXZ - > Patched by ACPI Platform Driver during POST) > + , > + , > + FIXZ // DescriptorName populated so iASL output= s offset for it > in a .h file > + > + ) > + }) > + > + Method(_CRS, 0x0, NotSerialized) { > + /// > + /// Patch 32b memory > + /// > + CreateDwordField(^RBUF, ^FPGM._MIN, FMN1) > + CreateDwordField(^RBUF, ^FPGM._MAX, FMX1) > + CreateDwordField(^RBUF, ^FPGM._LEN, FLN1) > + Store(FMB1, FMN1) > + Store(FML1, FMX1) > + Subtract (FMX1, FMN1, FLN1) > + Add (FLN1, 1, FLN1) > + > + /// > + /// Patch _BBN > + /// > + If(LGreater(FBL1, FBB1)) { > + CreateWordField(^RBUF, ^FBUS._MIN, BMIN) > + CreateWordField(^RBUF, ^FBUS._MAX, BMAX) > + CreateWordField(^RBUF, ^FBUS._LEN, BLEN) > + Store(FBB1, BMIN) > + Store(FBL1, BMAX) > + Subtract (BMAX, BMIN, BLEN) > + Add (BLEN, 1, BLEN) > + } > + Return (RBUF) > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpg > aBus02.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp > gaBus02.asi > new file mode 100644 > index 0000000000..e4731a63c1 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp > gaBus02.asi > @@ -0,0 +1,157 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2016 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + Name (SUPP, 0) > + Name (CTRL, 0) > + > + Method(_OSC,4) { > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,0,CDW1) > + CreateDWordField(Arg3,4,CDW2) > + If(LGreater(Arg2,2)) { > + CreateDWordField(Arg3,8,CDW3) > + } > + > + > + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + // > + // Save Capabilities DWord2 & 3 > + // > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > + > + // > + // Only allow native hot plug control if OS supports > + // * ASPM > + // * MSI/MSI-X > + // > + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions= not > met? > + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. > + Sleep(1000) > + } > + > + // > + // Never allow SHPC (no SHPC controller in system) > + // > + And(CTRL, 0x1D, CTRL) > + //And (CTRL, 0x1C, CTRL) > + > + If (LNotEqual(Arg1,one)) { // unknown revision > + Or(CDW1,0x08,CDW1) > + } > + > + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked > + Or(CDW1,0x10,CDW1) > + } > + // > + // update DWORD3 in the buffer > + // > + Store(CTRL,CDW3) > + Return(Arg3) > + > + } Else { > + // > + // Just indicate unrecognized UUID > + // Leave it at that > + // > + Or (CDW1,4,CDW1) > + Store (0xEE, IO80) > + Return(Arg3) > + } > + } > + > + Method(_STA){ > + // Check if Virtual FPGA is present > + if(LEqual(P2FB, 0x1)) { > + // Virtual FPGA present and logically online > + Return(0x0F) > + } > + // Virtual FPGA logically offline > + Return(0x00) > + > + } // End Method STA > + > + Name (RBUF, ResourceTemplate () { > + WORDBusNumber( // Bus number resource (0); the bridge pro= duces > bus numbers for its subsequent buses > + ResourceProducer, // bit 0 of general flags is 1 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, // PosDecode > + 0x0000, // Granularity > + 0x0000, // Min > + 0x0000, // Max > + 0x0000, // Translation > + 0x0001, // Range Length =3D Max-Min+1 > + , > + , > + FBUS > + ) > + > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIX7 - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIX7 - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IX7 - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIX7 - > Patched by ACPI Platform Driver during POST) > + , > + , > + FPGM // DescriptorName populated so iASL output= s offset for > it in a .h file > + ) > + > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIXZ - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIXZ - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IXZ - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIXZ - > Patched by ACPI Platform Driver during POST) > + , > + , > + FIXZ // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + }) > + > + Method(_CRS, 0x0, NotSerialized) { > + /// > + /// Patch 32b memory > + /// > + CreateDwordField(^RBUF, ^FPGM._MIN, FMN1) > + CreateDwordField(^RBUF, ^FPGM._MAX, FMX1) > + CreateDwordField(^RBUF, ^FPGM._LEN, FLN1) > + Store(FMB2, FMN1) > + Store(FML2, FMX1) > + Subtract (FMX1, FMN1, FLN1) > + Add (FLN1, 1, FLN1) > + > + /// > + /// Patch _BBN > + /// > + If(LGreater(FBL2, FBB2)) { > + CreateWordField(^RBUF, ^FBUS._MIN, BMIN) > + CreateWordField(^RBUF, ^FBUS._MAX, BMAX) > + CreateWordField(^RBUF, ^FBUS._LEN, BLEN) > + Store(FBB2, BMIN) > + Store(FBL2, BMAX) > + Subtract (BMAX, BMIN, BLEN) > + Add (BLEN, 1, BLEN) > + } > + Return (RBUF) > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpg > aBus03.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp > gaBus03.asi > new file mode 100644 > index 0000000000..51be7989ac > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp > gaBus03.asi > @@ -0,0 +1,157 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2016 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + Name (SUPP, 0) > + Name (CTRL, 0) > + > + Method(_OSC,4) { > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,0,CDW1) > + CreateDWordField(Arg3,4,CDW2) > + If(LGreater(Arg2,2)) { > + CreateDWordField(Arg3,8,CDW3) > + } > + > + > + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + // > + // Save Capabilities DWord2 & 3 > + // > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > + > + // > + // Only allow native hot plug control if OS supports > + // * ASPM > + // * MSI/MSI-X > + // > + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions= not > met? > + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. > + Sleep(1000) > + } > + > + // > + // Never allow SHPC (no SHPC controller in system) > + // > + And(CTRL, 0x1D, CTRL) > + //And (CTRL, 0x1C, CTRL) > + > + If (LNotEqual(Arg1,one)) { // unknown revision > + Or(CDW1,0x08,CDW1) > + } > + > + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked > + Or(CDW1,0x10,CDW1) > + } > + // > + // update DWORD3 in the buffer > + // > + Store(CTRL,CDW3) > + Return(Arg3) > + > + } Else { > + // > + // Just indicate unrecognized UUID > + // Leave it at that > + // > + Or (CDW1,4,CDW1) > + Store (0xEE, IO80) > + Return(Arg3) > + } > + } > + > + Method(_STA){ > + // Check if Virtual FPGA is present > + if(LEqual(P3FB, 0x1)) { > + // Virtual FPGA present and logically online > + Return(0x0F) > + } > + // Virtual FPGA logically offline > + Return(0x00) > + > + } // End Method STA > + > + Name (RBUF, ResourceTemplate () { > + WORDBusNumber( // Bus number resource (0); the bridge pro= duces > bus numbers for its subsequent buses > + ResourceProducer, // bit 0 of general flags is 1 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, // PosDecode > + 0x0000, // Granularity > + 0x0000, // Min > + 0x0000, // Max > + 0x0000, // Translation > + 0x0001, // Range Length =3D Max-Min+1 > + , > + , > + FBUS > + ) > + > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIX7 - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIX7 - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IX7 - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIX7 - > Patched by ACPI Platform Driver during POST) > + , > + , > + FPGM // DescriptorName populated so iASL output= s offset for > it in a .h file > + ) > + > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIXZ - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIXZ - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IXZ - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIXZ - > Patched by ACPI Platform Driver during POST) > + , > + , > + FIXZ // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + }) > + > + Method(_CRS, 0x0, NotSerialized) { > + /// > + /// Patch 32b memory > + /// > + CreateDwordField(^RBUF, ^FPGM._MIN, FMN1) > + CreateDwordField(^RBUF, ^FPGM._MAX, FMX1) > + CreateDwordField(^RBUF, ^FPGM._LEN, FLN1) > + Store(FMB3, FMN1) > + Store(FML3, FMX1) > + Subtract (FMX1, FMN1, FLN1) > + Add (FLN1, 1, FLN1) > + > + /// > + /// Patch _BBN > + /// > + If(LGreater(FBL3, FBB3)) { > + CreateWordField(^RBUF, ^FBUS._MIN, BMIN) > + CreateWordField(^RBUF, ^FBUS._MAX, BMAX) > + CreateWordField(^RBUF, ^FBUS._LEN, BLEN) > + Store(FBB3, BMIN) > + Store(FBL3, BMAX) > + Subtract (BMAX, BMIN, BLEN) > + Add (BLEN, 1, BLEN) > + } > + Return (RBUF) > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gp > e.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gp > e.asi > new file mode 100644 > index 0000000000..d695b13df9 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gp > e.asi > @@ -0,0 +1,137 @@ > +/** @file > + ACPI DSDT table > + > +@copyright > + Copyright 2011 - 2018 Intel Corporation. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // General Purpose Events. This Scope handles the Run-time and > + // Wake-time SCIs. The specific method called will be determined by > + // the _Lxx value, where xx equals the bit location in the General > + // Purpose Event register(s). > + > + > + // > + // If the Root Port is enabled, run PCI_EXP_STS handler > + // > + If(LNotEqual(\_SB.PC00.RP01.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP01.HPME() > + Notify(\_SB.PC00.RP01, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP02.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP02.HPME() > + Notify(\_SB.PC00.RP02, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP03.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP03.HPME() > + Notify(\_SB.PC00.RP03, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP04.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP04.HPME() > + Notify(\_SB.PC00.RP04, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP05.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP05.HPME() > + Notify(\_SB.PC00.RP05, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP06.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP06.HPME() > + Notify(\_SB.PC00.RP06, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP07.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP07.HPME() > + Notify(\_SB.PC00.RP07, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP08.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP08.HPME() > + Notify(\_SB.PC00.RP08, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP09.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP09.HPME() > + Notify(\_SB.PC00.RP09, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP10.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP10.HPME() > + Notify(\_SB.PC00.RP10, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP11.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP11.HPME() > + Notify(\_SB.PC00.RP11, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP12.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP12.HPME() > + Notify(\_SB.PC00.RP12, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP13.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP13.HPME() > + Notify(\_SB.PC00.RP13, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP14.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP14.HPME() > + Notify(\_SB.PC00.RP14, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP15.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP15.HPME() > + Notify(\_SB.PC00.RP15, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP16.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP16.HPME() > + Notify(\_SB.PC00.RP16, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP17.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP17.HPME() > + Notify(\_SB.PC00.RP17, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP18.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP18.HPME() > + Notify(\_SB.PC00.RP18, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP19.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP19.HPME() > + Notify(\_SB.PC00.RP19, 0x02) > + } > + > + If(LNotEqual(\_SB.PC00.RP20.VDID,0xFFFFFFFF)) > + { > + \_SB.PC00.RP20.HPME() > + Notify(\_SB.PC00.RP20, 0x02) > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieEdpcGpe.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieEdpcGpe.asi > new file mode 100644 > index 0000000000..7180f6d607 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieEdpcGpe.asi > @@ -0,0 +1,16 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + External(\_SB.EDGH, MethodObj) > + > + // > + // Handle eDPC SWGPE event > + // > + If (CondRefOf (\_SB.EDGH)) > + { > + \_SB.EDGH () > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieEdpcNotify10nm.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieEdpcNotify10nm.asi > new file mode 100644 > index 0000000000..78759e32f3 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieEdpcNotify10nm.asi > @@ -0,0 +1,183 @@ > +/** @file > + > + @copyright > + Copyright 2016 - 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > +External(\_SB.EDTM, MethodObj) > +External (\_SB.EDNT, FieldUnitObj) > +External (\_SB.EDVD, FieldUnitObj) > + > +#define PCIE_EDPC_NOTIFY(stack, port) = \ > + store (\_SB.stack._SEG, Local0) = \ > + store (\_SB.stack._BBN, Local1) = \ > + store (\_SB.stack.port._ADR, Local2) = \ > + And (Local2, 0xffff, Local3) = \ > + ShiftRight (Local2, 16, Local4) = \ > + If (\_SB.EDTM(Local0, Local1, Local4, Local3)) { = \ > + If (\_SB.EDNT) { = \ > + /* = \ > + we are going to notify this device, set the valid flag to > EDPC_INFO_NOTIFIED \ > + */ = \ > + store (2, \_SB.EDVD) = \ > + Notify(\_SB.stack.port, 0xf) /*Error Eject*/ = \ > + } else { = \ > + /* = \ > + we are going to notify this device, set the valid flag to > EDPC_INFO_NOTIFIED \ > + */ = \ > + store (2, \_SB.EDVD) = \ > + Notify(\_SB.stack.port, 0) /*Bus Check*/ = \ > + } = \ > + } > + > +Scope (\_SB) { > + // > + // eDPC Notify Method > + // > + Method (EDNM, 0) { > + // PC01 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC01, BR1A) > + PCIE_EDPC_NOTIFY(PC01, BR1B) > + PCIE_EDPC_NOTIFY(PC01, BR1C) > + PCIE_EDPC_NOTIFY(PC01, BR1D) > + > + // PC02 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC02, BR2A) > + PCIE_EDPC_NOTIFY(PC02, BR2B) > + PCIE_EDPC_NOTIFY(PC02, BR2C) > + PCIE_EDPC_NOTIFY(PC02, BR2D) > + > + // PC03 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC03, BR3A) > + PCIE_EDPC_NOTIFY(PC03, BR3B) > + PCIE_EDPC_NOTIFY(PC03, BR3C) > + PCIE_EDPC_NOTIFY(PC03, BR3D) > + > + // PC04 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC04, BR4A) > + PCIE_EDPC_NOTIFY(PC04, BR4B) > + PCIE_EDPC_NOTIFY(PC04, BR4C) > + PCIE_EDPC_NOTIFY(PC04, BR4D) > + > + // PC05 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC05, BR5A) > + PCIE_EDPC_NOTIFY(PC05, BR5B) > + PCIE_EDPC_NOTIFY(PC05, BR5C) > + PCIE_EDPC_NOTIFY(PC05, BR5D) > + > + #if MAX_SOCKET > 1 > + // PC07 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus check > + PCIE_EDPC_NOTIFY(PC07, QR1A) > + PCIE_EDPC_NOTIFY(PC07, QR1B) > + PCIE_EDPC_NOTIFY(PC07, QR1C) > + PCIE_EDPC_NOTIFY(PC07, QR1D) > + > + // PC08 Port 2A PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC08, QR2A) > + PCIE_EDPC_NOTIFY(PC08, QR2B) > + PCIE_EDPC_NOTIFY(PC08, QR2C) > + PCIE_EDPC_NOTIFY(PC08, QR2D) > + > + // PC09 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC09, QR3A) > + PCIE_EDPC_NOTIFY(PC09, QR3B) > + PCIE_EDPC_NOTIFY(PC09, QR3C) > + PCIE_EDPC_NOTIFY(PC09, QR3D) > + > + // PC08 Port 2A PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC10, QR4A) > + PCIE_EDPC_NOTIFY(PC10, QR4B) > + PCIE_EDPC_NOTIFY(PC10, QR4C) > + PCIE_EDPC_NOTIFY(PC10, QR4D) > + > + // PC09 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC11, QR5A) > + PCIE_EDPC_NOTIFY(PC11, QR5B) > + PCIE_EDPC_NOTIFY(PC11, QR5C) > + PCIE_EDPC_NOTIFY(PC11, QR5D) > + #endif > + #if MAX_SOCKET > 2 > + // PC13 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus check > + PCIE_EDPC_NOTIFY(PC13, RR1A) > + PCIE_EDPC_NOTIFY(PC13, RR1B) > + PCIE_EDPC_NOTIFY(PC13, RR1C) > + PCIE_EDPC_NOTIFY(PC13, RR1D) > + > + // PC14 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC14, RR2A) > + PCIE_EDPC_NOTIFY(PC14, RR2B) > + PCIE_EDPC_NOTIFY(PC14, RR2C) > + PCIE_EDPC_NOTIFY(PC14, RR2D) > + > + // PC15 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC15, RR3A) > + PCIE_EDPC_NOTIFY(PC15, RR3B) > + PCIE_EDPC_NOTIFY(PC15, RR3C) > + PCIE_EDPC_NOTIFY(PC15, RR3D) > + > + // PC16 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC16, RR4A) > + PCIE_EDPC_NOTIFY(PC16, RR4B) > + PCIE_EDPC_NOTIFY(PC16, RR4C) > + PCIE_EDPC_NOTIFY(PC16, RR4D) > + > + // PC17 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC17, RR5A) > + PCIE_EDPC_NOTIFY(PC17, RR5B) > + PCIE_EDPC_NOTIFY(PC17, RR5C) > + PCIE_EDPC_NOTIFY(PC17, RR5D) > + #endif > + #if MAX_SOCKET > 3 > + // PC19 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC19, SR1A) > + PCIE_EDPC_NOTIFY(PC19, SR1B) > + PCIE_EDPC_NOTIFY(PC19, SR1C) > + PCIE_EDPC_NOTIFY(PC19, SR1D) > + > + // PC20 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC20, SR2A) > + PCIE_EDPC_NOTIFY(PC20, SR2B) > + PCIE_EDPC_NOTIFY(PC20, SR2C) > + PCIE_EDPC_NOTIFY(PC20, SR2D) > + > + // PC21 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC21, SR3A) > + PCIE_EDPC_NOTIFY(PC21, SR3B) > + PCIE_EDPC_NOTIFY(PC21, SR3C) > + PCIE_EDPC_NOTIFY(PC21, SR3D) > + > + // PC21 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC22, SR4A) > + PCIE_EDPC_NOTIFY(PC22, SR4B) > + PCIE_EDPC_NOTIFY(PC22, SR4C) > + PCIE_EDPC_NOTIFY(PC22, SR4D) > + > + // PC22 PCI-Ex eDPC > + // If this is the eDPC event trigger, notify error eject or bus chec= k > + PCIE_EDPC_NOTIFY(PC23, SR5A) > + PCIE_EDPC_NOTIFY(PC23, SR5B) > + PCIE_EDPC_NOTIFY(PC23, SR5C) > + PCIE_EDPC_NOTIFY(PC23, SR5D) > + #endif > + } //endof the method EDGH > +} > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieEdpcOst.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieEdpcOst.asi > new file mode 100644 > index 0000000000..13c76067c3 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieEdpcOst.asi > @@ -0,0 +1,16 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + External(\_SB.EDOS, MethodObj) > + > + // > + // Handle eDPC _OST > + // > + If (CondRefOf (\_SB.EDOS)) > + { > + \_SB.EDOS (Arg0, Arg1, Arg2) > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieHotPlugGpeHandler10nm.asl > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieHotPlugGpeHandler10nm.asl > new file mode 100644 > index 0000000000..09ff73e148 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > PcieHotPlugGpeHandler10nm.asl > @@ -0,0 +1,1322 @@ > +/** @file > + > + @copyright > + Copyright 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // > + // Delay introduced as initial delay after entering ACPI hotplug metho= d > + // > + Sleep (200) > + Store (0x01, IO80) > + Sleep (10) > + Store (0,Local1) > + > + // PC00 Port 1A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC01.BR1A.PMEP,1) ) { > + Store(\_SB.PC01.BR1A.PMEH(1), Local0) > + } else { > + Store (\_SB.PC01.BR1A.HPEH(1), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(1, Local1) > + Notify(\_SB.PC01.BR1A, Local0) > + } > + > + // PC00 Port 1B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC01.BR1B.PMEP,1) ) { > + Store(\_SB.PC01.BR1B.PMEH(2), Local0) > + } else { > + Store (\_SB.PC01.BR1B.HPEH(2), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(2, Local1) > + Notify(\_SB.PC01.BR1B, Local0) > + } > + > + // PC00 Port 1C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC01.BR1C.PMEP,1) ) { > + Store(\_SB.PC01.BR1C.PMEH(3), Local0) > + } else { > + Store (\_SB.PC01.BR1C.HPEH(3), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(3, Local1) > + Notify(\_SB.PC01.BR1C, Local0) > + } > + > + // PC00 Port 1D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC01.BR1D.PMEP,1) ) { > + Store(\_SB.PC01.BR1D.PMEH(4), Local0) > + } else { > + Store (\_SB.PC01.BR1D.HPEH(4), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(4, Local1) > + Notify(\_SB.PC01.BR1D, Local0) > + } > + > + > + // PC01 Port 2A PCI-Ex Hot Plug > + If( LEqual(\_SB.PC02.BR2A.PMEP,1) ) { > + Store(\_SB.PC02.BR2A.PMEH(5), Local0) > + } else { > + Store (\_SB.PC02.BR2A.HPEH(5), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(5, Local1) > + Notify(\_SB.PC02.BR2A, Local0) > + } > + > + // PC01 Port 2B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC02.BR2B.PMEP,1) ) { > + Store(\_SB.PC02.BR2B.PMEH(6), Local0) > + } else { > + Store (\_SB.PC02.BR2B.HPEH(6), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(6, Local1) > + Notify(\_SB.PC02.BR2B, Local0) > + } > + > + // PC01 Port 2C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC02.BR2C.PMEP,1) ) { > + Store(\_SB.PC02.BR2C.PMEH(7), Local0) > + } else { > + Store (\_SB.PC02.BR2C.HPEH(7), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(7, Local1) > + Notify(\_SB.PC02.BR2C, Local0) > + } > + > + // PC01 Port 2D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC02.BR2D.PMEP,1) ) { > + Store(\_SB.PC02.BR2D.PMEH(8), Local0) > + } else { > + Store (\_SB.PC02.BR2D.HPEH(8), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(8, Local1) > + Notify(\_SB.PC02.BR2D, Local0) > + } > + > + // PC01 Port 3A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC03.BR3A.PMEP,1) ) { > + Store(\_SB.PC03.BR3A.PMEH(9), Local0) > + } else { > + Store (\_SB.PC03.BR3A.HPEH(9), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(9, Local1) > + Notify(\_SB.PC03.BR3A, Local0) > + } > + > + // PC01 Port 3B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC03.BR3B.PMEP,1) ) { > + Store(\_SB.PC03.BR3B.PMEH(10), Local0) > + } else { > + Store (\_SB.PC03.BR3B.HPEH(10), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(10, Local1) > + Notify(\_SB.PC03.BR3B, Local0) > + } > + > + // PC01 Port 3C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC03.BR3C.PMEP,1) ) { > + Store(\_SB.PC03.BR3C.PMEH(11), Local0) > + } else { > + Store (\_SB.PC03.BR3C.HPEH(11), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(11, Local1) > + Notify(\_SB.PC03.BR3C, Local0) > + } > + > + // PC01 Port 3D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC03.BR3D.PMEP,1) ) { > + Store(\_SB.PC03.BR3D.PMEH(12), Local0) > + } else { > + Store (\_SB.PC03.BR3D.HPEH(12), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(12, Local1) > + Notify(\_SB.PC03.BR3D, Local0) > + } > + > + // PC02 Port 4A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC04.BR4A.PMEP,1) ) { > + Store(\_SB.PC04.BR4A.PMEH(13), Local0) > + } else { > + Store (\_SB.PC04.BR4A.HPEH(13), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(13, Local1) > + Notify(\_SB.PC04.BR4A, Local0) > + } > + > + // PC02 Port 4B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC04.BR4B.PMEP,1) ) { > + Store(\_SB.PC04.BR4B.PMEH(14), Local0) > + } else { > + Store (\_SB.PC04.BR4B.HPEH(14), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(14, Local1) > + Notify(\_SB.PC04.BR4B, Local0) > + } > + > + // PC02 Port 4C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC04.BR4C.PMEP,1) ) { > + Store(\_SB.PC04.BR4C.PMEH(15), Local0) > + } else { > + Store (\_SB.PC04.BR4C.HPEH(15), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(15, Local1) > + Notify(\_SB.PC04.BR4C, Local0) > + } > + > + // PC02 Port 4D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC04.BR4D.PMEP,1) ) { > + Store(\_SB.PC04.BR4D.PMEH(16), Local0) > + } else { > + Store (\_SB.PC04.BR4D.HPEH(16), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(16, Local1) > + Notify(\_SB.PC04.BR4D, Local0) > + } > + > + // PC02 Port 5A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC05.BR5A.PMEP,1) ) { > + Store(\_SB.PC05.BR5A.PMEH(17), Local0) > + } else { > + Store (\_SB.PC05.BR5A.HPEH(17), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(17, Local1) > + Notify(\_SB.PC05.BR5A, Local0) > + } > + > + // PC02 Port 5B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC05.BR5B.PMEP,1) ) { > + Store(\_SB.PC05.BR5B.PMEH(18), Local0) > + } else { > + Store (\_SB.PC05.BR5B.HPEH(18), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(18, Local1) > + Notify(\_SB.PC05.BR5B, Local0) > + } > + > + // PC02 Port 5C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC05.BR5C.PMEP,1) ) { > + Store(\_SB.PC05.BR5C.PMEH(19), Local0) > + } else { > + Store (\_SB.PC05.BR5C.HPEH(19), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(19, Local1) > + Notify(\_SB.PC05.BR5C, Local0) > + } > + > + // PC02 Port 5D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC05.BR5D.PMEP,1) ) { > + Store(\_SB.PC05.BR5D.PMEH(20), Local0) > + } else { > + Store (\_SB.PC05.BR5D.HPEH(20), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(20, Local1) > + Notify(\_SB.PC05.BR5D, Local0) > + } > + > +#if MAX_SOCKET > 1 > + > + > + // PC06 Port 1A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC07.QR1A.PMEP,1) ) { > + Store(\_SB.PC07.QR1A.PMEH(1), Local0) > + } else { > + Store (\_SB.PC07.QR1A.HPEH(1), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(1, Local1) > + Notify(\_SB.PC07.QR1A, Local0) > + } > + > + // PC06 Port 1B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC07.QR1B.PMEP,1) ) { > + Store(\_SB.PC07.QR1B.PMEH(2), Local0) > + } else { > + Store (\_SB.PC07.QR1B.HPEH(2), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(2, Local1) > + Notify(\_SB.PC07.QR1B, Local0) > + } > + > + // PC06 Port 1C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC07.QR1C.PMEP,1) ) { > + Store(\_SB.PC07.QR1C.PMEH(3), Local0) > + } else { > + Store (\_SB.PC07.QR1C.HPEH(3), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(3, Local1) > + Notify(\_SB.PC07.QR1C, Local0) > + } > + > + // PC06 Port 1D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC07.QR1D.PMEP,1) ) { > + Store(\_SB.PC07.QR1D.PMEH(4), Local0) > + } else { > + Store (\_SB.PC07.QR1D.HPEH(4), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(4, Local1) > + Notify(\_SB.PC07.QR1D, Local0) > + } > + > + // PC04 Port 2A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC08.QR2A.PMEP,1) ) { > + Store(\_SB.PC08.QR2A.PMEH(5), Local0) > + } else { > + Store (\_SB.PC08.QR2A.HPEH(5), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(5, Local1) > + Notify(\_SB.PC08.QR2A, Local0) > + } > + > + // PC04 Port 2B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC08.QR2B.PMEP,1) ) { > + Store(\_SB.PC08.QR2B.PMEH(6), Local0) > + } else { > + Store (\_SB.PC08.QR2B.HPEH(6), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(6, Local1) > + Notify(\_SB.PC08.QR2B, Local0) > + } > + > + // PC04 Port 2C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC08.QR2C.PMEP,1) ) { > + Store(\_SB.PC08.QR2C.PMEH(7), Local0) > + } else { > + Store (\_SB.PC08.QR2C.HPEH(7), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(7, Local1) > + Notify(\_SB.PC08.QR2C, Local0) > + } > + > + // PC04 Port 2D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC08.QR2D.PMEP,1) ) { > + Store(\_SB.PC08.QR2D.PMEH(8), Local0) > + } else { > + Store (\_SB.PC08.QR2D.HPEH(8), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(8, Local1) > + Notify(\_SB.PC08.QR2D, Local0) > + } > + > + // PC04 Port 3A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC09.QR3A.PMEP,1) ) { > + Store(\_SB.PC09.QR3A.PMEH(9), Local0) > + } else { > + Store (\_SB.PC09.QR3A.HPEH(9), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(9, Local1) > + Notify(\_SB.PC09.QR3A, Local0) > + } > + > + // PC04 Port 3B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC09.QR3B.PMEP,1) ) { > + Store(\_SB.PC09.QR3B.PMEH(10), Local0) > + } else { > + Store (\_SB.PC09.QR3B.HPEH(10), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(10, Local1) > + Notify(\_SB.PC09.QR3B, Local0) > + } > + > + // PC04 Port 3C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC09.QR3C.PMEP,1) ) { > + Store(\_SB.PC09.QR3C.PMEH(11), Local0) > + } else { > + Store (\_SB.PC09.QR3C.HPEH(11), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(11, Local1) > + Notify(\_SB.PC09.QR3C, Local0) > + } > + > + // PC04 Port 3D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC09.QR3D.PMEP,1) ) { > + Store(\_SB.PC09.QR3D.PMEH(12), Local0) > + } else { > + Store (\_SB.PC09.QR3D.HPEH(12), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(12, Local1) > + Notify(\_SB.PC09.QR3D, Local0) > + } > + > + // PC10 Port 4A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC10.QR4A.PMEP,1) ) { > + Store(\_SB.PC10.QR4A.PMEH(13), Local0) > + } else { > + Store (\_SB.PC10.QR4A.HPEH(13), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(13, Local1) > + Notify(\_SB.PC10.QR4A, Local0) > + } > + > + // PC10 Port 4B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC10.QR4B.PMEP,1) ) { > + Store(\_SB.PC10.QR4B.PMEH(14), Local0) > + } else { > + Store (\_SB.PC10.QR4B.HPEH(14), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(14, Local1) > + Notify(\_SB.PC10.QR4B, Local0) > + } > + > + // PC10 Port 4C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC10.QR4C.PMEP,1) ) { > + Store(\_SB.PC10.QR4C.PMEH(15), Local0) > + } else { > + Store (\_SB.PC10.QR4C.HPEH(15), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(15, Local1) > + Notify(\_SB.PC10.QR4C, Local0) > + } > + > + // PC10 Port 4D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC10.QR4D.PMEP,1) ) { > + Store(\_SB.PC10.QR4D.PMEH(16), Local0) > + } else { > + Store (\_SB.PC10.QR4D.HPEH(16), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(16, Local1) > + Notify(\_SB.PC10.QR4D, Local0) > + } > + > + // PC10 Port 5A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC11.QR5A.PMEP,1) ) { > + Store(\_SB.PC11.QR5A.PMEH(17), Local0) > + } else { > + Store (\_SB.PC11.QR5A.HPEH(17), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(17, Local1) > + Notify(\_SB.PC11.QR5A, Local0) > + } > + > + // PC10 Port 5B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC11.QR5B.PMEP,1) ) { > + Store(\_SB.PC11.QR5B.PMEH(18), Local0) > + } else { > + Store (\_SB.PC11.QR5B.HPEH(18), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(18, Local1) > + Notify(\_SB.PC11.QR5B, Local0) > + } > + > + // PC10 Port 5C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC11.QR5C.PMEP,1) ) { > + Store(\_SB.PC11.QR5C.PMEH(19), Local0) > + } else { > + Store (\_SB.PC11.QR5C.HPEH(19), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(19, Local1) > + Notify(\_SB.PC11.QR5C, Local0) > + } > + > + // PC10 Port 5D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC11.QR5D.PMEP,1) ) { > + Store(\_SB.PC11.QR5D.PMEH(20), Local0) > + } else { > + Store (\_SB.PC11.QR5D.HPEH(20), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(20, Local1) > + Notify(\_SB.PC11.QR5D, Local0) > + } > +#endif > +#if MAX_SOCKET > 2 > + > + // PC06 Port 1A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC13.RR1A.PMEP,1) ) { > + Store(\_SB.PC13.RR1A.PMEH(1), Local0) > + } else { > + Store (\_SB.PC13.RR1A.HPEH(1), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(1, Local1) > + Notify(\_SB.PC13.RR1A, Local0) > + } > + > + // PC06 Port 1B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC13.RR1B.PMEP,1) ) { > + Store(\_SB.PC13.RR1B.PMEH(2), Local0) > + } else { > + Store (\_SB.PC13.RR1B.HPEH(2), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(2, Local1) > + Notify(\_SB.PC13.RR1B, Local0) > + } > + > + // PC06 Port 1C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC13.RR1C.PMEP,1) ) { > + Store(\_SB.PC13.RR1C.PMEH(3), Local0) > + } else { > + Store (\_SB.PC13.RR1C.HPEH(3), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(3, Local1) > + Notify(\_SB.PC13.RR1C, Local0) > + } > + > + // PC06 Port 1D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC13.RR1D.PMEP,1) ) { > + Store(\_SB.PC13.RR1D.PMEH(4), Local0) > + } else { > + Store (\_SB.PC13.RR1D.HPEH(4), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(4, Local1) > + Notify(\_SB.PC13.RR1D, Local0) > + } > + > + // PC07 Port 2A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC14.RR2A.PMEP,1) ) { > + Store(\_SB.PC14.RR2A.PMEH(5), Local0) > + } else { > + Store (\_SB.PC14.RR2A.HPEH(5), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(5, Local1) > + Notify(\_SB.PC14.RR2A, Local0) > + } > + > + // PC07 Port 2B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC14.RR2B.PMEP,1) ) { > + Store(\_SB.PC14.RR2B.PMEH(6), Local0) > + } else { > + Store (\_SB.PC14.RR2B.HPEH(6), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(6, Local1) > + Notify(\_SB.PC14.RR2B, Local0) > + } > + > + // PC07 Port 2C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC14.RR2C.PMEP,1) ) { > + Store(\_SB.PC14.RR2C.PMEH(7), Local0) > + } else { > + Store (\_SB.PC14.RR2C.HPEH(7), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(7, Local1) > + Notify(\_SB.PC14.RR2C, Local0) > + } > + > + // PC07 Port 2D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC14.RR2D.PMEP,1) ) { > + Store(\_SB.PC14.RR2D.PMEH(8), Local0) > + } else { > + Store (\_SB.PC14.RR2D.HPEH(8), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(8, Local1) > + Notify(\_SB.PC14.RR2D, Local0) > + } > + > + // PC07 Port 3A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC15.RR3A.PMEP,1) ) { > + Store(\_SB.PC15.RR3A.PMEH(9), Local0) > + } else { > + Store (\_SB.PC15.RR3A.HPEH(9), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(9, Local1) > + Notify(\_SB.PC15.RR3A, Local0) > + } > + > + // PC07 Port 3B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC15.RR3B.PMEP,1) ) { > + Store(\_SB.PC15.RR3B.PMEH(10), Local0) > + } else { > + Store (\_SB.PC15.RR3B.HPEH(10), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(10, Local1) > + Notify(\_SB.PC15.RR3B, Local0) > + } > + > + // PC07 Port 3C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC15.RR3C.PMEP,1) ) { > + Store(\_SB.PC15.RR3C.PMEH(11), Local0) > + } else { > + Store (\_SB.PC15.RR3C.HPEH(11), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(11, Local1) > + Notify(\_SB.PC15.RR3C, Local0) > + } > + > + // PC07 Port 3D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC15.RR3D.PMEP,1) ) { > + Store(\_SB.PC15.RR3D.PMEH(12), Local0) > + } else { > + Store (\_SB.PC15.RR3D.HPEH(12), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(12, Local1) > + Notify(\_SB.PC15.RR3D, Local0) > + } > + > + // PC08 Port 4A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC16.RR4A.PMEP,1) ) { > + Store(\_SB.PC16.RR4A.PMEH(13), Local0) > + } else { > + Store (\_SB.PC16.RR4A.HPEH(13), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(13, Local1) > + Notify(\_SB.PC16.RR4A, Local0) > + } > + > + // PC08 Port 4B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC16.RR4B.PMEP,1) ) { > + Store(\_SB.PC16.RR4B.PMEH(14), Local0) > + } else { > + Store (\_SB.PC16.RR4B.HPEH(14), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(14, Local1) > + Notify(\_SB.PC16.RR4B, Local0) > + } > + > + // PC08 Port 4C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC16.RR4C.PMEP,1) ) { > + Store(\_SB.PC16.RR4C.PMEH(15), Local0) > + } else { > + Store (\_SB.PC16.RR4C.HPEH(15), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(15, Local1) > + Notify(\_SB.PC16.RR4C, Local0) > + } > + > + // PC08 Port 4D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC16.RR4D.PMEP,1) ) { > + Store(\_SB.PC16.RR4D.PMEH(16), Local0) > + } else { > + Store (\_SB.PC16.RR4D.HPEH(16), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(16, Local1) > + Notify(\_SB.PC16.RR4D, Local0) > + } > + > + // PC08 Port 5A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC17.RR5A.PMEP,1) ) { > + Store(\_SB.PC17.RR5A.PMEH(17), Local0) > + } else { > + Store (\_SB.PC17.RR5A.HPEH(17), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(17, Local1) > + Notify(\_SB.PC17.RR5A, Local0) > + } > + > + // PC08 Port 5B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC17.RR5B.PMEP,1) ) { > + Store(\_SB.PC17.RR5B.PMEH(18), Local0) > + } else { > + Store (\_SB.PC17.RR5B.HPEH(18), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(18, Local1) > + Notify(\_SB.PC17.RR5B, Local0) > + } > + > + // PC08 Port 5C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC17.RR5C.PMEP,1) ) { > + Store(\_SB.PC17.RR5C.PMEH(19), Local0) > + } else { > + Store (\_SB.PC17.RR5C.HPEH(19), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(19, Local1) > + Notify(\_SB.PC17.RR5C, Local0) > + } > + > + // PC08 Port 5D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC17.RR5D.PMEP,1) ) { > + Store(\_SB.PC17.RR5D.PMEH(20), Local0) > + } else { > + Store (\_SB.PC17.RR5D.HPEH(20), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(20, Local1) > + Notify(\_SB.PC17.RR5D, Local0) > + } > +#endif > +#if MAX_SOCKET > 3 > + > + > + // PC09 Port 1A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC19.SR1A.PMEP,1) ) { > + Store(\_SB.PC19.SR1A.PMEH(1), Local0) > + } else { > + Store (\_SB.PC19.SR1A.HPEH(1), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(1, Local1) > + Notify(\_SB.PC19.SR1A, Local0) > + } > + > + // PC09 Port 1B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC19.SR1B.PMEP,1) ) { > + Store(\_SB.PC19.SR1B.PMEH(2), Local0) > + } else { > + Store (\_SB.PC19.SR1B.HPEH(2), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(2, Local1) > + Notify(\_SB.PC19.SR1B, Local0) > + } > + > + // PC09 Port 1C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC19.SR1C.PMEP,1) ) { > + Store(\_SB.PC19.SR1C.PMEH(3), Local0) > + } else { > + Store (\_SB.PC19.SR1C.HPEH(3), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(3, Local1) > + Notify(\_SB.PC19.SR1C, Local0) > + } > + > + // PC09 Port 1D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC19.SR1D.PMEP,1) ) { > + Store(\_SB.PC19.SR1D.PMEH(4), Local0) > + } else { > + Store (\_SB.PC19.SR1D.HPEH(4), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(4, Local1) > + Notify(\_SB.PC19.SR1D, Local0) > + } > + > + // PC10 Port 2A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC20.SR2A.PMEP,1) ) { > + Store(\_SB.PC20.SR2A.PMEH(5), Local0) > + } else { > + Store (\_SB.PC20.SR2A.HPEH(5), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(5, Local1) > + Notify(\_SB.PC20.SR2A, Local0) > + } > + > + // PC10 Port 2B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC20.SR2B.PMEP,1) ) { > + Store(\_SB.PC20.SR2B.PMEH(6), Local0) > + } else { > + Store (\_SB.PC20.SR2B.HPEH(6), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(6, Local1) > + Notify(\_SB.PC20.SR2B, Local0) > + } > + > + // PC10 Port 2C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC20.SR2C.PMEP,1) ) { > + Store(\_SB.PC20.SR2C.PMEH(7), Local0) > + } else { > + Store (\_SB.PC20.SR2C.HPEH(7), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(7, Local1) > + Notify(\_SB.PC20.SR2C, Local0) > + } > + > + // PC10 Port 2D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC20.SR2D.PMEP,1) ) { > + Store(\_SB.PC20.SR2D.PMEH(8), Local0) > + } else { > + Store (\_SB.PC20.SR2D.HPEH(8), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(8, Local1) > + Notify(\_SB.PC20.SR2D, Local0) > + } > + > + // PC10 Port 3A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC21.SR3A.PMEP,1) ) { > + Store(\_SB.PC21.SR3A.PMEH(9), Local0) > + } else { > + Store (\_SB.PC21.SR3A.HPEH(9), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(9, Local1) > + Notify(\_SB.PC21.SR3A, Local0) > + } > + > + // PC10 Port 3B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC21.SR3B.PMEP,1) ) { > + Store(\_SB.PC21.SR3B.PMEH(10), Local0) > + } else { > + Store (\_SB.PC21.SR3B.HPEH(10), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(10, Local1) > + Notify(\_SB.PC21.SR3B, Local0) > + } > + > + // PC10 Port 3C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC21.SR3C.PMEP,1) ) { > + Store(\_SB.PC21.SR3C.PMEH(11), Local0) > + } else { > + Store (\_SB.PC21.SR3C.HPEH(11), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(11, Local1) > + Notify(\_SB.PC21.SR3C, Local0) > + } > + > + // PC10 Port 3D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC21.SR3D.PMEP,1) ) { > + Store(\_SB.PC21.SR3D.PMEH(12), Local0) > + } else { > + Store (\_SB.PC21.SR3D.HPEH(12), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(12, Local1) > + Notify(\_SB.PC21.SR3D, Local0) > + } > + > + // PC11 Port 4A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC22.SR4A.PMEP,1) ) { > + Store(\_SB.PC22.SR4A.PMEH(13), Local0) > + } else { > + Store (\_SB.PC22.SR4A.HPEH(13), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(13, Local1) > + Notify(\_SB.PC22.SR4A, Local0) > + } > + > + // PC11 Port 4B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC22.SR4B.PMEP,1) ) { > + Store(\_SB.PC22.SR4B.PMEH(14), Local0) > + } else { > + Store (\_SB.PC22.SR4B.HPEH(14), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(14, Local1) > + Notify(\_SB.PC22.SR4B, Local0) > + } > + > + // PC11 Port 4C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC22.SR4C.PMEP,1) ) { > + Store(\_SB.PC22.SR4C.PMEH(15), Local0) > + } else { > + Store (\_SB.PC22.SR4C.HPEH(15), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(15, Local1) > + Notify(\_SB.PC22.SR4C, Local0) > + } > + > + // PC11 Port 4D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC22.SR4D.PMEP,1) ) { > + Store(\_SB.PC22.SR4D.PMEH(16), Local0) > + } else { > + Store (\_SB.PC22.SR4D.HPEH(16), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(16, Local1) > + Notify(\_SB.PC22.SR4D, Local0) > + } > + > + // PC11 Port 5A PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC23.SR5A.PMEP,1) ) { > + Store(\_SB.PC23.SR5A.PMEH(17), Local0) > + } else { > + Store (\_SB.PC23.SR5A.HPEH(17), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(17, Local1) > + Notify(\_SB.PC23.SR5A, Local0) > + } > + > + // PC11 Port 5B PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC23.SR5B.PMEP,1) ) { > + Store(\_SB.PC23.SR5B.PMEH(18), Local0) > + } else { > + Store (\_SB.PC23.SR5B.HPEH(18), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(18, Local1) > + Notify(\_SB.PC23.SR5B, Local0) > + } > + > + // PC11 Port 5C PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC23.SR5C.PMEP,1) ) { > + Store(\_SB.PC23.SR5C.PMEH(19), Local0) > + } else { > + Store (\_SB.PC23.SR5C.HPEH(19), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(19, Local1) > + Notify(\_SB.PC23.SR5C, Local0) > + } > + > + // PC11 Port 5D PCI-Ex Hot Plug > + // If PM_PME event clear INTs and AttnBtnPressed > + If( LEqual(\_SB.PC23.SR5D.PMEP,1) ) { > + Store(\_SB.PC23.SR5D.PMEH(20), Local0) > + } else { > + Store (\_SB.PC23.SR5D.HPEH(20), Local0) > + } > + If(Lnot(LEqual(Local0,0xFF))) { > + Store(20, Local1) > + Notify(\_SB.PC23.SR5D, Local0) > + } > +#endif > + > + //If a hotplug event was serviced check if this was generated by PM_PM= E > + If (Lnot (LEqual(Local0, 0))) { > + //Clear the status bit 16 of PMEStatus > + //Clear the PME Pending bit 17 of PMEStatus > + If( LEqual(Local1, 1)) { > + Store(1, \_SB.PC01.BR1A.PMES) > + Store(1, \_SB.PC01.BR1A.PMEP) > + } > + If( LEqual(Local1, 2)) { > + Store(1, \_SB.PC01.BR1B.PMES) > + Store(1, \_SB.PC01.BR1B.PMEP) > + } > + If( LEqual(Local1, 3)) { > + Store(1, \_SB.PC01.BR1C.PMES) > + Store(1, \_SB.PC01.BR1C.PMEP) > + } > + If( LEqual(Local1, 4)) { > + Store(1, \_SB.PC01.BR1D.PMES) > + Store(1, \_SB.PC01.BR1D.PMEP) > + } > + > + If( LEqual(Local1, 5)) { > + Store(1, \_SB.PC02.BR2A.PMES) > + Store(1, \_SB.PC02.BR2A.PMEP) > + } > + If( LEqual(Local1, 6)) { > + Store(1, \_SB.PC02.BR2B.PMES) > + Store(1, \_SB.PC02.BR2B.PMEP) > + } > + If( LEqual(Local1, 7)) { > + Store(1, \_SB.PC02.BR2C.PMES) > + Store(1, \_SB.PC02.BR2C.PMEP) > + } > + If( LEqual(Local1, 8)) { > + Store(1, \_SB.PC02.BR2D.PMES) > + Store(1, \_SB.PC02.BR2D.PMEP) > + } > + If( LEqual(Local1, 9)) { > + Store(1, \_SB.PC03.BR3A.PMES) > + Store(1, \_SB.PC03.BR3A.PMEP) > + } > + If( LEqual(Local1, 10)) { > + Store(1, \_SB.PC03.BR3B.PMES) > + Store(1, \_SB.PC03.BR3B.PMEP) > + } > + If( LEqual(Local1, 11)) { > + Store(1, \_SB.PC03.BR3C.PMES) > + Store(1, \_SB.PC03.BR3C.PMEP) > + } > + If( LEqual(Local1, 12)) { > + Store(1, \_SB.PC03.BR3D.PMES) > + Store(1, \_SB.PC03.BR3D.PMEP) > + } > + If( LEqual(Local1, 13)) { > + Store(1, \_SB.PC04.BR4A.PMES) > + Store(1, \_SB.PC04.BR4A.PMEP) > + } > + If( LEqual(Local1, 14)) { > + Store(1, \_SB.PC04.BR4B.PMES) > + Store(1, \_SB.PC04.BR4B.PMEP) > + } > + If( LEqual(Local1, 15)) { > + Store(1, \_SB.PC04.BR4C.PMES) > + Store(1, \_SB.PC04.BR4C.PMEP) > + } > + If( LEqual(Local1, 16)) { > + Store(1, \_SB.PC04.BR4D.PMES) > + Store(1, \_SB.PC04.BR4D.PMEP) > + } > + If( LEqual(Local1, 17)) { > + Store(1, \_SB.PC05.BR5A.PMES) > + Store(1, \_SB.PC05.BR5A.PMEP) > + } > + If( LEqual(Local1, 18)) { > + Store(1, \_SB.PC05.BR5B.PMES) > + Store(1, \_SB.PC05.BR5B.PMEP) > + } > + If( LEqual(Local1, 19)) { > + Store(1, \_SB.PC05.BR5C.PMES) > + Store(1, \_SB.PC05.BR5C.PMEP) > + } > + If( LEqual(Local1, 20)) { > + Store(1, \_SB.PC05.BR5D.PMES) > + Store(1, \_SB.PC05.BR5D.PMEP) > + } > + > +#if MAX_SOCKET > 1 > + If( LEqual(Local1, 1)) { > + Store(1, \_SB.PC07.QR1A.PMES) > + Store(1, \_SB.PC07.QR1A.PMEP) > + } > + If( LEqual(Local1, 2)) { > + Store(1, \_SB.PC07.QR1B.PMES) > + Store(1, \_SB.PC07.QR1B.PMEP) > + } > + If( LEqual(Local1, 3)) { > + Store(1, \_SB.PC07.QR1C.PMES) > + Store(1, \_SB.PC07.QR1C.PMEP) > + } > + If( LEqual(Local1, 4)) { > + Store(1, \_SB.PC07.QR1D.PMES) > + Store(1, \_SB.PC07.QR1D.PMEP) > + } > + If( LEqual(Local1, 5)) { > + Store(1, \_SB.PC08.QR2A.PMES) > + Store(1, \_SB.PC08.QR2A.PMEP) > + } > + If( LEqual(Local1, 6)) { > + Store(1, \_SB.PC08.QR2B.PMES) > + Store(1, \_SB.PC08.QR2B.PMEP) > + } > + If( LEqual(Local1, 7)) { > + Store(1, \_SB.PC08.QR2C.PMES) > + Store(1, \_SB.PC08.QR2C.PMEP) > + } > + If( LEqual(Local1, 8)) { > + Store(1, \_SB.PC08.QR2D.PMES) > + Store(1, \_SB.PC08.QR2D.PMEP) > + } > + If( LEqual(Local1, 9)) { > + Store(1, \_SB.PC09.QR3A.PMES) > + Store(1, \_SB.PC09.QR3A.PMEP) > + } > + If( LEqual(Local1, 10)) { > + Store(1, \_SB.PC09.QR3B.PMES) > + Store(1, \_SB.PC09.QR3B.PMEP) > + } > + If( LEqual(Local1, 11)) { > + Store(1, \_SB.PC09.QR3C.PMES) > + Store(1, \_SB.PC09.QR3C.PMEP) > + } > + If( LEqual(Local1, 12)) { > + Store(1, \_SB.PC09.QR3D.PMES) > + Store(1, \_SB.PC09.QR3D.PMEP) > + } > + If( LEqual(Local1, 13)) { > + Store(1, \_SB.PC10.QR4A.PMES) > + Store(1, \_SB.PC10.QR4A.PMEP) > + } > + If( LEqual(Local1, 14)) { > + Store(1, \_SB.PC10.QR4B.PMES) > + Store(1, \_SB.PC10.QR4B.PMEP) > + } > + If( LEqual(Local1, 15)) { > + Store(1, \_SB.PC10.QR4C.PMES) > + Store(1, \_SB.PC10.QR4C.PMEP) > + } > + If( LEqual(Local1, 16)) { > + Store(1, \_SB.PC10.QR4D.PMES) > + Store(1, \_SB.PC10.QR4D.PMEP) > + } > + If( LEqual(Local1, 17)) { > + Store(1, \_SB.PC11.QR5A.PMES) > + Store(1, \_SB.PC11.QR5A.PMEP) > + } > + If( LEqual(Local1, 18)) { > + Store(1, \_SB.PC11.QR5B.PMES) > + Store(1, \_SB.PC11.QR5B.PMEP) > + } > + If( LEqual(Local1, 19)) { > + Store(1, \_SB.PC11.QR5C.PMES) > + Store(1, \_SB.PC11.QR5C.PMEP) > + } > + If( LEqual(Local1, 20)) { > + Store(1, \_SB.PC11.QR5D.PMES) > + Store(1, \_SB.PC11.QR5D.PMEP) > + } > +#endif > +#if MAX_SOCKET > 2 > + > + If( LEqual(Local1, 1)) { > + Store(1, \_SB.PC13.RR1A.PMES) > + Store(1, \_SB.PC13.RR1A.PMEP) > + } > + If( LEqual(Local1, 2)) { > + Store(1, \_SB.PC13.RR1B.PMES) > + Store(1, \_SB.PC13.RR1B.PMEP) > + } > + If( LEqual(Local1, 3)) { > + Store(1, \_SB.PC13.RR1C.PMES) > + Store(1, \_SB.PC13.RR1C.PMEP) > + } > + If( LEqual(Local1, 4)) { > + Store(1, \_SB.PC13.RR1D.PMES) > + Store(1, \_SB.PC13.RR1D.PMEP) > + } > + If( LEqual(Local1, 5)) { > + Store(1, \_SB.PC14.RR2A.PMES) > + Store(1, \_SB.PC14.RR2A.PMEP) > + } > + If( LEqual(Local1, 6)) { > + Store(1, \_SB.PC14.RR2B.PMES) > + Store(1, \_SB.PC14.RR2B.PMEP) > + } > + If( LEqual(Local1, 7)) { > + Store(1, \_SB.PC14.RR2C.PMES) > + Store(1, \_SB.PC14.RR2C.PMEP) > + } > + If( LEqual(Local1, 8)) { > + Store(1, \_SB.PC14.RR2D.PMES) > + Store(1, \_SB.PC14.RR2D.PMEP) > + } > + If( LEqual(Local1, 9)) { > + Store(1, \_SB.PC15.RR3A.PMES) > + Store(1, \_SB.PC15.RR3A.PMEP) > + } > + If( LEqual(Local1, 10)) { > + Store(1, \_SB.PC15.RR3B.PMES) > + Store(1, \_SB.PC15.RR3B.PMEP) > + } > + If( LEqual(Local1, 11)) { > + Store(1, \_SB.PC15.RR3C.PMES) > + Store(1, \_SB.PC15.RR3C.PMEP) > + } > + If( LEqual(Local1, 12)) { > + Store(1, \_SB.PC15.RR3D.PMES) > + Store(1, \_SB.PC15.RR3D.PMEP) > + } > + If( LEqual(Local1, 13)) { > + Store(1, \_SB.PC16.RR4A.PMES) > + Store(1, \_SB.PC16.RR4A.PMEP) > + } > + If( LEqual(Local1, 14)) { > + Store(1, \_SB.PC16.RR4B.PMES) > + Store(1, \_SB.PC16.RR4B.PMEP) > + } > + If( LEqual(Local1, 15)) { > + Store(1, \_SB.PC16.RR4C.PMES) > + Store(1, \_SB.PC16.RR4C.PMEP) > + } > + If( LEqual(Local1, 16)) { > + Store(1, \_SB.PC16.RR4D.PMES) > + Store(1, \_SB.PC16.RR4D.PMEP) > + } > + If( LEqual(Local1, 17)) { > + Store(1, \_SB.PC17.RR5A.PMES) > + Store(1, \_SB.PC17.RR5A.PMEP) > + } > + If( LEqual(Local1, 18)) { > + Store(1, \_SB.PC17.RR5B.PMES) > + Store(1, \_SB.PC17.RR5B.PMEP) > + } > + If( LEqual(Local1, 19)) { > + Store(1, \_SB.PC17.RR5C.PMES) > + Store(1, \_SB.PC17.RR5C.PMEP) > + } > + If( LEqual(Local1, 20)) { > + Store(1, \_SB.PC17.RR5D.PMES) > + Store(1, \_SB.PC17.RR5D.PMEP) > + } > +#endif > +#if MAX_SOCKET > 3 > + > + If( LEqual(Local1, 1)) { > + Store(1, \_SB.PC19.SR1A.PMES) > + Store(1, \_SB.PC19.SR1A.PMEP) > + } > + If( LEqual(Local1, 2)) { > + Store(1, \_SB.PC19.SR1B.PMES) > + Store(1, \_SB.PC19.SR1B.PMEP) > + } > + If( LEqual(Local1, 3)) { > + Store(1, \_SB.PC19.SR1C.PMES) > + Store(1, \_SB.PC19.SR1C.PMEP) > + } > + If( LEqual(Local1, 4)) { > + Store(1, \_SB.PC19.SR1D.PMES) > + Store(1, \_SB.PC19.SR1D.PMEP) > + } > + If( LEqual(Local1, 5)) { > + Store(1, \_SB.PC20.SR2A.PMES) > + Store(1, \_SB.PC20.SR2A.PMEP) > + } > + If( LEqual(Local1, 6)) { > + Store(1, \_SB.PC20.SR2B.PMES) > + Store(1, \_SB.PC20.SR2B.PMEP) > + } > + If( LEqual(Local1, 7)) { > + Store(1, \_SB.PC20.SR2C.PMES) > + Store(1, \_SB.PC20.SR2C.PMEP) > + } > + If( LEqual(Local1, 8)) { > + Store(1, \_SB.PC20.SR2D.PMES) > + Store(1, \_SB.PC20.SR2D.PMEP) > + } > + If( LEqual(Local1, 9)) { > + Store(1, \_SB.PC21.SR3A.PMES) > + Store(1, \_SB.PC21.SR3A.PMEP) > + } > + If( LEqual(Local1, 10)) { > + Store(1, \_SB.PC21.SR3B.PMES) > + Store(1, \_SB.PC21.SR3B.PMEP) > + } > + If( LEqual(Local1, 11)) { > + Store(1, \_SB.PC21.SR3C.PMES) > + Store(1, \_SB.PC21.SR3C.PMEP) > + } > + If( LEqual(Local1, 12)) { > + Store(1, \_SB.PC21.SR3D.PMES) > + Store(1, \_SB.PC21.SR3D.PMEP) > + } > + If( LEqual(Local1, 13)) { > + Store(1, \_SB.PC22.SR4A.PMES) > + Store(1, \_SB.PC22.SR4A.PMEP) > + } > + If( LEqual(Local1, 14)) { > + Store(1, \_SB.PC22.SR4B.PMES) > + Store(1, \_SB.PC22.SR4B.PMEP) > + } > + If( LEqual(Local1, 15)) { > + Store(1, \_SB.PC22.SR4C.PMES) > + Store(1, \_SB.PC22.SR4C.PMEP) > + } > + If( LEqual(Local1, 16)) { > + Store(1, \_SB.PC22.SR4D.PMES) > + Store(1, \_SB.PC22.SR4D.PMEP) > + } > + If( LEqual(Local1, 17)) { > + Store(1, \_SB.PC23.SR5A.PMES) > + Store(1, \_SB.PC23.SR5A.PMEP) > + } > + If( LEqual(Local1, 18)) { > + Store(1, \_SB.PC23.SR5B.PMES) > + Store(1, \_SB.PC23.SR5B.PMEP) > + } > + If( LEqual(Local1, 19)) { > + Store(1, \_SB.PC23.SR5C.PMES) > + Store(1, \_SB.PC23.SR5C.PMEP) > + } > + If( LEqual(Local1, 20)) { > + Store(1, \_SB.PC23.SR5D.PMES) > + Store(1, \_SB.PC23.SR5D.PMEP) > + } > +#endif > + Store(0x01,PEES) //Clear bit 9 of Status > + Store(0x00,PMEE) //Clear bit 9 of GPE0_EN > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > RootBridge.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > RootBridge.asi > new file mode 100644 > index 0000000000..3126e29de7 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > RootBridge.asi > @@ -0,0 +1,328 @@ > +/** @file > + > + @copyright > + Copyright 2008 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + External (DBGM, FieldUnitObj) > + Name (SUPP, 0) > + Name (CTRL, 0) > + > + // > + // _BBN is ACPI method called by OS to read PCI base bus number for II= O > stack. > + // > + Method(_BBN, 0, NotSerialized) > + { > + Return(CONCATENATE3(BB, SOCKET, STACK)) > + } > + > + // > + // _PXM is ACPI method called by OS to read Proximity Domain (aka NUMA > Node) where IIO stack belongs to. > + // Without SNC (Sub-NUMA Cluster) proximity domain is socket. If two > SNC domains are enabled report > + // PCI stacks 0..2 in the first SNC domain of a socket, and upper stac= ks in > the second SNC domain in this socket. > + // If four SNC domains are enabled report stacks 0,1 in first domain; = stack 2 > in second; 3,4 in third; > + // and upper stacks in the fourth SNC domain in this socket. > + // > + Method(_PXM, 0, NotSerialized) > + { > + Store(SOCKET, Local0) > + Switch (ToInteger(CLOD)) { // CLOD contains the number of SNC domain= s > per socekt > + Case (2) { > + Multiply(Local0, CLOD, Local0) > +#if STACK > 2 > + Add(Local0, 1, Local0) > +#endif > + } > + Case (4) { > + Multiply(Local0, CLOD, Local0) > +#if STACK > 3 > + Add(Local0, 3, Local0) > +#elif STACK > 2 > + Add(Local0, 2, Local0) > +#elif STACK > 0 > + Add(Local0, 1, Local0) > +#endif > + } > + } > + Return(Local0) > + } > + > + // > + // _SEG is ACPI method called by OS to read PCI segment of IIO stack. > + // > + Method(_SEG, 0, NotSerialized) > + { > + Return(CONCATENATE2(SG0, SOCKET)) > + } > + > + // > + // _STA is ACPI method called by OS to read status of ACPI device, IIO= stack > in this case. > + // > + Method(_STA, 0, NotSerialized) > + { // > + // Check in processor present bitmap (PRBM) if processor is present,= then > + // in stack present bitmap of given processor (SPBx) if stack is pre= sent. > + // > + ShiftLeft(1, SOCKET, Local0) > + If (And(PRBM, Local0)) { > + > + ShiftLeft(1, CONCATENATE2(0x,STACK), Local1) > + if (And(CONCATENATE2(SPB, SOCKET), Local1)) { > + Return(0x0F) > + } > + } > + Return(0x00) > + } > + > + Method(_OSC, 4) > + { > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,0,CDW1) > + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,4,CDW2) > + > + // > + // Fill 3rd capability DWORD only if the count is greater than 2= . > + // > + If(LGreater(Arg2,2)) { > + CreateDWordField(Arg3,8,CDW3) > + } > + > + // > + // Save Capabilities DWord2 & 3 > + // > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > + > + // > + // Only allow native hot plug control if OS supports > + // * MSI/MSI-X > + // > + If (LOr(AHPE, LNotEqual(And(SUPP, 0x10), 0x10))) { // Conditions= not > met? > + And(CTRL, Not(1), CTRL) // Mask bit 0 to deny. > + Sleep(1000) > + } > + > + // > + // Never allow SHPC (no SHPC controller in system), Mask bit 1 > + // > + And(CTRL, Not(2), CTRL) > + > + > + // > + // Select Native PCIe AER/eDPC handling from OS or Firmware Firs= t > model > + // > + If (CondRefOf (\_SB.OSNC)) > + { > + //in case OS has AER capability. > + If (LEqual ( And(CTRL, 8), 8)) { > + > + //in case OS support multiple segment. > + If (And (SUPP, 8)) { > + If (CondRefof (^_SEG)) > + { > + Store (^_SEG, Local0) > + } Else { > + Store (0, Local0) > + } > + } Else { > + Store (0, Local0) > + } > + > + Store (^_BBN, Local1) > + > + // if BIOS allows OS take. Do nothing. > + If (\_SB.OSNC(Local0, Local1, SUPP, CTRL)) { > + > + } Else { > + And (CTRL, Not(0x88), CTRL) > + } > + } Else { > + And (CTRL, Not(0x88), CTRL) > + } > + } Else { > + // > + //Disable Native PCIe AER/eDPC handling from OS, AER is bit3, = eDPC is > bit7 > + // > + And (CTRL, Not(0x88), CTRL) > + } > + > + If (Not(And(CDW1,1))) { // Query Flag Clear? > + // > + // Disable GPEs for Features granted native control > + // > + If (And(CTRL, 0x01)) { // Native Hot plug control granted? > + \_SB.OSCM (_UID) > + Store (0x01, GPSH) // Clear Hotplug SCI Enabl= e in GPE0 > + } > + } > + > + If (LNotEqual(Arg1,one)) { // unknown revision > + Or(CDW1,0x08,CDW1) > + } > + > + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked > + Or(CDW1,0x10,CDW1) > + } > + // > + // update DWORD3 in the buffer > + // > + Store(CTRL,CDW3) > + Return(Arg3) > + > + } Else { > + // > + // Just indicate unrecognized UUID > + // Leave it at that > + // > + Or (CDW1,4,CDW1) > + if(LEqual(DBGM, 0x01)){ > + Store (0xEE, IO80) > + } > + Return(Arg3) > + } > + } // End _OSC > + > + Name(RBRS, ResourceTemplate() { > + //RESOURCE_CHUNK1_OFF > + WORDBusNumber( //Bus number resource (0); the bridge prod= uces > bus numbers for its subsequent buses > + ResourceProducer, // bit 0 of general flags is 1 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, // PosDecode > + 0x0000, // Granularity (FIX1 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Min (FIX1 - Patched by ACPI Pla= tform Driver during > POST) > + 0x0000, // Max (FIX1 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Translation > + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patc= hed by ACPI > Platform Driver during POST) > + , > + , > + FIX1 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + //: Off board video card not detected in device manager when it is > connected to CPU > + //RESOURCE_CHUNK5_OFF > + DWORDMEMORY( // descriptor for video RAM on video card > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, > + MinFixed, // Range is fixed > + MaxFixed, // Range is Fixed > + Cacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIX5 - Patched by ACPI Pl= atform Driver > during POST) > + 0x00000000, // Min (FIX5 - Patched by ACPI Pl= atform Driver > during POST) > + 0x00000000, // Max (FIX5 - Patched by ACPI Pl= atform Driver > during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (FIX5 - Patched by ACPI Pl= atform > Driver during POST) > + , > + , > + FIX5 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + //RESOURCE_CHUNK2_OFF > + WORDIO( //Consumed-and-produced resource (all I/O = above > CFF) > + ResourceProducer, // bit 0 of general flags is 0 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, > + EntireRange, > + 0x0000, // Granularity (FIX2 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Min (FIX2 - Patched by ACPI Pla= tform Driver during > POST) > + 0x0000, // Max (FIX2 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Translation > + 0x0001, // Range Length =3D Max-Min+1 (FIX2 - Patc= hed by ACPI > Platform Driver during POST) > + , > + , > + FIX2 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + //Off board video card not detected in device manager when it is > connected to CPU > + //Descriptor for IO space of the video card. > + WORDIO( // Consumed-and-produced resource (all I/O= below > CF8) > + ResourceProducer, // bit 0 of general flags is 0 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, > + EntireRange, > + 0x0000, // Granularity (FIX6 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Min (FIX6 - Patched by ACPI Pla= tform Driver during > POST) > + 0x0000, // Max (FIX6 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Translation > + 0x0000, // Range Length > + , > + , > + FIX6 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + //Off board video card not detected in device manager when it is > connected to CPU > + //Descriptor for IO space of the video card. > + WORDIO( // Consumed-and-produced resource (all I/O= below > CF8) > + ResourceProducer, // bit 0 of general flags is 0 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, > + EntireRange, > + 0x0000, // Granularity (FIX7 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Min (FIX7 - Patched by ACPI Pla= tform Driver during > POST) > + 0x0000, // Max (FIX7 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Translation > + 0x0000, // Range Length > + , > + , > + FIX7 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + // > + // PCI RESOURCE_32bit > + // > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIX3 - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIX3 - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IX3 - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIX3 - > Patched by ACPI Platform Driver during POST) > + , > + , > + FIX3 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + // > + // PCI RESOURCE_64bit > + // > + QWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Pla= tform > Driver during POST) > + 0x00000000000, // Min (calculated dynamically) (FIX4 - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IX4 - > Patched by ACPI Platform Driver during POST) > + 0x00000000000, // Translation > + 0x00000000000, // Range Length (calculated dynamically) (= FIX4 - > Patched by ACPI Platform Driver during POST) > + , > + , > + FIX4 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + }) // end of PRXX Buffer > + > + // Current resource template return > + Method(_CRS, 0x0, NotSerialized) > + { > + Return(RBRS) > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > RootBridgeIcx.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > RootBridgeIcx.asi > new file mode 100644 > index 0000000000..1dc42a9ca8 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio > RootBridgeIcx.asi > @@ -0,0 +1,270 @@ > +/** @file > + > + @copyright > + Copyright 2008 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "MaxSocket.h" > + > + Method(OSCM, 1) { > + > + if (LEqual(Arg0, 1)) { // PC01 > + \_SB.PC01.BR1A.OSHP () > + \_SB.PC01.BR1B.OSHP () > + \_SB.PC01.BR1C.OSHP () > + \_SB.PC01.BR1D.OSHP () > + } > + if (LEqual(Arg0, 2)) { // PC01 > + \_SB.PC02.BR2A.OSHP () > + \_SB.PC02.BR2B.OSHP () > + \_SB.PC02.BR2C.OSHP () > + \_SB.PC02.BR2D.OSHP () > + } > + if (LEqual(Arg0, 3)) { // PC02 > + \_SB.PC03.BR3A.OSHP () > + \_SB.PC03.BR3B.OSHP () > + \_SB.PC03.BR3C.OSHP () > + \_SB.PC03.BR3D.OSHP () > + } > + if (LEqual(Arg0, 4)) { // PC02 > + \_SB.PC04.BR4A.OSHP () > + \_SB.PC04.BR4B.OSHP () > + \_SB.PC04.BR4C.OSHP () > + \_SB.PC04.BR4D.OSHP () > + } > + if (LEqual(Arg0, 5)) { // PC01 > + \_SB.PC05.BR5A.OSHP () > + \_SB.PC05.BR5B.OSHP () > + \_SB.PC05.BR5C.OSHP () > + \_SB.PC05.BR5D.OSHP () > + } > + > +#if MAX_SOCKET > 1 > + if (LEqual(Arg0, 7)) { // PC07 > + \_SB.PC07.QR1A.OSHP () > + \_SB.PC07.QR1B.OSHP () > + \_SB.PC07.QR1C.OSHP () > + \_SB.PC07.QR1D.OSHP () > + } > + if (LEqual(Arg0, 8)) { // PC08 > + \_SB.PC08.QR2A.OSHP () > + \_SB.PC08.QR2B.OSHP () > + \_SB.PC08.QR2C.OSHP () > + \_SB.PC08.QR2D.OSHP () > + > + } > + if (LEqual(Arg0, 9)) { // PC09 > + \_SB.PC09.QR3A.OSHP () > + \_SB.PC09.QR3B.OSHP () > + \_SB.PC09.QR3C.OSHP () > + \_SB.PC09.QR3D.OSHP () > + > + } > + if (LEqual(Arg0, 10)) { // PC10 > + > + \_SB.PC10.QR4A.OSHP () > + \_SB.PC10.QR4B.OSHP () > + \_SB.PC10.QR4C.OSHP () > + \_SB.PC10.QR4D.OSHP () > + > + } > + if (LEqual(Arg0, 11)) { // PC11 > + \_SB.PC11.QR5A.OSHP () > + \_SB.PC11.QR5B.OSHP () > + \_SB.PC11.QR5C.OSHP () > + \_SB.PC11.QR5D.OSHP () > + } > + > +#endif > + > +#if MAX_SOCKET > 2 > + if (LEqual(Arg0, 13)) { // PC13 > + \_SB.PC13.RR1A.OSHP () > + \_SB.PC13.RR1B.OSHP () > + \_SB.PC13.RR1C.OSHP () > + \_SB.PC13.RR1D.OSHP () > + } > + if (LEqual(Arg0, 14)) { // PC14 > + \_SB.PC14.RR2A.OSHP () > + \_SB.PC14.RR2B.OSHP () > + \_SB.PC14.RR2C.OSHP () > + \_SB.PC14.RR2D.OSHP () > + > + } > + if (LEqual(Arg0, 15)) { // PC15 > + \_SB.PC15.RR3A.OSHP () > + \_SB.PC15.RR3B.OSHP () > + \_SB.PC15.RR3C.OSHP () > + \_SB.PC15.RR3D.OSHP () > + > + } > + if (LEqual(Arg0, 16)) { // PC16 > + > + \_SB.PC16.RR4A.OSHP () > + \_SB.PC16.RR4B.OSHP () > + \_SB.PC16.RR4C.OSHP () > + \_SB.PC16.RR4D.OSHP () > + > + } > + if (LEqual(Arg0, 17)) { // PC17 > + \_SB.PC17.RR5A.OSHP () > + \_SB.PC17.RR5B.OSHP () > + \_SB.PC17.RR5C.OSHP () > + \_SB.PC17.RR5D.OSHP () > + } > + > +#endif > + > + > +#if MAX_SOCKET > 3 > + if (LEqual(Arg0, 19)) { // PC19 > + \_SB.PC19.SR1A.OSHP () > + \_SB.PC19.SR1B.OSHP () > + \_SB.PC19.SR1C.OSHP () > + \_SB.PC19.SR1D.OSHP () > + } > + if (LEqual(Arg0, 20)) { // PC20 > + \_SB.PC20.SR2A.OSHP () > + \_SB.PC20.SR2B.OSHP () > + \_SB.PC20.SR2C.OSHP () > + \_SB.PC20.SR2D.OSHP () > + > + } > + if (LEqual(Arg0, 21)) { // PC21 > + \_SB.PC21.SR3A.OSHP () > + \_SB.PC21.SR3B.OSHP () > + \_SB.PC21.SR3C.OSHP () > + \_SB.PC21.SR3D.OSHP () > + > + } > + if (LEqual(Arg0, 22)) { // PC22 > + > + \_SB.PC22.SR4A.OSHP () > + \_SB.PC22.SR4B.OSHP () > + \_SB.PC22.SR4C.OSHP () > + \_SB.PC22.SR4D.OSHP () > + > + } > + if (LEqual(Arg0, 23)) { // PC23 > + \_SB.PC23.SR5A.OSHP () > + \_SB.PC23.SR5B.OSHP () > + \_SB.PC23.SR5C.OSHP () > + \_SB.PC23.SR5D.OSHP () > + } > + > +#endif > +#if MAX_SOCKET > 4 > + if (LEqual(Arg0,25)) { // PC12 > + \_SB.PC25.CR1A.OSHP () > + \_SB.PC25.CR1B.OSHP () > + \_SB.PC25.CR1C.OSHP () > + \_SB.PC25.CR1D.OSHP () > + } > + if (LEqual(Arg0,26)) { // PC13 > + \_SB.PC26.CR2A.OSHP () > + \_SB.PC26.CR2B.OSHP () > + \_SB.PC26.CR2C.OSHP () > + \_SB.PC26.CR2D.OSHP () > + > + } > + if (LEqual(Arg0,27)) { // PC12 > + \_SB.PC27.CR3A.OSHP () > + \_SB.PC27.CR3B.OSHP () > + \_SB.PC27.CR3C.OSHP () > + \_SB.PC27.CR3D.OSHP () > + } > + if (LEqual(Arg0,28)) { // PC13 > + \_SB.PC28.CR4A.OSHP () > + \_SB.PC28.CR4B.OSHP () > + \_SB.PC28.CR4C.OSHP () > + \_SB.PC28.CR4D.OSHP () > + } > + if (LEqual(Arg0,29)) { // PC14 > + \_SB.PC29.CR5A.OSHP () > + \_SB.PC29.CR5B.OSHP () > + \_SB.PC29.CR5C.OSHP () > + \_SB.PC29.CR5D.OSHP () > + } > +#endif > +#if MAX_SOCKET > 5 > + if (LEqual(Arg0,31)) { // PC15 > + \_SB.PC31.TR1A.OSHP () > + \_SB.PC31.TR1B.OSHP () > + \_SB.PC31.TR1C.OSHP () > + \_SB.PC31.TR1D.OSHP () > + } > + if (LEqual(Arg0,32)) { // PC16 > + \_SB.PC32.TR2A.OSHP () > + \_SB.PC32.TR2B.OSHP () > + \_SB.PC32.TR2C.OSHP () > + \_SB.PC32.TR2D.OSHP () > + > + } > + if (LEqual(Arg0,33)) { // PC15 > + \_SB.PC33.TR3A.OSHP () > + \_SB.PC33.TR3B.OSHP () > + \_SB.PC33.TR3C.OSHP () > + \_SB.PC33.TR3D.OSHP () > + } > + if (LEqual(Arg0,34)) { // PC16 > + \_SB.PC34.TR4A.OSHP () > + \_SB.PC34.TR4B.OSHP () > + \_SB.PC34.TR4C.OSHP () > + \_SB.PC34.TR4D.OSHP () > + } > + if (LEqual(Arg0,35)) { // PC17 > + \_SB.PC35.TR5A.OSHP () > + \_SB.PC35.TR5B.OSHP () > + \_SB.PC35.TR5C.OSHP () > + \_SB.PC35.TR5D.OSHP () > + } > +#endif > +#if MAX_SOCKET > 6 > + if (LEqual(Arg0,37)) { // PC37 > + \_SB.PC37.UR1A.OSHP () > + \_SB.PC37.UR1B.OSHP () > + \_SB.PC37.UR1C.OSHP () > + \_SB.PC37.UR1D.OSHP () > + } > + if (LEqual(Arg0,38)) { // PC38 > + \_SB.PC38.UR2A.OSHP () > + \_SB.PC38.UR2B.OSHP () > + \_SB.PC38.UR2C.OSHP () > + \_SB.PC38.UR2D.OSHP () > + > + } > + if (LEqual(Arg0,39)) { // PC39 > + \_SB.PC39.UR3A.OSHP () > + \_SB.PC39.UR3B.OSHP () > + \_SB.PC39.UR3C.OSHP () > + \_SB.PC39.UR3D.OSHP () > + } > + if (LEqual(Arg0,40)) { // PC40 > + \_SB.PC40.UR4A.OSHP () > + \_SB.PC40.UR4B.OSHP () > + \_SB.PC40.UR4C.OSHP () > + \_SB.PC40.UR4D.OSHP () > + } > + if (LEqual(Arg0,41)) { // PC41 > + > + \_SB.PC41.UR5A.OSHP () > + \_SB.PC41.UR5B.OSHP () > + \_SB.PC41.UR5C.OSHP () > + \_SB.PC41.UR5D.OSHP () > + } > +#endif > +#if MAX_SOCKET > 7 > + if (LEqual(Arg0,43)) { // PC43 > + \_SB.PC43.VR1A.OSHP () > + \_SB.PC43.VR1B.OSHP () > + \_SB.PC43.VR1C.OSHP () > + \_SB.PC43.VR1D.OSHP () > + } > + if (LEqual(Arg0,44)) { // PC44 > + } > + if (LEqual(Arg0,45)) { // PC45 > + } > +#endif > + } // end of OSCM > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mo > ther.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mo > ther.asi > new file mode 100644 > index 0000000000..90dbfabcbe > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mo > ther.asi > @@ -0,0 +1,164 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +Device (DMAC) { > + Name (_HID, EISAID("PNP0200")) > + Name (_CRS,ResourceTemplate() { > + IO(Decode16, 0x0, 0x0, 0, 0x10) > + IO(Decode16, 0x81, 0x81, 0, 0x3) > + IO(Decode16, 0x87, 0x87, 0, 0x1) > + IO(Decode16, 0x89, 0x89, 0, 0x3) > + IO(Decode16, 0x8f, 0x8f, 0, 0x1) > + IO(Decode16, 0xc0, 0xc0, 0, 0x20) > + DMA(Compatibility,NotBusMaster,Transfer8) {4} > + }) > +} > + > +Device (RTC) { > + Name (_HID,EISAID("PNP0B00")) > + Name (_CRS,ResourceTemplate() { > + IO(Decode16,0x70,0x70,0x01,0x02) > + IO(Decode16,0x72,0x72,0x01,0x02) > + IO(Decode16,0x74,0x74,0x01,0x04) > + IRQNoFlags(){8} > + }) > +} > + > +Device (PIC) { > + Name (_HID,EISAID("PNP0000")) > + Name (_CRS,ResourceTemplate() { > + IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes al= l aliases > + IO(Decode16,0xA0,0xA0,0x01,0x1E) > + IO(Decode16,0x4D0,0x4D0,0x01,0x02) > + }) > +} > + > +Device (FPU) { > + Name (_HID,EISAID("PNP0C04")) > + Name (_CRS,ResourceTemplate() { > + IO(Decode16,0xF0,0xF0,0x01,0x1) > + IRQNoFlags(){13} > + }) > +} > + > +Device(TMR) > +{ > + Name(_HID,EISAID("PNP0100")) > + > + Name(_CRS,ResourceTemplate() { > + IO(Decode16,0x40,0x40,0x01,0x04) > + IO(Decode16,0x50,0x50,0x01,0x04) // alias > + IRQNoFlags(){0} > + }) > +} > + > +Device (SPKR) { > + Name (_HID,EISAID("PNP0800")) > + Name (_CRS,ResourceTemplate() { > + IO(Decode16,0x61,0x61,0x01,0x01) > + }) > +} > + > +// > +// all "PNP0C02" devices- pieces that don't fit anywhere else > +// > +Device(XTRA) { > + Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices > + Name(_CRS, > + ResourceTemplate() { > + IO(Decode16,0x500,0x500,0x01,0xFF) // ACPI base > + IO(Decode16,0x400,0x400,0x01,0x20) // PM IO, ICH5 > + > + // > + // Resource conflict with COM Port > + // > + //IO(Decode16,0x680,0x680,0x01,0x80) // Runtime r= egisters, > National SIO > + IO(Decode16,0x10,0x10,0x01,0x10) > + IO(Decode16,0x80,0x80,0x01,0x01) > + IO(Decode16,0x84,0x84,0x01,0x03) > + IO(Decode16,0x88,0x88,0x01,0x01) > + IO(Decode16,0x8c,0x8c,0x01,0x03) > + IO(Decode16,0x90,0x90,0x01,0x10) > + // > + // Pilot Mail Box decode range > + // > + IO(Decode16,0x600,0x600,0x01,0x20) > + // > + // BMC KCS decode range > + // > + IO(Decode16,0xCA0,0xCA0,0x01,0x2) > + IO(Decode16,0xCA4,0xCA4,0x01,0x3) > + > + //IO Descriptor added for range 2F8-2FF for S501706 > + //IO(Decode16,0x2F8,0x2F8,0x01,0x08) > + //IO(Decode16,0x60,0x60,0x01,0x01) > + //IO(Decode16,0x64,0x64,0x01,0x01) > + > + // > + // FLASH range > + // > + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000) //16MB as per IIO > spec > + > + } > + ) > +} > + > +// > +// High Performance Event Timer (HPET) > +// > +Device (HPET) { > + Name (_HID, EisaId ("PNP0103")) > + > + Method (_STA, 0, NotSerialized) { > + If (\HPTE) { > + Return (0x0F) > + } Else { > + Return (0x00) > + } > + } > + > + Name (CRS0, ResourceTemplate () { > + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) > + }) > + > + Name (CRS1, ResourceTemplate () { > + Memory32Fixed (ReadWrite, 0xFED01000, 0x00000400) > + }) > + > + Name (CRS2, ResourceTemplate () { > + Memory32Fixed (ReadWrite, 0xFED02000, 0x00000400) > + }) > + > + Name (CRS3, ResourceTemplate () { > + Memory32Fixed (ReadWrite, 0xFED03000, 0x00000400) > + }) > + > + // > + // Owning control method can't be re-entrant, so _CRS must be Serializ= ed > + // > + Method (_CRS, 0, Serialized) { > + Switch (ToInteger(\HPTB)) { > + Case (0xFED00000) { > + Return (CRS0) > + } > + > + Case (0xFED01000) { > + Return (CRS1) > + } > + > + Case (0xFED02000) { > + Return (CRS2) > + } > + > + Case (0xFED03000) { > + Return (CRS3) > + } > + } > + Return (CRS0) > + } > +} > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Nv > dimmGpe.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Nv > dimmGpe.asi > new file mode 100644 > index 0000000000..f0c44e67c1 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Nv > dimmGpe.asi > @@ -0,0 +1,25 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +Method (NNPR, 0) // NTPR =3D=3D NoTify PRe > +{ > + External (\_SB.NVDR.NTPR, MethodObj) > + Store(Package () {}, Local0) > + if (CondRefOf (\_SB.NVDR.NTPR)) { > + Store (\_SB.NVDR.NTPR (), Local0) // Local0 =3D=3D Opaque Packa= ge > + } > + Return (Local0) > +} > + > +Method (NNDO, 1) // Nvdimm Notify DO > +{ > + External (\_SB.NVDR.NTDO, MethodObj) > + if (CondRefOf (\_SB.NVDR.NTDO)) { > + \_SB.NVDR.NTDO (Arg0) > + } > +} > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os. > asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os. > asi > new file mode 100644 > index 0000000000..e2d5fcc78f > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os. > asi > @@ -0,0 +1,66 @@ > +/** @file > + > + @copyright > + Copyright 2017-2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +Scope (\_SB) { > + > + Name (XCNT, 0) > + Name (OSYS, 0) // Global variable for type of OS. > + > + Method (_INI) { > + > + If (CondRefOf (_OSI)) { > + If (\_OSI ("Windows 2012")) { > + Store (13, OSYS) // Windows Server 2012 & Windows 8 > + } > + > + If (\_OSI ("Windows 2013")) { > + Store (14, OSYS) // Windows Server 2012 R2 & Windows 8.1 > + } > + > + If (\_OSI ("Windows 2015")) { > + Store (15, OSYS) // Windows 10 > + } > + // > + // Check Linux also > + // > + > + If (\_OSI ("FreeBSD")) { > + Store (2, OSYS) > + } > + > + If (\_OSI ("HP-UX")) { > + Store (3, OSYS) > + } > + > + If (\_OSI ("OpenVMS")) { > + Store (4, OSYS) > + } > + > + // > + // Running WinSvr2012, Win8, or later? > + // > + If (LGreaterEqual (\_SB.OSYS, 13)) { > + // > + // It is Svr2012 or Win8 > + // Call xHCI device to switch USB ports over > + // unless it has been done already > + // > + If (LEqual (XCNT, 0)) { > + if(LEqual(DBGM, 0x01)){ > + Store (0x84, IO80) > + } > + Increment (XCNT) > + } > + } Else { > + if(LEqual(DBGM, 0x01)){ > + Store (\_SB.OSYS, IO80) > + } > + } > + } > + } // End Method (_INI) > +} // End Scope (_SB) > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 0010nm.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 0010nm.asi > new file mode 100644 > index 0000000000..9f24076ef5 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 0010nm.asi > @@ -0,0 +1,427 @@ > +/** @file > + > + @copyright > + Copyright 2016 - 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + External (DBGM, FieldUnitObj) > + > + Name (SUPP, 0) > + Name (CTRL, 0) > + > + // > + // _BBN is ACPI method called by OS to read PCI base bus number for II= O > stack. > + // > + Method(_BBN, 0, NotSerialized) > + { > + Return(BB00) > + } > + > + // > + // _PXM is ACPI method called by OS to read Proximity Domain of IIO > stack. > + // > + Method(_PXM, 0, NotSerialized) > + { > + Return(0) > + } > + > + // > + // _SEG is ACPI method called by OS to read PCI segment of IIO stack. > + // > + Method(_SEG, 0, NotSerialized) > + { > + Return(SG00) > + } > + > + Method(_OSC,4) { > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,0,CDW1) > + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,4,CDW2) > + > + // > + // Fill 3rd capability DWORD only if the count is greater than 2= . > + // > + If(LGreater(Arg2,2)) { > + CreateDWordField(Arg3,8,CDW3) > + } > + > + // > + // Save Capabilities DWord2 & 3 > + // > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > + > + // > + // Never allow SHPC (no SHPC controller in system) > + // > + And(CTRL, 0x1D, CTRL) > + > + // > + // Select Native PCIe AER/eDPC handling from OS or Firmware Firs= t > model > + // > + If (CondRefOf (\_SB.OSNC)) > + { > + //in case OS has AER capability. > + If (LEqual ( And(CTRL, 8), 8)) { > + > + //in case OS support multiple segment. > + If (And (SUPP, 8)) { > + If (CondRefof (^_SEG)) > + { > + Store (^_SEG, Local0) > + } Else { > + Store (0, Local0) > + } > + } Else { > + Store (0, Local0) > + } > + > + Store (^_BBN, Local1) > + > + // if BIOS allows OS take. Do nothing. > + If (\_SB.OSNC(Local0, Local1, SUPP, CTRL)) { > + > + } Else { > + And (CTRL, Not(0x88), CTRL) > + } > + } Else { > + And (CTRL, Not(0x88), CTRL) > + } > + } Else { > + // > + //Disable Native PCIe AER/eDPC handling from OS, AER is bit3, = eDPC is > bit7 > + // > + And (CTRL, Not(0x88), CTRL) > + } > + > + If (Not(And(CDW1,1))) { // Query Flag Clear? > + // > + // Disable GPEs for Features granted native control > + // > + If (And(CTRL, 0x01)) { // Native Hot plug control granted? > + if(LEqual(DBGM, 0x01)){ > + Store (0xE3, IO80) > + } > + \_SB.PC01.BR1A.OSHP () > + \_SB.PC01.BR1B.OSHP () > + \_SB.PC01.BR1C.OSHP () > + \_SB.PC01.BR1D.OSHP () > + > + Store (0x01, GPSH) // Clear Hotplug SCI Enabl= e in GPE0 > + } > + } > + > + If (LNotEqual(Arg1,one)) { // unknown revision > + Or(CDW1,0x08,CDW1) > + } > + > + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked > + Or(CDW1,0x10,CDW1) > + } > + // > + // update DWORD3 in the buffer > + // > + Store(CTRL,CDW3) > + Return(Arg3) > + > + } Else { > + // > + // Just indicate unrecognized UUID > + // Leave it at that > + // > + Or (CDW1,4,CDW1) > + if(LEqual(DBGM, 0x01)){ > + Store (0xEE, IO80) > + } > + Return(Arg3) > + } > + } // End _OSC > + > +#include "PchApic.asi" > + > + > +#define RESOURCE_CHUNK1_OFF 0 > +#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16) > +#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8) > +#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16) > +#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16) > +#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26) > +#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26) > + > +#define PciResourceStart Local0 > +#define PciResourceLen Local1 > + > + Name(P0RS, ResourceTemplate() { > + //RESOURCE_CHUNK1_OFF > + WORDBusNumber( // Bus number resource (0); the bridge pro= duces > bus numbers for its subsequent buses > + ResourceProducer, // bit 0 of general flags is 1 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, // PosDecode > + 0x0000, // Granularity (FIX1 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Min (FIX1 - Patched by ACPI Pla= tform Driver during > POST) > + 0x0000, // Max (FIX1 - Patched by ACPI Pla= tform Driver > during POST) > + 0x0000, // Translation > + 0x0001, // Range Length =3D Max-Min+1 (FIX1 - Patc= hed by ACPI > Platform Driver during POST) > + , > + , > + FIX1 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + //RESOURCE_CHUNK2_OFF > + IO( // Consumed resource (CF8-CFF) > + Decode16, > + 0x0cf8, > + 0xcf8, > + 1, > + 8 > + ) > + > + //RESOURCE_CHUNK3_OFF > + WORDIO( // Consumed-and-produced resource (all I/O= below > CF8) > + ResourceProducer, // bit 0 of general flags is 0 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, > + EntireRange, > + 0x0000, // Granularity > + 0x0000, // Min > + 0x0cf7, // Max > + 0x0000, // Translation > + 0x0cf8 // Range Length > + ) > + > + //RESOURCE_CHUNK4_OFF > + WORDIO( // Consumed-and-produced resource (all I/O= above > CFF) > + ResourceProducer, // bit 0 of general flags is 0 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, > + EntireRange, > + 0x0000, // Granularity (FIX2 - Patched by ACPI Pl= atform Driver > during POST) > + 0x0000, // Min (FIX2 - Patched by ACPI Pl= atform Driver > during POST) > + 0x0000, // Max (FIX2 - Patched by ACPI Pl= atform Driver > during POST) > + 0x0000, // Translation > + 0x0001, // Range Length (FIX2 - Patched by ACPI Pl= atform Driver > during POST) > + , > + , > + FIX2 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + //RESOURCE_CHUNK5_OFF > + DWORDMEMORY( // descriptor for video RAM on video card > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, > + MinFixed, // Range is fixed > + MaxFixed, // Range is Fixed > + Cacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIX5 - Patched by ACPI Pl= atform Driver > during POST) > + 0x00000000, // Min (FIX5 - Patched by ACPI Pl= atform Driver > during POST) > + 0x00000000, // Max (FIX5 - Patched by ACPI Pl= atform Driver > during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (FIX5 - Patched by ACPI Pl= atform > Driver during POST) > + , > + , > + FIX5 // Descriptor Name > + ) > + > + //RESOURCE_CHUNK6_OFF > + DWORDMEMORY( // descriptor for Shadow RAM > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, > + MinFixed, // Range is fixed > + MaxFixed, // Range is Fixed > + Cacheable, > + ReadWrite, > + 0x00000000, // Granularity > + 0x00000000, // Min (calculated dynamically) > + 0x00000000, // Max (calculated dynamically) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) > + , > + , > + SRAM // DescriptorName populated so iASL doesn'= t flag 0 value > fields and no tag as error > + ) > +/* > + //RESOURCE_TPM > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity > + 0xFED40000, // Min (calculated dynamically) > + 0xFEDFFFFF, // Max =3D 4GB - 1MB (fwh + fwh alias...) > + 0x00000000, // Translation > + 0x000C0000 // Range Length (calculated dynamically) > + ) > +*/ > + > DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCac > heable, > + ReadWrite,0x00,0xFE010000,0xFE010FFF,0x00,0x1000) > + > + // > + // PCI RESOURCE_32bit > + // > + DWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000, // Granularity (FIX3 - Patched by ACPI Pla= tform Driver > during POST) > + 0x00000000, // Min (calculated dynamically) (FIX3 - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IX3 - Patched > by ACPI Platform Driver during POST) > + 0x00000000, // Translation > + 0x00000000, // Range Length (calculated dynamically) (= FIX3 - > Patched by ACPI Platform Driver during POST) > + , > + , > + FIX3 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + > + // > + // PCI RESOURCE_64bit > + // > + QWORDMemory( // Consumed-and-produced resource(all of > memory space) > + ResourceProducer, // bit 0 of general flags is 0 > + PosDecode, // positive Decode > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + NonCacheable, > + ReadWrite, > + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Pla= tform > Driver during POST) > + 0x00000000000, // Min (calculated dynamically) (FIX4 - Pa= tched by > ACPI Platform Driver during POST) > + 0x00000000000, // Max =3D 4GB - 1MB (fwh + fwh alias) (F= IX4 - > Patched by ACPI Platform Driver during POST) > + 0x00000000000, // Translation > + 0x00000000000, // Range Length (calculated dynamically) (= FIX4 - > Patched by ACPI Platform Driver during POST) > + , > + , > + FIX4 // DescriptorName populated so iASL output= s offset for it > in a .h file > + ) > + }) // end of P0RS Buffer > + > + OperationRegion(TMEM, PCI_Config, 0x00, 0x100) > + Field(TMEM, ByteAcc, NoLock, Preserve) { > + Offset(0x40), > + , 4, > + BSEG, 4, > + PAMS, 48, > + Offset(0x52), > + DIM0, 4, > + DIM1, 4, > + , 8, > + DIM2, 4, > + } > + > + Name(MTBL, Package(0x10) { > + 0x0, > + 0x20, > + 0x20, > + 0x30, > + 0x40, > + 0x40, > + 0x60, > + 0x80, > + 0x80, > + 0x80, > + 0x80, > + 0xc0, > + 0x100, > + 0x100, > + 0x100, > + 0x200 > + }) > + > + Name(ERNG, Package(0xd) { > + 0xc0000, > + 0xc4000, > + 0xc8000, > + 0xcc000, > + 0xd0000, > + 0xd4000, > + 0xd8000, > + 0xdc000, > + 0xe0000, > + 0xe4000, > + 0xe8000, > + 0xec000, > + 0xf0000 > + }) > + > + Name(PAMB, Buffer(0x7) { > + }) > + > + Method(EROM, 0x0, NotSerialized) { > + CreateDWordField(P0RS, ^SRAM._MIN, RMIN) // Do not reference hard- > coded address > + CreateDWordField(P0RS, ^SRAM._MAX, RMAX) // Do not reference > hard-coded address > + CreateDWordField(P0RS, ^SRAM._LEN, RLEN) // Do not reference hard- > coded address > + CreateByteField(PAMB, 0x6, BREG) > + Store(PAMS, PAMB) > + Store(BSEG, BREG) > + Store(0x0, RMIN) > + Store(0x0, RMAX) > + Store(0x0, RLEN) > + Store(0x0, Local0) > + While(LLess(Local0, 0xd)) > + { > + ShiftRight(Local0, 0x1, Local1) > + Store(DerefOf(Index(PAMB, Local1, )), Local2) > + If(And(Local0, 0x1, )) > + { > + ShiftRight(Local2, 0x4, Local2) > + } > + And(Local2, 0x3, Local2) > + If(RMIN) > + { > + If(Local2) > + { > + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) > + If(LEqual(RMAX, 0xf3fff)) > + { > + Store(0xfffff, RMAX) > + } > + Subtract(RMAX, RMIN, RLEN) > + Increment(RLEN) > + } > + Else > + { > + Store(0xc, Local0) > + } > + } > + Else > + { > + If(Local2) > + { > + Store(DerefOf(Index(ERNG, Local0, )), RMIN) > + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) > + If(LEqual(RMAX, 0xf3fff)) > + { > + Store(0xfffff, RMAX) > + } > + Subtract(RMAX, RMIN, RLEN) > + Increment(RLEN) > + } > + Else > + { > + } > + } > + Increment(Local0) > + } > + } > + > + // Current resource template return > + Method(_CRS, 0x0, NotSerialized) { > + EROM() > + Return(P0RS) > + } > + > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 0610nmEjd.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 0610nmEjd.asi > new file mode 100644 > index 0000000000..966cd82640 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 0610nmEjd.asi > @@ -0,0 +1,10 @@ > +/** @file > + > + @copyright > + Copyright 2016 - 0610 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // Eject device if PC06 is removed. > + Name(_EJD,"\\_SB.PC06") // Dependent on PC18 > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 1210nmEjd.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 1210nmEjd.asi > new file mode 100644 > index 0000000000..6c210da62d > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 1210nmEjd.asi > @@ -0,0 +1,10 @@ > +/** @file > + > + @copyright > + Copyright 2016 - 2018 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // Eject device if PC12 is removed. > + Name(_EJD,"\\_SB.PC12") // Dependent on PC18 > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 1810nmEjd.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 1810nmEjd.asi > new file mode 100644 > index 0000000000..7b6aa91cd5 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC > 1810nmEjd.asi > @@ -0,0 +1,10 @@ > +/** @file > + > + @copyright > + Copyright 2016 - 2018 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // Eject device if PC18 is removed. > + Name(_EJD,"\\_SB.PC18") // Dependent on PC18 > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pch > Apic.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pc > hApic.asi > new file mode 100644 > index 0000000000..e76063647e > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pc > hApic.asi > @@ -0,0 +1,18 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2012 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +Device(APIC) { > + Name (_HID,EISAID("PNP0003")) // APIC resources > + Name (_CRS, ResourceTemplate() { > + // > + // APIC range(0xFEC0_0000 to 0xFECF_FFFF) > + // > + Memory32Fixed (ReadOnly, 0xFEC00000, 0x100000) // IO APIC > + } > + ) > +} > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci > eHp.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci > eHp.asi > new file mode 100644 > index 0000000000..64484e5402 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci > eHp.asi > @@ -0,0 +1,669 @@ > +/** @file > + > + @copyright > + Copyright 2007 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + External (DBGM, FieldUnitObj) > + > + Method (_INI, 0, NotSerialized) > + { > + } > + > + Name(_HPP, Package(){0x08, 0x40, SERR, PERR}) > + > + // > + // begin hotplug code > + // > + Name(SHPC, 0x40) // Slot Hot-plug Capable > + > + Name(SPDS, 0x040) // Slot Presence Detect State > + > + Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on > + Name(CCOM, 0x010) // Command Complete > + Name(SPDC, 0x08) // Slot Presence Detect Changes > + Name(MRLC, 0x04) // Slot MRL Changed > + Name(SPFD, 0x02) // Slot Power Fault Detected > + Name(SABP, 0x01) // Slot Attention Button Pressed > + > + Name(SPOF, 0x10) // Slot Power Off > + Name(SPON, 0x0F) // Slot Power On Mask > + > + Name(ALMK, 0x1C) // Slot Atten. LED Mask > + Name(ALON, 0x01) // Slot Atten. LED On > + Name(ALBL, 0x02) // Slot Atten LED Blink > + Name(ALOF, 0x03) // Slot Atten LED Off > + > + Name(PLMK, 0x13) // Slot Pwr. LED Mask > + Name(PLON, 0x04) // Slot Pwr. LED On > + Name(PLBL, 0x08) // Slot Pwr. LED Blink > + Name(PLOF, 0x0C) // Slot Pwr. LED Off > + > + //;************************************* > + //; Bit 3 =3D Presence Detect Event > + //; Bit 2 =3D MRL Sensor Event > + //; Bit 1 =3D PWR Fault Event > + //; Bit 0 =3D Attention Button Event > + //;************************************* > + Name(HPEV, 0xF) // Possible interrupt events (all) > + > + > //;******************************************************** > ****************; > + //; PCIe Slot Capabilities Register > + //; Bit - 31-5 - Not used > + //; Bit - 4 - Power Indicator Present. > + //; Bit - 3 - Attention Indicator Present. > + //; Bit - 2 - MRL Sensor Present. > + //; Bit - 1 - Power Controller Present. > + //; Bit - 0 - Attention Button Present. > + //; > + //; PCIe Slot control Register > + //; Bit - 10 - PWR Control Disable > + //; Bit - 9:8 - Attn Indicator > + //; Bit - 7:6 - PWR Indicator > + //; Bit - 5 - Hot-Plug Interrupt Event Enable > + //; Bit - 4 - Command Complete Interrupt enable > + //; Bit - 3 - Presence Detect Changed Interrupt enable > + //; Bit - 2 - MRL Sensor Changed Interrupt enable > + //; Bit - 1 - PwrFault Detect Interrupt enable > + //; Bit - 0 - Attention Button Pressed Interrupt Enable > + //; > + //; PCIe Slot Status Registers > + //; Bit - 6 - Presence Detect State. > + //; Bit - 5 - MRL Sensor State. > + //; Bit - 4 - Command Completed. > + //; > + //; RWC Status Bits > + //; > + //; Bit - 3 - Presence Detect Changed. > + //; Bit - 2 - MRL Sensor Changed. > + //; Bit - 1 - Power Fault Detected. > + //; Bit - 0 - Attention Button Pressed. > + > //;******************************************************** > ****************; > + OperationRegion (PXCP, PCI_Config, IRPC, 0x40) > + Field (PXCP, ByteAcc, NoLock, Preserve) { > + Offset (0x10), // Link Control Register > + , 4, > + LDIS, 1, // Link Disable bit4. > + , 11, > + Offset (0x14), // PCI Slot Capabilities Register > + ATBP, 1, // Attention Button Present > + , 1, > + MRSP, 1, // MRL Sensor Present > + ATIP, 1, // Attention Indicator Present > + PWIP, 1, // Power Indicator Present > + , 14, > + PSNM, 13, // Physical Slot Number > + Offset (0x18), // Slot Control Register > + ABIE, 1, // Attention Button Pressed Interrupt Enab= le > + PFIE, 1, // Power Fault Detected Interrupt Enable > + MSIE, 1, // MRL Sensor Changed Interrupt Enable > + PDIE, 1, // Presence Detect Changed Interrupt Enabl= e. > + CCIE, 1, // Command Complete Interrupt Enable. > + HPIE, 1, // Hot-plug Interrupt Enable. > + SCTL, 5, // Attn/Power indicator and Power controll= er. > + , 5, > + Offset (0x1A), // Slot Status Register > + SSTS, 7, // The status bits in Slot Status Reg > + , 1, > + Offset (0x20), // Root Status Register > + , 16, > + PMES, 1, // PME Status bit 16 > + PMEP, 1, // PME Pending bit 17 > + , 14 > + } > + > + // > + // These Methods replace the bit field definitions in PPA8 > + // that were bit fields within SCTL > + // > + Method (ATID, 0) { > + Return (And (SCTL, 0x03)) > + } > + > + Method (PWID, 0) { > + Return (ShiftRight (And (SCTL, 0x0C), 2)) > + } > + > + Method (PWCC, 0) { > + Return (ShiftRight (And (SCTL, 0x10), 4)) > + } > + > + // > + // These methods replace the bit fields definitions in PPA8 > + // that were bit fields within SSTS > + // > + Method (ABPS, 1) { > + If (LEqual (Arg0, 1)) { > + Or (SSTS, 0x01, SSTS) > + } > + Return (And (SSTS, 0x01)) > + } > + > + Method (PFDS, 1) { > + If (LEqual (Arg0, 1)) { > + Or (SSTS, 0x02, SSTS) > + } > + Return (ShiftRight (And (SSTS, 0x02), 1)) > + } > + > + Method (MSCS, 1) { > + If (LEqual (Arg0, 1)) { > + Or (SSTS, 0x04, SSTS) > + } > + Return (ShiftRight (And (SSTS, 0x04), 2)) > + } > + > + Method (PDCS, 1) { > + If (LEqual (Arg0, 1)) { > + Or (SSTS, 0x08, SSTS) > + } > + Return (ShiftRight (And (SSTS, 0x08), 3)) > + } > + > + Method (CMCS, 1) { > + If (LEqual (Arg0, 1)) { > + Or (SSTS, 0x10, SSTS) > + } > + Return (ShiftRight (And (SSTS, 0x10), 4)) > + } > + > + Method (MSSC, 1) { > + If (LEqual (Arg0, 1)) { > + Or (SSTS, 0x20, SSTS) > + } > + Return (ShiftRight (And (SSTS, 0x20), 5)) > + } > + > + Method (PRDS, 1) { > + If (LEqual (Arg0, 1)) { > + Or (SSTS, 0x40, SSTS) > + } > + Return (ShiftRight (And (SSTS, 0x40), 6)) > + } > + > + > + > //;******************************************************** > ****************; > + //; This OSHP (Operating System Hot Plug) method is provided for each > HPC > + //; which is controlled by ACPI. This method disables ACPI access to t= he > + //; HPC and restores the normal System Interrupt and Wakeup Signal > + //; connection. > + > //;******************************************************** > ****************; > + Method(OSHP) { // OS call to unhook Legacy ASL PCI-Expres= s HP > code. > + Store(SSTS, Local0) // Clear any status (RW1C) > + Store(Local0, SSTS) // (use write thru Local to avoid iasl war= ning > 'Duplicate value in list ^ (Source is the same as Target)') > + } > + > + > //;******************************************************** > ****************; > + //; Hot Plug Controller Command Method > + //; > + //; Input: Arg0 - Command to issue > + //; > + > //;******************************************************** > ****************; > + Method(HPCC,1) { > + Store(SCTL, Local0) // get current command state > + Store(0, Local1) // reset the timeout value > + If(LNotEqual(Arg0, Local0)) { // see if state is different > + Store(Arg0, SCTL) // Update the Slot Control > + While(LAnd (LNot(CMCS(0)), LNotEqual(100, Local1))) { // spin whil= e > CMD complete bit is not set, > + // check for= timeout to avoid dead loop > + if(LEqual(DBGM, 0x01)){ > + Store(0xFB, IO80) > + } > + Sleep(2) // allow processor time slice > + Add(Local1, 2, Local1) > + } > + CMCS(1) // Clear the command complete status > + } > + } > + > + > //;******************************************************** > ****************; > + //; Attention Indicator Command > + //; > + //; Input: Arg0 - Command to issue > + //; 1 =3D ON > + //; 2 =3D Blink > + //; 3 =3D OFF > + > //;******************************************************** > ****************; > + Method(ATCM,1) { > + Store(SCTL, Local0) // Get Slot Control > + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits > + If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?" > + Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON" > + } > + If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?" > + Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLI= NK" > + } > + If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?" > + Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF= " > + } > + HPCC(Local0) > + } > + > + > //;******************************************************** > ****************; > + //; Power Indicator Command > + //; > + //; Input: Arg0 - Command to issue > + //; 1 =3D ON > + //; 2 =3D Blink > + //; 3 =3D OFF > + > //;******************************************************** > ****************; > + Method(PWCM,1){ > + Store(SCTL, Local0) // Get Slot Control > + And(Local0, PLMK, Local0) // Mask the Power Indicator Bits > + If(LEqual(Arg0, 0x1)){ // Power indicator "ON?" > + Or(Local0, PLON, Local0) // Set the Power Indicator to "ON" > + } > + If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?" > + Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK" > + } > + If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?" > + Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF" > + } > + HPCC(Local0) > + } > + > + > //;******************************************************** > ****************; > + //; Power Slot Command > + //; > + //; Input: Arg0 - Command to issue > + //; 1 =3D Slot Power ON > + //; 2 =3D Slot Power Off > + > //;******************************************************** > ****************; > + Method(PWSL,1){ > + Store(SCTL, Local0) // Get Slot Control > + If(Arg0){ // Power Slot "ON" Arg0 =3D 1 > + And(Local0, SPON, Local0) // Turns the Power "ON" > + } Else { // Power Slot "OFF" > + Or(Local0, SPOF, Local0) // Turns the Power "OFF" > + } > + HPCC(Local0) > + } > + > + > //;******************************************************** > ****************; > + //; _OST Methods to indicate that the device Eject/insert request is > + //; pending, OS could not complete it > + //; > + //; Input: Arg0 - Value used in Notify to OS > + //; 0x00 - card insert > + //; 0x03 - card eject > + //; Arg1 - status of Notify > + //; 0 - success > + //; 0x80 - Ejection not supported by OSPM > + //; 0x81 - Device in use > + //; 0x82 - Device Busy > + //; 0x84 - Ejection in progress-pending > + > //;******************************************************** > ****************; > + Method(_OST,3,Serialized) { > + Switch(And(Arg0,0xFF)) { // Mask to retain low byte > + Case(0x03) { // Ejection Request > + Switch(ToInteger(Arg1)) { > + Case(Package() {0x80, 0x81, 0x82, 0x83}) { > + // > + // Ejection Failure for some reason > + // > + If (Lnot(PWCC())) { // if slot is powered > + PWCM(0x1) // Set PowerIndicator to ON > + Store(0x1,ABIE) // Set AttnBtn Interrupt ON > + } > + } > + } > + } > + } > + #include "IioPcieEdpcOst.asi" > + } // End _OST > + > + // > + // _DSM Device Specific Method > + // > + // Arg0: UUID Unique function identifier > + // Arg1: Integer Revision Level > + // Arg2: Integer Function Index (0 =3D Return Supported Functions) > + // Arg3: Package Parameters > + Method(_DSM, 4, Serialized) { > + // > + // Switch based on which unique function identifier was passed in > + // > + If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { > + // > + // _DSM Definitions for Latency Tolerance Reporting > + // > + // Arguments: > + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D > + // Arg1: Revision ID: 3 > + // Arg2: Function Index: 0, c, d > + // Arg3: Empty Package > + // > + // Switch by function index > + // > + Switch(ToInteger(Arg2)) { > + // > + // Function Index:0 > + // Standard query - A bitmask of functions supported > + // > + Case (0) { > + Name(OPTS, Buffer(2) {0, 0}) > + CreateBitField(OPTS, 0, FUN0) > + CreateBitField(OPTS, 12, FUNC) > + CreateBitField(OPTS, 13, FUND) > + > + Store(1, FUN0) > + Store(1, FUNC) > + Store(1, FUND) > + Return(OPTS) > + } > + // > + // Function Index: C > + // Downstream Port Containment Hint > + // > + Case(12) { > + Return(1) > + } > + > + // > + // Function Index: D > + // Downstream Port Containment Device Location > + // > + Case(13) { > + Name(DLOC, Buffer(2){0, 0}) > + CreateField(DLOC, 0, 3, DFUN) > + CreateField(DLOC, 3, 5, DDEV) > + CreateField(DLOC, 8, 8, DBUS) > + Store(_BBN, DBUS) > + store(_ADR, Local2) > + And(Local2, 0xffff, Local3) > + ShiftRight (Local2, 16, Local4) > + Store(Local4, DDEV) > + Store(Local3, DFUN) > + Return(ToInteger(DLOC)) > + } > + > + } // End of switch(Arg2) > + } // End of if > + return (Buffer() {0x00}) > + } // End of _DSM > + > + > //;******************************************************** > ****************; > + //; Eject Control Methods to indicate that the device is hot-ejectable= and > + //; should "eject" the device. > + //; > + //; > + > //;******************************************************** > ****************; > + Method(EJ0L){ > + if(LEqual(DBGM, 0x01)){ > + Store(0xFF, IO80) > + } > + Store(SCTL, Local0) // Get IIO Port Control state > + if( LNot( LEqual( ATID(), 1))) { // Check if Attention LED is not s= olid "ON" > + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bit= s > + Or(Local0, ALBL, Local0) // Set the Attention Indicator to b= link > + } > + HPCC(Local0) // issue command > + > + Store(SCTL, Local0) // Get IIO Port Control state > + Or(Local0, SPOF, Local0) // Set the Power Controller Control = to Power > Off > + HPCC(Local0) > + > + Store(SCTL, Local0) // Get IIO Port Control state > + Or(Local0, PLOF, Local0) // Set the Power Indicator to Off. > + HPCC(Local0) > + > + Store(SCTL, Local0) // Get IIO Port Control state > + Or(Local0, ALOF, Local0) // Set the Attntion LED to Off. > + HPCC(Local0) > + > + } // End of EJ0L > + > + > //;******************************************************** > ****************; > + //; PM_PME Wake Handler for All Slots > + //; > + //; Input: Arg0 - Slot Numnber > + //; > + > //;******************************************************** > ****************; > + Method(PMEH,1){ // Handler for PCI-E PM_PME Wake > Event/Interupt (GPI xxh) > + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events > + If(ABPS(0)) { > + if(LEqual(DBGM, 0x01)){ > + if(LEqual(DBGM, 0x01)){ > + Store (Arg0, IO80) // Send slot number to Port 80 > + } > + } > + ABPS(1) // Clear the interrupt status > + Sleep(200) // delay 200ms > + } > + } > + Return (0xff) // Indicate that this controller did= not interrupt > + } // End of Method PMEH > + > + > //;******************************************************** > ****************; > + //; Hot-Plug Handler for All Slots. > + //; > + //; Input: Arg0 - Slot Number > + //; > + > //;******************************************************** > ****************; > + Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/= Interupt > (GPI xxh) > + if(LEqual(DBGM, 0x01)){ > + Store(0xFE, IO80) > + } > + Sleep(100) > + Store(0,CCIE) // Disable command interrupt > + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events > + if(LEqual(DBGM, 0x01)){ > + Store(0xFD, IO80) > + } > + Sleep(10) > + if(LEqual(DBGM, 0x01)){ > + Store (Arg0, IO80) // Send slot number to Port 80 > + } > + Sleep(10) > + Store(PPXH(), Local0) // Call Hot plug Interrupt Handler > + Return(Local0) // Return PPXH information > + } > + Else{ > + Return (0xff) // Indicate that this controller did= not interrupt > + } > + if(LEqual(DBGM, 0x01)){ > + Store(0xFC, IO80) > + } > + Sleep(10) > + } // End of Method HPEH > + > + > //;******************************************************** > ****************; > + //; Interrut Event Handler > + //; > + //; > + > //;******************************************************** > ****************; > + Method(PPXH){ // Hot plug Interrupt Handler > + // > + // Check for the Atention Button Press, Slot Empty/Presence, Power > Controller Control. > + // > + Sleep(200) // HW Workaround for AttentionButt= on Status to > stabilise > + If(ABPS(0)) { // Check if Attention Button Press= ed > + If(LNot(PRDS(0))) { // See if nothing installed (no ca= rd in slot) > + Store(0x1, LDIS) // Disable the Link associated wit= h PCI-E port > + PWSL(0x0) // make sure Power is Off > + PWCM(0x3) // Set Power Indicator to "OFF" > + // > + // Check for MRL here and set attn indicator accordingly > + // > + If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL close= d > + ATCM(0x2) // Set Attention Indicator to "BLI= NK" > + } else { // Standby power is off - MRL open > + ATCM(0x3) // set attention indicator "OFF" > + } > + Store(0x0, ABIE) // set Attention Button Interrupt = to disable > + ABPS(1) // Clear the interrupt status > + Sleep(200) // delay 200ms > + Return(0xff) // Attn Button pressed without car= d in slot. Do > nothing > + } > + // > + // Card is present in slot so.... > + // > + Store(0x0, ABIE) // set Attention Button Interrupt = to disable > + // Attn Btn Interrupt has to be en= abled only after an > insert oprn > + ABPS(1) // Clear the interrupt status > + Sleep(200) // delay 200ms > + // > + // Check for MRL here - only if SPWR is OFF blink AttnInd and retu= n 0xff > + // > + //If(LNot(LEqual(MSSC()),MRLS))) { // Standby power is off > + // PWSL(0x0) // make sure Power is Off > + // PWCM(0x3) // Set Power Indicator to "OFF" > + // ATCM(0x2) // Set Attention Indicator to "B= LINK" > + // Return(0xff) // Attn Button pressed with card= in slot, but MRL > open. Do nothing > + //} > + //Card Present, if StandbyPwr is ON proceed as below with Eject > Sequence > + If(PWCC()) { // Slot not Powered > + PWCM(0x3) // Set Power Indicator to "OFF" > + ATCM(0x2) // Set Attention Indicator to "BLI= NK" > + Return(0xff) // Attn Button pressed with card i= n slot, MRL > closed, Slot not powered. Do nothing > + } Else { // See if Slot is already Powered > + PWCM(0x2) // Set power Indicator to BLINK > + Sleep(600) // Wait 100ms > + Store(600, Local0) // set 5 second accumulator to 0 > + ABPS(1) // Clear the interrupt status > + Sleep(200) // delay 200ms > + While(LNot(ABPS(0))) { // check for someone pressing A= ttention > + Sleep(200) // Wait 200ms > + Add(Local0, 200, Local0) > + If(LEqual(5000, Local0)) { // heck if 5sec has passed without= pressing > attnetion btn > + ABPS(1) // Clear the interrupt status > + Sleep(200) // delay 200ms > + Return (0x3) // continue with Eject request > + } > + } > + PWCM(0x1) // Set power Indicator baCK "ON" > + ABPS(1) // Clear the Attention status > + Sleep(200) // delay 200ms > + Store(0x1, ABIE) // set Attention Button Interrupt = to enable > + Return (0xff) // do nothing and abort > + } > + } // End if for the Attention Button Hot Plug Interrupt. > + > + If(PFDS(0)) { // Check if Power Fault Detected > + PFDS(1) // Clear the Power Fault Status > + PWSL(0x0) // set Power Off > + PWCM(0x3) // set power indicator to OFF > + ATCM(0x1) // set attention indicator "ON" > + Store(0x1, LDIS) // Disable the Link associated wit= h PCI-E port > + Return(0x03) // Eject request. > + } // End if for the Power Fault Interrupt. > + > + If(MSCS(0)) { // Check interrupt caused by the M= RL Sensor > + MSCS(1) // Clear the MRL Status > + If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL close= d > + If(PRDS(0)) { // Card is Present > + > + ATCM(0x3) // Set Attention Indicator to off > + PWCM(0x2) // Set Power Indicator to Blink > + Sleep(600) // Wait 100ms > + Store(600, Local0) // set 5 second accumulator to 0 > + ABPS(1) // Clear the interrupt status > + While(LNot(ABPS(0))) { // check for someone pressing A= ttention > + Sleep(200) // Wait 200ms > + Add(Local0, 200, Local0) > + If(LEqual(5000, Local0)) { // Check if 5 sec elapsed > + Store(0x1, ABIE) // Enable Attention button interru= pt > + ATCM(0x3) // set attention indicator "OFF" > + Store(0x0, LDIS) // Enable the Link associated with= PCI-E port > + PWSL(0x1) // Power the Slot > + Sleep(500) // Wait for .5 Sec for the Power t= o Stabilize. > + // Check for the Power Fault Detection > + If(LNot(PFDS(0))) { // No Power Fault > + PWCM(0x1) // Set Power Indicator t= o "ON" > + // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 S= lot Clock > (GPIO16) > + // Notify the OS to load the Driver for the card > + Store(0x00, Local1) > + Store(0x1, ABIE) // Enable Attention butt= on interrupt > + } Else { // Power Fault present > + PWSL(0x0) // set Slot Power Off > + PWCM(0x3) // set power indicator t= o OFF > + ATCM(0x1) // set attention indicat= or "ON" > + Store(0x1, LDIS) // Disable the Link asso= ciated with PCI-E > port > + // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 = Slot Clock > (GPIO16) > + Store(0x03, Local1) // Eject request. > + } // End if for the Slot P= ower Fault > + ABPS(1) // Clear the Attention s= tatus > + Sleep(200) // delay 200ms > + Return(Local1) > + } > + } > + // > + // someone pressed Attention Button > + // > + ABPS(1) // Clear the Attention status > + Sleep(200) // delay 200ms > + PWSL(0x0) // Set Slot Power off > + PWCM(0x3) // Set Power Indicator back to "OFF" > + ATCM(02) // Set Attention Indicator to "BLINK= " > + Store(0x1, LDIS) // Disable the Link associated with = PCI-E port > + Return(0xff) // leave it off > + // End of Insert sequence > + } > + //MRL is closed, Card is not present > + PWSL(0x0) // Set Slot Power off > + PWCM(0x3) // Set Power Indicator back to "OFF" > + ATCM(02) // Set Attention Indicator to "BLINK= " > + Store(0x1, LDIS) // Disable the Link associated with = PCI-E port > + Return(0xff) // leave it off > + } Else { // MRL is open i.e Stdby power is tu= rned off > + If(PRDS(0)) { //card present MRL switched off > + ATCM(0x2) // Set Attention Indicator to "BLINK= " > + If(Lnot(PWCC())) { // If slot is powered > + // This event is not supported and someone has opened the MR= L and > dumped the power > + // on the slot with possible pending transactions. This cou= ld hose the > OS. > + // Try to Notify the OS to unload the drivers. > + PWSL(0x0) // Set Slot Power off > + PWCM(0x3) // Set Power Indicator back to "OFF" > + Store(0x1, LDIS) // Disable the Link associated with = PCI-E port > + Return(0x03) // Eject request. > + } Else { // Slot not powered, MRL is opened, = card still in slot - > Eject not fully complete > + Return(0xFF) > + } > + } > + //no card present and Stdby power switched off, turn AI off > + ATCM(0x3) // Set Attention Indicator to "OFF" > + Return(0xff) // leave it off > + } // End of MRL switch open/close stat= e > + } // End of MRL Sensor State Change > + > + If(PDCS(0)) { // Check if Presence Detect Changed = Status > + PDCS(1) // Clear the Presence Detect Changed= Status > + If(LNot(PRDS(0))) { // Slot is Empty > + PWSL(0x0) // Set Slot Power "OFF" > + PWCM(0x3) // set power indicator to "OFF" > + If(LEqual(MSSC(0),MRLS)) { // If Standby power is on > + ATCM(0x2) // Set Attention Indicator to "Blink= " > + } else { > + ATCM(0x3) // Set Attention Indicator to "OFF" > + } > + Store(0x1, LDIS) // Disable the Link associated with = PCI-E port > + Return(0xFF) // Do nothing > + } Else { // Slot Card is inserted > + // Irrespective of MRL state, do the following > + Store(0x0, LDIS) // Enable the Link associated with P= CI-E port > + PWSL(0x1) // Set Slot Power ON > + Sleep(500) // Wait for .5 Sec for the Power to = Stabilize. > + If(LNot(PFDS(0))) { // No Power Fault > + PWCM(0x1) // Set Power Indicator to "ON" > + Store(0x00, Local1) > + Store(0x1, ABIE) // Enable Attention button interrupt > + ATCM(0x3) // Set Attention Indicator to "OFF" > + } Else { // Power Fault present > + PWSL(0x0) // set Slot Power Off > + PWCM(0x3) // set power indicator to OFF > + ATCM(0x1) // set attention indicator "ON" > + Store(0x1, LDIS) // Disable the Link associated with = PCI-E port > + Store(0x03, Local1) // Eject request. > + } // End if for the Slot Power Fault > + ABPS(1) // Clear the Attention status > + Sleep(200) // delay 200ms > + Return(Local1) > + } > + } // End if for the Presence Detect Changed Hot Plug Interrupt. > + Return(0xff) // should not get here, but do device check if it do= es. > + } // End of method PP5H > + // > + // End of hotplug code > + // > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci > eHpDev.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci > eHpDev.asi > new file mode 100644 > index 0000000000..ce48d3800a > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci > eHpDev.asi > @@ -0,0 +1,53 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + Method(SNUM, 0, Serialized) { > + Store(PSNM, Local0) > + Return(Local0) > + } > + > + Device(H000) { > + Name(_ADR, 0x00000000) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot > + } > + Device(H001) { > + Name(_ADR, 0x00000001) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot > + } > + Device(H002) { > + Name(_ADR, 0x00000002) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot > + } > + Device(H003) { > + Name(_ADR, 0x00000003) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot > + } > + Device(H004) { > + Name(_ADR, 0x00000004) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot > + } > + Device(H005) { > + Name(_ADR, 0x00000005) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot > + } > + Device(H006) { > + Name(_ADR, 0x00000006) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot > + } > + Device(H007) { > + Name(_ADR, 0x00000007) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci > eNonHpDev.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci > eNonHpDev.asi > new file mode 100644 > index 0000000000..44872cefd4 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci > eNonHpDev.asi > @@ -0,0 +1,45 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + Method(SNUM, 0, Serialized) { > + Store(PSNM, Local0) > + Return(Local0) > + } > + > + Device(H000) { > + Name(_ADR, 0x00000000) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + } > + Device(H001) { > + Name(_ADR, 0x00000001) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + } > + Device(H002) { > + Name(_ADR, 0x00000002) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + } > + Device(H003) { > + Name(_ADR, 0x00000003) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + } > + Device(H004) { > + Name(_ADR, 0x00000004) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + } > + Device(H005) { > + Name(_ADR, 0x00000005) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + } > + Device(H006) { > + Name(_ADR, 0x00000006) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + } > + Device(H007) { > + Name(_ADR, 0x00000007) > + Method(_SUN, 0) { Return(SNUM) } // Slot User Number > + } > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla > tform.asl > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla > tform.asl > new file mode 100644 > index 0000000000..bd33a63efc > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla > tform.asl > @@ -0,0 +1,91 @@ > +/** @file > + ACPI DSDT table > + > + @copyright > + Copyright 2011 - 2019 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +// > +// Port from client > +// > + > +// > +// Original file line: 91 > +// > + > + > + External (\_SB.OSNC, MethodObj) > + > + > + > +// > +// Original file line: 163 > +// > + > +Method(ADBG,1,Serialized) > +{ > + Return(0) > +} > + > +// > +// Original file line: 1460 > +// > +Scope (\) > +{ > + // > + // Global Name, returns current Interrupt controller mode; > + // updated from _PIC control method > + // > + > + // > + // Procedure: GPRW > + // > + // Description: Generic Wake up Control Method ("Big brother") > + // to detect the Max Sleep State available in ASL Name sc= ope > + // and Return the Package compatible with _PRW format. > + // Input: Arg0 =3D bit offset within GPE register space device event = will be > triggered to. > + // Arg1 =3D Max Sleep state, device can resume the System from= . > + // If Arg1 =3D 0, Update Arg1 with Max _Sx state enable= d in the > System. > + // Output: _PRW package > + // > + Name(PRWP, Package(){Zero, Zero}) // _PRW Package > + > + Method(GPRW, 2) > + { > + Store(Arg0, Index(PRWP, 0)) // copy GPE# > + // > + // SS1-SS4 - enabled in BIOS Setup Sleep states > + // > + Store(ShiftLeft(SS1,1),Local0) // S1 ? > + Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ? > + Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ? > + Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ? > + // > + // Local0 has a bit mask of enabled Sx(1 based) > + // bit mask of enabled in BIOS Setup Sleep states(1 based) > + // > + If(And(ShiftLeft(1, Arg1), Local0)) > + { > + // > + // Requested wake up value (Arg1) is present in Sx list of availab= le Sleep > states > + // > + Store(Arg1, Index(PRWP, 1)) // copy Sx# > + } > + Else > + { > + // > + // Not available -> match Wake up value to the higher Sx state > + // > + ShiftRight(Local0, 1, Local0) > + // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x > + // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 =3D=3D Max Sx > + // } Else { // ??? Win2k / XP > + FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 =3D=3D Min Sx > + // } > + } > + > + Return(PRWP) > + } > +} > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla > tformGpe10nm.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla > tformGpe10nm.asi > new file mode 100644 > index 0000000000..4faa4cbaea > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla > tformGpe10nm.asi > @@ -0,0 +1,191 @@ > +/** @file > + > + @copyright > + Copyright 2017 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "MaxSocket.h" > +External(\_SB.WERR, DeviceObj) > + > +// General Purpose Event > + > +Scope (\_GPE) { > + > + // Based on Socket ID to be notified, evaluate appropriate devices. > + Method(NTFC, 2){ > + If(And(Arg0, 0x01)){ > + Notify(\_SB.SCK0, Arg1) > + } > + > +#if MAX_SOCKET > 1 > + If(And(Arg0, 0x02)){ > + Notify(\_SB.SCK1, Arg1) > + } > +#endif > + > +#if MAX_SOCKET > 2 > + If(And(Arg0, 0x04)){ > + Notify(\_SB.SCK2, Arg1) > + } > +#endif > + > +#if MAX_SOCKET > 3 > + If(And(Arg0, 0x08)){ > + Notify(\_SB.SCK3, Arg1) > + } > +#endif > + > +#if MAX_SOCKET > 4 > + If(And(Arg0, 0x10)){ > + Notify(\_SB.SCK4, Arg1) > + } > +#endif > + > +#if MAX_SOCKET > 5 > + If(And(Arg0, 0x20)){ > + Notify(\_SB.SCK5, Arg1) > + } > +#endif > + > +#if MAX_SOCKET > 6 > + If(And(Arg0, 0x40)){ > + Notify(\_SB.SCK6, Arg1) > + } > +#endif > + > +#if MAX_SOCKET > 7 > + If(And(Arg0, 0x80)){ > + Notify(\_SB.SCK7, Arg1) > + } > +#endif > + } //End Method NTFC > +#if 0 > + Method(NTFM, 2){ > + > + // Based on Memory Board ID to be notified, evaluate appropriate > devices. > + If(And(Arg0, 0x01)){ > + Notify(\_SB.SCK0.M000, Arg1) > + } > + If(And(Arg0, 0x02)){ > + Notify(\_SB.SCK0.M001, Arg1) > + } > +#if MAX_SOCKET > 1 > + If(And(Arg0, 0x04)){ > + Notify(\_SB.SCK1.M000, Arg1) > + } > + If(And(Arg0, 0x08)){ > + Notify(\_SB.SCK1.M001, Arg1) > + } > +#endif > +#if MAX_SOCKET > 2 > + If(And(Arg0, 0x10)){ > + Notify(\_SB.SCK2.M000, Arg1) > + } > + If(And(Arg0, 0x20)){ > + Notify(\_SB.SCK2.M001, Arg1) > + } > +#endif > +#if MAX_SOCKET > 3 > + If(And(Arg0, 0x40)){ > + Notify(\_SB.SCK3.M000, Arg1) > + } > + If(And(Arg0, 0x80)){ > + Notify(\_SB.SCK3.M001, Arg1) > + } > +#endif > + > + } // End Method NTFM > +#endif > + > + Method(NTFI, 2){ > +#if MAX_SOCKET > 1 > + If(And(Arg0, 0x01)){ > + Notify(\_SB.PC06, Arg1) > + Notify(\_SB.PC07, Arg1) > + Notify(\_SB.PC08, Arg1) > + Notify(\_SB.PC09, Arg1) > + Notify(\_SB.PC10, Arg1) > + Notify(\_SB.PC11, Arg1) > + > + } > +#endif > +#if MAX_SOCKET > 2 > + If(And(Arg0, 0x02)){ > + Notify(\_SB.PC12, Arg1) > + Notify(\_SB.PC13, Arg1) > + Notify(\_SB.PC14, Arg1) > + Notify(\_SB.PC15, Arg1) > + Notify(\_SB.PC16, Arg1) > + Notify(\_SB.PC17, Arg1) > + } > +#endif > +#if MAX_SOCKET > 3 > + If(And(Arg0, 0x04)){ > + Notify(\_SB.PC18, Arg1) > + Notify(\_SB.PC19, Arg1) > + Notify(\_SB.PC20, Arg1) > + Notify(\_SB.PC21, Arg1) > + Notify(\_SB.PC22, Arg1) > + Notify(\_SB.PC23, Arg1) > + } > +#endif > + } //End Method NTFI > + > + // Tell OS to run thru the new status of this device (Software SCI gen= erated > from SMM for all Hot plug events) > + Method (_L62, 0x0, NotSerialized) { > + if(LEqual(SCI0, 3)) { // Device ejection (Invoked with _EJ0 method c= alled) > + //NTFM (SCI1, 3) > + NTFC (SCI2, 3) > + Store (0, SCI0) > + } ElseIf (LEqual(SCI0, 1)) { // Device check (OS can still reject on= line > request based on resources and capability) > + NTFC (CPHP, 0) > + NTFI (IIOP, 0) > + Store (0, CPHP) > + Store (0, IIOP) > + Store (0, SCI0) > + } > + > + #include "NvdimmGpe.asi" > + > + // Retrieve leaf and root notification data pre SWGPE clear > + Store (NNPR (), Local0) > + > + Store (0, GPEC) > + > + if(LEqual(WSCI, 0x1)) { > + Store(0, WSCI) > + if(LEqual(DBGM, 0x01)){ > + Store (0x4A, IO80) > + } > + If (CondRefOf (\_SB.WERR)) { > + Notify (\_SB.WERR, 0x80) > + } > + } > + > + // Perform NVDIMM leaf and root notifications with notification data > updated post SWGPE clear > + NNDO (Local0) > + > + /// > + /// Handle HWP SCI event > + /// > + //#include "HwpLvt.asi" > + > + // > + // Handle eDPC SWGPE event > + // > + #include "IioPcieEdpcGpe.asi" > + } > + > + // PME supported for Slots, use GPE 9 for PME > + // Hot plug on all slots for now, change later. > + // Slot numbers on silk screen might be different than the port number= , > currently use port numbers. > + // > + // IIO PCI_E Slot Hotplug GPE Event > + // > + Method (_L61, 0, NotSerialized) { > + #include "IioPcieHotPlugGpeHandler10nm.asl" > + }// end of _L61 GPE Method > + > +}// end of _GPE scope > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla > tformPciTree10nm_EPRP.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla > tformPciTree10nm_EPRP.asi > new file mode 100644 > index 0000000000..2ad0a32d25 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla > tformPciTree10nm_EPRP.asi > @@ -0,0 +1,5388 @@ > +/** @file > + @copyright > + Copyright 2005 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#ifndef CONCATENATE2 > +#define CONCATENATE2_(a, b) a ## b > +#define CONCATENATE2(a, b) CONCATENATE2_(a, b) > +#endif > +#ifndef CONCATENATE3 > +#define CONCATENATE3_(a, b, c) a ## b ## c > +#define CONCATENATE3(a, b, c) CONCATENATE3_(a, b, c) > +#endif > + > +Scope (\_SB) { > + > + Name (AR00, Package() { > + // [IIM0]: IIOMISC on PC00 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [CB0A]: CB3DMA on PC00 > + // [CB0E]: CB3DMA on PC00 > + Package() { 0x0001FFFF, 0, 0, 17 }, > + // [CB0B]: CB3DMA on PC00 > + // [CB0F]: CB3DMA on PC00 > + Package() { 0x0001FFFF, 1, 0, 18 }, > + // [CB0C]: CB3DMA on PC00 > + // [CB0G]: CB3DMA on PC00 > + Package() { 0x0001FFFF, 2, 0, 19 }, > + // [CB0D]: CB3DMA on PC00 > + // [CB0H]: CB3DMA on PC00 > + Package() { 0x0001FFFF, 3, 0, 16 }, > + // [MSM1] MSM > + Package() { 0x0002FFFF, 0, 0, 18 }, > + // [PMON] PMON MSM > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + // [NRPK]: NorthPeak > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [DMI0]: Legacy PCI Express Port 0 on PC00 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + // [IHC1]: IE HECI #1 > + // [IHC3]: IE HECI #3 > + Package() { 0x0010FFFF, 0, 0, 16 }, > + // [IHC2]: IE HECI #2 > + Package() { 0x0010FFFF, 1, 0, 17 }, > + // [IIDR]: IE IDE-Redirection (IDE-R) > + Package() { 0x0010FFFF, 2, 0, 18 }, > + // [IMKT]: IE Keyboard and Text (KT) Redirection > + Package() { 0x0010FFFF, 3, 0, 19 }, > + // [SAT2]: sSATA Host controller on PCH > + // [MRO0]: MROM 0 function > + // [MRO1]: MROM 1 function > + Package() { 0x0011FFFF, 0, 0, 17 }, > + Package() { 0x0011FFFF, 1, 0, 18 }, > + Package() { 0x0011FFFF, 2, 0, 19 }, > + Package() { 0x0011FFFF, 3, 0, 16 }, > + // [XHCI]: xHCI controller 1 on PCH > + Package() { 0x0014FFFF, 0, 0, 16 }, > + Package() { 0x0014FFFF, 1, 0, 17 }, > + // [TERM]: Thermal Subsystem on PCH > + Package() { 0x0014FFFF, 2, 0, 18 }, > + Package() { 0x0014FFFF, 3, 0, 19 }, > + // [HEC1]: ME HECI #1 on PCH > + // [HEC3]: ME HECI #3 on PCH > + Package() { 0x0016FFFF, 0, 0, 18 }, > + // [HEC2]: ME HECI #2 on PCH > + Package() { 0x0016FFFF, 1, 0, 19 }, > + // [IDER]: ME IDE redirect on PCH > + Package() { 0x0016FFFF, 2, 0, 16 }, > + // [MEKT]: MEKT on PCH > + Package() { 0x0016FFFF, 3, 0, 17 }, > + // [SAT1]: SATA controller 1 on PCH > + Package() { 0x0017FFFF, 0, 0, 19 }, > + // [RP17]: PCIE PCH Root Port #17 > + Package() { 0x001BFFFF, 0, 0, 19 }, > + // [RP18]: PCIE PCH Root Port #18 > + Package() { 0x001BFFFF, 1, 0, 16 }, > + // [RP19]: PCIE PCH Root Port #19 > + Package() { 0x001BFFFF, 2, 0, 17 }, > + // [RP20]: PCIE PCH Root Port #20 > + Package() { 0x001BFFFF, 3, 0, 18 }, > + // [RP01]: PCIE PCH Root Port #1 > + // [RP05]: PCIE PCH Root Port #5 > + Package() { 0x001CFFFF, 0, 0, 16 }, > + // [RP02]: PCIE PCH Root Port #2 > + // [RP06]: PCIE PCH Root Port #6 > + Package() { 0x001CFFFF, 1, 0, 17 }, > + // [RP03]: PCIE PCH Root Port #3 > + // [RP07]: PCIE PCH Root Port #7 > + Package() { 0x001CFFFF, 2, 0, 18 }, > + // [RP04]: PCIE PCH Root Port #4 > + // [RP08]: PCIE PCH Root Port #8 > + Package() { 0x001CFFFF, 3, 0, 19 }, > + // [RP09]: PCIE PCH Root Port #9 > + // [RP13]: PCIE PCH Root Port #13 > + Package() { 0x001DFFFF, 0, 0, 17 }, > + // [RP10]: PCIE PCH Root Port #10 > + // [RP14]: PCIE PCH Root Port #14 > + Package() { 0x001DFFFF, 1, 0, 18 }, > + // [RP11]: PCIE PCH Root Port #11 > + // [RP15]: PCIE PCH Root Port #15 > + Package() { 0x001DFFFF, 2, 0, 19 }, > + // [RP12]: PCIE PCH Root Port #12 > + // [RP16]: PCIE PCH Root Port #16 > + Package() { 0x001DFFFF, 3, 0, 16 }, > + // [P2SB]: P2SB > + // [PMC1]: Power Management Controller on PCH > + // [CAVS]: HD Audio Subsystem Controller on PCH > + // [SMBS]: SMBus controller on PCH > + // [GBE1]: GbE Controller on PCH > + // [TRHB]: Intel Trace Hub on PCH > + Package() { 0x001FFFFF, 3, 0, 19 }, > + Package() { 0x001FFFFF, 2, 0, 18 }, > + Package() { 0x001FFFFF, 1, 0, 17 }, > + Package() { 0x001FFFFF, 0, 0, 16 }, > + }) > + > + Name (AR01, Package() { > + // [SLTH]: PCIE PCH Slot #17 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR02, Package() { > + // [SLTI]: PCIE PCH Slot #18 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR03, Package() { > + // [SLTJ]: PCIE PCH Slot #19 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR04, Package() { > + // [SLTK]: PCIE PCH Slot #20 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR05, Package() { > + // [SLT1]: PCIE PCH Slot #1 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR06, Package() { > + // [SLT2]: PCIE PCH Slot #2 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR07, Package() { > + // [SLT3]: PCIE PCH Slot #3 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR08, Package() { > + // [SLT4]: PCIE PCH Slot #4 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR09, Package() { > + // [SLT5]: PCIE PCH Slot #5 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR0A, Package() { > + // [SLT6]: PCIE PCH Slot #6 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR0B, Package() { > + // [SLT7]: PCIE PCH Slot #7 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR0C, Package() { > + // [SLT8]: PCIE PCH Slot #8 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR0D, Package() { > + // [SLT9]: PCIE PCH Slot #9 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR0E, Package() { > + // [SLTA]: PCIE PCH Slot #10 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR0F, Package() { > + // [SLTB]: PCIE PCH Slot #11 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR10, Package() { > + // [SLTC]: PCIE PCH Slot #12 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR11, Package() { > + // [SLTD]: PCIE PCH Slot #13 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR12, Package() { > + // [SLTE]: PCIE PCH Slot #14 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR13, Package() { > + // [SLTF]: PCIE PCH Slot #15 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR14, Package() { > + // [SLTG]: PCIE PCH Slot #16 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR15, Package() { > + // [BR1A]: PCI Express Port 1A on PC01 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [BR1B]: PCI Express Port 1B on PC01 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [BR1C]: PCI Express Port 1C on PC01 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [BR1D]: PCI Express Port 1D on PC01 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR16, Package() { > + // [SL01]: PCI Express Slot 1 on 1A on PC01 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR17, Package() { > + // [SL02]: PCI Express Slot 2 on 1B on PC01 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR18, Package() { > + // [SL03]: PCI Express Slot 3 on 1C on PC01 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR19, Package() { > + // [SL04]: PCI Express Slot 4 on 1D on PC01 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR1A, Package() { > + // [BR2A]: PCI Express Port 2A on PC02 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [BR2B]: PCI Express Port 2B on PC02 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [BR2C]: PCI Express Port 2C on PC02 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [BR2D]: PCI Express Port 2D on PC02 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR1B, Package() { > + // [SL05]: PCI Express Slot 5 on 2A on PC02 > + // [EPCU]: EVA PCIe Uplink > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR1C, Package() { > + // [VSP0]: EVA Virtual Switch Port 0 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + // [VSP1]: EVA Virtual Switch Port 1 > + Package() { 0x0001FFFF, 0, 0, 19 }, > + // [VSP2]: EVA Virtual Switch Port 2 > + Package() { 0x0002FFFF, 0, 0, 16 }, > + // [VSP3]: EVA Virtual Switch Port 3 > + Package() { 0x0003FFFF, 0, 0, 17 }, > + }) > + > + Name (AR1D, Package() { > + // [CPM0]: EVA CPM0 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + }) > + > + Name (AR1E, Package() { > + // [CPM1]: EVA CPM1 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + }) > + > + Name (AR1F, Package() { > + // [CPM2]: EVA CPM2 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + }) > + > + Name (AR20, Package() { > + // [SL06]: PCI Express Slot 6 on 2B on PC02 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR21, Package() { > + // [SL07]: PCI Express Slot 7 on 2C on PC02 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR22, Package() { > + // [SL08]: PCI Express Slot 8 on 2D on PC02 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR23, Package() { > + // [BR3A]: PCI Express Port 3A on PC03 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [BR3B]: PCI Express Port 3B on PC03 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [BR3C]: PCI Express Port 3C on PC03 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [BR3D]: PCI Express Port 3D on PC03 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR24, Package() { > + // [SL09]: PCI Express Slot 9 on 3A on PC03 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR25, Package() { > + // [SL0A]: PCI Express Slot 10 on 3B on PC03 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR26, Package() { > + // [SL0B]: PCI Express Slot 11 on 3C on PC03 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR27, Package() { > + // [SL0C]: PCI Express Slot 12 on 3D on PC03 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR28, Package() { > + // [BR4A]: PCI Express Port 4A on PC04 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [BR4B]: PCI Express Port 4B on PC04 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [BR4C]: PCI Express Port 4C on PC04 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [BR4D]: PCI Express Port 4D on PC04 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR29, Package() { > + // [SL0D]: PCI Express Slot 13 on 4A on PC04 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR2A, Package() { > + // [SL0E]: PCI Express Slot 14 on 4B on PC04 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR2B, Package() { > + // [SL0F]: PCI Express Slot 15 on 4C on PC04 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR2C, Package() { > + // [SL10]: PCI Express Slot 16 on 4D on PC04 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR2D, Package() { > + // [BR5A]: PCI Express Port 5A on PC05 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [BR5B]: PCI Express Port 5B on PC05 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [BR5C]: PCI Express Port 5C on PC05 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [BR5D]: PCI Express Port 5D on PC05 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR2E, Package() { > + // [SL11]: PCI Express Slot 17 on 5A on PC05 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR2F, Package() { > + // [SL12]: PCI Express Slot 18 on 5B on PC05 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR30, Package() { > + // [SL13]: PCI Express Slot 19 on 5C on PC05 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR31, Package() { > + // [SL14]: PCI Express Slot 20 on 5D on PC05 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR32, Package() { > + // [UBX0]: Uncore 0 UBOX Device > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [UP00]: Uncore 0 Misc 2 UPI 0-7 Device > + Package() { 0x0002FFFF, 0, 0, 16 }, > + Package() { 0x0002FFFF, 1, 0, 17 }, > + Package() { 0x0002FFFF, 2, 0, 18 }, > + Package() { 0x0002FFFF, 3, 0, 19 }, > + // [UP01]: Unocre 0 Misc 1 UPI 0-7 Device > + Package() { 0x0003FFFF, 0, 0, 16 }, > + Package() { 0x0003FFFF, 1, 0, 17 }, > + Package() { 0x0003FFFF, 2, 0, 18 }, > + Package() { 0x0003FFFF, 3, 0, 19 }, > + // [M2U0]: Uncore 0 M2UPI0 Device > + Package() { 0x0005FFFF, 0, 0, 16 }, > + Package() { 0x0005FFFF, 1, 0, 17 }, > + Package() { 0x0005FFFF, 2, 0, 18 }, > + Package() { 0x0005FFFF, 3, 0, 19 }, > + // [M2U1]: Uncore 0 M2UPI1 Device > + Package() { 0x0006FFFF, 0, 0, 16 }, > + Package() { 0x0006FFFF, 1, 0, 17 }, > + Package() { 0x0006FFFF, 2, 0, 18 }, > + Package() { 0x0006FFFF, 3, 0, 19 }, > + // [M2U2]: Uncore 0 M2UPI2 Device > + Package() { 0x0007FFFF, 0, 0, 16 }, > + Package() { 0x0007FFFF, 1, 0, 17 }, > + Package() { 0x0007FFFF, 2, 0, 18 }, > + Package() { 0x0007FFFF, 3, 0, 19 }, > + // [CSM0]: Uncore 0 CHASIS_SMBUS Devices > + Package() { 0x000BFFFF, 0, 0, 16 }, > + Package() { 0x000BFFFF, 1, 0, 17 }, > + Package() { 0x000BFFFF, 2, 0, 18 }, > + Package() { 0x000BFFFF, 3, 0, 19 }, > + // [M2M0]: Uncore 0 MS2MEM_SCF_MS2MEM0 Device > + Package() { 0x000CFFFF, 0, 0, 16 }, > + Package() { 0x000CFFFF, 1, 0, 17 }, > + Package() { 0x000CFFFF, 2, 0, 18 }, > + Package() { 0x000CFFFF, 3, 0, 19 }, > + // [M2M1]: Uncore 0 MS2MEM_SCF_MS2MEM1 Device > + Package() { 0x000DFFFF, 0, 0, 16 }, > + Package() { 0x000DFFFF, 1, 0, 17 }, > + Package() { 0x000DFFFF, 2, 0, 18 }, > + Package() { 0x000DFFFF, 3, 0, 19 }, > + // [MCD0]: Uncore 0 MCDDR0 Device > + Package() { 0x001AFFFF, 0, 0, 16 }, > + Package() { 0x001AFFFF, 1, 0, 17 }, > + Package() { 0x001AFFFF, 2, 0, 18 }, > + Package() { 0x001AFFFF, 3, 0, 19 }, > + // [MCD1]: Uncore 0 MCDDR1 Device > + Package() { 0x001BFFFF, 0, 0, 16 }, > + Package() { 0x001BFFFF, 1, 0, 17 }, > + Package() { 0x001BFFFF, 2, 0, 18 }, > + Package() { 0x001BFFFF, 3, 0, 19 }, > + }) > + > + Name (AR33, Package() { > + // [CHA0]: Uncore 1 GRP1_CHA0-7 Device > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [CHA1]: Uncore 1 GRP1_CHA8-15 Device > + Package() { 0x0001FFFF, 0, 0, 16 }, > + Package() { 0x0001FFFF, 1, 0, 17 }, > + Package() { 0x0001FFFF, 2, 0, 18 }, > + Package() { 0x0001FFFF, 3, 0, 19 }, > + // [CHA2]: Uncore 1 GRP1_CHA16-23 Device > + Package() { 0x0002FFFF, 0, 0, 16 }, > + Package() { 0x0002FFFF, 1, 0, 17 }, > + Package() { 0x0002FFFF, 2, 0, 18 }, > + Package() { 0x0002FFFF, 3, 0, 19 }, > + // [CHA3]: Uncore 1 GRP1_CHAU24-31 Device > + Package() { 0x0003FFFF, 0, 0, 16 }, > + Package() { 0x0003FFFF, 1, 0, 17 }, > + Package() { 0x0003FFFF, 2, 0, 18 }, > + Package() { 0x0003FFFF, 3, 0, 19 }, > + // [CHA4]: Uncore 1 GRP1_CHA32-33 Device > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [CHA5]: Uncore 1 GRP0_CHA0-7 Device > + Package() { 0x000AFFFF, 0, 0, 16 }, > + Package() { 0x000AFFFF, 1, 0, 17 }, > + Package() { 0x000AFFFF, 2, 0, 18 }, > + Package() { 0x000AFFFF, 3, 0, 19 }, > + // [CHA8]: Uncore 1 GRP0_CHA24-31 Device > + Package() { 0x000DFFFF, 0, 0, 16 }, > + Package() { 0x000DFFFF, 1, 0, 17 }, > + Package() { 0x000DFFFF, 2, 0, 18 }, > + Package() { 0x000DFFFF, 3, 0, 19 }, > + // [CHA9]: Uncore 1 GRP0_CHA32-33 Device > + Package() { 0x000EFFFF, 0, 0, 16 }, > + Package() { 0x000EFFFF, 1, 0, 17 }, > + Package() { 0x000EFFFF, 2, 0, 18 }, > + Package() { 0x000EFFFF, 3, 0, 19 }, > + // [CHA6]: Uncore 1 GRP0_CHA8-15 Device > + Package() { 0x00B0FFFF, 0, 0, 16 }, > + Package() { 0x00B0FFFF, 1, 0, 17 }, > + Package() { 0x00B0FFFF, 2, 0, 18 }, > + Package() { 0x00B0FFFF, 3, 0, 19 }, > + // [CHA7]: Uncore 1 GRP0_CHA16-23 Device > + Package() { 0x000CFFFF, 0, 0, 16 }, > + Package() { 0x000CFFFF, 1, 0, 17 }, > + Package() { 0x000CFFFF, 2, 0, 18 }, > + Package() { 0x000CFFFF, 3, 0, 19 }, > + // [CA00]: Uncore 1 CHAALL0-1 Device > + Package() { 0x001DFFFF, 0, 0, 16 }, > + Package() { 0x001DFFFF, 1, 0, 17 }, > + Package() { 0x001DFFFF, 2, 0, 18 }, > + Package() { 0x001DFFFF, 3, 0, 19 }, > + // [PUC0]: Uncore 1 CHASIS_PUINT0-7 Device > + Package() { 0x001EFFFF, 0, 0, 16 }, > + Package() { 0x001EFFFF, 1, 0, 17 }, > + Package() { 0x001EFFFF, 2, 0, 18 }, > + Package() { 0x001EFFFF, 3, 0, 19 }, > + // [GN30]: Uncore 1 Gen3Phy Device > + Package() { 0x001FFFFF, 0, 0, 16 }, > + Package() { 0x001FFFFF, 1, 0, 17 }, > + Package() { 0x001FFFFF, 2, 0, 18 }, > + Package() { 0x001FFFFF, 3, 0, 19 }, > + }) > +#if MAX_SOCKET > 1 > + Name (AR34, Package() { > + // [IIM1]: IIOMISC on PC06 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [CB1A]: CB3DMA on PC06 > + // [CB1E]: CB3DMA on PC06 > + Package() { 0x0001FFFF, 0, 0, 16 }, > + // [CB1B]: CB3DMA on PC06 > + // [CB1F]: CB3DMA on PC06 > + Package() { 0x0001FFFF, 1, 0, 17 }, > + // [CB1C]: CB3DMA on PC06 > + // [CB1G]: CB3DMA on PC06 > + Package() { 0x0001FFFF, 2, 0, 18 }, > + // [CB1D]: CB3DMA on PC06 > + // [CB1H]: CB3DMA on PC06 > + Package() { 0x0001FFFF, 3, 0, 19 }, > + // NorthPeak > + Package() { 0x0002FFFF, 0, 0, 18 }, > + }) > + > + Name (AR35, Package() { > + // [QR1A]: PCI Express Port 1A on PC07 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [QR1B]: PCI Express Port 1B on PC07 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [QR1C]: PCI Express Port 1C on PC07 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [QR1D]: PCI Express Port 1D on PC07 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR36, Package() { > + // [SL16]: PCI Express Slot 22 on 1A on PC07 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR37, Package() { > + // [SL17]: PCI Express Slot 23 on 1B on PC07 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR38, Package() { > + // [SL18]: PCI Express Slot 24 on 1C on PC07 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR39, Package() { > + // [SL19]: PCI Express Slot 25 on 1D on PC07 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR3A, Package() { > + // [QR2A]: PCI Express Port 2A on PC08 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [QR2B]: PCI Express Port 2B on PC08 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [QR2C]: PCI Express Port 2C on PC08 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [QR2D]: PCI Express Port 2D on PC08 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR3B, Package() { > + // [SL1A]: PCI Express Slot 26 on 2A on PC08 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR3C, Package() { > + // [SL1B]: PCI Express Slot 27 on 2B on PC08 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR3D, Package() { > + // [SL1C]: PCI Express Slot 28 on 2C on PC08 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR3E, Package() { > + // [SL1D]: PCI Express Slot 29 on 2D on PC08 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR3F, Package() { > + // [QR3A]: PCI Express Port 3A on PC09 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [QR3B]: PCI Express Port 3B on PC09 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [QR3C]: PCI Express Port 3C on PC09 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [QR3D]: PCI Express Port 3D on PC09 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR40, Package() { > + // [SL1E]: PCI Express Slot 30 on 3A on PC09 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR41, Package() { > + // [SL1F]: PCI Express Slot 31 on 3B on PC09 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR42, Package() { > + // [SL20]: PCI Express Slot 32 on 3C on PC09 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR43, Package() { > + // [SL21]: PCI Express Slot 33 on 3D on PC09 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR44, Package() { > + // [QR4A]: PCI Express Port 4A on PC10 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [QR4B]: PCI Express Port 4B on PC10 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [QR4C]: PCI Express Port 4C on PC10 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [QR4D]: PCI Express Port 4D on PC10 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR45, Package() { > + // [SL22]: PCI Express Slot 34 on 4A on PC10 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR46, Package() { > + // [SL23]: PCI Express Slot 35 on 4B on PC10 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR47, Package() { > + // [SL24]: PCI Express Slot 36 on 4C on PC10 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR48, Package() { > + // [SL25]: PCI Express Slot 37 on 4D on PC10 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR49, Package() { > + // [QR5A]: PCI Express Port 5A on PC11 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [QR5B]: PCI Express Port 5B on PC11 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [QR5C]: PCI Express Port 5C on PC11 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [QR5D]: PCI Express Port 5D on PC11 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR4A, Package() { > + // [SL26]: PCI Express Slot 38 on 5A on PC11 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR4B, Package() { > + // [SL27]: PCI Express Slot 39 on 5B on PC11 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR4C, Package() { > + // [SL28]: PCI Express Slot 40 on 5C on PC11 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR4D, Package() { > + // [SL29]: PCI Express Slot 41 on 5D on PC11 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR4E, Package() { > + // [UBX1]: Uncore 2 UBOX Device > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [UP02]: Uncore 2 Misc 2 UPI 0-7 Device > + Package() { 0x0002FFFF, 0, 0, 16 }, > + Package() { 0x0002FFFF, 1, 0, 17 }, > + Package() { 0x0002FFFF, 2, 0, 18 }, > + Package() { 0x0002FFFF, 3, 0, 19 }, > + // [UP03]: Uncore 2 Misc 1 UPI 0-7 Device > + Package() { 0x0003FFFF, 0, 0, 16 }, > + Package() { 0x0003FFFF, 1, 0, 17 }, > + Package() { 0x0003FFFF, 2, 0, 18 }, > + Package() { 0x0003FFFF, 3, 0, 19 }, > + // [M2U3]: Uncore 2 M2UPI0 Device > + Package() { 0x0005FFFF, 0, 0, 16 }, > + Package() { 0x0005FFFF, 1, 0, 17 }, > + Package() { 0x0005FFFF, 2, 0, 18 }, > + Package() { 0x0005FFFF, 3, 0, 19 }, > + // [M2U4]: Uncore 2 M2UPI1 Device > + Package() { 0x0006FFFF, 0, 0, 16 }, > + Package() { 0x0006FFFF, 1, 0, 17 }, > + Package() { 0x0006FFFF, 2, 0, 18 }, > + Package() { 0x0006FFFF, 3, 0, 19 }, > + // [M2U5]: Uncore 2 M2UPI2 Device > + Package() { 0x0007FFFF, 0, 0, 16 }, > + Package() { 0x0007FFFF, 1, 0, 17 }, > + Package() { 0x0007FFFF, 2, 0, 18 }, > + Package() { 0x0007FFFF, 3, 0, 19 }, > + // [CSM1]: Uncore 2 CHASIS_SMBUS Devices > + Package() { 0x000BFFFF, 0, 0, 16 }, > + Package() { 0x000BFFFF, 1, 0, 17 }, > + Package() { 0x000BFFFF, 2, 0, 18 }, > + Package() { 0x000BFFFF, 3, 0, 19 }, > + // [M2M2]: Uncore 2 MS2MEM_SCF_MS2MEM0 Device > + Package() { 0x000CFFFF, 0, 0, 16 }, > + Package() { 0x000CFFFF, 1, 0, 17 }, > + Package() { 0x000CFFFF, 2, 0, 18 }, > + Package() { 0x000CFFFF, 3, 0, 19 }, > + // [M2M3]: Uncore 2 MS2MEM_SCF_MS2MEM1 Device > + Package() { 0x000DFFFF, 0, 0, 16 }, > + Package() { 0x000DFFFF, 1, 0, 17 }, > + Package() { 0x000DFFFF, 2, 0, 18 }, > + Package() { 0x000DFFFF, 3, 0, 19 }, > + // [MCD2]: Uncore 2 MCDDR0 Device > + Package() { 0x001AFFFF, 0, 0, 16 }, > + Package() { 0x001AFFFF, 1, 0, 17 }, > + Package() { 0x001AFFFF, 2, 0, 18 }, > + Package() { 0x001AFFFF, 3, 0, 19 }, > + // [MCD3]: Uncore 2 MCDDR1 Device > + Package() { 0x001BFFFF, 0, 0, 16 }, > + Package() { 0x001BFFFF, 1, 0, 17 }, > + Package() { 0x001BFFFF, 2, 0, 18 }, > + Package() { 0x001BFFFF, 3, 0, 19 }, > + }) > + > + Name (AR4F, Package() { > + // [DHA0]: Uncore 3 GRP1_CHA0-7 Device > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [DHA1]: Uncore 3 GRP1_CHA8-15 Device > + Package() { 0x0001FFFF, 0, 0, 16 }, > + Package() { 0x0001FFFF, 1, 0, 17 }, > + Package() { 0x0001FFFF, 2, 0, 18 }, > + Package() { 0x0001FFFF, 3, 0, 19 }, > + // [DHA2]: Uncore 3 GRP1_CHA16-23 Device > + Package() { 0x0002FFFF, 0, 0, 16 }, > + Package() { 0x0002FFFF, 1, 0, 17 }, > + Package() { 0x0002FFFF, 2, 0, 18 }, > + Package() { 0x0002FFFF, 3, 0, 19 }, > + // [DHA3]: Uncore 3 GRP1_CHAU24-31 Device > + Package() { 0x0003FFFF, 0, 0, 16 }, > + Package() { 0x0003FFFF, 1, 0, 17 }, > + Package() { 0x0003FFFF, 2, 0, 18 }, > + Package() { 0x0003FFFF, 3, 0, 19 }, > + // [DHA4]: Uncore 3 GRP1_CHA32-33 Device > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [DHA5]: Uncore 3 GRP0_CHA0-7 Device > + Package() { 0x000AFFFF, 0, 0, 16 }, > + Package() { 0x000AFFFF, 1, 0, 17 }, > + Package() { 0x000AFFFF, 2, 0, 18 }, > + Package() { 0x000AFFFF, 3, 0, 19 }, > + // [DHA8]: Uncore 3 GRP0_CHA24-31 Device > + Package() { 0x000DFFFF, 0, 0, 16 }, > + Package() { 0x000DFFFF, 1, 0, 17 }, > + Package() { 0x000DFFFF, 2, 0, 18 }, > + Package() { 0x000DFFFF, 3, 0, 19 }, > + // [DHA9]: Uncore 3 GRP0_CHA32-33 Device > + Package() { 0x000EFFFF, 0, 0, 16 }, > + Package() { 0x000EFFFF, 1, 0, 17 }, > + Package() { 0x000EFFFF, 2, 0, 18 }, > + Package() { 0x000EFFFF, 3, 0, 19 }, > + // [DHA6]: Uncore 3 GRP0_CHA8-15 Device > + Package() { 0x00B0FFFF, 0, 0, 16 }, > + Package() { 0x00B0FFFF, 1, 0, 17 }, > + Package() { 0x00B0FFFF, 2, 0, 18 }, > + Package() { 0x00B0FFFF, 3, 0, 19 }, > + // [DHA7]: Uncore 3 GRP0_CHA16-23 Device > + Package() { 0x000CFFFF, 0, 0, 16 }, > + Package() { 0x000CFFFF, 1, 0, 17 }, > + Package() { 0x000CFFFF, 2, 0, 18 }, > + Package() { 0x000CFFFF, 3, 0, 19 }, > + // [CA01]: Uncore 3 CHAALL0-1 Device > + Package() { 0x001DFFFF, 0, 0, 16 }, > + Package() { 0x001DFFFF, 1, 0, 17 }, > + Package() { 0x001DFFFF, 2, 0, 18 }, > + Package() { 0x001DFFFF, 3, 0, 19 }, > + // [PUC1]: Uncore 3 CHASIS_PUINT0-7 Device > + Package() { 0x001EFFFF, 0, 0, 16 }, > + Package() { 0x001EFFFF, 1, 0, 17 }, > + Package() { 0x001EFFFF, 2, 0, 18 }, > + Package() { 0x001EFFFF, 3, 0, 19 }, > + // [GN31]: Uncore 3 Gen3Phy Device > + Package() { 0x001FFFFF, 0, 0, 16 }, > + Package() { 0x001FFFFF, 1, 0, 17 }, > + Package() { 0x001FFFFF, 2, 0, 18 }, > + Package() { 0x001FFFFF, 3, 0, 19 }, > + }) > +#endif > + > +#if MAX_SOCKET > 2 > + Name (AR50, Package() { > + // [IIM2]: IIOMISC on PC12 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [CB2A]: CB3DMA on PC12 > + // [CB2E]: CB3DMA on PC12 > + Package() { 0x0001FFFF, 0, 0, 16 }, > + // [CB2B]: CB3DMA on PC12 > + // [CB2F]: CB3DMA on PC12 > + Package() { 0x0001FFFF, 1, 0, 17 }, > + // [CB2C]: CB3DMA on PC12 > + // [CB2G]: CB3DMA on PC12 > + Package() { 0x0001FFFF, 2, 0, 18 }, > + // [CB2D]: CB3DMA on PC12 > + // [CB2H]: CB3DMA on PC12 > + Package() { 0x0001FFFF, 3, 0, 19 }, > + // NorthPeak > + Package() { 0x0002FFFF, 0, 0, 18 }, > + }) > + > + Name (AR51, Package() { > + // [RR1A]: PCI Express Port 1A on PC13 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [RR1B]: PCI Express Port 1B on PC13 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [RR1C]: PCI Express Port 1C on PC13 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [RR1D]: PCI Express Port 1D on PC13 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR52, Package() { > + // [SL2B]: PCI Express Slot 43 on 1A on PC13 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR53, Package() { > + // [SL2C]: PCI Express Slot 44 on 1B on PC13 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR54, Package() { > + // [SL2D]: PCI Express Slot 45 on 1C on PC13 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR55, Package() { > + // [SL2E]: PCI Express Slot 46 on 1D on PC13 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR56, Package() { > + // [RR2A]: PCI Express Port 2A on PC14 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [RR2B]: PCI Express Port 2B on PC14 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [RR2C]: PCI Express Port 2C on PC14 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [RR2D]: PCI Express Port 2D on PC14 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR57, Package() { > + // [SL2F]: PCI Express Slot 47 on 2A on PC14 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR58, Package() { > + // [SL30]: PCI Express Slot 48 on 2B on PC14 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR59, Package() { > + // [SL31]: PCI Express Slot 49 on 2C on PC14 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR5A, Package() { > + // [SL32]: PCI Express Slot 50 on 2D on PC14 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR5B, Package() { > + // [RR3A]: PCI Express Port 3A on PC15 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [RR3B]: PCI Express Port 3B on PC15 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [RR3C]: PCI Express Port 3C on PC15 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [RR3D]: PCI Express Port 3D on PC15 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR5C, Package() { > + // [SL33]: PCI Express Slot 51 on 3A on PC15 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR5D, Package() { > + // [SL34]: PCI Express Slot 52 on 3B on PC15 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR5E, Package() { > + // [SL35]: PCI Express Slot 53 on 3C on PC15 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR5F, Package() { > + // [SL36]: PCI Express Slot 54 on 3D on PC15 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR60, Package() { > + // [RR4A]: PCI Express Port 4A on PC16 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [RR4B]: PCI Express Port 4B on PC16 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [RR4C]: PCI Express Port 4C on PC16 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [RR4D]: PCI Express Port 4D on PC16 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR61, Package() { > + // [SL37]: PCI Express Slot 55 on 4A on PC16 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR62, Package() { > + // [SL38]: PCI Express Slot 56 on 4B on PC16 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR63, Package() { > + // [SL39]: PCI Express Slot 57 on 4C on PC16 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR64, Package() { > + // [SL3A]: PCI Express Slot 58 on 4D on PC16 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR65, Package() { > + // [RR5A]: PCI Express Port 5A on PC17 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [RR5B]: PCI Express Port 5B on PC17 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [RR5C]: PCI Express Port 5C on PC17 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [RR5D]: PCI Express Port 5D on PC17 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR66, Package() { > + // [SL3B]: PCI Express Slot 59 on 5A on PC17 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR67, Package() { > + // [SL3C]: PCI Express Slot 60 on 5B on PC17 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR68, Package() { > + // [SL3D]: PCI Express Slot 61 on 5C on PC17 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR69, Package() { > + // [SL3E]: PCI Express Slot 62 on 5D on PC17 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR6A, Package() { > + // [UBX2]: Uncore 4 UBOX Device > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [UP04]: Uncore 4 Misc 2 UPI 0-7 Device > + Package() { 0x0002FFFF, 0, 0, 16 }, > + Package() { 0x0002FFFF, 1, 0, 17 }, > + Package() { 0x0002FFFF, 2, 0, 18 }, > + Package() { 0x0002FFFF, 3, 0, 19 }, > + // [UP05]: Uncore 4 Misc 1 UPI 0-7 Device > + Package() { 0x0003FFFF, 0, 0, 16 }, > + Package() { 0x0003FFFF, 1, 0, 17 }, > + Package() { 0x0003FFFF, 2, 0, 18 }, > + Package() { 0x0003FFFF, 3, 0, 19 }, > + // [M2U6]: Uncore 4 M2UPI Device > + Package() { 0x0005FFFF, 0, 0, 16 }, > + Package() { 0x0005FFFF, 1, 0, 17 }, > + Package() { 0x0005FFFF, 2, 0, 18 }, > + Package() { 0x0005FFFF, 3, 0, 19 }, > + // [M2U7]: Uncore 4 M2UPI Device > + Package() { 0x0006FFFF, 0, 0, 16 }, > + Package() { 0x0006FFFF, 1, 0, 17 }, > + Package() { 0x0006FFFF, 2, 0, 18 }, > + Package() { 0x0006FFFF, 3, 0, 19 }, > + // [M2U8]: Uncore 4 M2UPI Device > + Package() { 0x0007FFFF, 0, 0, 16 }, > + Package() { 0x0007FFFF, 1, 0, 17 }, > + Package() { 0x0007FFFF, 2, 0, 18 }, > + Package() { 0x0007FFFF, 3, 0, 19 }, > + // [CSM2]: Uncore 4 CHASIS_SMBUS Devices > + Package() { 0x000BFFFF, 0, 0, 16 }, > + Package() { 0x000BFFFF, 1, 0, 17 }, > + Package() { 0x000BFFFF, 2, 0, 18 }, > + Package() { 0x000BFFFF, 3, 0, 19 }, > + // [M2M4]: Uncore 4 MS2MEM_SCF_MS2MEM0 Device > + Package() { 0x000CFFFF, 0, 0, 16 }, > + Package() { 0x000CFFFF, 1, 0, 17 }, > + Package() { 0x000CFFFF, 2, 0, 18 }, > + Package() { 0x000CFFFF, 3, 0, 19 }, > + // [M2M5]: Uncore 4 MS2MEM_SCF_MS2MEM1 Device > + Package() { 0x000DFFFF, 0, 0, 16 }, > + Package() { 0x000DFFFF, 1, 0, 17 }, > + Package() { 0x000DFFFF, 2, 0, 18 }, > + Package() { 0x000DFFFF, 3, 0, 19 }, > + // [MCD4]: Uncore 4 MCDDR0 Device > + Package() { 0x001AFFFF, 0, 0, 16 }, > + Package() { 0x001AFFFF, 1, 0, 17 }, > + Package() { 0x001AFFFF, 2, 0, 18 }, > + Package() { 0x001AFFFF, 3, 0, 19 }, > + // [MCD5]: Uncore 4 MCDDR1 Device > + Package() { 0x001BFFFF, 0, 0, 16 }, > + Package() { 0x001BFFFF, 1, 0, 17 }, > + Package() { 0x001BFFFF, 2, 0, 18 }, > + Package() { 0x001BFFFF, 3, 0, 19 }, > + }) > + > + Name (AR6B, Package() { > + // [EHA0]: Uncore 5 GRP1_CHA0-7 Device > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [EHA1]: Uncore 5 GRP1_CHA8-15 Device > + Package() { 0x0001FFFF, 0, 0, 16 }, > + Package() { 0x0001FFFF, 1, 0, 17 }, > + Package() { 0x0001FFFF, 2, 0, 18 }, > + Package() { 0x0001FFFF, 3, 0, 19 }, > + // [EHA2]: Uncore 5 GRP1_CHA16-23 Device > + Package() { 0x0002FFFF, 0, 0, 16 }, > + Package() { 0x0002FFFF, 1, 0, 17 }, > + Package() { 0x0002FFFF, 2, 0, 18 }, > + Package() { 0x0002FFFF, 3, 0, 19 }, > + // [EHA3]: Uncore 5 GRP1_CHAU24-31 Device > + Package() { 0x0003FFFF, 0, 0, 16 }, > + Package() { 0x0003FFFF, 1, 0, 17 }, > + Package() { 0x0003FFFF, 2, 0, 18 }, > + Package() { 0x0003FFFF, 3, 0, 19 }, > + // [EHA4]: Uncore 5 GRP1_CHA32-33 Device > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [EHA5]: Uncore 5 GRP0_CHA0-7 Device > + Package() { 0x000AFFFF, 0, 0, 16 }, > + Package() { 0x000AFFFF, 1, 0, 17 }, > + Package() { 0x000AFFFF, 2, 0, 18 }, > + Package() { 0x000AFFFF, 3, 0, 19 }, > + // [EHA8]: Uncore 5 GRP0_CHA24-31 Device > + Package() { 0x000DFFFF, 0, 0, 16 }, > + Package() { 0x000DFFFF, 1, 0, 17 }, > + Package() { 0x000DFFFF, 2, 0, 18 }, > + Package() { 0x000DFFFF, 3, 0, 19 }, > + // [EHA9]: Uncore 5 GRP0_CHA32-33 Device > + Package() { 0x000EFFFF, 0, 0, 16 }, > + Package() { 0x000EFFFF, 1, 0, 17 }, > + Package() { 0x000EFFFF, 2, 0, 18 }, > + Package() { 0x000EFFFF, 3, 0, 19 }, > + // [EHA6]: Uncore 5 GRP0_CHA8-15 Device > + Package() { 0x00B0FFFF, 0, 0, 16 }, > + Package() { 0x00B0FFFF, 1, 0, 17 }, > + Package() { 0x00B0FFFF, 2, 0, 18 }, > + Package() { 0x00B0FFFF, 3, 0, 19 }, > + // [EHA7]: Uncore 5 GRP0_CHA16-23 Device > + Package() { 0x000CFFFF, 0, 0, 16 }, > + Package() { 0x000CFFFF, 1, 0, 17 }, > + Package() { 0x000CFFFF, 2, 0, 18 }, > + Package() { 0x000CFFFF, 3, 0, 19 }, > + // [CA02]: Uncore 5 CHAALL0-1 Device > + Package() { 0x001DFFFF, 0, 0, 16 }, > + Package() { 0x001DFFFF, 1, 0, 17 }, > + Package() { 0x001DFFFF, 2, 0, 18 }, > + Package() { 0x001DFFFF, 3, 0, 19 }, > + // [PUC2]: Uncore 5 CHASIS_PUINT0-7 Device > + Package() { 0x001EFFFF, 0, 0, 16 }, > + Package() { 0x001EFFFF, 1, 0, 17 }, > + Package() { 0x001EFFFF, 2, 0, 18 }, > + Package() { 0x001EFFFF, 3, 0, 19 }, > + // [GN32]: Uncore 5 Gen3Phy Device > + Package() { 0x001FFFFF, 0, 0, 16 }, > + Package() { 0x001FFFFF, 1, 0, 17 }, > + Package() { 0x001FFFFF, 2, 0, 18 }, > + Package() { 0x001FFFFF, 3, 0, 19 }, > + }) > +#endif > + > +#if MAX_SOCKET > 3 > + Name (AR6C, Package() { > + // [IIM3]: IIOMISC on PC18 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [CB3A]: CB3DMA on PC18 > + // [CB3E]: CB3DMA on PC18 > + Package() { 0x0001FFFF, 0, 0, 16 }, > + // [CB3B]: CB3DMA on PC18 > + // [CB3F]: CB3DMA on PC18 > + Package() { 0x0001FFFF, 1, 0, 17 }, > + // [CB3C]: CB3DMA on PC18 > + // [CB3G]: CB3DMA on PC18 > + Package() { 0x0001FFFF, 2, 0, 18 }, > + // [CB3D]: CB3DMA on PC18 > + // [CB3H]: CB3DMA on PC18 > + Package() { 0x0001FFFF, 3, 0, 19 }, > + // NorthPeak > + Package() { 0x0002FFFF, 0, 0, 18 }, > + }) > + > + Name (AR6D, Package() { > + // [SR1A]: PCI Express Port 1A on PC19 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [SR1B]: PCI Express Port 1B on PC19 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [SR1C]: PCI Express Port 1C on PC19 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [SR1D]: PCI Express Port 1D on PC19 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR6E, Package() { > + // [SL40]: PCI Express Slot 64 on 1A on PC19 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR6F, Package() { > + // [SL41]: PCI Express Slot 65 on 1B on PC19 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR70, Package() { > + // [SL42]: PCI Express Slot 66 on 1C on PC19 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR71, Package() { > + // [SL43]: PCI Express Slot 67 on 1D on PC19 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR72, Package() { > + // [SR2A]: PCI Express Port 2A on PC20 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [SR2B]: PCI Express Port 2B on PC20 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [SR2C]: PCI Express Port 2C on PC20 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [SR2D]: PCI Express Port 2D on PC20 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR73, Package() { > + // [SL44]: PCI Express Slot 68 on 2A on PC20 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR74, Package() { > + // [SL45]: PCI Express Slot 69 on 2B on PC20 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR75, Package() { > + // [SL46]: PCI Express Slot 70 on 2C on PC20 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR76, Package() { > + // [SL47]: PCI Express Slot 71 on 2D on PC20 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR77, Package() { > + // [SR3A]: PCI Express Port 3A on PC21 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [SR3B]: PCI Express Port 3B on PC21 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [SR3C]: PCI Express Port 3C on PC21 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [SR3D]: PCI Express Port 3D on PC21 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR78, Package() { > + // [SL48]: PCI Express Slot 72 on 3A on PC21 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR79, Package() { > + // [SL49]: PCI Express Slot 73 on 3B on PC21 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR7A, Package() { > + // [SL4A]: PCI Express Slot 74 on 3C on PC21 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR7B, Package() { > + // [SL4B]: PCI Express Slot 75 on 3D on PC21 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR7C, Package() { > + // [SR4A]: PCI Express Port 4A on PC22 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [SR4B]: PCI Express Port 4B on PC22 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [SR4C]: PCI Express Port 4C on PC22 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [SR4D]: PCI Express Port 4D on PC22 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR7D, Package() { > + // [SL4C]: PCI Express Slot 76 on 4A on PC22 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR7E, Package() { > + // [SL4D]: PCI Express Slot 77 on 4B on PC22 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR7F, Package() { > + // [SL4D]: PCI Express Slot 78 on 4C on PC22 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR80, Package() { > + // [SL4E]: PCI Express Slot 79 on 4D on PC22 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR81, Package() { > + // [SR5A]: PCI Express Port 5A on PC23 > + Package() { 0x0002FFFF, 0, 0, 18 }, > + Package() { 0x0002FFFF, 1, 0, 19 }, > + Package() { 0x0002FFFF, 2, 0, 16 }, > + Package() { 0x0002FFFF, 3, 0, 17 }, > + // [SR5B]: PCI Express Port 5B on PC23 > + Package() { 0x0003FFFF, 0, 0, 19 }, > + Package() { 0x0003FFFF, 1, 0, 16 }, > + Package() { 0x0003FFFF, 2, 0, 17 }, > + Package() { 0x0003FFFF, 3, 0, 18 }, > + // [SR5C]: PCI Express Port 5C on PC23 > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [SR5D]: PCI Express Port 5D on PC23 > + Package() { 0x0005FFFF, 0, 0, 17 }, > + Package() { 0x0005FFFF, 1, 0, 18 }, > + Package() { 0x0005FFFF, 2, 0, 19 }, > + Package() { 0x0005FFFF, 3, 0, 16 }, > + }) > + > + Name (AR82, Package() { > + // [SL4F]: PCI Express Slot 80 on 5A on PC23 > + Package() { 0x0000FFFF, 0, 0, 18 }, > + Package() { 0x0000FFFF, 1, 0, 19 }, > + Package() { 0x0000FFFF, 2, 0, 16 }, > + Package() { 0x0000FFFF, 3, 0, 17 }, > + }) > + > + Name (AR83, Package() { > + // [SL50]: PCI Express Slot 81 on 5B on PC23 > + Package() { 0x0000FFFF, 0, 0, 19 }, > + Package() { 0x0000FFFF, 1, 0, 16 }, > + Package() { 0x0000FFFF, 2, 0, 17 }, > + Package() { 0x0000FFFF, 3, 0, 18 }, > + }) > + > + Name (AR84, Package() { > + // [SL51]: PCI Express Slot 82 on 5C on PC23 > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > + > + Name (AR85, Package() { > + // [SL52]: PCI Express Slot 83 on 5D on PC23 > + Package() { 0x0000FFFF, 0, 0, 17 }, > + Package() { 0x0000FFFF, 1, 0, 18 }, > + Package() { 0x0000FFFF, 2, 0, 19 }, > + Package() { 0x0000FFFF, 3, 0, 16 }, > + }) > + > + Name (AR86, Package() { > + // [UBX3]: Uncore 6 UBOX Device > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [UP06]: Uncore 6 Misc 2 UPI 0-7 Device > + Package() { 0x0002FFFF, 0, 0, 16 }, > + Package() { 0x0002FFFF, 1, 0, 17 }, > + Package() { 0x0002FFFF, 2, 0, 18 }, > + Package() { 0x0002FFFF, 3, 0, 19 }, > + // [UP07]: Uncore 6 Misc 1 UPI 0-7 Device > + Package() { 0x0003FFFF, 0, 0, 16 }, > + Package() { 0x0003FFFF, 1, 0, 17 }, > + Package() { 0x0003FFFF, 2, 0, 18 }, > + Package() { 0x0003FFFF, 3, 0, 19 }, > + // [M2U9]: Uncore 6 M2UPI0 Device > + Package() { 0x0005FFFF, 0, 0, 16 }, > + Package() { 0x0005FFFF, 1, 0, 17 }, > + Package() { 0x0005FFFF, 2, 0, 18 }, > + Package() { 0x0005FFFF, 3, 0, 19 }, > + // [M2UA]: Uncore 6 M2UPI1 Device > + Package() { 0x0006FFFF, 0, 0, 16 }, > + Package() { 0x0006FFFF, 1, 0, 17 }, > + Package() { 0x0006FFFF, 2, 0, 18 }, > + Package() { 0x0006FFFF, 3, 0, 19 }, > + // [M2UB]: Uncore 6 M2UPI2 Device > + Package() { 0x0007FFFF, 0, 0, 16 }, > + Package() { 0x0007FFFF, 1, 0, 17 }, > + Package() { 0x0007FFFF, 2, 0, 18 }, > + Package() { 0x0007FFFF, 3, 0, 19 }, > + // [CSM3]: Uncore 6 CHASIS_SMBUS Devices > + Package() { 0x000BFFFF, 0, 0, 16 }, > + Package() { 0x000BFFFF, 1, 0, 17 }, > + Package() { 0x000BFFFF, 2, 0, 18 }, > + Package() { 0x000BFFFF, 3, 0, 19 }, > + // [M2M6]: Uncore 6 MS2MEM_SCF_MS2MEM0 Device > + Package() { 0x000CFFFF, 0, 0, 16 }, > + Package() { 0x000CFFFF, 1, 0, 17 }, > + Package() { 0x000CFFFF, 2, 0, 18 }, > + Package() { 0x000CFFFF, 3, 0, 19 }, > + // [M2M7]: Uncore 6 MS2MEM_SCF_MS2MEM1 Device > + Package() { 0x000DFFFF, 0, 0, 16 }, > + Package() { 0x000DFFFF, 1, 0, 17 }, > + Package() { 0x000DFFFF, 2, 0, 18 }, > + Package() { 0x000DFFFF, 3, 0, 19 }, > + // [MCD6]: Uncore 6 MCDDR0 Device > + Package() { 0x001AFFFF, 0, 0, 16 }, > + Package() { 0x001AFFFF, 1, 0, 17 }, > + Package() { 0x001AFFFF, 2, 0, 18 }, > + Package() { 0x001AFFFF, 3, 0, 19 }, > + // [MCD7]: Uncore 6 MCDDR1 Device > + Package() { 0x001BFFFF, 0, 0, 16 }, > + Package() { 0x001BFFFF, 1, 0, 17 }, > + Package() { 0x001BFFFF, 2, 0, 18 }, > + Package() { 0x001BFFFF, 3, 0, 19 }, > + }) > + > + Name (AR87, Package() { > + // [FHA0]: Uncore 7 GRP1_CHA0-7 Device > + Package() { 0x0000FFFF, 0, 0, 16 }, > + Package() { 0x0000FFFF, 1, 0, 17 }, > + Package() { 0x0000FFFF, 2, 0, 18 }, > + Package() { 0x0000FFFF, 3, 0, 19 }, > + // [FHA1]: Uncore 7 GRP1_CHA8-15 Device > + Package() { 0x0001FFFF, 0, 0, 16 }, > + Package() { 0x0001FFFF, 1, 0, 17 }, > + Package() { 0x0001FFFF, 2, 0, 18 }, > + Package() { 0x0001FFFF, 3, 0, 19 }, > + // [FHA2]: Uncore 7 GRP1_CHA16-23 Device > + Package() { 0x0002FFFF, 0, 0, 16 }, > + Package() { 0x0002FFFF, 1, 0, 17 }, > + Package() { 0x0002FFFF, 2, 0, 18 }, > + Package() { 0x0002FFFF, 3, 0, 19 }, > + // [FHA3]: Uncore 7 GRP1_CHAU24-31 Device > + Package() { 0x0003FFFF, 0, 0, 16 }, > + Package() { 0x0003FFFF, 1, 0, 17 }, > + Package() { 0x0003FFFF, 2, 0, 18 }, > + Package() { 0x0003FFFF, 3, 0, 19 }, > + // [FHA4]: Uncore 7 GRP1_CHA32-33 Device > + Package() { 0x0004FFFF, 0, 0, 16 }, > + Package() { 0x0004FFFF, 1, 0, 17 }, > + Package() { 0x0004FFFF, 2, 0, 18 }, > + Package() { 0x0004FFFF, 3, 0, 19 }, > + // [FHA5]: Uncore 7 GRP0_CHA0-7 Device > + Package() { 0x000AFFFF, 0, 0, 16 }, > + Package() { 0x000AFFFF, 1, 0, 17 }, > + Package() { 0x000AFFFF, 2, 0, 18 }, > + Package() { 0x000AFFFF, 3, 0, 19 }, > + // [FHA8]: Uncore 7 GRP0_CHA24-31 Device > + Package() { 0x000DFFFF, 0, 0, 16 }, > + Package() { 0x000DFFFF, 1, 0, 17 }, > + Package() { 0x000DFFFF, 2, 0, 18 }, > + Package() { 0x000DFFFF, 3, 0, 19 }, > + // [FHA9]: Uncore 7 GRP0_CHA32-33 Device > + Package() { 0x000EFFFF, 0, 0, 16 }, > + Package() { 0x000EFFFF, 1, 0, 17 }, > + Package() { 0x000EFFFF, 2, 0, 18 }, > + Package() { 0x000EFFFF, 3, 0, 19 }, > + // [FHA6]: Uncore 7 GRP0_CHA8-15 Device > + Package() { 0x00B0FFFF, 0, 0, 16 }, > + Package() { 0x00B0FFFF, 1, 0, 17 }, > + Package() { 0x00B0FFFF, 2, 0, 18 }, > + Package() { 0x00B0FFFF, 3, 0, 19 }, > + // [FHA7]: Uncore 7 GRP0_CHA16-23 Device > + Package() { 0x000CFFFF, 0, 0, 16 }, > + Package() { 0x000CFFFF, 1, 0, 17 }, > + Package() { 0x000CFFFF, 2, 0, 18 }, > + Package() { 0x000CFFFF, 3, 0, 19 }, > + // [CA03]: Uncore 7 CHAALL0-1 Device > + Package() { 0x001DFFFF, 0, 0, 16 }, > + Package() { 0x001DFFFF, 1, 0, 17 }, > + Package() { 0x001DFFFF, 2, 0, 18 }, > + Package() { 0x001DFFFF, 3, 0, 19 }, > + // [PUC3]: Uncore 7 CHASIS_PUINT0-7 Device > + Package() { 0x001EFFFF, 0, 0, 16 }, > + Package() { 0x001EFFFF, 1, 0, 17 }, > + Package() { 0x001EFFFF, 2, 0, 18 }, > + Package() { 0x001EFFFF, 3, 0, 19 }, > + // [GN33]: Uncore 7 Gen3Phy Device > + Package() { 0x001FFFFF, 0, 0, 16 }, > + Package() { 0x001FFFFF, 1, 0, 17 }, > + Package() { 0x001FFFFF, 2, 0, 18 }, > + Package() { 0x001FFFFF, 3, 0, 19 }, > + }) > +#endif > + Name (AR88, Package() { > + // [FPG0]: FPGA Device > + Package() { 0x0000FFFF, 0, 0, 16 }, > + }) > + > +#if MAX_SOCKET > 1 > + Name (AR89, Package() { > + // [FPG1]: FPGA Device > + Package() { 0x0000FFFF, 1, 0, 17 }, > + }) > +#endif > + > +#if MAX_SOCKET > 2 > + Name (AR8A, Package() { > + // [FPG2]: FPGA Device > + Package() { 0x0000FFFF, 2, 0, 18 }, > + }) > +#endif > + > +#if MAX_SOCKET > 3 > + Name (AR8B, Package() { > + // [FPG3]: FPGA Device > + Package() { 0x0000FFFF, 3, 0, 19 }, > + }) > +#endif > + // > + // Socket 0 Root bridge (Stack 0) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 0 > +#define STACK 0 > + Device (PC00) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x00) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR00) > + } > + > + #include "PC0010nm.asi" > + > + // IIOMISC on PC00 > + Device (IIM0) { > + Name (_ADR, 0x00000000) > + } > + > + // CB3DMA on PC00 > + Device (CB0A) { > + Name (_ADR, 0x00010000) > + } > + > + // CB3DMA on PC00 > + Device (CB0B) { > + Name (_ADR, 0x00010001) > + } > + > + // CB3DMA on PC00 > + Device (CB0C) { > + Name (_ADR, 0x00010002) > + } > + > + // CB3DMA on PC00 > + Device (CB0D) { > + Name (_ADR, 0x00010003) > + } > + > + // CB3DMA on PC00 > + Device (CB0E) { > + Name (_ADR, 0x00010004) > + } > + > + // CB3DMA on PC00 > + Device (CB0F) { > + Name (_ADR, 0x00010005) > + } > + > + // CB3DMA on PC00 > + Device (CB0G) { > + Name (_ADR, 0x00010006) > + } > + > + // CB3DMA on PC00 > + Device (CB0H) { > + Name (_ADR, 0x00010007) > + } > + > + // MSM on PC00 > + Device (MSM1) { > + Name (_ADR, 0x00020000) > + } > + > + // PMON MSM on PC00 > + Device (PMON) { > + Name (_ADR, 0x00020001) > + } > + > + // NorthPeak on PC00 > + Device (NRPK) { > + Name (_ADR, 0x00020004) > + } > + > + // Legacy PCI Express Port 0 on PC00 > + Device (DMI0) { > + Name (_ADR, 0x00030000) > + } > + > + // IE HECI #1 > + Device (IHC1) { > + Name (_ADR, 0x00100000) > + } > + > + // IE HECI #2 > + Device (IHC2) { > + Name (_ADR, 0x00100001) > + } > + > + // IE IDE-Redirection (IDE-R) > + Device (IIDR) { > + Name (_ADR, 0x00100002) > + } > + > + // IE Keyboard and Text (KT) Redirection > + Device (IMKT) { > + Name (_ADR, 0x00100003) > + } > + > + // IE HECI #3 > + Device (IHC3) { > + Name (_ADR, 0x00100004) > + } > + > + // MROM 0 function function > + Device (MRO0) { > + Name (_ADR, 0x00110000) > + } > + > + // MROM 1 function function > + Device (MRO1) { > + Name (_ADR, 0x00110001) > + } > + > + // sSATA Host controller on PCH > + Device (SAT2) { > + Name (_ADR, 0x00110005) > + } > + > + // xHCI controller 1 on PCH > + Device (XHCI) { > + Name (_ADR, 0x00140000) > + } > + > + // Thermal Subsystem on PCH > + Device (TERM) { > + Name (_ADR, 0x00140002) > + } > + > + // ME HECI #1 on PCH > + Device (HEC1) { > + Name (_ADR, 0x00160000) > + } > + > + // ME HECI #2 on PCH > + Device (HEC2) { > + Name (_ADR, 0x00160001) > + } > + > + // ME IDE redirect on PCH > + Device (IDER) { > + Name (_ADR, 0x00160002) > + } > + > + // MEKT on PCH > + Device (MEKT) { > + Name (_ADR, 0x00160003) > + } > + > + // ME HECI #3 on PCH > + Device (HEC3) { > + Name (_ADR, 0x00160004) > + } > + > + // SATA controller 1 on PCH > + Device (SAT1) { > + Name (_ADR, 0x00170000) > + } > + > + // PCIE PCH Root Port #17 > + Device (RP17) { > + #include "RP17_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR01) > + } > + > + // PCIE PCH Slot #17 > + Device (SLTH) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #18 > + Device (RP18) { > + #include "RP18_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR02) > + } > + > + // PCIE PCH Slot #18 > + Device (SLTI) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #19 > + Device (RP19) { > + #include "RP19_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR03) > + } > + > + // PCIE PCH Slot #19 > + Device (SLTJ) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #20 > + Device (RP20) { > + #include "RP20_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR04) > + } > + > + // PCIE PCH Slot #20 > + Device (SLTK) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #1 > + Device (RP01) { > + #include "RP01_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR05) > + } > + } > + > + // PCIE PCH Root Port #2 > + Device (RP02) { > + #include "RP02_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR06) > + } > + } > + > + // PCIE PCH Root Port #3 > + Device (RP03) { > + #include "RP03_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR07) > + } > + } > + > + // PCIE PCH Root Port #4 > + Device (RP04) { > + #include "RP04_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR08) > + } > + } > + > + // PCIE PCH Root Port #5 > + Device (RP05) { > + #include "RP05_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR09) > + } > + } > + > + // PCIE PCH Root Port #6 > + Device (RP06) { > + #include "RP06_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR0A) > + } > + } > + > + // PCIE PCH Root Port #7 > + Device (RP07) { > + #include "RP07_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR0B) > + } > + } > + > + // PCIE PCH Root Port #8 > + Device (RP08) { > + #include "RP08_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR0C) > + } > + } > + > + // PCIE PCH Root Port #9 > + Device (RP09) { > + #include "RP09_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR0D) > + } > + > + // PCIE PCH Slot #9 > + Device (SLT9) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #10 > + Device (RP10) { > + #include "RP10_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR0E) > + } > + > + // PCIE PCH Slot #10 > + Device (SLTA) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #11 > + Device (RP11) { > + #include "RP11_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR0F) > + } > + > + // PCIE PCH Slot #11 > + Device (SLTB) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #12 > + Device (RP12) { > + #include "RP12_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR10) > + } > + > + // PCIE PCH Slot #12 > + Device (SLTC) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #13 > + Device (RP13) { > + #include "RP13_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR11) > + } > + > + // PCIE PCH Slot #13 > + Device (SLTD) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #14 > + Device (RP14) { > + #include "RP14_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR12) > + } > + > + // PCIE PCH Slot #14 > + Device (SLTE) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #15 > + Device (RP15) { > + #include "RP15_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR13) > + } > + > + // PCIE PCH Slot #15 > + Device (SLTF) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // PCIE PCH Root Port #16 > + Device (RP16) { > + #include "RP16_ADR.asl" > + Method (_PRT, 0) { > + > + Return (AR14) > + } > + > + // PCIE PCH Slot #16 > + Device (SLTG) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // ISA Bridge on PCH > + Device (LPC0) { > + Name (_ADR, 0x001F0000) > + > + #include "Mother.asi" > + } > + > + // P2SB > + Device (P2SB) { > + Name (_ADR, 0x001F0001) > + } > + > + // Power Management Controller on PCH > + Device (PMC1) { > + Name (_ADR, 0x001F0002) > + } > + > + // HD Audio Subsystem Controller on PCH > + Device (CAVS) { > + Name (_ADR, 0x001F0003) > + } > + > + // SMBus controller on PCH > + Device (SMBS) { > + Name (_ADR, 0x001F0004) > + } > + > + // SPI controller on PCH > + Device (SPIC) { > + Name (_ADR, 0x001F0005) > + } > + > + // GbE Controller on PCH > + Device (GBE1) { > + Name (_ADR, 0x001F0006) > + } > + > + // Intel Trace Hub on PCH > + Device (TRHB) { > + Name (_ADR, 0x001F0007) > + } > + } > + > + // Socket 0 Root bridge (Stack 1) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 0 > +#define STACK 1 > + Device (PC01) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x01) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR15) > + } > + > + #include "IioRootBridge.asi" > + > + // PCI Express Port 1A on PC01 > + Device (BR1A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR16) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 1B on PC01 > + Device (BR1B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR17) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 1C on PC01 > + Device (BR1C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR18) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 1D on PC01 > + Device (BR1D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR19) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + } > + > + // Socket 0 Root bridge (Stack 2) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 0 > +#define STACK 2 > + Device (PC02) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x02) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR1A) > + } > + > + #include "IioRootBridge.asi" > + > + // PCI Express Port 2A on PC02 > + Device (BR2A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR1B) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + > + // EVA PCIe Uplink > + Device (EPCU) { > + Name (_ADR, 0x00000000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x0B, 0x00}) > + } > + Method (_PRT, 0) { > + > + Return (AR1C) > + } > + > + // EVA Virtual Switch Port 0 > + Device (VSP0) { > + Name (_ADR, 0x00000000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x0B, 0x00}) > + } > + Method (_PRT, 0) { > + > + Return (AR1D) > + } > + > + // EVA CPM0 > + Device (CPM0) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // EVA Virtual Switch Port 1 > + Device (VSP1) { > + Name (_ADR, 0x00010000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x0B, 0x00}) > + } > + Method (_PRT, 0) { > + > + Return (AR1E) > + } > + > + // EVA CPM1 > + Device (CPM1) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // EVA Virtual Switch Port 2 > + Device (VSP2) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x0B, 0x00}) > + } > + Method (_PRT, 0) { > + > + Return (AR1F) > + } > + > + // EVA CPM2 > + Device (CPM2) { > + Name (_ADR, 0x00000000) > + } > + } > + > + // EVA Virtual Switch Port 3 > + Device (VSP3) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x0B, 0x00}) > + } > + } > + } > + } > + > + // PCI Express Port 2B on PC02 > + Device (BR2B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR20) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 2C on PC02 > + Device (BR2C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR21) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 2D on PC02 > + Device (BR2D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR22) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + } > + > + // Socket 0 Root bridge (Stack 3) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 0 > +#define STACK 3 > + Device (PC03) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x03) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR23) > + } > + > + #include "IioRootBridge.asi" > + > + // PCI Express Port 3A on PC03 > + Device (BR3A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR24) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 3B on PC03 > + Device (BR3B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR25) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 3C on PC03 > + Device (BR3C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR26) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 3D on PC03 > + Device (BR3D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR27) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + } > + > + // Socket 0 Root bridge (Stack 4) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 0 > +#define STACK 4 > + Device (PC04) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x04) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR28) > + } > + > + #include "IioRootBridge.asi" > + > + // PCI Express Port 4A on PC04 > + Device (BR4A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR29) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + } > + > + // PCI Express Port 4B on PC04 > + Device (BR4B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR2A) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 4C on PC04 > + Device (BR4C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR2B) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 4D on PC04 > + Device (BR4D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR2C) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + } > + > + // Socket 0 Root bridge (Stack 5) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 0 > +#define STACK 5 > + Device (PC05) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x05) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR2D) > + } > + > + #include "IioRootBridge.asi" > + > + // PCI Express Port 5A on PC05 > + Device (BR5A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR2E) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 5B on PC05 > + Device (BR5B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR2F) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 5C on PC05 > + Device (BR5C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR30) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + > + // PCI Express Port 5D on PC05 > + Device (BR5D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR31) > + } > + > + #include "PcieHp.asi" > + #include "PcieNonHpDev.asi" > + } > + } > + > + // Socket 0 Uncore 0 > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 0 > +#define STACK 6 > + Device (CONCATENATE3(UC, SOCKET, STACK)) { > + Name (_HID, EISAID("PNP0A03")) > + Name (_UID, 0x32) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR32) > + } > + > + #include "Uncore.asi" > + > + // Uncore 0 UBOX Device > + Device (UBX0) { > + Name (_ADR, 0x00000000) > + } > + > + // Uncore 0 Misc 2 UPI 0-7 Device > + Device (UP00) { > + Name (_ADR, 0x00020000) > + } > + > + // Unocre 0 Misc 1 UPI 0-7 Device > + Device (UP01) { > + Name (_ADR, 0x00030000) > + } > + > + // Uncore 0 M2UPI0 Device > + Device (M2U0) { > + Name (_ADR, 0x00050000) > + } > + > + // Uncore 0 M2UPI1 Device > + Device (M2U1) { > + Name (_ADR, 0x00060000) > + } > + > + // Uncore 0 M2UPI2 Device > + Device (M2U2) { > + Name (_ADR, 0x00070000) > + } > + > + // Uncore 0 CHASIS_SMBUS Devices > + Device (CSM0) { > + Name (_ADR, 0x000B0000) > + } > + > + // Uncore 0 MS2MEM_SCF_MS2MEM0 Device > + Device (M2M0) { > + Name (_ADR, 0x000C0000) > + } > + > + // Uncore 0 MS2MEM_SCF_MS2MEM1 Device > + Device (M2M1) { > + Name (_ADR, 0x000D0000) > + } > + > + // Uncore 0 MCDDR0 Device > + Device (MCD0) { > + Name (_ADR, 0x001A0000) > + } > + > + // Uncore 0 MCDDR1 Device > + Device (MCD1) { > + Name (_ADR, 0x001B0000) > + } > + } > + > + // Socket 0 Uncore 1 > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 0 > +#define STACK 7 > + Device (CONCATENATE3(UC, SOCKET, STACK)) { > + Name (_HID, EISAID("PNP0A03")) > + Name (_UID, 0x33) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR33) > + } > + > + #include "Uncore.asi" > + > + // Uncore 1 GRP1_CHA0-7 Device > + Device (CHA0) { > + Name (_ADR, 0x00000000) > + } > + > + // Uncore 1 GRP1_CHA8-15 Device > + Device (CHA1) { > + Name (_ADR, 0x00010000) > + } > + > + // Uncore 1 GRP1_CHA16-23 Device > + Device (CHA2) { > + Name (_ADR, 0x00020000) > + } > + > + // Uncore 1 GRP1_CHAU24-31 Device > + Device (CHA3) { > + Name (_ADR, 0x00030000) > + } > + > + // Uncore 1 GRP1_CHA32-33 Device > + Device (CHA4) { > + Name (_ADR, 0x00040000) > + } > + > + // Uncore 1 GRP0_CHA0-7 Device > + Device (CHA5) { > + Name (_ADR, 0x000A0000) > + } > + > + // Uncore 1 GRP0_CHA24-31 Device > + Device (CHA8) { > + Name (_ADR, 0x000D0000) > + } > + > + // Uncore 1 GRP0_CHA32-33 Device > + Device (CHA9) { > + Name (_ADR, 0x000E0000) > + } > + > + // Uncore 1 GRP0_CHA8-15 Device > + Device (CHA6) { > + Name (_ADR, 0x00B00000) > + } > + > + // Uncore 1 GRP0_CHA16-23 Device > + Device (CHA7) { > + Name (_ADR, 0x000C0000) > + } > + > + // Uncore 1 CHAALL0-1 Device > + Device (CA00) { > + Name (_ADR, 0x001D0000) > + } > + > + // Uncore 1 CHASIS_PUINT0-7 Device > + Device (PUC0) { > + Name (_ADR, 0x001E0000) > + } > + > + // Uncore 1 Gen3Phy Device > + Device (GN30) { > + Name (_ADR, 0x001F0000) > + } > + } > + > +#if MAX_SOCKET > 1 > + // > + // Socket 1 Root bridge (Stack 0) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 1 > +#define STACK 0 > + Device (PC06) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x06) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR34) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck1Ejd.asi" > + > + // IIOMISC on PC06 > + Device (IIM1) { > + Name (_ADR, 0x00000000) > + } > + > + // CB3DMA on PC06 > + Device (CB1A) { > + Name (_ADR, 0x00010000) > + } > + > + // CB3DMA on PC06 > + Device (CB1B) { > + Name (_ADR, 0x00010001) > + } > + > + // CB3DMA on PC06 > + Device (CB1C) { > + Name (_ADR, 0x00010002) > + } > + > + // CB3DMA on PC06 > + Device (CB1D) { > + Name (_ADR, 0x00010003) > + } > + > + // CB3DMA on PC06 > + Device (CB1E) { > + Name (_ADR, 0x00010004) > + } > + > + // CB3DMA on PC06 > + Device (CB1F) { > + Name (_ADR, 0x00010005) > + } > + > + // CB3DMA on PC06 > + Device (CB1G) { > + Name (_ADR, 0x00010006) > + } > + > + // CB3DMA on PC06 > + Device (CB1H) { > + Name (_ADR, 0x00010007) > + } > + } > + > + // Socket 1 Root bridge (Stack 1) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 1 > +#define STACK 1 > + Device (PC07) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x07) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR35) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck1Ejd.asi" > + > + // PCI Express Port 1A on PC07 > + Device (QR1A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR36) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 1B on PC07 > + Device (QR1B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR37) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 1C on PC07 > + Device (QR1C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR38) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 1D on PC07 > + Device (QR1D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR39) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + } > + > + // Socket 1 Root bridge (Stack 2) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 1 > +#define STACK 2 > + Device (PC08) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x08) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR3A) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck1Ejd.asi" > + > + // PCI Express Port 2A on PC08 > + Device (QR2A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR3B) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 2B on PC08 > + Device (QR2B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR3C) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 2C on PC08 > + Device (QR2C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR3D) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 2D on PC08 > + Device (QR2D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR3E) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + } > + > + // Socket 1 Root bridge (Stack 3) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 1 > +#define STACK 3 > + Device (PC09) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x09) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR3F) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck1Ejd.asi" > + > + // PCI Express Port 3A on PC09 > + Device (QR3A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR40) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 3B on PC09 > + Device (QR3B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR41) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 3C on PC09 > + Device (QR3C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR42) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 3D on PC09 > + Device (QR3D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR43) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + } > + > + // Socket 1 Root bridge (Stack 4) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 1 > +#define STACK 4 > + Device (PC10) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x0A) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR44) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck1Ejd.asi" > + > + // PCI Express Port 4A on PC10 > + Device (QR4A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR45) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 4B on PC10 > + Device (QR4B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR46) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 4C on PC10 > + Device (QR4C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR47) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 4D on PC10 > + Device (QR4D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR48) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + } > + > + // Socket 1 Root bridge (Stack 5) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 1 > +#define STACK 5 > + Device (PC11) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x0B) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR49) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck1Ejd.asi" > + > + // PCI Express Port 5A on PC11 > + Device (QR5A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR4A) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 5B on PC11 > + Device (QR5B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR4B) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 5C on PC11 > + Device (QR5C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR4C) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + > + // PCI Express Port 5D on PC11 > + Device (QR5D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR4D) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC0610nmEjd.asi" > + } > + } > + > + // Socket 1 Uncore 0 > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 1 > +#define STACK 6 > + Device (CONCATENATE3(UC, SOCKET, STACK)) { > + Name (_HID, EISAID("PNP0A03")) > + Name (_UID, 0x34) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR4E) > + } > + > + #include "Uncore.asi" > + > + // Uncore 2 UBOX Device > + Device (UBX1) { > + Name (_ADR, 0x00000000) > + } > + > + // Uncore 2 Misc 2 UPI 0-7 Device > + Device (UP02) { > + Name (_ADR, 0x00020000) > + } > + > + // Uncore 2 Misc 1 UPI 0-7 Device > + Device (UP03) { > + Name (_ADR, 0x00030000) > + } > + > + // Uncore 2 M2UPI0 Device > + Device (M2U3) { > + Name (_ADR, 0x00050000) > + } > + > + // Uncore 2 M2UPI1 Device > + Device (M2U4) { > + Name (_ADR, 0x00060000) > + } > + > + // Uncore 2 M2UPI2 Device > + Device (M2U5) { > + Name (_ADR, 0x00070000) > + } > + > + // Uncore 2 CHASIS_SMBUS Devices > + Device (CSM1) { > + Name (_ADR, 0x000B0000) > + } > + > + // Uncore 2 MS2MEM_SCF_MS2MEM0 Device > + Device (M2M2) { > + Name (_ADR, 0x000C0000) > + } > + > + // Uncore 2 MS2MEM_SCF_MS2MEM1 Device > + Device (M2M3) { > + Name (_ADR, 0x000D0000) > + } > + > + // Uncore 2 MCDDR0 Device > + Device (MCD2) { > + Name (_ADR, 0x001A0000) > + } > + > + // Uncore 2 MCDDR1 Device > + Device (MCD3) { > + Name (_ADR, 0x001B0000) > + } > + } > + > + // Socket 1 Uncore 1 > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 1 > +#define STACK 7 > + Device (CONCATENATE3(UC, SOCKET, STACK)) { > + Name (_HID, EISAID("PNP0A03")) > + Name (_UID, 0x35) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR4F) > + } > + > + #include "Uncore.asi" > + > + // Uncore 3 GRP1_CHA0-7 Device > + Device (DHA0) { > + Name (_ADR, 0x00000000) > + } > + > + // Uncore 3 GRP1_CHA8-15 Device > + Device (DHA1) { > + Name (_ADR, 0x00010000) > + } > + > + // Uncore 3 GRP1_CHA16-23 Device > + Device (DHA2) { > + Name (_ADR, 0x00020000) > + } > + > + // Uncore 3 GRP1_CHAU24-31 Device > + Device (DHA3) { > + Name (_ADR, 0x00030000) > + } > + > + // Uncore 3 GRP1_CHA32-33 Device > + Device (DHA4) { > + Name (_ADR, 0x00040000) > + } > + > + // Uncore 3 GRP0_CHA0-7 Device > + Device (DHA5) { > + Name (_ADR, 0x000A0000) > + } > + > + // Uncore 3 GRP0_CHA24-31 Device > + Device (DHA8) { > + Name (_ADR, 0x000D0000) > + } > + > + // Uncore 3 GRP0_CHA32-33 Device > + Device (DHA9) { > + Name (_ADR, 0x000E0000) > + } > + > + // Uncore 3 GRP0_CHA8-15 Device > + Device (DHA6) { > + Name (_ADR, 0x00B00000) > + } > + > + // Uncore 3 GRP0_CHA16-23 Device > + Device (DHA7) { > + Name (_ADR, 0x000C0000) > + } > + > + // Uncore 3 CHAALL0-1 Device > + Device (CA01) { > + Name (_ADR, 0x001D0000) > + } > + > + // Uncore 3 CHASIS_PUINT0-7 Device > + Device (PUC1) { > + Name (_ADR, 0x001E0000) > + } > + > + // Uncore 3 Gen3Phy Device > + Device (GN31) { > + Name (_ADR, 0x001F0000) > + } > + } > +#endif > + > +#if MAX_SOCKET > 2 > + // Socket 2 Root bridge (Stack 0) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 2 > +#define STACK 0 > + Device (PC12) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x0C) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR50) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck2Ejd.asi" > + > + // IIOMISC on PC12 > + Device (IIM2) { > + Name (_ADR, 0x00000000) > + } > + > + // CB3DMA on PC12 > + Device (CB2A) { > + Name (_ADR, 0x00010000) > + } > + > + // CB3DMA on PC12 > + Device (CB2B) { > + Name (_ADR, 0x00010001) > + } > + > + // CB3DMA on PC12 > + Device (CB2C) { > + Name (_ADR, 0x00010002) > + } > + > + // CB3DMA on PC12 > + Device (CB2D) { > + Name (_ADR, 0x00010003) > + } > + > + // CB3DMA on PC12 > + Device (CB2E) { > + Name (_ADR, 0x00010004) > + } > + > + // CB3DMA on PC12 > + Device (CB2F) { > + Name (_ADR, 0x00010005) > + } > + > + // CB3DMA on PC12 > + Device (CB2G) { > + Name (_ADR, 0x00010006) > + } > + > + // CB3DMA on PC12 > + Device (CB2H) { > + Name (_ADR, 0x00010007) > + } > + } > + > + // Socket 2 Root bridge (Stack 1) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 2 > +#define STACK 1 > + Device (PC13) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x0D) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR51) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck2Ejd.asi" > + > + // PCI Express Port 1A on PC13 > + Device (RR1A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR52) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 1B on PC13 > + Device (RR1B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR53) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 1C on PC13 > + Device (RR1C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR54) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 1D on PC13 > + Device (RR1D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR55) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + } > + > + // Socket 2 Root bridge (Stack 2) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 2 > +#define STACK 2 > + Device (PC14) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x0E) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR56) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck2Ejd.asi" > + > + // PCI Express Port 2A on PC14 > + Device (RR2A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR57) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 2B on PC14 > + Device (RR2B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR58) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 2C on PC14 > + Device (RR2C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR59) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 2D on PC14 > + Device (RR2D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR5A) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + } > + > + // Socket 2 Root bridge (Stack 3) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 2 > +#define STACK 3 > + Device (PC15) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x0F) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR5B) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck2Ejd.asi" > + > + // PCI Express Port 3A on PC15 > + Device (RR3A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR5C) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 3B on PC15 > + Device (RR3B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR5D) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 3C on PC15 > + Device (RR3C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR5E) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 3D on PC15 > + Device (RR3D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR5F) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + } > + > + // Socket 2 Root bridge (Stack 4) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 2 > +#define STACK 4 > + Device (PC16) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x10) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR60) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck2Ejd.asi" > + > + // PCI Express Port 4A on PC16 > + Device (RR4A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR61) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 4B on PC16 > + Device (RR4B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR62) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 4C on PC16 > + Device (RR4C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR63) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 4D on PC16 > + Device (RR4D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR64) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + } > + > + // Socket 2 Root bridge (Stack 5) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 2 > +#define STACK 5 > + Device (PC17) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x11) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR65) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck2Ejd.asi" > + > + // PCI Express Port 5A on PC17 > + Device (RR5A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR66) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 5B on PC17 > + Device (RR5B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR67) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 5C on PC17 > + Device (RR5C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR68) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + > + // PCI Express Port 5D on PC17 > + Device (RR5D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR69) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1210nmEjd.asi" > + } > + } > + > + // Socket 2 Uncore 0 > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 2 > +#define STACK 6 > + Device (CONCATENATE3(UC, SOCKET, STACK)) { > + Name (_HID, EISAID("PNP0A03")) > + Name (_UID, 0x36) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR6A) > + } > + > + #include "Uncore.asi" > + > + // Uncore 4 UBOX Device > + Device (UBX2) { > + Name (_ADR, 0x00000000) > + } > + > + // Uncore 4 Misc 2 UPI 0-7 Device > + Device (UP04) { > + Name (_ADR, 0x00020000) > + } > + > + // Uncore 4 Misc 1 UPI 0-7 Device > + Device (UP05) { > + Name (_ADR, 0x00030000) > + } > + > + // Uncore 4 M2UPI Device > + Device (M2U6) { > + Name (_ADR, 0x00050000) > + } > + > + // Uncore 4 M2UPI Device > + Device (M2U7) { > + Name (_ADR, 0x00060000) > + } > + > + // Uncore 4 M2UPI Device > + Device (M2U8) { > + Name (_ADR, 0x00070000) > + } > + > + // Uncore 4 CHASIS_SMBUS Devices > + Device (CSM2) { > + Name (_ADR, 0x000B0000) > + } > + > + // Uncore 4 MS2MEM_SCF_MS2MEM0 Device > + Device (M2M4) { > + Name (_ADR, 0x000C0000) > + } > + > + // Uncore 4 MS2MEM_SCF_MS2MEM1 Device > + Device (M2M5) { > + Name (_ADR, 0x000D0000) > + } > + > + // Uncore 4 MCDDR0 Device > + Device (MCD4) { > + Name (_ADR, 0x001A0000) > + } > + > + // Uncore 4 MCDDR1 Device > + Device (MCD5) { > + Name (_ADR, 0x001B0000) > + } > + } > + > + // Socket 2 Uncore 1 > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 2 > +#define STACK 7 > + Device (CONCATENATE3(UC, SOCKET, STACK)) { > + Name (_HID, EISAID("PNP0A03")) > + Name (_UID, 0x37) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR6B) > + } > + > + #include "Uncore.asi" > + > + // Uncore 5 GRP1_CHA0-7 Device > + Device (EHA0) { > + Name (_ADR, 0x00000000) > + } > + > + // Uncore 5 GRP1_CHA8-15 Device > + Device (EHA1) { > + Name (_ADR, 0x00010000) > + } > + > + // Uncore 5 GRP1_CHA16-23 Device > + Device (EHA2) { > + Name (_ADR, 0x00020000) > + } > + > + // Uncore 5 GRP1_CHAU24-31 Device > + Device (EHA3) { > + Name (_ADR, 0x00030000) > + } > + > + // Uncore 5 GRP1_CHA32-33 Device > + Device (EHA4) { > + Name (_ADR, 0x00040000) > + } > + > + // Uncore 5 GRP0_CHA0-7 Device > + Device (EHA5) { > + Name (_ADR, 0x000A0000) > + } > + > + // Uncore 5 GRP0_CHA24-31 Device > + Device (EHA8) { > + Name (_ADR, 0x000D0000) > + } > + > + // Uncore 5 GRP0_CHA32-33 Device > + Device (EHA9) { > + Name (_ADR, 0x000E0000) > + } > + > + // Uncore 5 GRP0_CHA8-15 Device > + Device (EHA6) { > + Name (_ADR, 0x00B00000) > + } > + > + // Uncore 5 GRP0_CHA16-23 Device > + Device (EHA7) { > + Name (_ADR, 0x000C0000) > + } > + > + // Uncore 5 CHAALL0-1 Device > + Device (CA02) { > + Name (_ADR, 0x001D0000) > + } > + > + // Uncore 5 CHASIS_PUINT0-7 Device > + Device (PUC2) { > + Name (_ADR, 0x001E0000) > + } > + > + // Uncore 5 Gen3Phy Device > + Device (GN32) { > + Name (_ADR, 0x001F0000) > + } > + } > +#endif > + > +#if MAX_SOCKET > 3 > + // Socket 3 Root bridge (Stack 0) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 3 > +#define STACK 0 > + Device (PC18) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x12) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR6C) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck3Ejd.asi" > + > + // IIOMISC on PC18 > + Device (IIM3) { > + Name (_ADR, 0x00000000) > + } > + > + // CB3DMA on PC18 > + Device (CB3A) { > + Name (_ADR, 0x00010000) > + } > + > + // CB3DMA on PC18 > + Device (CB3B) { > + Name (_ADR, 0x00010001) > + } > + > + // CB3DMA on PC18 > + Device (CB3C) { > + Name (_ADR, 0x00010002) > + } > + > + // CB3DMA on PC18 > + Device (CB3D) { > + Name (_ADR, 0x00010003) > + } > + > + // CB3DMA on PC18 > + Device (CB3E) { > + Name (_ADR, 0x00010004) > + } > + > + // CB3DMA on PC18 > + Device (CB3F) { > + Name (_ADR, 0x00010005) > + } > + > + // CB3DMA on PC18 > + Device (CB3G) { > + Name (_ADR, 0x00010006) > + } > + > + // CB3DMA on PC18 > + Device (CB3H) { > + Name (_ADR, 0x00010007) > + } > + } > + > + // Socket 3 Root bridge (Stack 1) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 3 > +#define STACK 1 > + Device (PC19) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x13) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR6D) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck3Ejd.asi" > + > + // PCI Express Port 1A on PC19 > + Device (SR1A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR6E) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 1B on PC19 > + Device (SR1B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR6F) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 1C on PC19 > + Device (SR1C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR70) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 1D on PC19 > + Device (SR1D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR71) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + } > + > + // Socket 3 Root bridge (Stack 2) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 3 > +#define STACK 2 > + Device (PC20) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x14) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR72) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck3Ejd.asi" > + > + // PCI Express Port 2A on PC20 > + Device (SR2A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR73) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 2B on PC20 > + Device (SR2B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR74) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 2C on PC20 > + Device (SR2C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR75) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 2D on PC20 > + Device (SR2D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR76) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + } > + > + // Socket 3 Root bridge (Stack 3) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 3 > +#define STACK 3 > + Device (PC21) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x15) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR77) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck3Ejd.asi" > + > + // PCI Express Port 3A on PC21 > + Device (SR3A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR78) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 3B on PC21 > + Device (SR3B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR79) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 3C on PC21 > + Device (SR3C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR7A) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 3D on PC21 > + Device (SR3D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR7B) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + } > + > + // Socket 3 Root bridge (Stack 4) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 3 > +#define STACK 4 > + Device (PC22) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x16) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR7C) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck3Ejd.asi" > + > + // PCI Express Port 4A on PC22 > + Device (SR4A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR7D) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 4B on PC22 > + Device (SR4B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR7E) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 4C on PC22 > + Device (SR4C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR7F) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 4D on PC22 > + Device (SR4D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR80) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + } > + > + // Socket 3 Root bridge (Stack 5) > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 3 > +#define STACK 5 > + Device (PC23) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x17) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR81) > + } > + > + #include "IioRootBridge.asi" > + #include "Sck3Ejd.asi" > + > + // PCI Express Port 5A on PC23 > + Device (SR5A) { > + Name (_ADR, 0x00020000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR82) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 5B on PC23 > + Device (SR5B) { > + Name (_ADR, 0x00030000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR83) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 5C on PC23 > + Device (SR5C) { > + Name (_ADR, 0x00040000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR84) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + > + // PCI Express Port 5D on PC23 > + Device (SR5D) { > + Name (_ADR, 0x00050000) > + Method (_PRW, 0) { > + Return (Package (0x02) {0x09, 0x04}) > + } > + Method (_PRT, 0) { > + > + Return (AR85) > + } > + > + #include "PcieHp.asi" > + #include "PcieHpDev.asi" > + #include "PC1810nmEjd.asi" > + } > + } > + > + // Socket 3 Uncore 0 > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 3 > +#define STACK 6 > + Device (CONCATENATE3(UC, SOCKET, STACK)) { > + Name (_HID, EISAID("PNP0A03")) > + Name (_UID, 0x38) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR86) > + } > + > + #include "Uncore.asi" > + > + // Uncore 6 UBOX Device > + Device (UBX3) { > + Name (_ADR, 0x00000000) > + } > + > + // Uncore 6 Misc 2 UPI 0-7 Device > + Device (UP06) { > + Name (_ADR, 0x00020000) > + } > + > + // Uncore 6 Misc 1 UPI 0-7 Device > + Device (UP07) { > + Name (_ADR, 0x00030000) > + } > + > + // Uncore 6 M2UPI0 Device > + Device (M2U9) { > + Name (_ADR, 0x00050000) > + } > + > + // Uncore 6 M2UPI1 Device > + Device (M2UA) { > + Name (_ADR, 0x00060000) > + } > + > + // Uncore 6 M2UPI2 Device > + Device (M2UB) { > + Name (_ADR, 0x00070000) > + } > + > + // Uncore 6 CHASIS_SMBUS Devices > + Device (CSM3) { > + Name (_ADR, 0x000B0000) > + } > + > + // Uncore 6 MS2MEM_SCF_MS2MEM0 Device > + Device (M2M6) { > + Name (_ADR, 0x000C0000) > + } > + > + // Uncore 6 MS2MEM_SCF_MS2MEM1 Device > + Device (M2M7) { > + Name (_ADR, 0x000D0000) > + } > + > + // Uncore 6 MCDDR0 Device > + Device (MCD6) { > + Name (_ADR, 0x001A0000) > + } > + > + // Uncore 6 MCDDR1 Device > + Device (MCD7) { > + Name (_ADR, 0x001B0000) > + } > + } > + > + // Socket 3 Uncore 1 > + // > +#undef SOCKET > +#undef STACK > +#define SOCKET 3 > +#define STACK 7 > + Device (CONCATENATE3(UC, SOCKET, STACK)) { > + Name (_HID, EISAID("PNP0A03")) > + Name (_UID, 0x39) > + > + // > + // _PRT is ACPI method called by OS to read PCI Routing Table. > + // > + Method (_PRT, 0) > + { > + Return (AR87) > + } > + > + #include "Uncore.asi" > + > + // Uncore 7 GRP1_CHA0-7 Device > + Device (FHA0) { > + Name (_ADR, 0x00000000) > + } > + > + // Uncore 7 GRP1_CHA8-15 Device > + Device (FHA1) { > + Name (_ADR, 0x00010000) > + } > + > + // Uncore 7 GRP1_CHA16-23 Device > + Device (FHA2) { > + Name (_ADR, 0x00020000) > + } > + > + // Uncore 7 GRP1_CHAU24-31 Device > + Device (FHA3) { > + Name (_ADR, 0x00030000) > + } > + > + // Uncore 7 GRP1_CHA32-33 Device > + Device (FHA4) { > + Name (_ADR, 0x00040000) > + } > + > + // Uncore 7 GRP0_CHA0-7 Device > + Device (FHA5) { > + Name (_ADR, 0x000A0000) > + } > + > + // Uncore 7 GRP0_CHA24-31 Device > + Device (FHA8) { > + Name (_ADR, 0x000D0000) > + } > + > + // Uncore 7 GRP0_CHA32-33 Device > + Device (FHA9) { > + Name (_ADR, 0x000E0000) > + } > + > + // Uncore 7 GRP0_CHA8-15 Device > + Device (FHA6) { > + Name (_ADR, 0x00B00000) > + } > + > + // Uncore 7 GRP0_CHA16-23 Device > + Device (FHA7) { > + Name (_ADR, 0x000C0000) > + } > + > + // Uncore 7 CHAALL0-1 Device > + Device (CA03) { > + Name (_ADR, 0x001D0000) > + } > + > + // Uncore 7 CHASIS_PUINT0-7 Device > + Device (PUC3) { > + Name (_ADR, 0x001E0000) > + } > + > + // Uncore 7 Gen3Phy Device > + Device (GN33) { > + Name (_ADR, 0x001F0000) > + } > + } > +#endif > + > + // Virtual FPGA Bridge on Socket 0 > + Device (VFP0) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x18) > + Method (_BBN, 0, NotSerialized) { > + return (FBB0) > + } > + > + Method (_PRT, 0) { > + > + Return (AR88) > + } > + > + #include "FpgaBus00.asi" > + > + // FPGA Device > + Device (FPG0) { > + Name (_ADR, 0x00000000) > + } > + } > +#if MAX_SOCKET > 1 > + > + // Virtual FPGA Bridge on Socket 1 > + Device (VFP1) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x19) > + Method (_BBN, 0, NotSerialized) { > + return (FBB1) > + } > + > + Method (_PRT, 0) { > + > + Return (AR89) > + } > + > + #include "FpgaBus01.asi" > + > + // FPGA Device > + Device (FPG1) { > + Name (_ADR, 0x00000000) > + } > + } > +#endif > + > +#if MAX_SOCKET > 2 > + // Virtual FPGA Bridge on Socket 2 > + Device (VFP2) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x1A) > + Method (_BBN, 0, NotSerialized) { > + return (FBB2) > + } > + > + Method (_PRT, 0) { > + > + Return (AR8A) > + } > + > + #include "FpgaBus02.asi" > + > + // FPGA Device > + Device (FPG2) { > + Name (_ADR, 0x00000000) > + } > + } > +#endif > + > +#if MAX_SOCKET > 3 > + // Virtual FPGA Bridge on Socket 3 > + Device (VFP3) { > + Name (_HID, EISAID("PNP0A08")) > + Name (_CID, EISAID("PNP0A03")) > + Name (_UID, 0x1B) > + Method (_BBN, 0, NotSerialized) { > + return (FBB3) > + } > + > + Method (_PRT, 0) { > + > + Return (AR8B) > + } > + > + #include "FpgaBus03.asi" > + > + // FPGA Device > + Device (FPG3) { > + Name (_ADR, 0x00000000) > + } > + } > +#endif > +} > + > +Scope (\_GPE) { > + // [BR1A]: PCI Express Port 1A on PC01 > + // [BR1B]: PCI Express Port 1B on PC01 > + // [BR1C]: PCI Express Port 1C on PC01 > + // [BR1D]: PCI Express Port 1D on PC01 > + // [BR2A]: PCI Express Port 2A on PC02 > + // [BR2B]: PCI Express Port 2B on PC02 > + // [BR2C]: PCI Express Port 2C on PC02 > + // [BR2D]: PCI Express Port 2D on PC02 > + // [BR3A]: PCI Express Port 3A on PC03 > + // [BR3B]: PCI Express Port 3B on PC03 > + // [BR3C]: PCI Express Port 3C on PC03 > + // [BR3D]: PCI Express Port 3D on PC03 > + // [BR4A]: PCI Express Port 4A on PC04 > + // [BR4B]: PCI Express Port 4B on PC04 > + // [BR4C]: PCI Express Port 4C on PC04 > + // [BR4D]: PCI Express Port 4D on PC04 > + // [BR5A]: PCI Express Port 5A on PC05 > + // [BR5B]: PCI Express Port 5B on PC05 > + // [BR5C]: PCI Express Port 5C on PC05 > + // [BR5D]: PCI Express Port 5D on PC05 > + // [QR1A]: PCI Express Port 1A on PC07 > + // [QR1B]: PCI Express Port 1B on PC07 > + // [QR1C]: PCI Express Port 1C on PC07 > + // [QR1D]: PCI Express Port 1D on PC07 > + // [QR2A]: PCI Express Port 2A on PC08 > + // [QR2B]: PCI Express Port 2B on PC08 > + // [QR2C]: PCI Express Port 2C on PC08 > + // [QR2D]: PCI Express Port 2D on PC08 > + // [QR3A]: PCI Express Port 3A on PC09 > + // [QR3B]: PCI Express Port 3B on PC09 > + // [QR3C]: PCI Express Port 3C on PC09 > + // [QR3D]: PCI Express Port 3D on PC09 > + // [QR4A]: PCI Express Port 4A on PC10 > + // [QR4B]: PCI Express Port 4B on PC10 > + // [QR4C]: PCI Express Port 4C on PC10 > + // [QR4D]: PCI Express Port 4D on PC10 > + // [QR5A]: PCI Express Port 5A on PC11 > + // [QR5B]: PCI Express Port 5B on PC11 > + // [QR5C]: PCI Express Port 5C on PC11 > + // [QR5D]: PCI Express Port 5D on PC11 > + // [RR1A]: PCI Express Port 1A on PC13 > + // [RR1B]: PCI Express Port 1B on PC13 > + // [RR1C]: PCI Express Port 1C on PC13 > + // [RR1D]: PCI Express Port 1D on PC13 > + // [RR2A]: PCI Express Port 2A on PC14 > + // [RR2B]: PCI Express Port 2B on PC14 > + // [RR2C]: PCI Express Port 2C on PC14 > + // [RR2D]: PCI Express Port 2D on PC14 > + // [RR3A]: PCI Express Port 3A on PC15 > + // [RR3B]: PCI Express Port 3B on PC15 > + // [RR3C]: PCI Express Port 3C on PC15 > + // [RR3D]: PCI Express Port 3D on PC15 > + // [RR4A]: PCI Express Port 4A on PC16 > + // [RR4B]: PCI Express Port 4B on PC16 > + // [RR4C]: PCI Express Port 4C on PC16 > + // [RR4D]: PCI Express Port 4D on PC16 > + // [RR5A]: PCI Express Port 5A on PC17 > + // [RR5B]: PCI Express Port 5B on PC17 > + // [RR5C]: PCI Express Port 5C on PC17 > + // [RR5D]: PCI Express Port 5D on PC17 > + // [SR1A]: PCI Express Port 1A on PC19 > + // [SR1B]: PCI Express Port 1B on PC19 > + // [SR1C]: PCI Express Port 1C on PC19 > + // [SR1D]: PCI Express Port 1D on PC19 > + // [SR2A]: PCI Express Port 2A on PC20 > + // [SR2B]: PCI Express Port 2B on PC20 > + // [SR2C]: PCI Express Port 2C on PC20 > + // [SR2D]: PCI Express Port 2D on PC20 > + // [SR3A]: PCI Express Port 3A on PC21 > + // [SR3B]: PCI Express Port 3B on PC21 > + // [SR3C]: PCI Express Port 3C on PC21 > + // [SR3D]: PCI Express Port 3D on PC21 > + // [SR4A]: PCI Express Port 4A on PC22 > + // [SR4B]: PCI Express Port 4B on PC22 > + // [SR4C]: PCI Express Port 4C on PC22 > + // [SR4D]: PCI Express Port 4D on PC22 > + // [SR5A]: PCI Express Port 5A on PC23 > + // [SR5B]: PCI Express Port 5B on PC23 > + // [SR5C]: PCI Express Port 5C on PC23 > + // [SR5D]: PCI Express Port 5D on PC23 > + Method (_L09, 0x0, NotSerialized) { > + #include "Gpe.asi" > + Notify (\_SB.PC01.BR1A, 0x02) > + Notify (\_SB.PC01.BR1B, 0x02) > + Notify (\_SB.PC01.BR1C, 0x02) > + Notify (\_SB.PC01.BR1D, 0x02) > + Notify (\_SB.PC02.BR2A, 0x02) > + Notify (\_SB.PC02.BR2B, 0x02) > + Notify (\_SB.PC02.BR2C, 0x02) > + Notify (\_SB.PC02.BR2D, 0x02) > + Notify (\_SB.PC03.BR3A, 0x02) > + Notify (\_SB.PC03.BR3B, 0x02) > + Notify (\_SB.PC03.BR3C, 0x02) > + Notify (\_SB.PC03.BR3D, 0x02) > + Notify (\_SB.PC04.BR4A, 0x02) > + Notify (\_SB.PC04.BR4B, 0x02) > + Notify (\_SB.PC04.BR4C, 0x02) > + Notify (\_SB.PC04.BR4D, 0x02) > + Notify (\_SB.PC05.BR5A, 0x02) > + Notify (\_SB.PC05.BR5B, 0x02) > + Notify (\_SB.PC05.BR5C, 0x02) > + Notify (\_SB.PC05.BR5D, 0x02) > +#if MAX_SOCKET > 1 > + Notify (\_SB.PC07.QR1A, 0x02) > + Notify (\_SB.PC07.QR1B, 0x02) > + Notify (\_SB.PC07.QR1C, 0x02) > + Notify (\_SB.PC07.QR1D, 0x02) > + Notify (\_SB.PC08.QR2A, 0x02) > + Notify (\_SB.PC08.QR2B, 0x02) > + Notify (\_SB.PC08.QR2C, 0x02) > + Notify (\_SB.PC08.QR2D, 0x02) > + Notify (\_SB.PC09.QR3A, 0x02) > + Notify (\_SB.PC09.QR3B, 0x02) > + Notify (\_SB.PC09.QR3C, 0x02) > + Notify (\_SB.PC09.QR3D, 0x02) > + Notify (\_SB.PC10.QR4A, 0x02) > + Notify (\_SB.PC10.QR4B, 0x02) > + Notify (\_SB.PC10.QR4C, 0x02) > + Notify (\_SB.PC10.QR4D, 0x02) > + Notify (\_SB.PC11.QR5A, 0x02) > + Notify (\_SB.PC11.QR5B, 0x02) > + Notify (\_SB.PC11.QR5C, 0x02) > + Notify (\_SB.PC11.QR5D, 0x02) > +#endif > +#if MAX_SOCKET > 2 > + Notify (\_SB.PC13.RR1A, 0x02) > + Notify (\_SB.PC13.RR1B, 0x02) > + Notify (\_SB.PC13.RR1C, 0x02) > + Notify (\_SB.PC13.RR1D, 0x02) > + Notify (\_SB.PC14.RR2A, 0x02) > + Notify (\_SB.PC14.RR2B, 0x02) > + Notify (\_SB.PC14.RR2C, 0x02) > + Notify (\_SB.PC14.RR2D, 0x02) > + Notify (\_SB.PC15.RR3A, 0x02) > + Notify (\_SB.PC15.RR3B, 0x02) > + Notify (\_SB.PC15.RR3C, 0x02) > + Notify (\_SB.PC15.RR3D, 0x02) > + Notify (\_SB.PC16.RR4A, 0x02) > + Notify (\_SB.PC16.RR4B, 0x02) > + Notify (\_SB.PC16.RR4C, 0x02) > + Notify (\_SB.PC16.RR4D, 0x02) > + Notify (\_SB.PC17.RR5A, 0x02) > + Notify (\_SB.PC17.RR5B, 0x02) > + Notify (\_SB.PC17.RR5C, 0x02) > + Notify (\_SB.PC17.RR5D, 0x02) > +#endif > +#if MAX_SOCKET > 3 > + Notify (\_SB.PC19.SR1A, 0x02) > + Notify (\_SB.PC19.SR1B, 0x02) > + Notify (\_SB.PC19.SR1C, 0x02) > + Notify (\_SB.PC19.SR1D, 0x02) > + Notify (\_SB.PC20.SR2A, 0x02) > + Notify (\_SB.PC20.SR2B, 0x02) > + Notify (\_SB.PC20.SR2C, 0x02) > + Notify (\_SB.PC20.SR2D, 0x02) > + Notify (\_SB.PC21.SR3A, 0x02) > + Notify (\_SB.PC21.SR3B, 0x02) > + Notify (\_SB.PC21.SR3C, 0x02) > + Notify (\_SB.PC21.SR3D, 0x02) > + Notify (\_SB.PC22.SR4A, 0x02) > + Notify (\_SB.PC22.SR4B, 0x02) > + Notify (\_SB.PC22.SR4C, 0x02) > + Notify (\_SB.PC22.SR4D, 0x02) > + Notify (\_SB.PC23.SR5A, 0x02) > + Notify (\_SB.PC23.SR5B, 0x02) > + Notify (\_SB.PC23.SR5C, 0x02) > + Notify (\_SB.PC23.SR5D, 0x02) > +#endif > + } > + > + // [EPCU]: EVA PCIe Uplink > + // [VSP0]: EVA Virtual Switch Port 0 > + // [VSP1]: EVA Virtual Switch Port 1 > + // [VSP2]: EVA Virtual Switch Port 2 > + // [VSP3]: EVA Virtual Switch Port 3 > + Method (_L0B, 0x0, NotSerialized) { > + Notify (\_SB.PC02.BR2A.EPCU, 0x02) > + Notify (\_SB.PC02.BR2A.EPCU.VSP0, 0x02) > + Notify (\_SB.PC02.BR2A.EPCU.VSP1, 0x02) > + Notify (\_SB.PC02.BR2A.EPCU.VSP2, 0x02) > + Notify (\_SB.PC02.BR2A.EPCU.VSP3, 0x02) > + } > +} > + > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck > 1Ejd.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck > 1Ejd.asi > new file mode 100644 > index 0000000000..5c5c5fbade > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck > 1Ejd.asi > @@ -0,0 +1,10 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2012 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // Eject device if SCK1 is removed. > + Name(_EJD,"\\_SB.SCK1") // Dependent on SCK1 > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck > 2Ejd.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck > 2Ejd.asi > new file mode 100644 > index 0000000000..f8b0cd107d > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck > 2Ejd.asi > @@ -0,0 +1,10 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2012 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // Eject device if SCK2 is removed. > + Name(_EJD,"\\_SB.SCK2") // Dependent on SCK2 > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck > 3Ejd.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck > 3Ejd.asi > new file mode 100644 > index 0000000000..175d5d871b > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck > 3Ejd.asi > @@ -0,0 +1,10 @@ > +/** @file > + > + @copyright > + Copyright 2001 - 2012 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // Eject device if SCK3 is removed. > + Name(_EJD,"\\_SB.SCK3") // Dependent on SCK3 > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx > .asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx > .asi > new file mode 100644 > index 0000000000..d6a1e5da71 > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx > .asi > @@ -0,0 +1,219 @@ > +/** @file > + > + @copyright > + Copyright 2007 - 2017 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +Device (EPC) { > + Name (_HID, EISAID ("INT0E0C")) > + Name (_STR, Unicode ("Enclave Page Cache 1.0")) > + Name (_MLS, Package () {Package (2) { "en", Unicode ("Enclave Page > Cache 1.0")}}) > + > + Name (RBUF, ResourceTemplate () { > + QWordMemory ( > + ResourceConsumer, // ResourceUsage > + PosDecode, // Decode _DEC > + MinNotFixed, // IsMinFixed _MIF > + MaxNotFixed, // IsMaxFixed _MAF > + NonCacheable, // Cacheable _MEM > + ReadWrite, // ReadAndWrite _RW > + 0, // AddressGranularity _GRA > + 0, // AddressMinimum _MIN <=3D To be patc= hed in Runtime > + 0, // AddressMaximum _MAX <=3D To be patc= hed in Runtime > + 0, // AddressTranslation _TRA > + 0, // RangeLength _LEN <=3D To be patc= hed in Runtime > + , // ResourceSourceIndex > + , // ResourceSource > + EPC0 // DescriptorName > + ) > + QWordMemory ( > + ResourceConsumer, // ResourceUsage > + PosDecode, // Decode _DEC > + MinNotFixed, // IsMinFixed _MIF > + MaxNotFixed, // IsMaxFixed _MAF > + NonCacheable, // Cacheable _MEM > + ReadWrite, // ReadAndWrite _RW > + 0, // AddressGranularity _GRA > + 0, // AddressMinimum _MIN <=3D To be patc= hed in Runtime > + 0, // AddressMaximum _MAX <=3D To be patc= hed in Runtime > + 0, // AddressTranslation _TRA > + 0, // RangeLength _LEN <=3D To be patc= hed in Runtime > + , // ResourceSourceIndex > + , // ResourceSource > + EPC1 // DescriptorName > + ) > + QWordMemory ( > + ResourceConsumer, // ResourceUsage > + PosDecode, // Decode _DEC > + MinNotFixed, // IsMinFixed _MIF > + MaxNotFixed, // IsMaxFixed _MAF > + NonCacheable, // Cacheable _MEM > + ReadWrite, // ReadAndWrite _RW > + 0, // AddressGranularity _GRA > + 0, // AddressMinimum _MIN <=3D To be patc= hed in Runtime > + 0, // AddressMaximum _MAX <=3D To be patc= hed in Runtime > + 0, // AddressTranslation _TRA > + 0, // RangeLength _LEN <=3D To be patc= hed in Runtime > + , // ResourceSourceIndex > + , // ResourceSource > + EPC2 // DescriptorName > + ) > + QWordMemory ( > + ResourceConsumer, // ResourceUsage > + PosDecode, // Decode _DEC > + MinNotFixed, // IsMinFixed _MIF > + MaxNotFixed, // IsMaxFixed _MAF > + NonCacheable, // Cacheable _MEM > + ReadWrite, // ReadAndWrite _RW > + 0, // AddressGranularity _GRA > + 0, // AddressMinimum _MIN <=3D To be patc= hed in Runtime > + 0, // AddressMaximum _MAX <=3D To be patc= hed in Runtime > + 0, // AddressTranslation _TRA > + 0, // RangeLength _LEN <=3D To be patc= hed in Runtime > + , // ResourceSourceIndex > + , // ResourceSource > + EPC3 // DescriptorName > + ) > + QWordMemory ( > + ResourceConsumer, // ResourceUsage > + PosDecode, // Decode _DEC > + MinNotFixed, // IsMinFixed _MIF > + MaxNotFixed, // IsMaxFixed _MAF > + NonCacheable, // Cacheable _MEM > + ReadWrite, // ReadAndWrite _RW > + 0, // AddressGranularity _GRA > + 0, // AddressMinimum _MIN <=3D To be patc= hed in Runtime > + 0, // AddressMaximum _MAX <=3D To be patc= hed in Runtime > + 0, // AddressTranslation _TRA > + 0, // RangeLength _LEN <=3D To be patc= hed in Runtime > + , // ResourceSourceIndex > + , // ResourceSource > + EPC4 // DescriptorName > + ) > + QWordMemory ( > + ResourceConsumer, // ResourceUsage > + PosDecode, // Decode _DEC > + MinNotFixed, // IsMinFixed _MIF > + MaxNotFixed, // IsMaxFixed _MAF > + NonCacheable, // Cacheable _MEM > + ReadWrite, // ReadAndWrite _RW > + 0, // AddressGranularity _GRA > + 0, // AddressMinimum _MIN <=3D To be patc= hed in Runtime > + 0, // AddressMaximum _MAX <=3D To be patc= hed in Runtime > + 0, // AddressTranslation _TRA > + 0, // RangeLength _LEN <=3D To be patc= hed in Runtime > + , // ResourceSourceIndex > + , // ResourceSource > + EPC5 // DescriptorName > + ) > + QWordMemory ( > + ResourceConsumer, // ResourceUsage > + PosDecode, // Decode _DEC > + MinNotFixed, // IsMinFixed _MIF > + MaxNotFixed, // IsMaxFixed _MAF > + NonCacheable, // Cacheable _MEM > + ReadWrite, // ReadAndWrite _RW > + 0, // AddressGranularity _GRA > + 0, // AddressMinimum _MIN <=3D To be patc= hed in Runtime > + 0, // AddressMaximum _MAX <=3D To be patc= hed in Runtime > + 0, // AddressTranslation _TRA > + 0, // RangeLength _LEN <=3D To be patc= hed in Runtime > + , // ResourceSourceIndex > + , // ResourceSource > + EPC6 // DescriptorName > + ) > + QWordMemory ( > + ResourceConsumer, // ResourceUsage > + PosDecode, // Decode _DEC > + MinNotFixed, // IsMinFixed _MIF > + MaxNotFixed, // IsMaxFixed _MAF > + NonCacheable, // Cacheable _MEM > + ReadWrite, // ReadAndWrite _RW > + 0, // AddressGranularity _GRA > + 0, // AddressMinimum _MIN <=3D To be patc= hed in Runtime > + 0, // AddressMaximum _MAX <=3D To be patc= hed in Runtime > + 0, // AddressTranslation _TRA > + 0, // RangeLength _LEN <=3D To be patc= hed in Runtime > + , // ResourceSourceIndex > + , // ResourceSource > + EPC7 // DescriptorName > + ) > + }) > + > + Method (_CRS, 0x0, NotSerialized) { > + If (LNotEqual (EBA0, 0)) { > + CreateQwordField (RBUF, ^EPC0._MIN, MIN0) > + CreateQwordField (RBUF, ^EPC0._MAX, MAX0) > + CreateQwordField (RBUF, ^EPC0._LEN, LEN0) > + Store (EBA0, MIN0) > + Store (ELN0, LEN0) > + Subtract (Add (EBA0, ELN0), 1, MAX0) > + } > + If (LNotEqual (EBA1, 0)) { > + CreateQwordField (RBUF, ^EPC1._MIN, MIN1) > + CreateQwordField (RBUF, ^EPC1._MAX, MAX1) > + CreateQwordField (RBUF, ^EPC1._LEN, LEN1) > + Store (EBA1, MIN1) > + Store (ELN1, LEN1) > + Subtract (Add (EBA1, ELN1), 1, MAX1) > + } > + If (LNotEqual (EBA2, 0)) { > + CreateQwordField (RBUF, ^EPC2._MIN, MIN2) > + CreateQwordField (RBUF, ^EPC2._MAX, MAX2) > + CreateQwordField (RBUF, ^EPC2._LEN, LEN2) > + Store (EBA2, MIN2) > + Store (ELN2, LEN2) > + Subtract (Add (EBA2, ELN2), 1, MAX2) > + } > + If (LNotEqual (EBA3, 0)) { > + CreateQwordField (RBUF, ^EPC3._MIN, MIN3) > + CreateQwordField (RBUF, ^EPC3._MAX, MAX3) > + CreateQwordField (RBUF, ^EPC3._LEN, LEN3) > + Store (EBA3, MIN3) > + Store (ELN3, LEN3) > + Subtract (Add (EBA3, ELN3), 1, MAX3) > + } > + If (LNotEqual (EBA4, 0)) { > + CreateQwordField (RBUF, ^EPC4._MIN, MIN4) > + CreateQwordField (RBUF, ^EPC4._MAX, MAX4) > + CreateQwordField (RBUF, ^EPC4._LEN, LEN4) > + Store (EBA4, MIN4) > + Store (ELN4, LEN4) > + Subtract (Add (EBA4, ELN4), 1, MAX4) > + } > + If (LNotEqual (EBA5, 0)) { > + CreateQwordField (RBUF, ^EPC5._MIN, MIN5) > + CreateQwordField (RBUF, ^EPC5._MAX, MAX5) > + CreateQwordField (RBUF, ^EPC5._LEN, LEN5) > + Store (EBA5, MIN5) > + Store (ELN5, LEN5) > + Subtract (Add (EBA5, ELN5), 1, MAX5) > + } > + If (LNotEqual (EBA6, 0)) { > + CreateQwordField (RBUF, ^EPC6._MIN, MIN6) > + CreateQwordField (RBUF, ^EPC6._MAX, MAX6) > + CreateQwordField (RBUF, ^EPC6._LEN, LEN6) > + Store (EBA6, MIN6) > + Store (ELN6, LEN6) > + Subtract (Add (EBA6, ELN6), 1, MAX6) > + } > + If (LNotEqual (EBA7, 0)) { > + CreateQwordField (RBUF, ^EPC7._MIN, MIN7) > + CreateQwordField (RBUF, ^EPC7._MAX, MAX7) > + CreateQwordField (RBUF, ^EPC7._LEN, LEN7) > + Store (EBA7, MIN7) > + Store (ELN7, LEN7) > + Subtract (Add (EBA7, ELN7), 1, MAX7) > + } > + Return (RBUF) > + } > + > + Method (_STA, 0x0, NotSerialized) { > + If (LNotEqual (EPCS, 0)) { > + Return (0xF) > + } > + Return (0x0) > + } > +} // end EPC Device > diff --git > a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Un > core.asi > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Un > core.asi > new file mode 100644 > index 0000000000..bfda78432c > --- /dev/null > +++ > b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Un > core.asi > @@ -0,0 +1,163 @@ > +/** @file > + > + @copyright > + Copyright 2016 - 2020 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // > + // _BBN is ACPI method called by OS to read PCI base bus number for II= O > stack. > + // > + Method(_BBN, 0, NotSerialized) > + { > + Return(CONCATENATE3(BB, SOCKET, STACK)) > + } > + > + // > + // _PXM is ACPI method called by OS to read Proximity Domain (aka NUMA > Node) where IIO stack belongs to. > + // > + Method(_PXM, 0, NotSerialized) > + { > + Store(SOCKET, Local0) > + If (CLOD) { > + // > + // If Sub-NUMA Cluster (SNC) enabled report PCI in the first of SN= C > domains of a socket, > + // so multiplicate socket number by the number of SNC domains. > + // > + Multiply(Local0, CLOD, Local0) > + } > + Return(Local0) > + } > + > + // > + // _SEG is ACPI method called by OS to read PCI segment of IIO stack. > + // > + Method(_SEG, 0, NotSerialized) > + { > + Return(CONCATENATE2(SG0, SOCKET)) > + } > + > + // > + // _STA is a ACPI method called by OS to read status of ACPI device, I= IO > stack in this case. > + // > + Method(_STA, 0, NotSerialized) > + { // > + // Check in processor present bitmap (PRBM) if processor is present,= then > + // in stack present bitmap of given processor (SPBx) if stack is pre= sent. > + // > + ShiftLeft(1, SOCKET, Local0) > + If (And(PRBM, Local0)) { > + > + ShiftLeft(1, CONCATENATE2(0x,STACK), Local1) > + if (And(CONCATENATE2(SPB, SOCKET), Local1)) { > + Return(0x0F) > + } > + } > + Return(0x00) > + } > + > + External (DBGM, FieldUnitObj) > + Name (SUPP, 0) > + Name (CTRL, 0) > + > + Method(_OSC,4) { > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,0,CDW1) > + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + > + // > + // Create DWord-addressable fields from the capabilities Buffer > + // > + CreateDWordField(Arg3,4,CDW2) > + > + // > + // Fill 3rd capability DWORD only if the count is greater than 2= . > + // > + If(LGreater(Arg2,2)) { > + CreateDWordField(Arg3,8,CDW3) > + } > + > + // > + // Save Capabilities DWord2 & 3 > + // > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > + > + // > + // Only allow native hot plug control if OS supports > + // * ASPM > + // * MSI/MSI-X > + // > + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions= not > met? > + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. > + Sleep(1000) > + } > + > + // > + // Never allow SHPC (no SHPC controller in system) > + // > + And(CTRL, 0x1D, CTRL) > + // > + // Disable Native PCIe AER handling from OS so that it uses Firm= ware > First model in WHEA > + // > + And (CTRL, 0x17, CTRL) > + If (Not(And(CDW1,1))) { // Query Flag Clear? > + // > + // Disable GPEs for Features granted native control > + // > + If (And(CTRL, 0x01)) { // Native Hot plug control granted? > + Store (0x01, GPSH) // Clear Hotplug SCI Enabl= e in GPE0 > + } > + } > + > + If (LNotEqual(Arg1,one)) { // unknown revision > + Or(CDW1,0x08,CDW1) > + } > + > + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked > + Or(CDW1,0x10,CDW1) > + } > + // > + // update DWORD3 in the buffer > + // > + Store(CTRL,CDW3) > + Return(Arg3) > + > + } Else { > + // > + // Just indicate unrecognized UUID > + // Leave it at that > + // > + Or (CDW1,4,CDW1) > + if(LEqual(DBGM, 0x01)){ > + Store (0xEE, IO80) > + } > + Return(Arg3) > + } > + } // End _OSC > + > + Name (UNRS, ResourceTemplate() { > + WORDBusNumber ( // Bus number resource (0); the bridge produce= s > bus numbers for its subsequent buses > + ResourceProducer, // bit 0 of general flags is 1 > + MinFixed, // Range is fixed > + MaxFixed, // Range is fixed > + PosDecode, // PosDecode > + 0x0000, // Granularity (FIX9 - Patched by ACPI Platfor= m Driver > during POST) > + 0x0000, // Min (FIX9 - Patched by ACPI Platfor= m Driver during > POST) > + 0x0000, // Max (FIX9 - Patched by ACPI Platfor= m Driver during > POST) > + 0x0000, // Translation > + 0x0001, // Range Length =3D Max-Min+1 (FIX9 - Patched = by ACPI > Platform Driver during POST) > + , > + , > + FIX9 // DescriptorName populated so iASL outputs of= fset for it in > a .h file > + ) > + }) > + > + // Current resource template return > + Method(_CRS, 0x0, NotSerialized) > + { > + Return(UNRS) > + } > diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc > b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc > index 42680254d1..9c2b8a1048 100644 > --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc > +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc > @@ -805,6 +805,7 @@ >=20 > $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf >=20 > + $(RP_PKG)/Features/Acpi/AcpiTables/AcpiTables10nm.inf > $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf >=20 > $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf > diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf > b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf > index 45460570d9..ca3514b8ba 100644 > --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf > +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf > @@ -671,6 +671,7 @@ SET > gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D 0x01000000 > INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf > INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf >=20 > + INF RuleOverride =3D ACPITABLE > WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf > INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf > INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf >=20 > -- > 2.27.0.windows.1