Re: [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components

["Nate DeSimone" <nathaniel.l.desimone@intel.com>]

Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com> 
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components

Adds the following modules:
  - IpBlock/Graphics/Include
  - IpBlock/Graphics/IncludePrivate
  - IpBlock/Graphics/Library
  - IpBlock/Graphics/LibraryPrivate
  - IpBlock/HostBridge/IncludePrivate
  - IpBlock/PcieRp/Library

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
 .../Include/Ppi/GraphicsPlatformPolicyPpi.h   |  76 +++++++++++
 .../Library/DxeGraphicsPolicyLib.h            |  71 +++++++++++
 .../Library/DxeIgdOpRegionInitLib.h           | 115 +++++++++++++++++
 .../GraphicsInfoLibVer1.c                     |  52 ++++++++
 .../GraphicsInfoLibVer1.inf                   |  33 +++++
 .../DxeGraphicsPolicyLib.c                    | 116 +++++++++++++++++
 .../DxeGraphicsPolicyLib.inf                  |  36 ++++++
 .../DxeIgdOpRegionInit.c                      | 119 ++++++++++++++++++
 .../DxeIgdOpRegionInitLib.inf                 |  47 +++++++
 .../IncludePrivate/HostBridgeDataHob.h        |  25 ++++
 .../PchPcieRpLibInternal.h                    |  20 +++
 .../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c  |  71 +++++++++++
 .../PeiDxeSmmPchPcieRpLibVer2.inf             |  37 ++++++
 13 files changed, 818 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 0000000000..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra
+++ phicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+  The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI Graphics PEIM.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+  Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \
+  0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 
+0x99, 0x5 } \ }
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION         1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI 
+PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+  Enum defining the different lid status values **/ typedef enum {
+  LidClosed,
+  LidOpen,
+  LidStatusMax
+} LID_STATUS;
+
+/**
+  This function gets the platform lid status for LFP displays.
+
+  @param[out] CurrentLidStatus  Output variable to store the lid status.
+
+  @retval EFI_SUCCESS           Correct lid status is returned.
+  @retval EFI_UNSUPPORTED       Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+  OUT LID_STATUS  *CurrentLidStatus
+  );
+
+/**
+  This function gets the base address of loaded VBT.
+
+  @param[out] VbtAddress    Starting address of the VBT is returned in this parameter.
+  @param[out] VbtSize       Size of the VBT is returned in this parameter.
+
+  @retval     EFI_SUCCESS   If the VBT is loaded and parameters contain valid values.
+  @return     Other error codes meaning VBT is not loaded and parameters contain invalid values.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+  OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+  OUT UINT32               *VbtSize
+  );
+
+/**
+  This defines the PEI Graphics Platform Policy PPI structure.
+**/
+struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI {
+  UINT32                        Revision;               ///< Revision of current implementation.
+  GET_PLATFORM_LID_STATUS       GetPlatformLidStatus;   ///< Function Pointer for get platform lid status.
+  GET_VBT_DATA                  GetVbtData;             ///< Function pointer for get vbt data.
+};
+
+extern EFI_GUID gPeiGraphicsPlatformPpiGuid;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
new file mode 100644
index 0000000000..0347d4c94c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/
+++ Library/DxeGraphicsPolicyLib.h
@@ -0,0 +1,71 @@
+/** @file
+  Header file for the DXE Graphics Policy Init library.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef 
+_DXE_GRAPHICS_POLICY_LIB_H_ #define _DXE_GRAPHICS_POLICY_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Protocol/SaPolicy.h> 
+#include <ConfigBlock.h> #include <GraphicsConfig.h> #include 
+<Library/SiConfigBlockLib.h>
+
+#define WORD_FIELD_VALID_BIT  BIT15
+
+extern EFI_GUID gGraphicsDxeConfigGuid;
+
+/**
+  This function prints the Graphics DXE phase policy.
+
+  @param[in] SaPolicy - SA DXE Policy protocol **/ VOID 
+GraphicsDxePolicyPrint (
+  IN  SA_POLICY_PROTOCOL      *SaPolicy
+  );
+
+/**
+  This function Load default Graphics DXE policy.
+
+  @param[in] ConfigBlockPointer    The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+  IN VOID    *ConfigBlockPointer
+  );
+
+
+/**
+  Get DXE Graphics config block table total size.
+
+  @retval     Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+  VOID
+  );
+
+/**
+  GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+  @param[in] ConfigBlockTableAddress    The pointer to add SA config blocks
+
+  @retval EFI_SUCCESS                   The policy default is initialized.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+  IN VOID           *ConfigBlockTableAddress
+  );
+
+#endif // _DXE_GRAPHICs_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
new file mode 100644
index 0000000000..02e4988b2b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/
+++ Library/DxeIgdOpRegionInitLib.h
@@ -0,0 +1,115 @@
+/** @file
+  This is part of the implementation of an Intel Graphics drivers 
+OpRegion /
+  Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef 
+_DXE_IGD_OPREGION_INIT_LIB_H_ #define _DXE_IGD_OPREGION_INIT_LIB_H_
+
+///
+/// Statements that include other header files.
+///
+#include <Uefi.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/IoLib.h> 
+#include <Library/DebugLib.h> #include <Library/HobLib.h> #include 
+<Library/UefiLib.h> #include <Library/S3BootScriptLib.h> #include 
+<Register/IgdRegs.h> #include <SiConfigHob.h> #include 
+<Register/SaRegsHostBridge.h> /// /// Driver Consumed Protocol 
+Prototypes /// #include <Protocol/PciIo.h> #include 
+<Protocol/PciRootBridgeIo.h> #include <Protocol/SaPolicy.h> /// /// 
+Driver Produced Protocol Prototypes /// #include 
+<Protocol/IgdOpRegion.h>
+
+#pragma pack(push, 1)
+///
+///
+/// OpRegion (Miscellaneous) defines.
+///
+/// OpRegion Header defines.
+///
+typedef UINT16  STRING_REF;
+///
+/// Typedef stuctures
+///
+typedef struct {
+  UINT16  Signature;  /// 0xAA55
+  UINT8   Size512;
+  UINT8   Reserved[21];
+  UINT16  PcirOffset;
+  UINT16  VbtOffset;
+} INTEL_VBIOS_OPTION_ROM_HEADER;
+
+typedef struct {
+  UINT32  Signature;  /// "PCIR"
+  UINT16  VendorId;   /// 0x8086
+  UINT16  DeviceId;
+  UINT16  Reserved0;
+  UINT16  Length;
+  UINT8   Revision;
+  UINT8   ClassCode[3];
+  UINT16  ImageLength;
+  UINT16  CodeRevision;
+  UINT8   CodeType;
+  UINT8   Indicator;
+  UINT16  Reserved1;
+} INTEL_VBIOS_PCIR_STRUCTURE;
+
+typedef struct {
+  UINT8   HeaderSignature[20];
+  UINT16  HeaderVersion;
+  UINT16  HeaderSize;
+  UINT16  HeaderVbtSize;
+  UINT8   HeaderVbtCheckSum;
+  UINT8   HeaderReserved;
+  UINT32  HeaderOffsetVbtDataBlock;
+  UINT32  HeaderOffsetAim1;
+  UINT32  HeaderOffsetAim2;
+  UINT32  HeaderOffsetAim3;
+  UINT32  HeaderOffsetAim4;
+  UINT8   DataHeaderSignature[16];
+  UINT16  DataHeaderVersion;
+  UINT16  DataHeaderSize;
+  UINT16  DataHeaderDataBlockSize;
+  UINT8   CoreBlockId;
+  UINT16  CoreBlockSize;
+  UINT16  CoreBlockBiosSize;
+  UINT8   CoreBlockBiosType;
+  UINT8   CoreBlockReleaseStatus;
+  UINT8   CoreBlockHWSupported;
+  UINT8   CoreBlockIntegratedHW;
+  UINT8   CoreBlockBiosBuild[4];
+  UINT8   CoreBlockBiosSignOn[155];
+} VBIOS_VBT_STRUCTURE;
+#pragma pack(pop)
+///
+/// Driver Private Function definitions ///
+
+/**
+  Update Graphics OpRegion after PCI enumeration.
+
+  @retval EFI_SUCCESS     - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+  VOID
+  );
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
new file mode 100644
index 0000000000..9dd9b33a49
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS
+++ mmGraphicsInfoLib/GraphicsInfoLibVer1.c
@@ -0,0 +1,52 @@
+/** @file
+  Source file for common Graphics Info Lib.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include 
+<Library/GraphicsInfoLib.h> #include <Register/IgdRegs.h> #include 
+<Library/TimerLib.h> #include <Base.h>
+
+/**
+  GetIgdBusNumber: Get IGD Bus Number
+
+  @retval PCI bus number for IGD
+**/
+UINT8
+GetIgdBusNumber (
+  VOID
+  )
+{
+  return (UINT8) IGD_BUS_NUM;
+}
+
+/**
+  GetIgdDevNumber: Get IGD Dev Number
+
+  @retval PCI dev number for IGD
+**/
+UINT8
+GetIgdDevNumber (
+  VOID
+  )
+{
+  return (UINT8) IGD_DEV_NUM;
+}
+
+/**
+  GetIgdFunNumber: Get IGD Fun Number
+
+  @retval PCI fun number for IGD
+**/
+UINT8
+GetIgdFuncNumber (
+  VOID
+  )
+{
+  return (UINT8) IGD_FUN_NUM;
+}
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
new file mode 100644
index 0000000000..ca363ce105
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS
+++ mmGraphicsInfoLib/GraphicsInfoLibVer1.inf
@@ -0,0 +1,33 @@
+## @file
+# Graphics information library.
+#
+# All function in this library is available for PEI, DXE, and SMM, # 
+But do not support UEFI RUNTIME environment call.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGraphicsInfoLib
+FILE_GUID = AE4D5DE8-F092-4B2A-8003-F1A4CCBDC3E4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GraphicsInfoLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+BaseMemoryLib
+PciSegmentLib
+TimerLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+GraphicsInfoLibVer1.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
new file mode 100644
index 0000000000..a9344b424d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
@@ -0,0 +1,116 @@
+/** @file
+  This file provide services for DXE phase Graphics policy default initialization.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Library/DxeGraphicsPolicyLib.h>
+
+/**
+  This function prints the Graphics DXE phase policy.
+
+  @param[in] SaPolicy - SA DXE Policy protocol **/ VOID 
+GraphicsDxePolicyPrint (
+  IN  SA_POLICY_PROTOCOL      *SaPolicy
+  )
+{
+  EFI_STATUS                  Status;
+  GRAPHICS_DXE_CONFIG         *GraphicsDxeConfig;
+
+  //
+  // Get requisite IP Config Blocks which needs to be used here  //  
+ Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, 
+ (VOID *)&GraphicsDxeConfig);  ASSERT_EFI_ERROR (Status);
+
+
+  DEBUG_CODE_BEGIN ();
+  DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE) 
+ print BEGIN -----------------\n"));  DEBUG ((DEBUG_INFO, " Revision : 
+ %d\n", GraphicsDxeConfig->Header.Revision));
+  ASSERT (GraphicsDxeConfig->Header.Revision == 
+ GRAPHICS_DXE_CONFIG_REVISION);  DEBUG ((DEBUG_INFO, 
+ "\n------------------------ Graphics Policy (DXE) print END 
+ -----------------\n"));  DEBUG_CODE_END ();
+
+  return;
+}
+
+
+/**
+  This function Load default Graphics DXE policy.
+
+  @param[in] ConfigBlockPointer    The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+  IN VOID    *ConfigBlockPointer
+  )
+{
+  GRAPHICS_DXE_CONFIG        *GraphicsDxeConfig;
+
+  GraphicsDxeConfig = ConfigBlockPointer;
+
+  ///
+  /// Initialize the Graphics configuration
+  ///
+  GraphicsDxeConfig->PlatformConfig           = 1;
+  GraphicsDxeConfig->AlsEnable                = 2;
+  GraphicsDxeConfig->BacklightControlSupport  = 2;
+  GraphicsDxeConfig->IgdBlcConfig             = 2;
+  GraphicsDxeConfig->GfxTurboIMON             = 31;
+  ///
+  /// <EXAMPLE> Create a static Backlight Brightness Level Duty cycle 
+Mapping Table
+  /// Possible 20 entries (example used 11), each 16 bits as follows:
+  /// [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).
+  ///
+  GraphicsDxeConfig->BCLM[0] = (0x0000 + WORD_FIELD_VALID_BIT);  ///< 
+0%
+  GraphicsDxeConfig->BCLM[1] = (0x0A19 + WORD_FIELD_VALID_BIT);  ///< 
+10%
+  GraphicsDxeConfig->BCLM[2] = (0x1433 + WORD_FIELD_VALID_BIT);  ///< 
+20%
+  GraphicsDxeConfig->BCLM[3] = (0x1E4C + WORD_FIELD_VALID_BIT);  ///< 
+30%
+  GraphicsDxeConfig->BCLM[4] = (0x2866 + WORD_FIELD_VALID_BIT);  ///< 
+40%
+  GraphicsDxeConfig->BCLM[5] = (0x327F + WORD_FIELD_VALID_BIT);  ///< 
+50%
+  GraphicsDxeConfig->BCLM[6] = (0x3C99 + WORD_FIELD_VALID_BIT);  ///< 
+60%
+  GraphicsDxeConfig->BCLM[7] = (0x46B2 + WORD_FIELD_VALID_BIT);  ///< 
+70%
+  GraphicsDxeConfig->BCLM[8] = (0x50CC + WORD_FIELD_VALID_BIT);  ///< 
+80%
+  GraphicsDxeConfig->BCLM[9] = (0x5AE5 + WORD_FIELD_VALID_BIT);  ///< 
+90%
+  GraphicsDxeConfig->BCLM[10] = (0x64FF + WORD_FIELD_VALID_BIT);  ///< 
+100% }
+
+static COMPONENT_BLOCK_ENTRY  mGraphicsDxeIpBlocks = {
+  &gGraphicsDxeConfigGuid, sizeof (GRAPHICS_DXE_CONFIG), 
+GRAPHICS_DXE_CONFIG_REVISION, LoadIgdDxeDefault};
+
+
+/**
+  Get DXE Graphics config block table total size.
+
+  @retval     Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+  VOID
+  )
+{
+  return mGraphicsDxeIpBlocks.Size;
+}
+
+/**
+  GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+  @param[in] ConfigBlockTableAddress    The pointer to add SA config blocks
+
+  @retval EFI_SUCCESS                   The policy default is initialized.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+  IN VOID           *ConfigBlockTableAddress
+  )
+{
+  EFI_STATUS  Status;
+  Status = AddComponentConfigBlocks (ConfigBlockTableAddress, 
+&mGraphicsDxeIpBlocks, 1);
+  return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
new file mode 100644
index 0000000000..0fd6aba0bb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Component description file for the DXE Graphics Policy Init library.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeGraphicsPolicyLib
+FILE_GUID = C6190599-287E-40F9-9B46-EE112A322EBF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = DxeGraphicsPolicyLib
+
+[LibraryClasses]
+BaseMemoryLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+HobLib
+SiConfigBlockLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+DxeGraphicsPolicyLib.c
+
+[Guids]
+gGraphicsDxeConfigGuid
+
+[Pcd]
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
new file mode 100644
index 0000000000..b3c9d28078
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
@@ -0,0 +1,119 @@
+/** @file
+  This is part of the implementation of an Intel Graphics drivers 
+OpRegion /
+  Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+  The code in this file will load the driver and initialize the 
+interface
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Library/DxeIgdOpRegionInitLib.h>
+
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL           mIgdOpRegion;
+
+
+/**
+  Update Graphics OpRegion after PCI enumeration.
+
+  @param[in] void         - None
+  @retval EFI_SUCCESS     - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+  VOID
+)
+{
+  EFI_STATUS                    Status;
+  UINTN                         HandleCount;
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         Index;
+  EFI_PCI_IO_PROTOCOL           *PciIo;
+  PCI_TYPE00                    Pci;
+  UINTN                         Segment;
+  UINTN                         Bus;
+  UINTN                         Device;
+  UINTN                         Function;
+
+  Bus      = 0;
+  Device   = 0;
+  Function = 0;
+
+  DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n"));
+
+  mIgdOpRegion.OpRegion->Header.PCON |= BIT8; //Set External Gfx 
+ Adapter field is valid  mIgdOpRegion.OpRegion->Header.PCON &= (UINT32) 
+ (~BIT7); //Assume No External Gfx Adapter
+
+  ///
+  /// Get all PCI IO protocols handles
+  ///
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiPciIoProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer
+                  );
+
+  if (!EFI_ERROR (Status)) {
+    for (Index = 0; Index < HandleCount; Index++) {
+      ///
+      /// Get the PCI IO Protocol Interface corresponding to each handle
+      ///
+      Status = gBS->HandleProtocol (
+                      HandleBuffer[Index],
+                      &gEfiPciIoProtocolGuid,
+                      (VOID **) &PciIo
+                      );
+
+      if (!EFI_ERROR (Status)) {
+        ///
+        /// Read the PCI configuration space
+        ///
+        Status = PciIo->Pci.Read (
+                              PciIo,
+                              EfiPciIoWidthUint32,
+                              0,
+                              sizeof (Pci) / sizeof (UINT32),
+                              &Pci
+                              );
+
+        ///
+        /// Find the display controllers devices
+        ///
+        if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) {
+          Status = PciIo->GetLocation (
+                            PciIo,
+                            &Segment,
+                            &Bus,
+                            &Device,
+                            &Function
+                            );
+
+          //
+          // Assumption: Onboard devices will be sits on Bus no 0, while external devices will be sits on Bus no > 0
+          //
+          if (!EFI_ERROR (Status) && (Bus > 0)) {
+            //External Gfx Adapter Detected and Available
+            DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected and Available\n"));
+            mIgdOpRegion.OpRegion->Header.PCON |= BIT7;
+            break;
+          }
+        }
+      }
+    }
+  }
+
+  ///
+  /// Free any allocated buffers
+  ///
+  if (HandleBuffer != NULL) {
+    FreePool (HandleBuffer);
+  }
+
+  ///
+  /// Return final status
+  ///
+  return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
new file mode 100644
index 0000000000..e3a56d5563
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the Dxe IGD OpRegion library.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeIgdOpRegionInitLib
+FILE_GUID = 18D47D72-555E-475B-A4E4-AD20C3BD8B15
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = DxeIgdOpRegionInitLib
+
+[LibraryClasses]
+UefiLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+PciSegmentLib
+BaseMemoryLib
+MemoryAllocationLib
+IoLib
+S3BootScriptLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+[Sources]
+DxeIgdOpRegionInit.c
+
+[Guids]
+gGraphicsDxeConfigGuid        ## CONSUMES
+
+[Protocols]
+gIgdOpRegionProtocolGuid               ## PRODUCES
+gSaPolicyProtocolGuid                  ## CONSUMES
+gEfiPciIoProtocolGuid                  ## CONSUMES
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
new file mode 100644
index 0000000000..671e821342
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivat
+++ e/HostBridgeDataHob.h
@@ -0,0 +1,25 @@
+/** @file
+  The GUID definition for Host Bridge Data Hob
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef 
+_HOST_BRIDGE_DATA_HOB_H_ #define _HOST_BRIDGE_DATA_HOB_H_
+
+#include <Base.h>
+
+extern EFI_GUID gHostBridgeDataHobGuid; #pragma pack (push,1)
+
+///
+/// Host Bridge Data Hob
+///
+typedef struct {
+  EFI_HOB_GUID_TYPE        EfiHobGuidType;                       ///< GUID Hob type structure for gSaDataHobGuid
+  UINT8                    EnableAbove4GBMmio;                   ///< 0=Disable above 4GB MMIO resource support, 1=Enable above 4GB MMIO resource support
+  BOOLEAN                  SkipPamLock;                          ///< 0=All PAM registers will be locked in System Agent code, 1=Do not lock PAM registers in System Agent code.
+  UINT8                    Rsvd1[2];                             ///< Reserved for future use
+} HOST_BRIDGE_DATA_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
new file mode 100644
index 0000000000..e2be00fae7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PchPcieRpLibInternal.h
@@ -0,0 +1,20 @@
+/** @file
+  PCIE root port library.
+  All function in this library is available for PEI, DXE, and SMM,
+  But do not support UEFI RUNTIME environment call.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PCIE_RP_LIB_INTERNAL_H_
+#define _PCH_PCIE_RP_LIB_INTERNAL_H_
+
+typedef struct {
+  UINT8 DevNum;
+  UINT8 Pid;
+  UINT8 RpNumBase;
+} PCH_PCIE_CONTROLLER_INFO;
+
+#endif
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
new file mode 100644
index 0000000000..0702792597
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PchPcieRpLibVer2.c
@@ -0,0 +1,71 @@
+/** @file
+  PCIE root port library.
+  All function in this library is available for PEI, DXE, and SMM,
+  But do not support UEFI RUNTIME environment call.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Register/PchRegs.h>
+#include <PchBdfAssignment.h>
+#include <PchPcieRpInfo.h>
+#include <Register/PchPcieRpRegs.h>
+#include <Register/PchPcrRegs.h>
+
+#include "PchPcieRpLibInternal.h"
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_CONTROLLER_INFO 
+mPchPcieControllerInfo[] = {
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1,  PID_SPA,  0 },
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5,  PID_SPB,  4 },
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9,  PID_SPC,  8 },
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13, PID_SPD, 12 },
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17, PID_SPE, 16 }, // PCH-H 
+only
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21, PID_SPF, 20 }  // PCH-H 
+only };
+
+/**
+  Get Pch Pcie Root Port Device and Function Number by Root Port 
+physical Number
+
+  @param[in]  RpNumber              Root port physical number. (0-based)
+  @param[out] RpDev                 Return corresponding root port device number.
+  @param[out] RpFun                 Return corresponding root port function number.
+
+  @retval     EFI_SUCCESS           Root port device and function is retrieved
+  @retval     EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+  IN  UINTN   RpNumber,
+  OUT UINTN   *RpDev,
+  OUT UINTN   *RpFun
+  )
+{
+  UINTN       Index;
+  UINTN       FuncIndex;
+  UINT32      PciePcd;
+
+  if (RpNumber >= GetPchMaxPciePortNum ()) {
+    DEBUG ((DEBUG_ERROR, "GetPchPcieRpDevFun invalid RpNumber %x", RpNumber));
+    ASSERT (FALSE);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Index = RpNumber / PCH_PCIE_CONTROLLER_PORTS;  FuncIndex = RpNumber - 
+ mPchPcieControllerInfo[Index].RpNumBase;
+  *RpDev = mPchPcieControllerInfo[Index].DevNum;
+  PciePcd = PchPcrRead32 (mPchPcieControllerInfo[Index].Pid, 
+ R_SPX_PCR_PCD);  *RpFun = (PciePcd >> (FuncIndex * 
+ S_SPX_PCR_PCD_RP_FIELD)) & B_SPX_PCR_PCD_RP1FN;
+
+  return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
new file mode 100644
index 0000000000..0acafbfc43
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
@@ -0,0 +1,37 @@
+## @file
+# PCIE root port Library.
+#
+# All function in this library is available for PEI, DXE, and SMM, # 
+But do not support UEFI RUNTIME environment call.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcieRpLib
+FILE_GUID = B522981C-E0C5-4E04-A82A-C61D4F0B2C75
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcieRpLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PciSegmentLib
+PchInfoLib
+PchPcrLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchPcieRpLibVer2.c
+
--
2.36.1.windows.1



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