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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: FquT3LRw8NfSF6oxLJmrSzZlx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=iCzTSJTf; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Chinni, Using the FspGlobalDataPointer as a scratchpad for your top of CAR early an= d then putting the real global data into it later is an ugly hack. If you a= re going to initialize the FspGlobalDataPointer in FSP-T, then FSP-T needs = to actually initialize that FSP global data structure fully. Moreover, you have added the assumption that FspGlobalDataPointer is initia= lized to top of CAR to SecFsp.c but you don't actually write top of CAR to = that location in the IA32 version of TempRamInit(), only the X64 version ha= s that addition. Since SecFsp.c is used on both, you have effectively broke= n all 32-bit FSP builds. For obvious reasons, your patch will not be merged= without additional work. Additional feedback below inline. Thanks, Nate > -----Original Message----- > From: Duggapu, Chinni B > Sent: Thursday, February 15, 2024 9:07 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L ; Chiu, Chasel > ; Duggapu, Chinni B > Subject: [PATCH v2] IntelFsp2Pkg: Fsp 2.x Changes >=20 > Changes to support spec changes >=20 > 1. Remove usage of Pcd. > 2. Change code to validate the Temporary Ram size input. > 3. Consume the input saved in YMM Register >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Cc: Chiu Chasel > Cc: Duggapu Chinni B >=20 >=20 > Signed-off-by: Duggapu Chinni B > --- > IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 2 +- > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 2 +- > IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 1 + > .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 1 - > .../FspSecCore/Ia32/FspApiEntryM.nasm | 1 - > .../FspSecCore/Ia32/FspApiEntryT.nasm | 110 ++++++++++++------ > .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 11 ++ > IntelFsp2Pkg/FspSecCore/SecFsp.c | 23 ++-- > IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 4 +- > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 79 +++++++++++-- > IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 6 +- > IntelFsp2Pkg/Include/FspEas/FspApi.h | 5 +- > .../Include/SaveRestoreSseAvxNasm.inc | 21 ++++ > IntelFsp2Pkg/IntelFsp2Pkg.dec | 4 + > .../SecRamInitData.c | 3 +- > 15 files changed, 206 insertions(+), 67 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf b/IntelFsp2Pkg/Fsp= SecCore/Fsp24SecCoreM.inf > index cb011f99f9..cf8cb2eda9 100644 > --- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf > @@ -63,11 +63,11 @@ > =20 > [Pcd] > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUM= ES > - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUM= ES > + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUM= ES > =20 > [Ppis] > gEfiTemporaryRamSupportPpiGuid ## PRODUCE= S > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSe= cCore/FspSecCoreM.inf > index 8029832235..717941c33f 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > @@ -62,11 +62,11 @@ > =20 > [Pcd] > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUM= ES > - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUM= ES > + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUM= ES > =20 > [Ppis] > gEfiTemporaryRamSupportPpiGuid ## PRODUCE= S > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf b/IntelFsp2Pkg/FspSe= cCore/FspSecCoreT.inf > index e5a6eaa164..05c0d5f48b 100644 > --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf > @@ -51,6 +51,7 @@ > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUM= ES > gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUM= ES > + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUM= ES > =20 > [Ppis] > gEfiTemporaryRamSupportPpiGuid ## PRODUCE= S > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2= Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm > index 15f8ecea83..5fa5c03569 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm > @@ -11,7 +11,6 @@ > ; Following are fixed PCDs > ; > extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) > -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) > extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) > extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) > =20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/FspApiEntryM.nasm > index 61ab4612a3..861cce4d01 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > @@ -11,7 +11,6 @@ > ; Following are fixed PCDs > ; > extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) > -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) > extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) > extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) > =20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/FspApiEntryT.nasm > index 900126b93b..2f8465df3d 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > @@ -109,7 +109,8 @@ struc LoadMicrocodeParamsFsp24 > .FsptArchReserved: resb 3 > .FsptArchLength: resd 1 > .FspDebugHandler resq 1 > - .FsptArchUpd: resd 4 > + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison= is >=3D 3 > + .FsptArchUpd: resd 3 > ; } > ; FSPT_CORE_UPD { > .MicrocodeCodeAddr: resq 1 > @@ -178,29 +179,6 @@ endstruc > jmp ebp ; restore EIP from EBP > %endmacro > =20 > -; > -; Load UPD region pointer in ECX > -; > -global ASM_PFX(LoadUpdPointerToECX) > -ASM_PFX(LoadUpdPointerToECX): > - ; > - ; esp + 4 is input UPD parameter > - ; If esp + 4 is NULL the default UPD should be used > - ; ecx will be the UPD region that should be used > - ; > - mov ecx, dword [esp + 4] > - cmp ecx, 0 > - jnz ParamValid > - > - ; > - ; Fall back to default UPD region > - ; > - CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack) > - mov ecx, DWORD [eax + 01Ch] ; Read FsptImageBaseAddress > - add ecx, DWORD [eax + 024h] ; Get Cfg Region base address = =3D FsptImageBaseAddress + CfgRegionOffset > -ParamValid: > - RET_EBP > - > ; > ; @todo: The strong/weak implementation does not work. > ; This needs to be reviewed later. > @@ -267,7 +245,7 @@ ASM_PFX(LoadMicrocodeDefault): > cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 > jb Fsp20UpdHeader > cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 > - je Fsp24UpdHeader > + jae Fsp24UpdHeader > jmp Fsp22UpdHeader > =20 > Fsp20UpdHeader: > @@ -405,7 +383,7 @@ CheckAddress: > cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 > jb Fsp20UpdHeader1 > cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 > - je Fsp24UpdHeader1; > + jae Fsp24UpdHeader1; > jmp Fsp22UpdHeader1 > =20 > Fsp20UpdHeader1: > @@ -497,7 +475,8 @@ ASM_PFX(EstablishStackFsp): > ; Enable FSP STACK > ; > mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] > - add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))] > + LOAD_TEMPORARY_RAM_SIZE eax > + add esp, eax > =20 > push DATA_LEN_OF_MCUD ; Size of the data region > push 4455434Dh ; Signature of the data region 'MCUD' > @@ -506,7 +485,7 @@ ASM_PFX(EstablishStackFsp): > cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], = 2 > jb Fsp20UpdHeader2 > cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 > - je Fsp24UpdHeader2 > + jae Fsp24UpdHeader2 > jmp Fsp22UpdHeader2 > =20 > Fsp20UpdHeader2: > @@ -554,12 +533,13 @@ ContinueAfterUpdPush: > ; > ; Set ECX/EDX to the BootLoader temporary memory range > ; > - mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] > - mov edx, ecx > - add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))] > + mov edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] > + LOAD_TEMPORARY_RAM_SIZE ecx > + add edx, ecx > sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))] > + mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] > =20 > - cmp ecx, edx ;If PcdFspReservedBufferSize >=3D PcdTempora= ryRamSize, then error. > + cmp ecx, edx ;If PcdFspReservedBufferSize >=3D TemporaryR= amSize, then error. > jb EstablishStackFspSuccess > mov eax, 80000003h ;EFI_UNSUPPORTED > jmp EstablishStackFspExit > @@ -589,6 +569,30 @@ ASM_PFX(TempRamInitApi): > ; > SAVE_REGS > =20 > + ; > + ; > + ; Read Fsp Info header and save in esi > + ; > + CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack) > + xor esi, esi > + mov esi, eax > + ; > + ; esp + 4 is input UPD parameter > + ; If esp + 4 is NULL the default UPD should be used > + ; ecx will be the UPD region that should be used > + ; > + mov ecx, dword [esp + 4] > + cmp ecx, 0 > + jnz ParamValid > + > + ; > + ; Fall back to default UPD region > + ; > + xor ecx, ecx > + mov ecx, DWORD [esi + 01Ch] ; Read FsptImageBaseAddress > + add ecx, DWORD [esi + 024h] ; Get Cfg Region base address = =3D FsptImageBaseAddress + CfgRegionOffset > +ParamValid: > + SAVE_ECX What is the reason for removing the LoadUpdPointerToECX function and puttin= g the equivalent logic inline? > ; > ; Save timestamp into XMM6 > ; > @@ -596,9 +600,47 @@ ASM_PFX(TempRamInitApi): > SAVE_EAX > SAVE_EDX > =20 > - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param > - SAVE_ECX ; save UPD param to slot 3 in x= mm6 > + mov edx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > + mov edx, DWORD [edx] > + ; > + ; Read ARCH2 UPD input value. > + ; > + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSi= ze] > + ; > + ; As per spec, if Bootloader pass zero, use Fsp defined Size > + ; Irrespective of whether this UPD is supported or not, Fallback > + ; to Fsp defined size if input is zero. > + ; > + cmp ebx, 0 > + jz UseTemporaryRamSizePcd > =20 > + xor eax, eax > + mov ax, WORD [esi + 020h] ; Read ImageAttribute > + test ax, 16 ; check if Bit4 is set > + jnz ConsumeInputConfiguration > + ; > + ; Sometimes user may change input value even if it is not supported > + ; return error if input is Non-Zero and not same as PcdTemporaryRamSiz= e. > + ; > + cmp ebx, edx > + je UseTemporaryRamSizePcd > + mov eax, 080000002h ; RETURN_INVALID_PARAMETER > + jmp TempRamInitExit > +ConsumeInputConfiguration: > + ; > + ; Read Fsp Arch2 revision > + ; > + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3 > + jb UseTemporaryRamSizePcd > + ; > + ; Read ARCH2 UPD value and Save. > + ; > + SAVE_TEMPORARY_RAM_SIZE ebx > + jmp GotTemporaryRamSize > +UseTemporaryRamSizePcd: > + SAVE_TEMPORARY_RAM_SIZE edx > +GotTemporaryRamSize: > + LOAD_ECX > ; > ; Sec Platform Init > ; > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelF= sp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > index 016f943b43..4d6ec1e984 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > @@ -128,6 +128,17 @@ > SXMMN xmm5, 1, eax > %endmacro > =20 > +; > +; XMM5 slot 2 for TemporaryRamSize > +; > +%macro LOAD_TEMPORARY_RAM_SIZE 1 > + LXMMN xmm5, %1, 2 > + %endmacro > + > +%macro SAVE_TEMPORARY_RAM_SIZE 1 > + SXMMN xmm5, 2, %1 > + %endmacro > + > %macro ENABLE_SSE 0 > ; > ; Initialize floating point units > diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/S= ecFsp.c > index 11be1f97ca..0c74e533a4 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c > @@ -47,11 +47,11 @@ FspGetExceptionHandler ( > VOID > EFIAPI > SecGetPlatformData ( > - IN OUT FSP_GLOBAL_DATA *FspData > + IN OUT FSP_GLOBAL_DATA *FspData, > + IN UINTN TopOfCar > ) > { > FSP_PLAT_DATA *FspPlatformData; > - UINT32 TopOfCar; > UINT32 *StackPtr; > UINT32 DwordSize; > =20 > @@ -68,11 +68,11 @@ SecGetPlatformData ( > FspPlatformData->CodeRegionBase =3D 0; > FspPlatformData->CodeRegionSize =3D 0; > =20 > - // > - // Pointer to the size field > - // > - TopOfCar =3D PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRa= mSize); > - StackPtr =3D (UINT32 *)(TopOfCar - sizeof (UINT32)); > + if (TopOfCar =3D=3D 0) { > + return; > + } > + > + StackPtr =3D (UINT32 *)((UINT32)TopOfCar - sizeof (UINT32)); > =20 > if (*(StackPtr - 1) =3D=3D FSP_MCUD_SIGNATURE) { > while (*StackPtr !=3D 0) { > @@ -123,7 +123,14 @@ FspGlobalDataInit ( > VOID *FspmUpdDataPtr; > CHAR8 ImageId[9]; > UINTN Idx; > + UINTN *TopOfCar; > =20 > + // > + // If TempRam is initilized using FspTempRamInitApi (), GlobalDataPoin= ter > + // will point to the Top of the Car and any Data that FspTempRamInitAp= i > + // wants to Handoff to later stages will be pushed on to the Top of th= e car. > + // > + TopOfCar =3D *(VOID **)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress); There are some customers that do not run FSP-T. The assumption that this wi= ll be initialized to the TopOfCar during FSP-T would not hold on those plat= forms. > // > // Set FSP Global Data pointer > // > @@ -147,7 +154,7 @@ FspGlobalDataInit ( > // It may have multiple FVs, so look into the last one for FSP header > // > PeiFspData->FspInfoHeader =3D (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoH= eader (); > - SecGetPlatformData (PeiFspData); > + SecGetPlatformData (PeiFspData, (UINTN)TopOfCar); > =20 > // > // Set API calling mode > diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSec= Core/SecFspApiChk.c > index 5f59938518..33aaac66c1 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > @@ -42,9 +42,7 @@ FspApiCallingCheck ( > // > // FspMemoryInit check > // > - if (((UINTN)FspData !=3D MAX_ADDRESS) && ((UINTN)FspData !=3D MAX_UI= NT32)) { > - Status =3D EFI_UNSUPPORTED; > - } else if (ApiParam =3D=3D NULL) { One cannot assume that FspGlobalDataPointer gets initialized by FSP-T as me= ntioned above. > + if (ApiParam =3D=3D NULL) { > Status =3D EFI_SUCCESS; > } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) { > Status =3D EFI_INVALID_PARAMETER; > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg= /FspSecCore/X64/FspApiEntryT.nasm > index 698bb063a7..c2b7b25b36 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm > @@ -16,6 +16,7 @@ > extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) > extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) > +extern ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress)) > =20 > ; > ; Following functions will be provided in PlatformSecLib > @@ -76,7 +77,8 @@ struc LoadMicrocodeParamsFsp24 > .FsptArchReserved: resb 3 > .FsptArchLength: resd 1 > .FspDebugHandler resq 1 > - .FsptArchUpd: resd 4 > + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison = is >=3D 3 > + .FsptArchUpd: resd 3 > ; } > ; FSPT_CORE_UPD { > .MicrocodeCodeAddr: resq 1 > @@ -163,7 +165,7 @@ ASM_PFX(LoadMicrocodeDefault): > cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2 > jb ParamError > cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2 > - jne ParamError > + jb ParamError > =20 > ; UPD structure is compliant with FSP spec 2.4 > mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] > @@ -273,7 +275,7 @@ CheckAddress: > cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2 > jb ParamError > cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2 > - jne ParamError > + jb ParamError > =20 > ; UPD structure is compliant with FSP spec 2.4 > ; Is automatic size detection ? > @@ -337,9 +339,16 @@ ASM_PFX(EstablishStackFsp): > ; > mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) > mov esp, DWORD[rax] > - mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > - add esp, DWORD[rax] > - > + LOAD_TEMPORARY_RAM_SIZE rax > + add esp, eax > + ; > + ; Save top of the TemporaryRam in PcdGlobalDataPointerAddress > + ; where the FspTempRamInitAPI information is pushed as part of below c= ode > + ; which will be used in other Fsp APIs to retrive the same. > + ; > + mov rax, ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress)) > + mov eax, DWORD[rax] > + mov DWORD[eax], esp Using the FspGlobalDataPointer as a scratchpad for your top of CAR early an= d then putting the real global data into it later is an ugly hack. If you a= re going to initialize the FspGlobalDataPointer in FSP-T, then FSP-T needs = to actually initialize that FSP global data structure fully. > sub esp, 4 > mov dword[esp], DATA_LEN_OF_MCUD ; Size of the data region > sub esp, 4 > @@ -349,7 +358,7 @@ ASM_PFX(EstablishStackFsp): > cmp byte [rdx + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], = 2 > jb ParamError1 > cmp byte [rdx + LoadMicrocodeParamsFsp24.FsptArchRevision], 2 > - je Fsp24UpdHeader > + jnb Fsp24UpdHeader > =20 > ParamError1: > mov rax, 08000000000000002h > @@ -397,8 +406,8 @@ ContinueAfterUpdPush: > ; > mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) > mov edx, [ecx] > - mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > - add edx, [ecx] > + LOAD_TEMPORARY_RAM_SIZE rcx > + add edx, ecx > mov rcx, ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) > sub edx, [ecx] > mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) > @@ -439,6 +448,12 @@ ASM_PFX(TempRamInitApi): > ; > SAVE_BFV rbp > =20 > + ; > + ; Read Fsp Info header and save in rsi > + ; > + CALL_RDI ASM_PFX(AsmGetFspInfoHeaderNoStack) > + xor rsi, rsi > + mov rsi, rax > ; > ; Save Input Parameter in YMM10 > ; > @@ -448,10 +463,9 @@ ASM_PFX(TempRamInitApi): > ; > ; Fall back to default UPD > ; > - CALL_RDI ASM_PFX(AsmGetFspInfoHeaderNoStack) > xor rcx, rcx > - mov ecx, DWORD [rax + 01Ch] ; Read FsptImageBaseAddress > - add ecx, DWORD [rax + 024h] ; Get Cfg Region base address = =3D FsptImageBaseAddress + CfgRegionOffset > + mov ecx, DWORD [rsi + 01Ch] ; Read FsptImageBaseAddress > + add ecx, DWORD [rsi + 024h] ; Get Cfg Region base address = =3D FsptImageBaseAddress + CfgRegionOffset > ParamValid: > SAVE_RCX > =20 > @@ -463,6 +477,47 @@ ParamValid: > or rax, rdx > SAVE_TS rax > =20 > + mov rdx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > + mov edx, DWORD [rdx] > + ; > + ; Read ARCH2 UPD input value. > + ; > + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSi= ze] > + ; > + ; As per spec, if Bootloader pass zero, use Fsp defined Size > + ; Irrespective of whether this UPD is supported or not, Fallback > + ; to Fsp defined size if input is zero. > + ; > + cmp ebx, 0 > + jz UseTemporaryRamSizePcd > + > + xor rax, rax > + mov ax, WORD [rsi + 020h] ; Read ImageAttribute > + test ax, 16 ; check if Bit4 is set > + jnz ConsumeInputConfiguration > + ; > + ; Sometimes user may change input value even if it is not supported > + ; return error if input is Non-Zero and not same as PcdTemporaryRamSiz= e. > + ; > + cmp ebx, edx > + je UseTemporaryRamSizePcd > + mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER > + jmp TempRamInitExit > +ConsumeInputConfiguration: > + ; > + ; Read Fsp Arch2 revision > + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3 > + jb UseTemporaryRamSizePcd > + ; > + ; Read ARCH2 UPD value and Save. > + ; Only low-32 bits of rbx/rdx holds the temporary ram size. > + ; > + SAVE_TEMPORARY_RAM_SIZE rbx > + jmp GotTemporaryRamSize > +UseTemporaryRamSizePcd: > + SAVE_TEMPORARY_RAM_SIZE rdx > + > +GotTemporaryRamSize: > ; > ; Sec Platform Init > ; > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/Fs= pSecCore/X64/FspHelper.nasm > index 32a60270b8..61ebaa8ccf 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > @@ -28,7 +28,7 @@ ASM_PFX(FspInfoHeaderRelativeOff): > global ASM_PFX(AsmGetFspInfoHeaderNoStack) > ASM_PFX(AsmGetFspInfoHeaderNoStack): > lea rax, [ASM_PFX(AsmGetFspInfoHeader)] > - lea rcx, [ASM_PFX(FspInfoHeaderRelativeOff)] > - mov ecx, [rcx] > - sub rax, rcx > + lea rsi, [ASM_PFX(FspInfoHeaderRelativeOff)] > + mov esi, [rsi] > + sub rax, rsi > jmp rdi > diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/= FspEas/FspApi.h > index 40e063e944..27d5ec3a3c 100644 > --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h > +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h > @@ -139,7 +139,7 @@ typedef struct { > /// > typedef struct { > /// > - /// Revision of the structure is 2 for this version of the specificati= on. > + /// Revision of the structure is 3 for this version of the specificati= on. > /// > UINT8 Revision; > UINT8 Reserved[3]; > @@ -152,7 +152,8 @@ typedef struct { > /// occurring during FSP execution. > /// > EFI_PHYSICAL_ADDRESS FspDebugHandler; > - UINT8 Reserved1[16]; > + UINT32 FspTemporaryRamSize; > + UINT8 Reserved1[12]; > } FSPT_ARCH2_UPD; > =20 > /// > diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pk= g/Include/SaveRestoreSseAvxNasm.inc > index 002a5a1412..2168564e6d 100644 > --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc > @@ -201,6 +201,27 @@ > movq rcx, xmm5 > %endmacro > =20 > +; > +; Save TemporaryRamSize to YMM10[192:255] > +; arg 1:general purpose register which holds TemporaryRamSize > +; Modified: XMM5 and YMM10[192:255] > +; > +%macro SAVE_TEMPORARY_RAM_SIZE 1 > + LYMMN ymm10, xmm5, 1 > + SXMMN xmm5, 1, %1 > + SYMMN ymm10, 1, xmm5 > + %endmacro > + > +; > +; Restore TemporaryRamSize from YMM10[192:255] > +; arg 1:general purpose register where to save TemporaryRamSize > +; Modified: XMM5 and %1 > +; > +%macro LOAD_TEMPORARY_RAM_SIZE 1 > + LYMMN ymm10, xmm5, 1 > + LXMMN xmm5, %1, 1 > + %endmacro > + > ; > ; YMM7[128:191] for calling stack > ; arg 1:Entry > diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.de= c > index d1c3d3ee7b..47ced1759e 100644 > --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec > +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec > @@ -85,6 +85,10 @@ > gFspEventEndOfFirmwareGuid =3D { 0xbd44f629, 0xeae7, 0x4198= , { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } } > =20 > [PcdsFixedAtBuild] > + # > + # As part of FSP-T execution, this will be initialized to TopOfCar add= ress where Fsp T data will be saved. > + # Once Fsp Global Data is initialed later in FSP-M, this will hold the= Global data buffer address. > + # > gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UI= NT32|0x00000001 > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UI= NT32|0x10001001 > gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UI= NT32|0x10001002 > diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSampl= e/SecRamInitData.c b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLi= bSample/SecRamInitData.c > index fb0d9a8683..316c2fa86a 100644 > --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRa= mInitData.c > +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRa= mInitData.c > @@ -49,8 +49,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA = FsptUpdDataPtr =3D { > }, > 0x00000020, > 0x00000000, > + 0x00000000, > { > - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > } > }, > --=20 > 2.39.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#115897): https://edk2.groups.io/g/devel/message/115897 Mute This Topic: https://groups.io/mt/104388042/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-