From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id D7611740034 for ; Thu, 1 Feb 2024 00:11:02 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=3/0ULe/Vmn5mmpzwH35RFileLVognHZWXuEpqV0uFAw=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1706746261; v=1; b=XGh7VcCzj7D1Bb3arKl9eh6lnc0nr0fmvfg6UeUDSxMUAoAm8+viKQrByemU30tOvo4ROIK9 9q6b3XkUEZsAF34hWW4jwxwziHADyT3VrNB2TrQu1KHyQzR35gfpgarQWtv61MSGFoSKF36yxBR Zj1kWib7ZQEEkcVTThMqAPuo= X-Received: by 127.0.0.2 with SMTP id kqi8YY7687511xu7g4FmIveM; Wed, 31 Jan 2024 16:11:01 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.4030.1706746259744051413 for ; Wed, 31 Jan 2024 16:11:00 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10969"; a="467997008" X-IronPort-AV: E=Sophos;i="6.05,233,1701158400"; d="scan'208";a="467997008" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2024 16:10:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10969"; a="908068201" X-IronPort-AV: E=Sophos;i="6.05,233,1701158400"; d="scan'208";a="908068201" X-Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by fmsmga002.fm.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 31 Jan 2024 16:10:30 -0800 X-Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 31 Jan 2024 16:10:29 -0800 X-Received: from fmsmsx602.amr.corp.intel.com (10.18.126.82) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 31 Jan 2024 16:10:29 -0800 X-Received: from FMSEDG603.ED.cps.intel.com (10.1.192.133) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Wed, 31 Jan 2024 16:10:29 -0800 X-Received: from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.168) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Wed, 31 Jan 2024 16:10:28 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YGVQTuJA/KqY2QAZmChGRvcpt3cE+DYAE/cphsHs/qLJO2ZcSnocr+JSDlGc00c5Z8m/cHzL7GcCWEod483iXMujLWoF3+mE3pL0KfSbRInyMQ83o73ran0CJYNidIz+TazMEWxxZUEqX5qxYJlE8j2Iz3t1pk2NdVT/VWdDnFvEhp38tZDPaCBol7gsoVJXJOdbHcQg9Oiv/XlFz3WgwylKdU+qBuwyG2BjANtsWpNIpXQKV7gnFOjpRJLh3flwgygLrQU30Lfe4MC/dsYEYbdqm4LDveT4ASep/WXHjcWnz639dUnB4d2nkT43STT/1Uhu9oWcL7b9TKXxfIuGNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OkKTmgPrg6QMfxdaCtR3ZGEml3ygFl+fPgLZ2eVZqOs=; b=Wkh+ic3GNVGpWq6MCMGrxi5S9fBiky8WTqlc3bezSd5fSf1g8nfLqVqCZnyz1ps0+jdlGeIBL+hzS8OQf1aY7c4fOk7znsKubR7ts2VY4AWNGdoma3F8LN/HN6g8Duwbzz7e2GqlvzrTpx2LuThFdkYL7tw/a2z2EKArQw8zygmU4IQo3JQ8KVsupaTlnMJWMQ9M65OzQgJL0hRcm0U53s8sr2KLZlLuLKp8KYGl33sjTRN9MUJGwCl9ON7Qknb7MuKX4dYb+GVgfhLVAxypzYcXGpYTI0u/Mk1fpj3bsB9yOXdiO5tlkzruhEE6nNBCf+xtK5n/q8oAy6i9tv1qmQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from MW4PR11MB5821.namprd11.prod.outlook.com (2603:10b6:303:184::5) by BL3PR11MB6339.namprd11.prod.outlook.com (2603:10b6:208:3b3::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.32; Thu, 1 Feb 2024 00:10:25 +0000 X-Received: from MW4PR11MB5821.namprd11.prod.outlook.com ([fe80::7d4f:b2b0:e284:aeff]) by MW4PR11MB5821.namprd11.prod.outlook.com ([fe80::7d4f:b2b0:e284:aeff%5]) with mapi id 15.20.7249.024; Thu, 1 Feb 2024 00:10:25 +0000 From: "Nate DeSimone" To: "Kuo, Ted" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Dong, Eric" , "S, Ashraf Ali" , "Duggapu, Chinni B" , Liming Gao Subject: Re: [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64 Thread-Topic: [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64 Thread-Index: AQHaU+ti4xEOxGeZ9UCP0ePsqcSyu7D0ni/A Date: Thu, 1 Feb 2024 00:10:24 +0000 Message-ID: References: <72fdc320f044cc7576e19ec3e3463450eadc2a33.1706667131.git.ted.kuo@intel.com> In-Reply-To: <72fdc320f044cc7576e19ec3e3463450eadc2a33.1706667131.git.ted.kuo@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW4PR11MB5821:EE_|BL3PR11MB6339:EE_ x-ms-office365-filtering-correlation-id: cc81c45a-fb83-45b1-2efd-08dc22ba303f x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: LgnEKFhUA8JJY/9FSOFcYIFb167Vr5EihsuGeeA2jxXl9xrW3oGoSp6PALOCqetysoGkl2Ye4SBzqf1ygBG8vWaf46aMjzv3kNBVtB7VxLjUZAWJEjozKCzkDb3LQXKG2BAJ9Q6tyM7A6j1TgwD1TCj7ulm2njtAsMDJaJFFJLA0YADCDMt7MqO5DzSdWLfb1d6+K3HcEl8S5nq4mpbxnb6ch1pU9JZKaXgdQYh5lX8YFG/h75guZNs1En/lyJksBf0tebSQa/IACYDRN87AkGzwV0VguKY6peGmO1/8NJ5SWDqIv3Q9W0zD6BihL9sVyc8IdesQbOQ+fX9SMA+Ben53OUhyNpKii3d7TGffKwDdWwnQqFXkadb5tkWwAZmJG2V/HZxDKxnYgcKHfocRgDy28804JkpSLBrJjepPihnq40YduS/A8recYd78UsB4yzttjv6nayYN2iySfc7UoagYoSMIoAVWRJpEMqUceTtQvxNWYwJx4e3kRUeGCpWcVwXYqTm/LZIZjxhcGiS68xrg+GbvQ2lxA7mJrWkbZ9nj4SvqQmdo5UE+Ylpy8LvXxhO+Rh2a9ZWt+11UWVzqQg+cYvNtp96rgH7JtT0kBUFpazcSopw0VVFeHJ7b1I0y4XrDBf+rlGTDHdb4jrtyqc6gIB0YLQo2Fal+dy4DNBimVVUhUbwjAU0G4qNGPV8Mk8ltOld0ECpdjN0GNBPPog== x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?DRgXFD7TR8CFhRflK6fWWvsZslIziKOnH21FRWGTVdk2tcIF34IAIqBRZ1V7?= =?us-ascii?Q?G2OyOePlTh7FO4opo4AWMpQxVPgaBehZMnpveCJDTCSp0h3bug3NUCVu0tkN?= =?us-ascii?Q?yeFH+hPzXHhkUxO8aW5zoJ9Z9QL3fw2/yn6R09rgCEulpZmd7+C9ZffscMXH?= =?us-ascii?Q?OUzkns/FPLabqEMocdLRUeo/gFKDWNJHvVGadKaPdqe90Mm3FKuoNXYLhBFe?= =?us-ascii?Q?yFRfqa88oUxrew1TyKsMiN3ZFBrWnnq+s1guqsEly31+TK7LtZC2Rsl6Jc5e?= =?us-ascii?Q?94aBBFXMZqD6/jaeBR/V4vCNZlWTaZgFqlrFga6aTd8lQdoOp6yKKoXYLxGF?= =?us-ascii?Q?Gvo3ObN7AU3x4fEYaY68Zk43tpTu48/cKyes7Jhx506jM+kXO1l3f547jy/g?= =?us-ascii?Q?MahRPC2yJBN4Dd9bBvG0j9qVWFzu9fR3wO4fpyz+IWdjGlNUX3FObiAtCQK0?= =?us-ascii?Q?4xJEDDkezWQ4KEuYYLh056CRTSNeBPh2zDz/uzGR7v5PzSLDD3IJnImB8ohi?= =?us-ascii?Q?pGIZgnsaCcSX8Zv2rqcMtq33x3ce6D2qjnA+ayExk5xI8SER7BzT0eMs5AM5?= =?us-ascii?Q?1j+1gxU40LRJO7gd82CzE6roEvy9p6kijlKxomaT//wu4FvMJl1IbLR7HoG3?= =?us-ascii?Q?/X8xgF97gBYTpgi1vTSs6m/D9qIxfBYAJKreA/nE9J4GyCPlOTocgy07ILDG?= =?us-ascii?Q?gbtE2N8zp3BwFiERdovQQfBfiXYCBGcpJSU5NJuFjUV/q4dz8TumAvnqfVu+?= =?us-ascii?Q?uAFMC+bdehpQCvNVDCN3A8tiTRABXm56bnoDn+VkfFHtlcOxNBOcFjQJ2W0m?= =?us-ascii?Q?M1/BuX88/h/iBr2sPCnmV4b52ghFQx8NQJ0UfGN1onDc1AM9y3XZhEMv5OmY?= =?us-ascii?Q?+Akevuvzgt79XwFwIzCeb+NfZUWgfYwwftYPav+IZVqpMO1mUUeGL7qPcvy/?= =?us-ascii?Q?lp8OMfuDVp1Qg6g6OBWJhv79V81w5EvnMwdGoosRWxbMRz7yWejo+820bv88?= =?us-ascii?Q?3G+dpVNJcusotkEHFAVRMgNqNnq/NfyBkNlN9xdUp6afRHHbXvEPk0RM800E?= =?us-ascii?Q?ZYjyTPRvvCAPL7I9e/Ia+k6J/YfnwwlAc9UFzSkguXRjchiE7fzmr06HFzUp?= =?us-ascii?Q?hidqi5tc3YZ/n51mzI4r857B3LheNaHap+ElNk8HaHYwXLIUm2BwB+1P/P+r?= =?us-ascii?Q?5lQ7sJDZztHKd1/eut+hF9SMOpf3OCmegpDtEfZ4m8+FxJwgx5ijVRwdosN3?= =?us-ascii?Q?sXRp7pFLkCwGgsOMwyEM0O6XGRl+8SKLt593di+NVrKYApbDyk1lS6uw3q5h?= =?us-ascii?Q?cSOTsHDrpveJD/IGRNizN6GlG6p9WNIsXMqd4DtiezWjlPOhlsPKl+ozJTQF?= =?us-ascii?Q?BcEpYcyehBevNdfbNHBd5A8Ykubh0TE/eEUyOhl2nU+QJ8SHzvVysqXldBrO?= =?us-ascii?Q?WLlacYrxeDFT9lFxO6wng8cJfnZGr6BXGuxkdI0crN8ttTykLaULO8bD8PHM?= =?us-ascii?Q?6z54nBZsTz1BWaZsFpYAOpkQLnxivBobVde8/9eHVuew41yiPxCRLEBeQ7U8?= =?us-ascii?Q?hKWtAuA4upm/S1rOW0KtpBuLcll7Quevyfurr99rHTuHInEQhNLCH/L8iYYu?= =?us-ascii?Q?0A=3D=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW4PR11MB5821.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cc81c45a-fb83-45b1-2efd-08dc22ba303f X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Feb 2024 00:10:24.7909 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7FAXcFPG25Wb2qXIijQr53WgT1ab1JmcUPQA+vCBvNqsDnNBgvE08nlPb+YmjRidZJhph4+wthb/cydHcIYdqIlG7l2PY6u54LNiKyWY1Mo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR11MB6339 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 5dWoON6tJcv0cLeg4wZzJysbx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=XGh7VcCz; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Nate DeSimone > -----Original Message----- > From: Kuo, Ted > Sent: Tuesday, January 30, 2024 6:15 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Chiu, Chasel > ; Desimone, Nathaniel L > ; Dong, Eric ; S, > Ashraf Ali ; Duggapu, Chinni B > ; Liming Gao > Subject: [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support > SecFspWrapperPlatformSecLib in X64 >=20 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D4623 > 1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64. > 2.Made changes in common files to support both IA32 and X64. > 3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP. > - PcdFspWrapperResetVectorInFsp > - PcdFspWrapperBfvforResetVectorInFsp > - PcdFsptUpdHeaderRevision > - PcdFsptArchUpdRevision >=20 > Cc: Sai Chaganty > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Eric Dong > Cc: Ashraf Ali S > Cc: Chinni B Duggapu > Cc: Liming Gao > Signed-off-by: Ted Kuo > --- > .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++- > .../Ia32/SecEntry.nasm | 4 +- > .../SecFspWrapperPlatformSecLib.inf | 12 +- > .../SecGetPerformance.c | 11 +- > .../SecPlatformInformation.c | 8 +- > .../SecRamInitData.c | 77 +++++-- > .../X64/PeiCoreEntry.nasm | 207 ++++++++++++++++++ > .../X64/SecEntry.nasm | 199 +++++++++++++++++ > .../X64/Stack.nasm | 72 ++++++ > .../Ia32 =3D> Include}/Fsp.h | 6 +- > .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 23 +- > 11 files changed, 612 insertions(+), 32 deletions(-) create mode 100644 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform > SecLib/X64/PeiCoreEntry.nasm > create mode 100644 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform > SecLib/X64/SecEntry.nasm > create mode 100644 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform > SecLib/X64/Stack.nasm > rename > Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32 =3D> Include}/Fsp.h (79%) >=20 > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/FsptCoreUpd.h > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/FsptCoreUpd.h > index 7c0f605b92..24c18f25b8 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/FsptCoreUpd.h > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/FsptCoreUpd.h > @@ -1,6 +1,6 @@ > /** @file -Copyright (c) 2017, Intel Corporation. All rights > reserved.
+Copyright (c) 2017 - 2024, Intel Corporation. All rights > reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6 > +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #pragma pack(1) +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <=3D 1 /** F= sp T > Core UPD **/ typedef struct {@@ -34,6 +35,28 @@ typedef struct { > **/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#else+/= ** Fsp T > Core UPD+**/+typedef struct {++/** Offset 0x0040+**/+ > EFI_PHYSICAL_ADDRESS MicrocodeRegionBase;++/** Offset 0x0048+**/+ > UINT64 MicrocodeRegionSize;++/** Offset 0x0050+**/+ > EFI_PHYSICAL_ADDRESS CodeRegionBase;++/** Offset 0x0058+**/+ > UINT64 CodeRegionSize;+} FSPT_CORE_UPD;+#endif #pra= gma > pack() diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/SecEntry.nasm > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/Ia32/SecEntry.nasm > index 7f6d771e41..0b3f343991 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/SecEntry.nasm > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/Ia32/SecEntry.nasm > @@ -1,6 +1,6 @@ > ;-----------------------------------------------------------------------= ------- ;-; > Copyright (c) 2019, Intel Corporation. All rights reserved.
+; Copyrig= ht (c) > 2019 - 2024, Intel Corporation. All rights reserved.
; SPDX-License- > Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@ ; ;---= --- > ------------------------------------------------------------------------ = -#include > "Fsp.h"+#include SECTION .text diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecFspWrapperPlatformSecLib.inf > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecFspWrapperPlatformSecLib.inf > index 2e0d67eae4..e85243c6e3 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecFspWrapperPlatformSecLib.inf > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/SecFspWrapperPlatformSecLib.inf > @@ -1,7 +1,7 @@ > ## @file # Provide FSP wrapper platform sec related function. #-# Copy= right > (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright= (c) > 2017 - 2024, Intel Corporation. All rights reserved.
# # SPDX-License= - > Identifier: BSD-2-Clause-Patent #@@ -47,7 +47,11 @@ > Ia32/SecEntry.nasm Ia32/PeiCoreEntry.nasm Ia32/Stack.nasm- > Ia32/Fsp.h++[Sources.X64]+ X64/SecEntry.nasm+ X64/PeiCoreEntry.nasm+ > X64/Stack.nasm > ################################################################### > ############# #@@ -96,3 +100,7 @@ > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## > CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection > ## CONSUMES > gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## > CONSUMES+ > gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp ## > CONSUMES+ > gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp ## > CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision > ## CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision > ## CONSUMESdiff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecGetPerformance.c > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecGetPerformance.c > index ac2deeabec..1699bd9710 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecGetPerformance.c > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/SecGetPerformance.c > @@ -1,7 +1,7 @@ > /** @file Sample to provide SecGetPerformance function. -Copyright (c) > 2017 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 20= 17 - > 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier= : BSD- > 2-Clause-Patent **/@@ -58,6 +58,7 @@ SecGetPerformance ( > if (EFI_ERROR (Status)) { return EFI_NOT_FOUND; }+ // // |--= ------------| > <- TopOfTemporaryRam - BL // | List Ptr |@@ -77,12 +78,12 @@ > SecGetPerformance ( > // | TSC[31:00] | // |--------------| //- TopOfTemporaryRam =3D= (UINTN) > TopOfTemporaryRamPpi - sizeof (UINT32);- TopOfTemporaryRam -=3D sizeof > (UINT32) * 2;- Count =3D *(UINT32 *)(TopOfTemporaryRam - siz= eof > (UINT32));+ TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof > (UINTN);+ TopOfTemporaryRam -=3D sizeof(UINTN) * 2;+ Count = =3D > *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32)); Size = =3D > Count * sizeof (UINT32); - Ticker =3D *(UINT64 *) (TopOfTemporaryRam - s= izeof > (UINT32) - Size - sizeof (UINT32) * 2);+ Ticker =3D *(UINT64 *) (UINTN) > (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT64)); > Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker); return > EFI_SUCCESS;diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecPlatformInformation.c > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecPlatformInformation.c > index 24d55ed838..4cbde95c2d 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecPlatformInformation.c > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/SecPlatformInformation.c > @@ -1,7 +1,7 @@ > /** @file Provide SecPlatformInformation function. -Copyright (c) 2017= - > 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 20= 24, > Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-= 2- > Clause-Patent **/@@ -59,9 +59,9 @@ SecPlatformInformation ( > // This routine copies the BIST information to the buffer pointed by = // > PlatformInformationRecord for output. //- TopOfTemporaryRam =3D (UINTN= ) > TopOfTemporaryRamPpi - sizeof (UINT32);- TopOfTemporaryRam -=3D sizeof > (UINT32) * 2;- Count =3D *((UINT32 *)(TopOfTemporaryRam - si= zeof > (UINT32)));+ TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - > sizeof (UINTN);+ TopOfTemporaryRam -=3D sizeof (UINTN) * 2;+ Count = =3D > *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32))); Size = =3D > Count * sizeof (IA32_HANDOFF_STATUS); if ((*StructureSize) < (UINT64) > Size) {diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecRamInitData.c > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecRamInitData.c > index 355d1e6509..f91c4c1d19 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecRamInitData.c > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/SecRamInitData.c > @@ -1,7 +1,7 @@ > /** @file Provide TempRamInitParams data. -Copyright (c) 2017 - 2021, > Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2024, In= tel > Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clau= se- > Patent **/@@ -10,27 +10,76 @@ SPDX-License-Identifier: BSD-2-Clause- > Patent > #include #include "FsptCoreUpd.h" +#if defined (MDE_CPU_IA32) > && FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) =3D=3D 1+#error > "PcdFspWrapperResetVectorInFsp =3D=3D TRUE only supported for X64 > builds"+#endif+ typedef struct { FSP_UPD_HEADER FspUpdHeader;+#if > FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 1+ FSPT_ARCH_UPD > FsptArchUpd;+#elif FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 2+ > FSPT_ARCH2_UPD FsptArchUpd;+#endif FSPT_CORE_UPD FsptCoreUpd;- > } FSPT_UPD_CORE_DATA;+ UINT16 UpdTerminator;+} FSPT_UPD_DATA; > -GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA > FsptUpdDataPtr =3D {+GLOBAL_REMOVE_IF_UNREFERENCED CONST > FSPT_UPD_DATA FsptUpdDataPtr =3D {+ {+ 0x4450555F54505346, > // FSP-T UPD Header Signature - FSPT_UPD+ FixedPcdGet8 > (PcdFsptUpdHeaderRevision), // FSP-T UPD Header Revi= sion+ { > // Reserved[23]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0= 0, > 0x00,+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ > 0x00, 0x00, 0x00+ }+ },+#if FixedPcdGet8 (PcdFsptArchUpdRevision) =3D= =3D 1+ > {+ 0x01, // FS= P-T ARCH UPD Revision+ { > // Reserved[3]+ 0x00, 0x00, 0x00+ },+ 0x00000020, > // Length of FSP-T ARCH UPD+ 0, = // > FspDebugHandler+ { = // Reserved1[20]+ > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ 0x00, 0= x00, > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00+ }+ },+#elif FixedPcdG= et8 > (PcdFsptArchUpdRevision) =3D=3D 2 {- 0x4450555F54505346,- 0x00,- = { > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00, 0= x00, > 0x00, 0x00, 0x00, 0x00, 0x00+ 0x02, = // FSP-T > ARCH2 UPD Revision+ { = // Reserved[3]+ > 0x00, 0x00, 0x00+ },+ 0x00000020, = // Length of > FSP-T ARCH2 UPD+ 0, = // FspDebugHandler+ { > // Reserved1[16]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x= 00, > 0x00,+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } },+#endif+#if Fixe= dPcdGet8 > (PcdFsptArchUpdRevision) <=3D 1 {- FixedPcdGet32 > (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv),- > FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 > (PcdMicrocodeOffsetInFv),- 0, // Set CodeRegionBase as 0, so = that > caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize)= will > be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),- { 0x00, 0x00, 0x0= 0, > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ FixedPcdGet32 > (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeOffsetInFv), // > MicrocodeRegionBase+ FixedPcdGet32 (PcdFlashFvMicrocodeSize) - > FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionSize+ 0, // = Set > CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSiz= e ? > LLCSize : CodeRegionSize) will be used.+ FixedPcdGet32 > (PcdFlashCodeCacheSize), // Co= deRegionSize+ { > // Reserved[16]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0= 0, > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }- }+ },+#else+ {+ > FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 > (PcdMicrocodeOffsetInFv), // MicrocodeRegionBase+ FixedPcdGet32 > (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv), // > MicrocodeRegionSize+ 0, // Set CodeRegionBase as 0, so that caching wi= ll be > 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.+ > FixedPcdGet32 (PcdFlashCodeCacheSize) = // > CodeRegionSize+ },+#endif+ 0x55AA };-diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/X64/PeiCoreEntry.nasm > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/X64/PeiCoreEntry.nasm > new file mode 100644 > index 0000000000..08933c6d37 > --- /dev/null > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/X64/PeiCoreEntry.nasm > @@ -0,0 +1,207 @@ > +;-----------------------------------------------------------------------= -------+;+; > Copyright (c) 2024, Intel Corporation. All rights reserved.
+; SPDX-Li= cense- > Identifier: BSD-2-Clause-Patent+;+; Module Name:+;+; PeiCoreEntry.nasm+;= +; > Abstract:+;+; Find and call SecStartup+;+;-----------------------------= --------------- > ----------------------------------++SECTION .text++extern > ASM_PFX(SecStartup)+extern ASM_PFX(PlatformInit)+extern > ASM_PFX(PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))++;-------------- > ---------------------------------------------------------------+; Macro: > PUSHA_64+;+; Description: Saves all registers on stack+;+; Input: > None+;+; Output: None+;-------------------------------------------= ---------------- > ------------------+%macro PUSHA_64 0+ push r8+ push r9+ push = r10+ > push r11+ push r12+ push r13+ push r14+ push r15+ pus= h rax+ > push rcx+ push rdx+ push rbx+ push rsp+ push rbp+ pus= h rsi+ push > rdi+%endmacro++;---------------------------------------------------------= -------------- > ------+; Macro: POPA_64+;+; Description: Restores all registers= from > stack+;+; Input: None+;+; Output: None+;------------------= ----------------- > ------------------------------------------+%macro POPA_64 0+ pop rd= i+ pop > rsi+ pop rbp+ pop rsp+ pop rbx+ pop rdx+ pop rcx+ po= p rax+ pop > r15+ pop r14+ pop r13+ pop r12+ pop r11+ pop r10+ po= p r9+ pop > r8+%endmacro++global > ASM_PFX(CallPeiCoreEntryPoint)+ASM_PFX(CallPeiCoreEntryPoint):+ ;+ ; Pe= r > X64 calling convention, make sure RSP is 16-byte aligned.+ ;+ mov r= ax, rsp+ > and rax, 0fh+ sub rsp, rax++ ;+ ; Platform init+ ;+ PUSHA_64= + sub rsp, > 20h+ call ASM_PFX(PlatformInit)+ add rsp, 20h+ POPA_64++ ;+ ;= Set > stack top pointer+ ;+ mov rsp, r8++ ;+ ; Push the hob list pointe= r+ ;+ push > rcx++ ;+ ; RBP holds start of BFV passed from Vtf0. Save it to r10.+ ;= + mov > r10, rbp++ ;+ ; Save the value+ ; RDX: start of range+ ; r8: end = of range+ ;+ > mov rbp, rsp+ push rdx+ push r8+ mov r14, rdx+ mov = r15, r8++ ;+ > ; Push processor count to stack first, then BIST status (AP then BSP)+ ;= + mov > eax, 1+ cpuid+ shr ebx, 16+ and ebx, 0000000FFh+ cmp bl, = 1+ jae > PushProcessorCount++ ;+ ; Some processors report 0 logical processors. > Effectively 0 =3D 1.+ ; So we fix up the processor count+ ;+ inc > ebx++PushProcessorCount:+ sub rsp, 4+ mov rdi, rsp+ mov DW= ORD > [rdi], ebx++ ;+ ; We need to implement a long-term solution for BIST ca= pture. > For now, we just copy BSP BIST+ ; for all processor threads+ ;+ xor = ecx, ecx+ > mov cl, bl+PushBist:+ sub rsp, 4+ mov rdi, rsp+ movd ea= x, mm0+ > mov DWORD [rdi], eax+ loop PushBist++ ;+ ; FSP saves the timest= amp of > the beginning of firmware execution in mm5.+ ; Get the timestamp from mm= 5 > and then push to stack.+ ;+ movq rax, mm5+ push rax++ ;+ ; Per= X64 > calling convention, make sure RSP is 16-byte aligned.+ ;+ mov rax, = rsp+ and > rax, 0fh+ sub rsp, rax++ ;+ ; Pass entry point of the PEI core+ ;= + mov rdi, > 0FFFFFFE0h+ mov edi, DWORD [rdi]+ mov r9, rdi++ ;+ ; Pass BFV= into the > PEI Core+ ;+#if FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) =3D=3D 1= + ;+ ; > Reset Vector and initial SEC core (to initialize Temp Ram) is part of FSP= -O.+ ; > Default UefiCpuPkg Reset Vector locates FSP-O as BFV. However the actual+= ; > SEC core that launches PEI is part of another FV. We need to pass that FV= + ; as > BFV to PEI core.+ ;+ mov r8, ASM_PFX (PcdGet64 > (PcdFspWrapperBfvforResetVectorInFsp))+ mov rcx, QWORD[r8]+ mov > r8, rcx+#else+ mov r8, r10+#endif++ ;+ ; Pass stack size into the= PEI Core+ > ;+ mov rcx, r15 ; Start of TempRam+ mov rdx, r14 ; End of Tem= pRam++ > sub rcx, rdx ; Size of TempRam++ ;+ ; Pass Control into the PEI Co= re+ ;+ sub > rsp, 20h+ call ASM_PFX(SecStartup)+diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/X64/SecEntry.nasm > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/X64/SecEntry.nasm > new file mode 100644 > index 0000000000..2618860366 > --- /dev/null > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/X64/SecEntry.nasm > @@ -0,0 +1,199 @@ > +;-----------------------------------------------------------------------= -------+;+; > Copyright (c) 2024, Intel Corporation. All rights reserved.
+; SPDX-Li= cense- > Identifier: BSD-2-Clause-Patent+; Module Name:+;+; SecEntry.nasm+;+; > Abstract:+;+; This is the code that passes control to PEI core.+;+;-----= ------------ > -------------------------------------------------------------++#include > ++SECTION .text++extern ASM_PFX(CallPeiCoreEntryPoint)+extern > ASM_PFX(FsptUpdDataPtr)+; Pcds+extern ASM_PFX(PcdGet32 > (PcdFspTemporaryRamSize))+extern ASM_PFX(PcdGet32 > (PcdFsptBaseAddress))++;-------------------------------------------------= ------------- > --------------+;+; Procedure: _ModuleEntryPoint+;+; Input: None= +;+; > Output: None+;+; Destroys: Assume all registers+;+; Description= :+;+; Call > TempRamInit API from FSP binary if reset vector in FSP is not supproted.+= ; > After TempRamInit done, pass control to PEI core.+;+; Return: None+= ;+; > MMX Usage:+; MM0 =3D BIST State+;+;-------------------------= ----------------- > ----------------------------------++BITS 64+align 16+global > ASM_PFX(_ModuleEntryPoint)+ASM_PFX(_ModuleEntryPoint):+#if > FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) =3D=3D 1+ push rax+ = mov > rax, ASM_PFX(FsptUpdDataPtr) ; This is dummy code to include > TempRamInitParams in SecCore for FSP-O.+ pop rax+#else+ fninit > ; clear any pending Floating point exceptions+ ;+ ; Store the BIST valu= e in > mm0+ ;+ movd mm0, eax+ cli++ ;+ ; Trigger warm reset if PCIEBAR r= egister > is not in reset/default value state+ ;+ mov eax, 80000060h ; > PCIEX_BAR_REG B0:D0:F0:R60+ mov dx, 0CF8h+ out dx, eax+ mov = dx, > 0CFCh+ in eax, dx+ cmp eax, 0+ jz NotWarmStart++ ;+ ; = @note Issue > warm reset, since if CPU only reset is issued not all MSRs are restored t= o their > defaults+ ;+ mov dx, 0CF9h+ mov al, 06h+ out dx, al+ jmp > $++NotWarmStart:++ ; Find the fsp info header+ mov rax, > ASM_PFX(PcdGet32 (PcdFsptBaseAddress))+ mov edi, [eax]++ mov ea= x, > dword [edi + FVH_SIGINATURE_OFFSET]+ cmp eax, > FVH_SIGINATURE_VALID_VALUE+ jnz FspHeaderNotFound++ xor eax, > eax+ mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]+ cmp ax, = 0+ > jnz FspFvExtHeaderExist++ xor eax, eax+ mov ax, word [edi + > FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header+ add edi, eax+ jmp > FspCheckFfsHeader++FspFvExtHeaderExist:+ add edi, eax+ mov eax, > dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header+ add > edi, eax++ ; Round up to 8 byte alignment+ mov eax, edi+ and a= l, 07h+ jz > FspCheckFfsHeader++ and edi, 0FFFFFFF8h+ add edi, > 08h++FspCheckFfsHeader:+ ; Check the ffs guid+ mov eax, dword [edi]= + > cmp eax, FSP_HEADER_GUID_DWORD1+ jnz FspHeaderNotFound++ mov > eax, dword [edi + 4]+ cmp eax, FSP_HEADER_GUID_DWORD2+ jnz > FspHeaderNotFound++ mov eax, dword [edi + 8]+ cmp eax, > FSP_HEADER_GUID_DWORD3+ jnz FspHeaderNotFound++ mov eax, > dword [edi + 0Ch]+ cmp eax, FSP_HEADER_GUID_DWORD4+ jnz > FspHeaderNotFound++ add edi, FFS_HEADER_SIZE_VALUE ; Bypass = the > ffs header++ ; Check the section type as raw section+ mov al, byte = [edi + > SECTION_HEADER_TYPE_OFFSET]+ cmp al, 019h+ jnz > FspHeaderNotFound++ add edi, RAW_SECTION_HEADER_SIZE_VALUE ; > Bypass the section header+ jmp FspHeaderFound++FspHeaderNotFound:+ > jmp $++FspHeaderFound:+ ; Get the fsp TempRamInit Api address+ mov > eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]+ add eax, dword [edi > + FSP_HEADER_TEMPRAMINIT_OFFSET]++ ; Setup the hardcode stack+ mov > rsp, TempRamInitStack ; move return address to rsp+ mov rcx, > ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams++ ; Call the fsp > TempRamInit Api+ jmp rax++TempRamInitDone:+ mov rbx, > 0800000000000000Eh+ cmp rax, rbx ; Check if EFI_NOT_F= OUND > returned. Error code for Microcode Update not found.+ je CallSecFsp= Init > ; If microcode not found, don't hang, but continue.++ test rax, rax = ; > Check if EFI_SUCCESS returned.+ jnz > FspApiFailed++CallSecFspInit:+#endif++ ; RDX: start of range+ ; R8: end= of > range+#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1+ push rax+ mov = rax, > ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))+ sub edx, dword [rax] > ; TemporaryRam for FSP+ pop rax+#endif++ mov r8, rdx+ mov = rdx, rcx+ > xor ecx, ecx ; zero - no Hob List Yet+ mov = rsp, r8++ ;+ ; Per X64 > calling convention, make sure RSP is 16-byte aligned.+ ;+ mov rax, = rsp+ and > rax, 0fh+ sub rsp, rax++ call > ASM_PFX(CallPeiCoreEntryPoint)++FspApiFailed:+ jmp $++#if > FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) =3D=3D 0+align > 10h+TempRamInitStack:+ DQ TempRamInitDone+#endifdiff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/X64/Stack.nasm > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/X64/Stack.nasm > new file mode 100644 > index 0000000000..21010bf4ef > --- /dev/null > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/X64/Stack.nasm > @@ -0,0 +1,72 @@ > +;-----------------------------------------------------------------------= -------+;+; > Copyright (c) 2024, Intel Corporation. All rights reserved.
+; SPDX-Li= cense- > Identifier: BSD-2-Clause-Patent+; Abstract:+;+; Switch the stack from > temporary memory to permanent memory.+;+;--------------------------------= ----- > -----------------------------------------++ SECTION .text++;----------= ----------------- > ---------------------------------------------------+; VOID+; EFIAPI+; Sec= SwitchStack > (+; UINT32 TemporaryMemoryBase,+; UINT32 PermanentMemoryBase+; > );+;---------------------------------------------------------------------= ---------+global > ASM_PFX(SecSwitchStack)+ASM_PFX(SecSwitchStack):+ ;+ ; Save four > register: rax, rbx, rcx, rdx+ ;+ push rax+ push rbx+ push = rcx+ push > rdx++ ;+ ; !!CAUTION!! this function address's is pushed into stack= after+ ; > migration of whole temporary memory, so need save it to permanent+ ; > memory at first!+ ;++ mov rbx, rcx ; Save the fir= st parameter+ > mov rcx, rdx ; Save the second parameter++ ;+ ; S= ave this > function's return address into permanent memory at first.+ ; Then, Fix= up the > esp point to permanent memory+ ;+ mov rax, rsp+ sub rax, rbx= + add > rax, rcx+ mov rdx, qword [rsp] ; copy pushed register's valu= e to > permanent memory+ mov qword [rax], rdx+ mov rdx, qword [rsp + 8= ]+ > mov qword [rax + 8], rdx+ mov rdx, qword [rsp + 16]+ mov qwor= d [rax + > 16], rdx+ mov rdx, qword [rsp + 24]+ mov qword [rax + 24], rdx+= mov > rdx, qword [rsp + 32] ; Update this function's return address into per= manent > memory+ mov qword [rax + 32], rdx+ mov rsp, rax = ; From now, > rsp is pointed to permanent memory++ ;+ ; Fixup the rbp point to > permanent memory+ ;+ mov rax, rbp+ sub rax, rbx+ add ra= x, rcx+ > mov rbp, rax ; From now, rbp is pointed to permanent me= mory++ > pop rdx+ pop rcx+ pop rbx+ pop rax+ ret+diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/Fsp.h b/Platform/Intel/MinPlatformPkg/Include/Fsp.h > similarity index 79% > rename from > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform > SecLib/Ia32/Fsp.h > rename to Platform/Intel/MinPlatformPkg/Include/Fsp.h > index 9f6cdcf476..319e1e3372 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/Fsp.h > +++ b/Platform/Intel/MinPlatformPkg/Include/Fsp.h > @@ -1,7 +1,7 @@ > /** @file Fsp related definitions -Copyright (c) 2017, Intel Corporati= on. All > rights reserved.
+Copyright (c) 2017 - 2024, Intel Corporation. All ri= ghts > reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -36,7 > +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > // // Fsp Header //-#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C- > #define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30+#define > FSP_HEADER_IMAGEBASE_OFFSET 0x1C+#define > FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 #endifdiff --git > a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > index a14c6b2db5..74e1bce87f 100644 > --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > @@ -6,7 +6,7 @@ > # INF files to generate AutoGen.c and AutoGen.h files # for the build > infrastructure. #-# Copyright (c) 2017 - 2021, Intel Corporation. All rig= hts > reserved.
+# Copyright (c) 2017 - 2024, Intel Corporation. All rights > reserved.
# Copyright (C) 2023 Advanced Micro Devices, Inc. All right= s > reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent@@ -393,6 > +393,27 @@ > # > gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE > |BOOLEAN|0xF00000A8 + ## Reset Vector in FSP+ # FALSE: Reset Vector is = in > FSP Wrapper+ # TRUE: Reset Vector is in FSP - This is only supported in= X64+ > #+ > gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp|FALSE|B > OOLEAN|0xF00000A9++ ## BFV Location for Reset Vector in FSP+ # The > default of BFV Location for Reset Vector in FSP is 0x00000000FFFF0000.+ = #+ > gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp|0x > 00000000FFFF0000|UINT64|0xF00000AA++ ## FSP-T UPD Header > Revision+ # The default of FSP-T UPD Header Revision is 0.+ #+ > gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision|0x0|UINT8|0x > F00000AB++ ## FSP-T ARCH UPD Revision+ # The default of FSP-T ARCH UPD > Revision is 0.+ #+ > gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision|0x0|UINT8|0xF0 > 0000AC+ [PcdsFeatureFlag] > gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit > |FALSE|BOOLEAN|0xF00000A1-- > 2.40.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114922): https://edk2.groups.io/g/devel/message/114922 Mute This Topic: https://groups.io/mt/104067932/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-