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Thread-Topic: [PATCH] AlderlakeOpenBoardPkg: Fix BootStage 5 can't install Windows11. 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smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none) Hi Dora, Feedback below. Thanks, Nate > -----Original Message----- > From: Hsueh, DoraX > Sent: Monday, April 22, 2024 1:37 AM > To: devel@edk2.groups.io > Cc: Hsueh, DoraX ; Chaganty, Rangasai V > ; Chuang, Rosen ; > Kasbekar, Saloni ; Tang, Haoyu > ; Desimone, Nathaniel L > ; Chiu, Chasel > Subject: [PATCH] AlderlakeOpenBoardPkg: Fix BootStage 5 can't install > Windows11. >=20 > From: DoraX Hsueh >=20 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D4665 >=20 > 1. Since installing windows does not meet the minimum system requirements= , > Added TPM related code to meet the requirements. > 2. Support stage 6, add FvAdvancedPreMemory. >=20 > Cc: Sai Chaganty > Cc: Rosen Chuang > Cc: Saloni Kasbekar > Cc: Haoyu Tang > Cc: Nate DeSimone > Cc: Chasel Chiu > Signed-off-by: DoraX Hsueh > --- > .../Include/Fdf/FlashMapInclude.fdf | 26 +++++++------ > .../AlderlakePRvp/OpenBoardPkg.dsc | 1 + > .../AlderlakePRvp/OpenBoardPkg.fdf | 37 +++++++++++++++++-- > .../AlderlakePRvp/OpenBoardPkgPcd.dsc | 10 ++++- > 4 files changed, 57 insertions(+), 17 deletions(-) >=20 > diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/F= df/FlashMapInclude.fdf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp= /Include/Fdf/FlashMapInclude.fdf > index 03c198c0..3e515d4e 100644 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/Flas= hMapInclude.fdf > +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Include/Fdf/Flas= hMapInclude.fdf > @@ -26,27 +26,29 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFt= wSpareOffset =3D 0x000300 > SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = =3D 0x00030000 # > =20 > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = =3D 0x000E0000 # Flash addr (0xFF0E0000) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = =3D 0x00310000 # > -SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset = =3D 0x003F0000 # Flash addr (0xFF400000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = =3D 0x002E0000 # > +SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset = =3D 0x003C0000 # Flash addr (0xFF3C0000) > SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize = =3D 0x00360000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = =3D 0x00750000 # Flash addr (0xFF760000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = =3D 0x00720000 # Flash addr (0xFF720000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = =3D 0x00090000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = =3D 0x007E0000 # Flash addr (0xFF7F0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = =3D 0x007B0000 # Flash addr (0xFF7B0000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = =3D 0x000A0000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = =3D 0x00880000 # Flash addr (0xFF860000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = =3D 0x00850000 # Flash addr (0xFF850000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = =3D 0x00180000 # > =20 > -SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset = =3D 0x00A00000 # Flash addr (0xFFA00000) > +SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset = =3D 0x009D0000 # Flash addr (0xFF9D0000) > SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize = =3D 0x00080000 # Keep 0x80000 or larger > -SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = =3D 0x00A80000 # Flash addr (0xFFA80000) > +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = =3D 0x00A50000 # Flash addr (0xFFA50000) > SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = =3D 0x00230000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = =3D 0x00CB0000 # Flash addr (0xFFCB0000) > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = =3D 0x00040000 # > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = =3D 0x00CF0000 # Flash addr (0xFFCF0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = =3D 0x00C80000 # Flash addr (0xFFC80000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = =3D 0x00060000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = =3D 0x00CE0000 # Flash addr (0xFFCE0000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = =3D 0x000A0000 > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = =3D 0x00D90000 # Flash addr (0xFFD90000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = =3D 0x00D80000 # Flash addr (0xFFD80000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = =3D 0x00150000 > -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = =3D 0x00EE0000 # Flash addr (0xFFEE0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = =3D 0x00ED0000 # Flash addr (0xFFED0000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = =3D 0x00010000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = =3D 0x00EE0000 # Flash addr (0xFFEE0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = =3D 0x00010000 # > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = =3D 0x00EF0000 # Flash addr (0xFFEF0000) > SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = =3D 0x00110000 > diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoard= Pkg.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.d= sc > index 4cdc9c01..8468410e 100644 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc > +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc > @@ -49,6 +49,7 @@ > # Include PCD configuration for this board > # > !include OpenBoardPkgPcd.dsc > + !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc > =20 > ########################################################################= ######## > # > diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoard= Pkg.fdf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.f= df > index f1ce271b..3115ce50 100644 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf > +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf > @@ -113,9 +113,15 @@ DATA =3D { > #Blockmap[1]: End > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > ## This is the VARIABLE_STORE_HEADER > +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE > + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, = 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} > + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, > + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, > +!else > # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x9= 8, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} > 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, > 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, > +!endif > #Size: 0x2E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariab= leSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x2DFB8 > # This can speed up the Variable Dispatch a bit. > 0xB8, 0xDF, 0x02, 0x00, > @@ -189,6 +195,10 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMi= nPlatformPkgTokenSpaceGuid.P > # FSP_T Section > FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd > =20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlat= formPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatfo= rmPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize > +FV =3D FvAdvancedPreMemory > + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvPreMemorySize > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTok= enSpaceGuid.PcdFlashFvPreMemorySize > FV =3D FvPreMemory > @@ -646,6 +656,29 @@ INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2Pla= tformDxe.inf > =20 > INF IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf > =20 > +# > +# Pre-memory Advanced Features > +# > +[FV.FvAdvancedPreMemory] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305 > + > +!include AdvancedFeaturePkg/Include/PreMemory.fdf > =20 You forgot to add FvAdvancedUncompact and the include for AdvancedFeaturePk= g/Include/PostMemory.fdf. Something like this should be added: [FV.FvAdvancedUncompact] FvAlignment =3D 16 ERASE_POLARITY =3D 1 MEMORY_MAPPED =3D TRUE STICKY_WRITE =3D TRUE LOCK_CAP =3D TRUE LOCK_STATUS =3D TRUE WRITE_DISABLED_CAP =3D TRUE WRITE_ENABLED_CAP =3D TRUE WRITE_STATUS =3D TRUE WRITE_LOCK_CAP =3D TRUE WRITE_LOCK_STATUS =3D TRUE READ_DISABLED_CAP =3D TRUE READ_ENABLED_CAP =3D TRUE READ_STATUS =3D TRUE READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE FvNameGuid =3D BE3DF86F-E464-44A3-83F7-0D27E6B88C27 !include AdvancedFeaturePkg/Include/PostMemory.fdf > [FV.FvAdvanced] > BlockSize =3D $(FLASH_BLOCK_SIZE) > @@ -688,10 +721,6 @@ READ_LOCK_CAP =3D TRUE > READ_LOCK_STATUS =3D TRUE > FvNameGuid =3D 8B98AB22-E354-42f0-88B9-049810F0FDAA > =20 You forgot to add the nested FV for FvAdvancedUncompact. Something like thi= s should be included: FILE FV_IMAGE =3D 5248467B-B87B-4E74-AC02-398AF4BCB712 { SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI= RED =3D TRUE { SECTION FV_IMAGE =3D FvAdvancedUncompact } } > - > - > - > - > [FV.FvOptional] > BlockSize =3D $(FLASH_BLOCK_SIZE) > FvAlignment =3D 16 > diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoard= PkgPcd.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPk= gPcd.dsc > index 3eb9a575..b52ed92c 100644 > --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.= dsc > +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.= dsc > @@ -25,7 +25,7 @@ > # Stage 5 - boot to OS with security boot enabled > # Stage 6 - boot with advanced features enabled > # > - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 > + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|5 > =20 > # > # 0: FSP Wrapper is running in Dispatch mode. > @@ -313,6 +313,14 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddres= s|0x00000000 > gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 > gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|F= ALSE > =20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 > + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x= 28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} > +!endif > + > +[PcdsDynamicHii.common.DEFAULT] > + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg= 2ConfigFormSetGuid|0x8|4|NV,BS > + > [PcdsDynamicHii.X64.DEFAULT] > gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalV= ariableGuid|0x0|5 # Variable: L"Timeout" > gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport= "|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" > --=20 > 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#118542): https://edk2.groups.io/g/devel/message/118542 Mute This Topic: https://groups.io/mt/105665553/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-