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From: "Nate DeSimone" <nathaniel.l.desimone@intel.com>
To: "Kasbekar, Saloni" <saloni.kasbekar@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>,
	"Chuang, Rosen" <rosen.chuang@intel.com>
Subject: Re: [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
Date: Fri, 15 Sep 2023 23:56:54 +0000	[thread overview]
Message-ID: <MW4PR11MB5821F4E409ACCCD89480C7C9CDF6A@MW4PR11MB5821.namprd11.prod.outlook.com> (raw)
In-Reply-To: <dcbfd123d30016f61c2f7039c79fd2aa0f117e23.1694752604.git.saloni.kasbekar@intel.com>

Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com> 
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes

Adds the following Includes:
  - Include/
  - Include/Protocol
  - Include/Register

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
 .../AlderlakeSiliconPkg/Include/ConfigBlock.h |  53 +++
 .../AlderlakeSiliconPkg/Include/CpuPcieHob.h  |  48 +++
 .../Include/Protocol/IgdOpRegion.h            |  22 ++
 .../Include/Protocol/Spi.h                    | 346 ++++++++++++++++++
 .../Include/Protocol/Wdt.h                    | 111 ++++++
 .../Include/Register/FlashRegs.h              |  73 ++++
 .../Include/Register/GpioRegs.h               | 103 ++++++
 .../Include/Register/GpioRegsVer2.h           | 211 +++++++++++
 .../Include/Register/PchDmi14Regs.h           |  49 +++
 .../Include/Register/PchDmiRegs.h             |  51 +++
 .../Include/Register/PchPcieRpRegs.h          |  45 +++
 .../Include/Register/PchRegsLpc.h             |  77 ++++
 .../Include/Register/PmcRegs.h                | 134 +++++++
 .../Include/Register/RtcRegs.h                |  44 +++
 .../Include/Register/TcoRegs.h                |  71 ++++
 .../Include/SerialIoDevices.h                 | 226 ++++++++++++
 .../AlderlakeSiliconPkg/Include/SiConfigHob.h |  17 +
 .../Include/SiPolicyStruct.h                  |  64 ++++
 18 files changed, 1745 insertions(+)
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
 create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h

diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 0000000000..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+  Header file for Config Block Lib implementation
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+  EFI_HOB_GUID_TYPE GuidHob;                      ///< Offset 0-23  GUID extension HOB header
+  UINT8             Revision;                     ///< Offset 24    Revision of this config block
+  UINT8             Attributes;                   ///< Offset 25    The main revision for config block
+  UINT8             Reserved[2];                  ///< Offset 26-27 Reserved for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+  CONFIG_BLOCK_HEADER            Header;          ///< Offset 0-27  Header of config block
+  //
+  // Config Block Data
+  //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+  CONFIG_BLOCK_HEADER            Header;          ///< Offset 0-27  GUID number for main entry of config block
+  UINT8                          Rsvd0[2];        ///< Offset 28-29 Reserved for future use
+  UINT16                         NumberOfBlocks;  ///< Offset 30-31 Number of config blocks (N)
+  UINT32                         AvailableSize;   ///< Offset 32-35 Current config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#pragma pack (pop)
+
+#endif // _CONFIG_BLOCK_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
new file mode 100644
index 0000000000..dccd6e7d7a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
@@ -0,0 +1,48 @@
+/** @file
+  The GUID definition for CpuPcieHob
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_HOB_H_
+#define _CPU_PCIE_HOB_H_
+
+#include <Base.h>
+#include <CpuPcieInfo.h>
+#include <CpuPcieConfig.h>
+
+extern EFI_GUID gCpuPcieHobGuid;
+#pragma pack (push,1)
+
+
+/**
+  The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers
+**/
+typedef struct {
+  ///
+  /// These members describe the configuration of each CPU PCIe root port.
+  ///
+  EFI_HOB_GUID_TYPE           EfiHobGuidType;                           ///< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid
+  CPU_PCIE_ROOT_PORT_CONFIG   RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+  UINT8                       L1SubStates[CPU_PCIE_MAX_ROOT_PORTS];  ///< The L1 Substates configuration of the root port
+
+  UINT32                      DekelFwVersionMinor;                      ///< Dekel Firmware Minor Version
+  UINT32                      DekelFwVersionMajor;                      ///< Dekel Firmware Major Version
+  BOOLEAN                     InitPcieAspmAfterOprom;                   ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
+  UINT32                      RpEnabledMask;                            ///< Rootport enabled mask based on DEVEN register
+  UINT32                      RpEnMaskFromDevEn;                        ///< Rootport enabled mask based on Device Id
+  UINT8                       DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS];     ///< 1=ClkReqMsg disabled, 0=ClkReqMsg enabled
+  UINT8                       SlotSelection;                            ///< 1=M2 slot, 0=CEMx4 slot
+  BOOLEAN                     ComplianceTest;                           ///< Compliance Test based on policy
+  UINT32                      HsPhyRecipeVersionMajor;                  ///< HS-Phy Recipe Major Version
+  UINT32                      HsPhyRecipeVersionMinor;                  ///< HS-Phy Recipe Minor Version
+  UINT32                      HsPhyFwProdMajor;                         ///< HS-Phy Firmware Product Major Verison
+  UINT32                      HsPhyFwProdMinor;                         ///< HS-Phy Firmware Product Minor Verison
+  UINT32                      HsPhyFwHotFix;                            ///< HS-Phy Firmware Hot Fix Version
+  UINT32                      HsPhyFwBuild;                             ///< HS-Phy Firmware Build version
+  UINT32                      HsPhyFwEvBitProgMajor;                    ///< HS-Phy Firmware EV Bit Prog Major
+  UINT32                      HsPhyFwEvBitProgMinor;                    ///< HS-Phy Firmware EV Bit Prog Minor
+  UINT32                      HsPhyMap;                                 ///< HS-Phy Mapping Based on HS-Py supported ports
+} CPU_PCIE_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
new file mode 100644
index 0000000000..9f69671f35
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
@@ -0,0 +1,22 @@
+/** @file
+  This file is part of the IGD OpRegion Implementation.  The IGD OpRegion is
+  an interface between system BIOS, ASL code, and Graphics drivers.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+#include <IndustryStandard/IgdOpRegion.h>
+
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+///
+/// IGD OpRegion Protocol
+///
+typedef struct {
+  IGD_OPREGION_STRUCTURE  *OpRegion; ///< IGD Operation Region Structure
+} IGD_OPREGION_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
new file mode 100644
index 0000000000..cbf2883fa4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
@@ -0,0 +1,346 @@
+/** @file
+  This file defines the PCH SPI Protocol which implements the
+  Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+  @note The APIs in this file are designed to be backward compatible with
+  previous versions. Any change in behavior of these APIs will result in
+  newer version of the API.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PROTOCOL_H_
+#define _PCH_SPI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID                   gPchSpiProtocolGuid;
+extern EFI_GUID                   gPchSmmSpiProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SPI_PROTOCOL  PCH_SPI_PROTOCOL;
+
+//
+// SPI protocol data structures and definitions
+//
+
+/**
+  Flash Region Type
+**/
+typedef enum {
+  FlashRegionDescriptor,
+  FlashRegionBios,
+  FlashRegionMe,
+  FlashRegionGbE,
+  FlashRegionPlatformData,
+  FlashRegionDer,
+  FlashRegionSecondaryBios,
+  FlashRegionuCodePatch,
+  FlashRegionEC,
+  FlashRegionDeviceExpansion2,
+  FlashRegionIE,
+  FlashRegion10Gbe_A,
+  FlashRegion10Gbe_B,
+  FlashRegion13,
+  FlashRegion14,
+  FlashRegion15,
+  FlashRegionAll,
+  FlashRegionMax
+} FLASH_REGION_TYPE;
+
+//
+// Protocol member functions
+//
+
+/**
+  Read data from the flash part.
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] FlashRegionType      The Flash Region type for flash cycle which
+                                  is listed in the Descriptor.
+  @param[in] Address              The Flash Linear Address must fall within a
+                                  region for which BIOS has access permissions.
+  @param[in] ByteCount            Number of bytes in the data portion of the
+                                  SPI cycle.
+  @param[out] Buffer              The Pointer to caller-allocated buffer
+                                  containing the dada received.
+                                  It is the caller's responsibility to make
+                                  sure Buffer is large enough for the total
+                                  number of bytes read.
+
+  @retval EFI_SUCCESS             Command succeed.
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     FLASH_REGION_TYPE  FlashRegionType,
+  IN     UINT32             Address,
+  IN     UINT32             ByteCount,
+  OUT    UINT8              *Buffer
+  );
+
+/**
+  Write data to the flash part. Remark: Erase may be needed before write to the
+  flash part.
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] FlashRegionType      The Flash Region type for flash cycle which
+                                  is listed in the Descriptor.
+  @param[in] Address              The Flash Linear Address must fall within a
+                                  region for which BIOS has access permissions.
+  @param[in] ByteCount            Number of bytes in the data portion of the
+                                  SPI cycle.
+  @param[in] Buffer               Pointer to caller-allocated buffer containing
+                                  the data sent during the SPI cycle.
+
+  @retval EFI_SUCCESS             Command succeed.
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     FLASH_REGION_TYPE  FlashRegionType,
+  IN     UINT32             Address,
+  IN     UINT32             ByteCount,
+  IN     UINT8              *Buffer
+  );
+
+/**
+  Erase area on the flash part.
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] FlashRegionType      The Flash Region type for flash cycle which
+                                  is listed in the Descriptor.
+  @param[in] Address              The Flash Linear Address must fall within a
+                                  region for which BIOS has access permissions.
+  @param[in] ByteCount            Number of bytes in the data portion of the
+                                  SPI cycle.
+
+  @retval EFI_SUCCESS             Command succeed.
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_ERASE) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     FLASH_REGION_TYPE  FlashRegionType,
+  IN     UINT32             Address,
+  IN     UINT32             ByteCount
+  );
+
+/**
+  Read SFDP data from the flash part.
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] ComponentNumber      The Componen Number for chip select
+  @param[in] Address              The starting byte address for SFDP data read.
+  @param[in] ByteCount            Number of bytes in SFDP data portion of the
+                                  SPI cycle
+  @param[out] SfdpData            The Pointer to caller-allocated buffer
+                                  containing the SFDP data received
+                                  It is the caller's responsibility to make
+                                  sure Buffer is large enough for the total
+                                  number of bytes read
+
+  @retval EFI_SUCCESS             Command succeed.
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_SFDP) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     UINT8              ComponentNumber,
+  IN     UINT32             Address,
+  IN     UINT32             ByteCount,
+  OUT    UINT8              *SfdpData
+  );
+
+/**
+  Read Jedec Id from the flash part.
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] ComponentNumber      The Componen Number for chip select
+  @param[in] ByteCount            Number of bytes in JedecId data portion of
+                                  the SPI cycle, the data size is 3 typically
+  @param[out] JedecId             The Pointer to caller-allocated buffer
+                                  containing JEDEC ID received.
+                                  It is the caller's responsibility to make
+                                  sure Buffer is large enough for the total
+                                  number of bytes read.
+
+  @retval EFI_SUCCESS             Command succeed.
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     UINT8              ComponentNumber,
+  IN     UINT32             ByteCount,
+  OUT    UINT8              *JedecId
+  );
+
+/**
+  Write the status register in the flash part.
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] ByteCount            Number of bytes in Status data portion of the
+                                  SPI cycle, the data size is 1 typically
+  @param[in] StatusValue          The Pointer to caller-allocated buffer
+                                  containing the value of Status register writing
+
+  @retval EFI_SUCCESS             Command succeed.
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     UINT32             ByteCount,
+  IN     UINT8              *StatusValue
+  );
+
+/**
+  Read status register in the flash part.
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] ByteCount            Number of bytes in Status data portion of the
+                                  SPI cycle, the data size is 1 typically
+  @param[out] StatusValue         The Pointer to caller-allocated buffer
+                                  containing the value of Status register received.
+
+  @retval EFI_SUCCESS             Command succeed.
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_STATUS) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     UINT32             ByteCount,
+  OUT    UINT8              *StatusValue
+  );
+
+/**
+  Get the SPI region base and size, based on the enum type
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] FlashRegionType      The Flash Region type for for the base address
+                                   which is listed in the Descriptor.
+  @param[out] BaseAddress         The Flash Linear Address for the Region 'n'
+                                  Base
+  @param[out] RegionSize          The size for the Region 'n'
+
+  @retval EFI_SUCCESS             Read success
+  @retval EFI_INVALID_PARAMETER   Invalid region type given
+  @retval EFI_DEVICE_ERROR        The region is not used
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     FLASH_REGION_TYPE  FlashRegionType,
+  OUT    UINT32             *BaseAddress,
+  OUT    UINT32             *RegionSize
+  );
+
+/**
+  Read PCH Soft Strap Values
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] SoftStrapAddr        PCH Soft Strap address offset from FPSBA.
+  @param[in] ByteCount            Number of bytes in SoftStrap data portion of
+                                  the SPI cycle
+  @param[out] SoftStrapValue      The Pointer to caller-allocated buffer
+                                  containing PCH Soft Strap Value.
+                                  If the value of ByteCount is 0, the data type
+                                  of SoftStrapValue should be UINT16 and
+                                  SoftStrapValue will be PCH Soft Strap Length.
+                                  It is the caller's responsibility to make sure
+                                  Buffer is large enough for the total number of
+                                  bytes read.
+
+  @retval EFI_SUCCESS             Command succeed.
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     UINT32             SoftStrapAddr,
+  IN     UINT32             ByteCount,
+  OUT    VOID               *SoftStrapValue
+  );
+
+/**
+  Read CPU Soft Strap Values
+
+  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
+  @param[in] SoftStrapAddr        CPU Soft Strap address offset from FCPUSBA.
+  @param[in] ByteCount            Number of bytes in SoftStrap data portion of
+                                  the SPI cycle.
+  @param[out] SoftStrapValue      The Pointer to caller-allocated buffer
+                                  containing CPU Soft Strap Value.
+                                  If the value of ByteCount is 0, the data type
+                                  of SoftStrapValue should be UINT16 and
+                                  SoftStrapValue will be PCH Soft Strap Length
+                                  It is the caller's responsibility to make sure
+                                  Buffer is large enough for the total number
+                                  of bytes read.
+
+  @retval EFI_SUCCESS             Command succeed.
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) (
+  IN     PCH_SPI_PROTOCOL   *This,
+  IN     UINT32             SoftStrapAddr,
+  IN     UINT32             ByteCount,
+  OUT    VOID               *SoftStrapValue
+  );
+
+/**
+  These protocols/PPI allows a platform module to perform SPI operations
+  through the Intel PCH SPI Host Controller Interface.
+**/
+struct _PCH_SPI_PROTOCOL {
+  /**
+    This member specifies the revision of this structure. This field is
+    used to indicate backwards compatible changes to the protocol.
+  **/
+  UINT8                             Revision;
+  PCH_SPI_FLASH_READ                FlashRead;          ///< Read data from the flash part.
+  PCH_SPI_FLASH_WRITE               FlashWrite;         ///< Write data to the flash part. Remark: Erase may be needed before write to the flash part.
+  PCH_SPI_FLASH_ERASE               FlashErase;         ///< Erase some area on the flash part.
+  PCH_SPI_FLASH_READ_SFDP           FlashReadSfdp;      ///< Read SFDP data from the flash part.
+  PCH_SPI_FLASH_READ_JEDEC_ID       FlashReadJedecId;   ///< Read Jedec Id from the flash part.
+  PCH_SPI_FLASH_WRITE_STATUS        FlashWriteStatus;   ///< Write the status register in the flash part.
+  PCH_SPI_FLASH_READ_STATUS         FlashReadStatus;    ///< Read status register in the flash part.
+  PCH_SPI_GET_REGION_ADDRESS        GetRegionAddress;   ///< Get the SPI region base and size
+  PCH_SPI_READ_PCH_SOFTSTRAP        ReadPchSoftStrap;   ///< Read PCH Soft Strap Values
+  PCH_SPI_READ_CPU_SOFTSTRAP        ReadCpuSoftStrap;   ///< Read CPU Soft Strap Values
+};
+
+/**
+  PCH SPI PPI/PROTOCOL revision number
+
+  Revision 1:   Initial version
+**/
+#define PCH_SPI_SERVICES_REVISION       1
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
new file mode 100644
index 0000000000..a68085fa54
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
@@ -0,0 +1,111 @@
+/** @file
+  Watchdog Timer protocol
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DXE_WDT_H_
+#define _DXE_WDT_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID               gWdtProtocolGuid;
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _WDT_PROTOCOL  WDT_PROTOCOL;
+
+/**
+  Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which
+  causes the next reset to be treated as watchdog expiration - unless AllowKnownReset()
+  function was called too.
+
+  @param[in] TimeoutValue         Time in seconds before WDT times out. Supported range = 1 - 1024.
+
+  @retval EFI_SUCCESS             if everything's OK
+  @retval EFI_INVALID_PARAMETER   if TimeoutValue parameter is wrong
+**/
+typedef
+EFI_STATUS
+(EFIAPI *WDT_RELOAD_AND_START) (
+  UINT32 TimeoutValue
+  );
+
+/**
+  Returns WDT failure status.
+
+  @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE   If there was WDT expiration or unexpected reset
+  @retval V_PCH_OC_WDT_CTL_STATUS_OK        Otherwise
+**/
+typedef
+UINT8
+(EFIAPI *WDT_CHECK_STATUS) (
+  VOID
+  );
+
+/**
+  Returns information if WDT coverage for the duration of BIOS execution
+  was requested by an OS application.
+
+  @retval TRUE                    if WDT was requested
+  @retval FALSE                   if WDT was not requested
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_REQUIRED) (
+  VOID
+  );
+
+/**
+  Returns WDT enabled/disabled status.
+
+  @retval TRUE                    if WDT is enabled
+  @retval FALSE                   if WDT is disabled
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_ENABLED) (
+  VOID
+  );
+
+/**
+  Disables WDT timer.
+**/
+typedef
+VOID
+(EFIAPI *WDT_DISABLE) (
+  VOID
+  );
+
+/**
+  Normally, each reboot performed while watchdog runs is considered a failure.
+  This function allows platform to perform expected reboots with WDT running,
+  without being interpreted as failures.
+  In DXE phase, it is enough to call this function any time before reset.
+  In PEI phase, between calling this function and performing reset, ReloadAndStart()
+  must not be called.
+**/
+typedef
+VOID
+(EFIAPI *WDT_ALLOW_KNOWN_RESET) (
+  VOID
+  );
+
+/**
+  These protocols and PPI allow a platform module to perform watch dog timer operations
+  through the Intel PCH LPC Host Controller Interface. The WDT protocol and WDT PPI
+  implement the Intel (R) Watch Dog timer for DXE, and PEI environments, respectively.
+  WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_PPI, as they
+  share the identical data structure.
+**/
+struct _WDT_PROTOCOL {
+  WDT_RELOAD_AND_START  ReloadAndStart;   ///< Reloads WDT with new timeout value and starts it.
+  WDT_CHECK_STATUS      CheckStatus;      ///< Returns WDT failure status.
+  WDT_DISABLE           Disable;          ///< Disables WDT timer.
+  WDT_ALLOW_KNOWN_RESET AllowKnownReset;  ///< Perform expected reboots with WDT running, without being interpreted as failures.
+  IS_WDT_REQUIRED       IsWdtRequired;    ///< Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application.
+  IS_WDT_ENABLED        IsWdtEnabled;     ///< Returns WDT enabled/disabled status.
+};
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
new file mode 100644
index 0000000000..860f823655
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
@@ -0,0 +1,73 @@
+/** @file
+  Register names for Flash registers
+
+  Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_REGS_H_
+#define _FLASH_REGS_H_
+
+
+//
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
+//
+#define R_FLASH_FDBAR_FLASH_MAP0          0x04
+#define B_FLASH_FDBAR_NC                  0x00000300                    ///< Number Of Components
+#define N_FLASH_FDBAR_NC                  8                             ///< Number Of Components
+#define R_FLASH_FDBAR_FLASH_MAP1          0x08
+#define B_FLASH_FDBAR_FPSBA               0x00FF0000                    ///< PCH Strap Base Address, [23:16] represents [11:4]
+#define N_FLASH_FDBAR_FPSBA               16                            ///< PCH Strap base Address bit position
+#define N_FLASH_FDBAR_FPSBA_REPR          4                             ///< PCH Strap base Address bit represents position
+#define B_FLASH_FDBAR_PCHSL               0xFF000000                    ///< PCH Strap Length, [31:24] represents number of Dwords
+#define N_FLASH_FDBAR_PCHSL               24                            ///< PCH Strap Length bit position
+#define R_FLASH_FDBAR_FLASH_MAP2          0x0C
+#define B_FLASH_FDBAR_FCPUSBA             0x00000FFC                    ///< CPU Strap Base Address [11:2]
+#define N_FLASH_FDBAR_FCPUSBA             2                             ///< CPU Strap Base Address bit position
+#define B_FLASH_FDBAR_CPUSL               0x00FF0000                    ///< CPU Strap Length, [23:16] represents number of Dwords
+#define N_FLASH_FDBAR_CPUSL               16                            ///< CPU Strap Length bit position
+
+//
+// Flash Component Base Address (FCBA) from Flash Region 0
+//
+#define R_FLASH_FCBA_FLCOMP               0x00                          ///< Flash Components Register
+#define B_FLASH_FLCOMP_COMP1_MASK         0xF0                          ///< Flash Component 1 Size MASK
+#define N_FLASH_FLCOMP_COMP1              4                             ///< Flash Component 1 Size bit position
+#define B_FLASH_FLCOMP_COMP0_MASK         0x0F                          ///< Flash Component 0 Size MASK
+#define V_FLASH_FLCOMP_COMP_512KB         0x80000
+//
+// Descriptor Upper Map Section from Flash Region 0
+//
+#define R_FLASH_UMAP1                     0xEFC                         ///< Flash Upper Map 1
+#define B_FLASH_UMAP1_MDTBA               0xFF000000                    ///< MIP Descriptor Table Base Address
+#define N_FLASH_UMAP1_MDTBA               24                            ///< MDTBA bits position
+#define N_FLASH_UMAP1_MDTBA_REPR          4                             ///< MDTBA address representation position
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
new file mode 100644
index 0000000000..c89dccb7bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
@@ -0,0 +1,103 @@
+/** @file
+  Register names for PCH GPIO
+
+Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_H_
+#define _GPIO_REGS_H_
+
+//
+// PADCFG register is split into multiple DW registers
+// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers for one pad
+//
+#define S_GPIO_PCR_PADCFG               0x10
+
+//
+// Pad Configuration Register DW0
+//
+
+
+//RX Raw Override to 1
+#define B_GPIO_PCR_RX_RAW1              BIT28
+#define N_GPIO_PCR_RX_RAW1              28
+
+//RX Level/Edge Configuration
+#define B_GPIO_PCR_RX_LVL_EDG           (BIT26 | BIT25)
+#define N_GPIO_PCR_RX_LVL_EDG           25
+
+//RX Invert
+#define B_GPIO_PCR_RXINV                BIT23
+#define N_GPIO_PCR_RXINV                23
+
+//GPIO Input Route IOxAPIC
+#define B_GPIO_PCR_RX_APIC_ROUTE        BIT20
+
+//GPIO Input Route SCI
+#define B_GPIO_PCR_RX_SCI_ROUTE         BIT19
+
+//GPIO Input Route SMI
+#define B_GPIO_PCR_RX_SMI_ROUTE         BIT18
+
+//GPIO Input Route NMI
+#define B_GPIO_PCR_RX_NMI_ROUTE         BIT17
+#define N_GPIO_PCR_RX_NMI_ROUTE         17
+
+//GPIO Pad Mode
+#define B_GPIO_PCR_PAD_MODE             (BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_PAD_MODE             10
+
+//GPIO RX Disable
+#define B_GPIO_PCR_RXDIS                BIT9
+
+//GPIO TX Disable
+#define B_GPIO_PCR_TXDIS                BIT8
+#define N_GPIO_PCR_TXDIS                8
+
+//GPIO TX State
+#define B_GPIO_PCR_TX_STATE             BIT0
+#define N_GPIO_PCR_TX_STATE             0
+
+//Termination
+#define B_GPIO_PCR_TERM                (BIT13 | BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_TERM                 10
+
+
+///
+/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL
+/// Below defines are to be used internally by PCH SMI dispatcher only
+///
+#define PCH_GPIO_NUM_SUPPORTED_GPIS       512
+#define S_GPIO_PCR_GP_SMI_STS               4
+
+#endif // _GPIO_REGS_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
new file mode 100644
index 0000000000..7789236b5e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
@@ -0,0 +1,211 @@
+/** @file
+  Register names for VER2 GPIO
+
+Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_VER2_H_
+#define _GPIO_REGS_VER2_H_
+
+#define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX    26
+#define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX    25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX    8
+#define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX      17
+#define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX    8
+#define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX    24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX    21
+#define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX    25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX    24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX    25
+
+//
+// GPIO Community 0 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN        0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN        0x38
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK     0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX   0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK     0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX   0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN     0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN     0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS         0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS         0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE         0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE         0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS    0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS    0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN     0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN     0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS        0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN         0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS        0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN         0x01E0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET  0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET  0x9A0
+
+//
+// GPIO Community 1 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN        0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN        0x24
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN        0x30
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK     0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX   0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK     0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX   0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK     0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX   0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN     0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN     0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN     0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS         0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS         0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS         0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE         0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE         0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE         0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS    0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS    0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS    0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN     0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN     0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN     0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS        0x0188
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN         0x01A8
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS        0x01C8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN         0x01E8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET  0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET  0x780
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET  0x900
+//
+// GPIO Community 2 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN          0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK       0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX     0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN       0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS           0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE           0x0120
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS      0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN       0x0160
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET    0x700
+
+//
+// GPIO Community 4 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN        0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN        0x2C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN        0x40
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK     0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX   0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK     0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX   0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK     0x98
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX   0x9C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN     0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN     0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN     0xBC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS         0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS         0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS         0x010C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE         0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE         0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE         0x012C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS    0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS    0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS    0x014C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN     0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN     0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN     0x016C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS        0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS        0x018C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN         0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN         0x01AC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS        0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS        0x01CC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN         0x01E0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN         0x01EC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET  0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET  0x880
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET  0xA70
+
+//
+// GPIO Community 5 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN        0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK     0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX   0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN     0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS         0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE         0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS    0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN     0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET  0x700
+
+#endif // _GPIO_REGS_VER2_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
new file mode 100644
index 0000000000..f30bf62614
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
@@ -0,0 +1,49 @@
+/** @file
+  Register names for PCH DMI SIP14
+
+Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI14_REGS_H_
+#define _PCH_DMI14_REGS_H_
+
+//
+// DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// DMI Control
+//
+#define R_PCH_DMI14_PCR_DMIC                       0x2234                              ///< DMI Control
+#define B_PCH_DMI14_PCR_DMIC_SRL                   BIT31                               ///< Secured register lock
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
new file mode 100644
index 0000000000..649e8dd17b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
@@ -0,0 +1,51 @@
+/** @file
+  Register names for PCH DMI and OP-DMI
+
+Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_REGS_H_
+#define _PCH_DMI_REGS_H_
+
+//
+// PCH DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// PCH DMI Source Decode PCRs (Common)
+//
+#define R_PCH_DMI_PCR_LPCIOD                     0x2770                       ///< LPC I/O Decode Ranges
+#define R_PCH_DMI_PCR_LPCIOE                     0x2774                       ///< LPC I/O Enables
+#define R_PCH_DMI_PCR_TCOBASE                    0x2778                       ///< TCO Base Address
+#define B_PCH_DMI_PCR_TCOBASE_TCOBA              0xFFE0                       ///< TCO Base Address Mask
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
new file mode 100644
index 0000000000..17c68cbaaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
@@ -0,0 +1,45 @@
+/** @file
+  Register names for PCH PCI-E root port devices
+
+  Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PCIE_H_
+#define _PCH_REGS_PCIE_H_
+
+//
+// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)
+//
+#define R_SPX_PCR_PCD                         0                       ///< Port configuration and disable
+#define B_SPX_PCR_PCD_RP1FN                   (BIT2 | BIT1 | BIT0)    ///< Port 1 Function Number
+#define S_SPX_PCR_PCD_RP_FIELD                4                       ///< 4 bits for each RP FN
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
new file mode 100644
index 0000000000..326b266352
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
@@ -0,0 +1,77 @@
+/** @file
+  Register names for PCH LPC/eSPI device
+
+Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_LPC_H_
+#define _PCH_REGS_LPC_H_
+
+//
+// PCI to LPC Bridge Registers
+//
+
+#define R_LPC_CFG_IOD                             0x80
+#define R_LPC_CFG_IOE                             0x82
+#define R_ESPI_CFG_CS1IORE                        0xA0
+
+#define R_LPC_CFG_ULKMC                           0x94
+#define B_LPC_CFG_ULKMC_A20PASSEN                 BIT5
+#define B_LPC_CFG_ULKMC_64WEN                     BIT3
+#define B_LPC_CFG_ULKMC_64REN                     BIT2
+#define B_LPC_CFG_ULKMC_60WEN                     BIT1
+#define B_LPC_CFG_ULKMC_60REN                     BIT0
+
+//
+// APM Registers
+//
+#define R_PCH_IO_APM_CNT                             0xB2
+#define R_PCH_IO_APM_STS                             0xB3
+#define R_LPC_CFG_BC                              0xDC            ///< Bios Control
+#define S_LPC_CFG_BC                              1
+#define N_LPC_CFG_BC_LE                           1
+
+//
+// Reset Generator I/O Port
+//
+#define R_PCH_IO_RST_CNT                             0xCF9
+#define V_PCH_IO_RST_CNT_FULLRESET                   0x0E
+#define V_PCH_IO_RST_CNT_HARDRESET                   0x06
+//
+// eSPI PCR Registers
+//
+#define R_ESPI_PCR_CFG_VAL                    0xC00C          ///< ESPI Enabled Strap
+#define B_ESPI_PCR_CFG_VAL_ESPI_EN            BIT0            ///< ESPI Enabled Strap bit position
+#define R_ESPI_PCR_SOFTSTRAPS                 0xC210          ///< eSPI Sofstraps Register 0
+#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN          BIT12           ///< CS1# Enable
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
new file mode 100644
index 0000000000..f7153b931c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
@@ -0,0 +1,134 @@
+/** @file
+  Register names for PCH PMC device
+
+  Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PMC_H_
+#define _PCH_REGS_PMC_H_
+
+//
+// ACPI and legacy I/O register offsets from ACPIBASE
+//
+#define R_ACPI_IO_PM1_STS                        0x00
+#define S_ACPI_IO_PM1_STS                        2
+#define B_ACPI_IO_PM1_STS_PRBTNOR                BIT11
+#define B_ACPI_IO_PM1_STS_PWRBTN                 BIT8
+#define N_ACPI_IO_PM1_STS_RTC                    10
+#define N_ACPI_IO_PM1_STS_PWRBTN                 8
+#define N_ACPI_IO_PM1_STS_TMROF                  0
+
+#define R_ACPI_IO_PM1_EN                         0x02
+#define S_ACPI_IO_PM1_EN                         2
+#define B_ACPI_IO_PM1_EN_PWRBTN                  BIT8
+#define N_ACPI_IO_PM1_EN_RTC                     10
+#define N_ACPI_IO_PM1_EN_PWRBTN                  8
+#define N_ACPI_IO_PM1_EN_TMROF                   0
+
+#define R_ACPI_IO_PM1_CNT                        0x04                                   ///< Power Management 1 Control
+#define B_ACPI_IO_PM1_CNT_SLP_EN                 BIT13                                  ///< Sleep Enable
+#define B_ACPI_IO_PM1_CNT_SLP_TYP                (BIT12 | BIT11 | BIT10)                ///< Sleep Type
+#define V_ACPI_IO_PM1_CNT_S0                     0
+#define V_ACPI_IO_PM1_CNT_S1                     BIT10
+#define V_ACPI_IO_PM1_CNT_S3                     (BIT12 | BIT10)
+#define V_ACPI_IO_PM1_CNT_S4                     (BIT12 | BIT11)
+#define V_ACPI_IO_PM1_CNT_S5                     (BIT12 | BIT11 | BIT10)
+#define B_ACPI_IO_PM1_CNT_SCI_EN                 BIT0                                   ///< SCI Enable
+
+#define R_ACPI_IO_PM1_TMR                        0x08                                   ///< Power Management 1 Timer
+#define B_ACPI_IO_PM1_TMR_TMR_VAL                0xFFFFFF                               ///< Timer Value
+#define V_ACPI_IO_PM1_TMR_MAX_VAL                0x1000000       ///< The timer is 24 bit overflow
+
+#define R_ACPI_IO_SMI_EN                              0x30                              ///< SMI Control and Enable
+#define S_ACPI_IO_SMI_EN                              4
+#define B_ACPI_IO_SMI_EN_LEGACY_USB2                  BIT17
+#define B_ACPI_IO_SMI_EN_TCO                          BIT13
+#define B_ACPI_IO_SMI_EN_SWSMI_TMR                    BIT6
+#define B_ACPI_IO_SMI_EN_APMC                         BIT5
+#define B_ACPI_IO_SMI_EN_LEGACY_USB                   BIT3
+#define B_ACPI_IO_SMI_EN_EOS                          BIT1                              ///< End of SMI
+#define B_ACPI_IO_SMI_EN_GBL_SMI                      BIT0
+#define N_ACPI_IO_SMI_EN_LEGACY_USB3                  31
+#define N_ACPI_IO_SMI_EN_PERIODIC                     14
+#define N_ACPI_IO_SMI_EN_TCO                          13
+#define N_ACPI_IO_SMI_EN_MCSMI                        11
+#define N_ACPI_IO_SMI_EN_SWSMI_TMR                    6
+#define N_ACPI_IO_SMI_EN_APMC                         5
+#define N_ACPI_IO_SMI_EN_ON_SLP_EN                    4
+#define N_ACPI_IO_SMI_EN_LEGACY_USB                   3
+
+#define R_ACPI_IO_SMI_STS                             0x34                              ///< SMI Status Register
+#define S_ACPI_IO_SMI_STS                             4
+#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK                 BIT27
+#define B_ACPI_IO_SMI_STS_TCO                         BIT13
+#define B_ACPI_IO_SMI_STS_APM                         BIT5
+#define N_ACPI_IO_SMI_STS_LEGACY_USB3                 31
+#define N_ACPI_IO_SMI_STS_SPI                         26
+#define N_ACPI_IO_SMI_STS_SMBUS                       16
+#define N_ACPI_IO_SMI_STS_SERIRQ                      15
+#define N_ACPI_IO_SMI_STS_PERIODIC                    14
+#define N_ACPI_IO_SMI_STS_TCO                         13
+#define N_ACPI_IO_SMI_STS_MCSMI                       11
+#define N_ACPI_IO_SMI_STS_GPIO_SMI                    10
+#define N_ACPI_IO_SMI_STS_GPE0                        9
+#define N_ACPI_IO_SMI_STS_PM1_STS_REG                 8
+#define N_ACPI_IO_SMI_STS_SWSMI_TMR                   6
+#define N_ACPI_IO_SMI_STS_APM                         5
+#define N_ACPI_IO_SMI_STS_ON_SLP_EN                   4
+#define N_ACPI_IO_SMI_STS_LEGACY_USB                  3
+
+#define R_ACPI_IO_GPE0_STS_127_96                  0x6C                                 ///< General Purpose Event 0 Status [127:96]
+#define S_ACPI_IO_GPE0_STS_127_96                  4
+#define B_ACPI_IO_GPE0_STS_127_96_WADT             BIT18
+#define N_ACPI_IO_GPE0_STS_127_96_PME_B0           13
+#define N_ACPI_IO_GPE0_STS_127_96_PME              11
+#define R_ACPI_IO_GPE0_EN_127_96                   0x7C                                 ///< General Purpose Event 0 Enable [127:96]
+#define S_ACPI_IO_GPE0_EN_127_96                   4
+#define B_ACPI_IO_GPE0_EN_127_96_WADT              BIT18
+#define N_ACPI_IO_GPE0_EN_127_96_PME_B0            13
+#define N_ACPI_IO_GPE0_EN_127_96_PME               11
+
+//
+// PWRM Registers
+//
+#define R_PMC_PWRM_GEN_PMCON_A                              0x1020                        ///< General PM Configuration A
+#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL                   0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS              0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS              0x80
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS              0x40
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS             0x00
+#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL                  (BIT2|BIT1)                 ///< Period SMI Select
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S                  0x0000
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S                  0x0002
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S                  0x0004
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S                   0x0006
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
new file mode 100644
index 0000000000..8424ef5897
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
@@ -0,0 +1,44 @@
+/** @file
+  Register names for RTC device
+
+Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _REGS_RTC_H_
+#define _REGS_RTC_H_
+
+#define R_RTC_IO_INDEX_ALT                       0x74
+#define R_RTC_IO_TARGET_ALT                      0x75
+#define R_RTC_IO_EXT_INDEX_ALT                   0x76
+#define R_RTC_IO_REGD                            0x0D
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
new file mode 100644
index 0000000000..c3afcd5079
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
@@ -0,0 +1,71 @@
+/** @file
+  Register names for PCH TCO device
+
+  Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -H denoted by "_PCH_H_" in component name.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TCO_REGS_H_
+#define _TCO_REGS_H_
+
+//
+// TCO register I/O map
+//
+#define R_TCO_IO_TCO1_STS                            0x04
+#define S_TCO_IO_TCO1_STS                            2
+#define B_TCO_IO_TCO1_STS_DMISERR                    BIT12
+#define B_TCO_IO_TCO1_STS_DMISMI                     BIT10
+#define B_TCO_IO_TCO1_STS_DMISCI                     BIT9
+#define B_TCO_IO_TCO1_STS_BIOSWR                     BIT8
+#define B_TCO_IO_TCO1_STS_NEWCENTURY                 BIT7
+#define B_TCO_IO_TCO1_STS_TIMEOUT                    BIT3
+#define B_TCO_IO_TCO1_STS_TCO_INT                    BIT2
+#define B_TCO_IO_TCO1_STS_SW_TCO_SMI                 BIT1
+#define N_TCO_IO_TCO1_STS_DMISMI                     10
+#define N_TCO_IO_TCO1_STS_BIOSWR                     8
+#define N_TCO_IO_TCO1_STS_NEWCENTURY                 7
+#define N_TCO_IO_TCO1_STS_TIMEOUT                    3
+#define N_TCO_IO_TCO1_STS_SW_TCO_SMI                 1
+#define N_TCO_IO_TCO1_STS_NMI2SMI                    0
+
+#define R_TCO_IO_TCO2_STS                            0x06
+#define S_TCO_IO_TCO2_STS                            2
+#define N_TCO_IO_TCO2_STS_INTRD_DET                  0
+
+#define R_TCO_IO_TCO1_CNT                            0x08
+#define S_TCO_IO_TCO1_CNT                            2
+#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN                 9
+
+#define R_TCO_IO_TCO2_CNT                            0x0A
+#define S_TCO_IO_TCO2_CNT                            2
+#define N_TCO_IO_TCO2_CNT_INTRD_SEL                  2
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
new file mode 100644
index 0000000000..1829fb90ff
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
@@ -0,0 +1,226 @@
+/** @file
+  Serial IO policy
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_DEVICES_H_
+#define _SERIAL_IO_DEVICES_H_
+
+#include <Protocol/SerialIo.h>
+#include <PchLimits.h>
+
+#pragma pack (push,1)
+
+/**
+  Available working modes for SerialIo SPI Host Controller
+
+       0: SerialIoSpiDisabled;
+          - Device is placed in D3
+          - Gpio configuration is skipped
+          - PSF:
+          !important! If given device is Function 0 and other higher functions on given device
+                      are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+                      This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+    <b>1: SerialIoSpiPci;</b>
+          - Gpio pin configuration in native mode for each assigned pin
+          - Device will be enabled in PSF
+          - Only BAR0 will be enabled
+       2: SerialIoSpiHidden;
+          - Gpio pin configuration in native mode for each assigned pin
+          - Device disabled in the PSF
+          - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+          - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+       @note
+           If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+  SerialIoSpiDisabled,
+  SerialIoSpiPci,
+  SerialIoSpiHidden
+} SERIAL_IO_SPI_MODE;
+
+/**
+  Used to set Inactive/Idle polarity of Spi Chip Select
+**/
+typedef enum {
+  SerialIoSpiCsActiveLow  = 0,
+  SerialIoSpiCsActiveHigh = 1
+} SERIAL_IO_CS_POLARITY;
+
+/**
+  SPI signals pin muxing settings. If signal can be enable only on a single pin
+  then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h
+  for supported settings on a given platform
+**/
+typedef struct {
+  UINT32 Cs[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS];  ///< CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*
+  UINT32 Clk;                                    ///< CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*
+  UINT32 Miso;                                   ///< MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*
+  UINT32 Mosi;                                   ///< MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*
+} SPI_PIN_MUX;
+
+/**
+  The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
+**/
+typedef struct {
+  UINT8       Mode;                                          ///< <b>SerialIoSpiPci </b> see SERIAL_IO_SPI_MODE
+  UINT8       DefaultCsOutput;                               ///< <b>0 = CS0</b> CS1, CS2, CS3. Default CS used by the SPI HC
+  UINT8       CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI ChipSelect signal polarity, 0 = low <b>1 = High</b>
+  UINT8       CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS];   ///< <b>0 = Enable</b> 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
+  UINT8       CsMode;                                        ///< <b>0 = HW Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
+  UINT8       CsState;                                       ///< <b>0 = CS is set to low</b> 1 = CS is set to high
+  SPI_PIN_MUX PinMux;                                        ///< SPI Pinmux configuration
+} SERIAL_IO_SPI_CONFIG;
+
+/**
+  Available working modes for SerialIo UART Host Controller
+
+       0: SerialIoUartDisabled;
+          - Device is placed in D3
+          - Gpio configuration is skipped
+          - PSF:
+          !important! If given device is Function 0 and other higher functions on given device
+                      are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+                      This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+    <b>1: SerialIoUartPci;</b>
+          - Designated for Serial IO UART OS driver usage
+          - Gpio pin configuration in native mode for each assigned pin
+          - Device will be enabled in PSF
+          - Only BAR0 will be enabled
+       2: SerialIoUartHidden;
+          - Designated for BIOS and/or DBG2 OS kernel debug
+          - Gpio pin configuration in native mode for each assigned pin
+          - Device disabled in the PSF
+          - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+          - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+       @note
+           If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+       3: SerialIoUartCom;
+          - Designated for 16550/PNP0501 compatible COM device
+          - Gpio pin configuration in native mode for each assigned pin
+          - Device disabled in the PSF
+          - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+          - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+       4: SerialIoUartSkipInit;
+          - Gpio configuration is skipped
+          - PSF configuration is skipped
+          - BAR assignemnt is skipped
+          - D-satate setting is skipped
+
+**/
+typedef enum {
+  SerialIoUartDisabled,
+  SerialIoUartPci,
+  SerialIoUartHidden,
+  SerialIoUartCom,
+  SerialIoUartSkipInit
+} SERIAL_IO_UART_MODE;
+
+/**
+  UART Settings
+**/
+typedef struct {
+  UINT32      BaudRate;    ///< <b> 115200 </b> Max 6000000  MdePkg.dec  PcdUartDefaultBaudRate
+  UINT8       Parity;      ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
+  UINT8       DataBits;    ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
+  UINT8       StopBits;    ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE  MdePkg.dec  PcdUartDefaultStopBits
+  UINT8       AutoFlow;    ///< <b>FALSE</b>  IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
+} SERIAL_IO_UART_ATTRIBUTES;
+
+/**
+  UART signals pin muxing settings. If signal can be enable only on a single pin
+  then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
+  for supported settings on a given platform
+**/
+typedef struct {
+  UINT32 Rx;  ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
+  UINT32 Tx;  ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
+  UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
+  UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
+} UART_PIN_MUX;
+
+/**
+  Serial IO UART Controller Configuration
+**/
+typedef struct {
+  SERIAL_IO_UART_ATTRIBUTES Attributes;  ///< see SERIAL_IO_UART_ATTRIBUTES
+  UART_PIN_MUX              PinMux;      ///< UART pin mux configuration
+  UINT8                     Mode;        ///< <b> SerialIoUartPci </b> see SERIAL_IO_UART_MODE
+  UINT8                     DBG2;        ///< <b> FALSE </b> If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
+  UINT8                     PowerGating; ///< <b> SerialIoUartPgAuto </b> Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
+  UINT8                     DmaEnable;   ///< <b> TRUE </b> Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
+} SERIAL_IO_UART_CONFIG;
+
+typedef enum {
+  SerialIoUartPgDisabled,  ///< No _PS0/_PS3 support, device left in D0, after initialization
+/**
+  In mode: SerialIoUartCom;
+           _PS0/_PS3  that supports getting device out of reset
+  In mode: SerialIoUartPci
+           Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
+**/
+  SerialIoUartPgEnabled,
+  SerialIoUartPgAuto       ///< _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
+} SERIAL_IO_UART_PG;
+
+/**
+  Available working modes for SerialIo I2C Host Controller
+
+       0: SerialIoI2cDisabled;
+          - Device is placed in D3
+          - Gpio configuration is skipped
+          - PSF:
+          !important! If given device is Function 0 and other higher functions on given device
+                      are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+                      This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+    <b>1: SerialIoI2cPci;</b>
+          - Gpio pin configuration in native mode for each assigned pin
+          - Device will be enabled in PSF
+          - Only BAR0 will be enabled
+       2: SerialIoI2cHidden;
+          - Gpio pin configuration in native mode for each assigned pin
+          - Device disabled in the PSF
+          - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+          - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+       @note
+           If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+  SerialIoI2cDisabled,
+  SerialIoI2cPci,
+  SerialIoI2cHidden
+} SERIAL_IO_I2C_MODE;
+
+/**
+  I2C signals pin muxing settings. If signal can be enable only on a single pin
+  then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h
+  for supported settings on a given platform
+**/
+typedef struct {
+  UINT32   Sda;   ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
+  UINT32   Scl;   ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
+} I2C_PIN_MUX;
+
+/**
+  Serial IO I2C Controller Configuration
+**/
+typedef struct {
+  UINT8        Mode;        /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
+  /**
+    I2C Pads Internal Termination.
+    For more information please see Platform Design Guide.
+    Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
+    <b>GpioTermNone: No termination</b>,
+    GpioTermWpu1K: 1kOhm weak pull-up,
+    GpioTermWpu5K: 5kOhm weak pull-up,
+    GpioTermWpu20K: 20kOhm weak pull-up
+  **/
+  UINT8        PadTermination;
+  UINT8        Reserved[2];
+  I2C_PIN_MUX  PinMux;      ///< I2C pin mux configuration
+} SERIAL_IO_I2C_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_DEVICES_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
new file mode 100644
index 0000000000..089141d143
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
@@ -0,0 +1,17 @@
+/** @file
+  Silicon Config HOB is used for gathering platform
+  related Intel silicon information and config setting.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_HOB_H_
+#define _SI_CONFIG_HOB_H_
+
+#include <SiPolicyStruct.h>
+
+extern EFI_GUID gSiConfigHobGuid;
+
+// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB structure.
+typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA;
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
new file mode 100644
index 0000000000..4dacba242e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
@@ -0,0 +1,64 @@
+/** @file
+  Intel reference code configuration policies.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_STRUCT_H_
+#define _SI_POLICY_STRUCT_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/SiPreMemConfig.h>
+#include <ConfigBlock/SiConfig.h>
+
+/**
+  Silicon Policy revision number
+  Any change to this structure will result in an update in the revision number
+
+  This member specifies the revision of the Silicon Policy. This field is used to indicate change
+  to the policy structure.
+
+  <b>Revision 1</b>:
+   - Initial version.
+**/
+#define SI_POLICY_REVISION  1
+
+/**
+  Silicon pre-memory Policy revision number
+  Any change to this structure will result in an update in the revision number
+
+  <b>Revision 1</b>:
+   - Initial version.
+**/
+#define SI_PREMEM_POLICY_REVISION  1
+
+
+/**
+  SI Policy PPI in Pre-Mem\n
+  All SI config block change history will be listed here\n\n
+
+  - <b>Revision 1</b>:
+    - Initial version.\n
+**/
+struct _SI_PREMEM_POLICY_STRUCT {
+  CONFIG_BLOCK_TABLE_HEADER      TableHeader;   ///< Config Block Table Header
+/*
+  Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+/**
+  SI Policy PPI\n
+  All SI config block change history will be listed here\n\n
+
+  - <b>Revision 1</b>:
+    - Initial version.\n
+**/
+struct _SI_POLICY_STRUCT {
+  CONFIG_BLOCK_TABLE_HEADER      TableHeader;   ///< Config Block Table Header
+/*
+  Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+#endif
-- 
2.36.1.windows.1



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  parent reply	other threads:[~2023-09-15 23:57 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-15  4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
2023-09-15  4:45 ` [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components Saloni Kasbekar
2023-09-15  5:42   ` Chaganty, Rangasai V
2023-09-15 13:27     ` Chuang, Rosen
2023-09-15 23:56   ` Nate DeSimone
2023-09-15  4:45 ` [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components Saloni Kasbekar
2023-09-15  5:42   ` Chaganty, Rangasai V
2023-09-15 13:28     ` Chuang, Rosen
2023-09-15 23:56   ` Nate DeSimone
2023-09-15  4:45 ` [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components Saloni Kasbekar
2023-09-15  5:42   ` Chaganty, Rangasai V
2023-09-15 13:28     ` Chuang, Rosen
2023-09-15 23:56   ` Nate DeSimone
2023-09-15  4:45 ` [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers Saloni Kasbekar
2023-09-15  5:42   ` Chaganty, Rangasai V
2023-09-15 13:28     ` Chuang, Rosen
2023-09-15 23:56   ` Nate DeSimone
2023-09-15  4:45 ` [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes Saloni Kasbekar
2023-09-15  5:43   ` Chaganty, Rangasai V
2023-09-15 13:28     ` Chuang, Rosen
2023-09-15 23:56   ` Nate DeSimone
2023-09-15  4:45 ` [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes Saloni Kasbekar
2023-09-15  5:43   ` Chaganty, Rangasai V
2023-09-15 13:28     ` Chuang, Rosen
2023-09-15 23:56   ` Nate DeSimone [this message]
2023-09-15  4:45 ` [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru Saloni Kasbekar
2023-09-15  5:43   ` Chaganty, Rangasai V
2023-09-15 13:29     ` Chuang, Rosen
2023-09-15 23:56   ` Nate DeSimone
2023-09-15  4:45 ` [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Saloni Kasbekar
2023-09-15  5:43   ` Chaganty, Rangasai V
2023-09-15 13:29     ` Chuang, Rosen
2023-09-15 23:57   ` Nate DeSimone
2023-09-15  4:45 ` [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec Saloni Kasbekar
2023-09-15  5:43   ` Chaganty, Rangasai V
2023-09-15 13:29     ` Chuang, Rosen
2023-09-15 23:57   ` Nate DeSimone
2023-09-15  5:42 ` [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Chaganty, Rangasai V
2023-09-15 13:27   ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-16  0:26 ` Nate DeSimone

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