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Thread-Topic: [PATCH v4] Update CPUID Leaf 06H to follow latest SDM. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks William Looks good to me Reviewed-by: Kuo, Donald donald.kuo@intel.com -----Original Message----- From: Wang, William2 =20 Sent: Monday, January 16, 2023 4:50 PM To: devel@edk2.groups.io Cc: Wang, William2 ; Kinney, Michael D ; Gao, Liming ; Ni, Ray ; Kuo, Donald ; Kumar, Chandana C Subject: [PATCH v4] Update CPUID Leaf 06H to follow latest SDM. From: William2 Wang REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4262 Update CPUID Leaf 06H to follow latest SDM. Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni Cc: Donald Kuo Cc: Chandana C Kumar --- MdePkg/Include/Register/Intel/Cpuid.h | 59 +++++++++++++++++++- 1 file changed, 56 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Registe= r/Intel/Cpuid.h index 350bf60252..9569a8805a 100644 --- a/MdePkg/Include/Register/Intel/Cpuid.h +++ b/MdePkg/Include/Register/Intel/Cpuid.h @@ -1195,12 +1195,24 @@ typedef union { /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supporte= d if set. /// UINT32 FastAccessMode : 1; - UINT32 Reserved4 : 1; + /// + /// [Bit 19] IA32_HW_FEEDBACK_PTR MSR, IA32_HW_FEEDBACK_CONFIG MSR, + /// IA32_PACKAGE_THERM_STATUS MSR bit 26, and IA32_PACKAGE_THERM_INTER= RUPT MSR bit 25 are supported if set. + UINT32 HW_FEEDBACK : 1; /// /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported = if set. /// UINT32 IgnoringIdleLogicalProcessorHWPRequest : 1; - UINT32 Reserved5 : 11; + UINT32 Reserved3 : 2; + /// + /// [Bit 23] Intel Thread Director supported if set. IA32_HW_FEEDBACK_= CHAR and + /// IA32_HW_FEEDBACK_THREAD_CONFIG MSRs are supported if set. + UINT32 ThreadDirector : 1; + /// + /// [Bit 24] IA32_THERM_INTERRUPT MSR bit 25 is supported if set. + /// + UINT32 IA32_THERM_INTERRUPT : 1; + UINT32 Reserved4 : 7; } Bits; /// /// All bit fields as a 32-bit value @@ -1252,7 +1264,13 @@ typedef union { /// (1B0H). /// UINT32 PerformanceEnergyBias : 1; - UINT32 Reserved2 : 28; + UINT32 Reserved2 : 4; + /// + /// {Bit 15:8] Number of Intel Thread Director classes supported by th= e processor. Information for that + /// many classes is written into the Intel Thread Director Table by th= e hardware. + /// + UINT32 ThreadDirectorClasses : 8; + UINT32 Reserved3 : 16; } Bits; /// /// All bit fields as a 32-bit value @@ -1260,6 +1278,41 @@ typedef union { UINT32 Uint32; } CPUID_THERMAL_POWER_MANAGEMENT_ECX; =20 +/** + CPUID Thermal and Power Management Information returned in EDX for CPUID= leaf + #CPUID_THERMAL_POWER_MANAGEMENT. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// {Bits 7:0] Bitmap of supported hardware feedback interface capabil= ities. + /// 0 =3D When set to 1, indicates support for performance capabilit= y reporting. + /// 1 =3D When set to 1, indicates support for energy efficiency cap= ability reporting. + /// 2-7 =3D Reserved + /// + UINT32 InterfaceCapability : 8; + /// + /// {Bits 11:8] Enumerates the size of the hardware feedback interface= structure in number of 4 KB pages; + /// add one to the return value to get the result. + /// + UINT32 InterfaceStructureSize : 4; + UINT32 Reserved : 4; + /// + /// {Bits 31:16] : Index (starting at 0) of this logical processor's r= ow in the hardware feedback interface structure. + /// Note that on some parts the index may be same for multiple logical= processors. On some parts the + /// indices may not be contiguous, i.e., there may be unused rows in t= he hardware feedback interface structure. + /// + UINT32 LogicalProcessorRowIndex : 16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_THERMAL_POWER_MANAGEMENT_EDX; + /** CPUID Structured Extended Feature Flags Enumeration =20 --=20 2.34.1.windows.1