* [PATCH v2] Update Architecture MSR to follow latest SDM.
@ 2023-01-13 8:19 william2.wang
0 siblings, 0 replies; 3+ messages in thread
From: william2.wang @ 2023-01-13 8:19 UTC (permalink / raw)
To: devel
Cc: William2 Wang, Michael D Kinney, Liming Gao, Ray Ni, Donald Kuo,
Chandana C Kumar
From: William2 Wang <william2.wang@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4262
Update Architecture MSR contains the MSR10A.BIT23 and
MSR195.BIT2-0 for overclocking undervolt protection.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Donald Kuo <Donald.Kuo@intel.com>
Cc: Chandana C Kumar <chandana.c.kumar@intel.com>
---
MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 198 ++++++++++++++++++++
1 file changed, 198 insertions(+)
diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
index 071a8c689c..f548b56672 100644
--- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
+++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
@@ -682,6 +682,149 @@ typedef union {
UINT64 Uint64;
} MSR_IA32_MTRRCAP_REGISTER;
+/**
+ Enumeration of Architectural Features (R/O). If CPUID.(EAX=07H, ECX=0):EDX[29]=1.
+
+ @param ECX IA32_ARCH_CAPABILITIES (0x0000010A)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type IA32_ARCH_CAPABILITIES_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type IA32_ARCH_CAPABILITIES_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ IA32_ARCH_CAPABILITIES_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (IA32_ARCH_CAPABILITIES);
+ @endcode
+ @note IA32_ARCH_CAPABILITIES is defined as IA32_ARCH_CAPABILITIES in SDM.
+**/
+#define IA32_ARCH_CAPABILITIES 0x0000010A
+
+/**
+ MSR information returned for MSR index #IA32_ARCH_CAPABILITIES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 0] RDCL_NO: The processor is not susceptible to Rogue Data Cache Load (RDCL).
+ ///
+ UINT32 RDCL_NO : 1;
+ ///
+ /// [Bit 1] IBRS_ALL: The processor supports enhanced IBRS.
+ ///
+ UINT32 IBRS_ALL : 1;
+ ///
+ /// [Bit 2] RSBA: The processor supports RSB Alternate. Alternative branch predictors
+ /// may be used by RET instructions when the RSB is empty. SW using retpoline may be
+ /// affected by this behavior.
+ ///
+ UINT32 RSBA : 1;
+ ///
+ /// [Bit 3] SKIP_L1DFL_VMENTRY: A value of 1 indicates the hypervisor need not flush the
+ /// L1D on VM entry.
+ ///
+ UINT32 SKIP_L1DFL_VMENTRY : 1;
+ ///
+ /// [Bit 4] SSB_NO: Processor is not susceptible to Speculative Store Bypass.
+ ///
+ UINT32 SSB_NO : 1;
+ ///
+ /// [Bit 5] MDS_NO: Processor is not susceptible to Microarchitectural Data Sampling (MDS).
+ ///
+ UINT32 MDS_NO : 1;
+ ///
+ /// [Bit 6] IF_PSCHANGE_MC_NO: The processor is not susceptible to a machine check error due to
+ /// modifying the size of a code page without TLB invalidation.
+ ///
+ UINT32 IF_PSCHANGE_MC_NO : 1;
+ ///
+ /// [Bit 7] TSX_CTRL: If 1, indicates presence of IA32_TSX_CTRL MSR.
+ ///
+ UINT32 TSX_CTRL : 1;
+ ///
+ /// [Bit 8] TAA_NO: If 1, processor is not affected by TAA.
+ ///
+ UINT32 TAA_NO : 1;
+ UINT32 Reserved1 : 1;
+ ///
+ /// [Bit 10] MISC_PACKAGE_CTLS: The processor supports IA32_MISC_PACKAGE_CTLS MSR.
+ ///
+ UINT32 MISC_PACKAGE_CTLS : 1;
+ ///
+ /// [Bit 11] ENERGY_FILTERING_CTL: The processor supports setting and reading the
+ /// IA32_MISC_PACKAGE_CTLS[0] (ENERGY_FILTERING_ENABLE) bit.
+ ///
+ UINT32 ENERGY_FILTERING_CTL : 1;
+ ///
+ /// [Bit 12] DOITM: If 1, the processor supports Data Operand Independent Timing Mode.
+ ///
+ UINT32 DOITM : 1;
+ ///
+ /// [Bit 13] SBDR_SSDP_NO: The processor is not affected by either the Shared Buffers Data
+ /// Read (SBDR) vulnerability or the Sideband Stale Data Propagator (SSDP).
+ ///
+ UINT32 SBDR_SSDP_NO : 1;
+ ///
+ /// [Bit 14] FBSDP_NO: The processor is not affected by the Fill Buffer Stale Data Propagator (FBSDP).
+ ///
+ UINT32 FBSDP_NO : 1;
+ ///
+ /// [Bit 15] PSDP_NO: The processor is not affected by vulnerabilities involving the Primary Stale Data Propagator (PSDP).
+ ///
+ UINT32 PSDP_NO : 1;
+ UINT32 Reserved2 : 1;
+ ///
+ /// [Bit 17] FB_CLEAR: If 1, the processor supports overwrite of fill buffer values as part of MD_CLEAR operations
+ /// with the VERW instruction.
+ ///
+ UINT32 FB_CLEAR : 1;
+ ///
+ /// [Bit 18] FB_CLEAR_CTRL: If 1, the processor supports the IA32_MCU_OPT_CTRL MSR
+ /// and allows software to set bit 3 of that MSR (FB_CLEAR_DIS).
+ ///
+ UINT32 FB_CLEAR_CTRL : 1;
+ ///
+ /// [Bit 19] RRSBA: A value of 1 indicates the processor may have the RRSBA alternate prediction
+ /// behavior, if not disabled by RRSBA_DIS_U or RRSBA_DIS_S.
+ ///
+ UINT32 RRSBA : 1;
+ ///
+ /// [Bit 20] BHI_NO: A value of 1 indicates BHI_NO branch prediction behavior, regardless of
+ /// the value of IA32_SPEC_CTRL[BHI_DIS_S] MSR bit.
+ ///
+ UINT32 BHI_NO : 1;
+ //
+ /// [Bit 21] XAPIC_DISABLE_STATUS: Enumerates that the IA32_XAPIC_DISABLE_STATUS MSR exists,
+ /// and that bit 0 specifies whether the legacy xAPIC is disabled and APIC state is locked to x2APIC.
+ ///
+ UINT32 XAPIC_DISABLE_STATUS : 1;
+ UINT32 Reserved3 : 1;
+ ///
+ /// [Bit 23] OVERCLOCKING_STATUS: If set, the IA32_OVERCLOCKING_STATUS MSR exists.
+ ///
+ UINT32 OVERCLOCKING_STATUS : 1;
+ ///
+ /// [Bit 24] PBRSB_NO: If 1, the processor is not affected by issues related to Post-Barrier
+ /// Return Stack Buffer Predictions.
+ ///
+ UINT32 PBRSB_NO : 1;
+ UINT32 Reserved4 : 7;
+ UINT32 Reserved5 : 32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} IA32_ARCH_CAPABILITIES_REGISTER;
+
/**
SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@@ -1035,6 +1178,61 @@ typedef union {
UINT64 Uint64;
} MSR_IA32_PERFEVTSEL_REGISTER;
+/**
+ Overclocking Status (R/O) IA32_ARCH_CAPABILITIES[bit 23] enumerates support for this MSR.
+
+ @param ECX IA32_OVERCLOCKING_STATUS (0x00000195)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type IA32_OVERCLOCKING_STATUS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type IA32_OVERCLOCKING_STATUS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ IA32_OVERCLOCKING_STATUS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (IA32_OVERCLOCKING_STATUS);
+ @endcode
+ @note IA32_OVERCLOCKING_STATUS is defined as IA32_OVERCLOCKING_STATUS in SDM.
+**/
+#define IA32_OVERCLOCKING_STATUS 0x00000195
+
+/**
+ MSR information returned for MSR index #IA32_ARCH_CAPABILITIES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 0] Indicates if specific forms of overclocking have been enabled on this boot or reset
+ /// cycle: 0 indicates no, 1 indicates yes.
+ ///
+ UINT32 OverclockingUtilized : 1;
+ ///
+ /// [Bits 1] Indicates if the “Dynamic OC Undervolt Protection” security feature is active:
+ /// 0 indicates disabled, 1 indicates enabled.
+ ///
+ UINT32 UndervoltProtection : 1;
+ ///
+ /// [Bits 2] Indicates that overclocking capabilities have been unlocked by BIOS,
+ /// with or without overclocking: 0 indicates Not Secured, 1 indicates Secure.
+ ///
+ UINT32 OverclockingSecureStatus : 1;
+ UINT32 Reserved1 : 29;
+ UINT32 Reserved2 : 32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} IA32_OVERCLOCKING_STATUS_REGISTER;
+
/**
Current performance state(P-State) operating point (RO). Introduced at
Display Family / Display Model 0F_03H.
--
2.34.1.windows.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v2] Update Architecture MSR to follow latest SDM.
@ 2023-01-13 8:22 william2.wang
2023-01-16 8:47 ` Donald Kuo
0 siblings, 1 reply; 3+ messages in thread
From: william2.wang @ 2023-01-13 8:22 UTC (permalink / raw)
To: devel
Cc: William2 Wang, Michael D Kinney, Liming Gao, Ray Ni, Donald Kuo,
Chandana C Kumar
From: William2 Wang <william2.wang@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4263
Update Architecture MSR contains the MSR10A.BIT23 and
MSR195.BIT2-0 for overclocking undervolt protection.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Donald Kuo <Donald.Kuo@intel.com>
Cc: Chandana C Kumar <chandana.c.kumar@intel.com>
---
MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 198 ++++++++++++++++++++
1 file changed, 198 insertions(+)
diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
index 071a8c689c..f548b56672 100644
--- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
+++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
@@ -682,6 +682,149 @@ typedef union {
UINT64 Uint64;
} MSR_IA32_MTRRCAP_REGISTER;
+/**
+ Enumeration of Architectural Features (R/O). If CPUID.(EAX=07H, ECX=0):EDX[29]=1.
+
+ @param ECX IA32_ARCH_CAPABILITIES (0x0000010A)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type IA32_ARCH_CAPABILITIES_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type IA32_ARCH_CAPABILITIES_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ IA32_ARCH_CAPABILITIES_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (IA32_ARCH_CAPABILITIES);
+ @endcode
+ @note IA32_ARCH_CAPABILITIES is defined as IA32_ARCH_CAPABILITIES in SDM.
+**/
+#define IA32_ARCH_CAPABILITIES 0x0000010A
+
+/**
+ MSR information returned for MSR index #IA32_ARCH_CAPABILITIES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 0] RDCL_NO: The processor is not susceptible to Rogue Data Cache Load (RDCL).
+ ///
+ UINT32 RDCL_NO : 1;
+ ///
+ /// [Bit 1] IBRS_ALL: The processor supports enhanced IBRS.
+ ///
+ UINT32 IBRS_ALL : 1;
+ ///
+ /// [Bit 2] RSBA: The processor supports RSB Alternate. Alternative branch predictors
+ /// may be used by RET instructions when the RSB is empty. SW using retpoline may be
+ /// affected by this behavior.
+ ///
+ UINT32 RSBA : 1;
+ ///
+ /// [Bit 3] SKIP_L1DFL_VMENTRY: A value of 1 indicates the hypervisor need not flush the
+ /// L1D on VM entry.
+ ///
+ UINT32 SKIP_L1DFL_VMENTRY : 1;
+ ///
+ /// [Bit 4] SSB_NO: Processor is not susceptible to Speculative Store Bypass.
+ ///
+ UINT32 SSB_NO : 1;
+ ///
+ /// [Bit 5] MDS_NO: Processor is not susceptible to Microarchitectural Data Sampling (MDS).
+ ///
+ UINT32 MDS_NO : 1;
+ ///
+ /// [Bit 6] IF_PSCHANGE_MC_NO: The processor is not susceptible to a machine check error due to
+ /// modifying the size of a code page without TLB invalidation.
+ ///
+ UINT32 IF_PSCHANGE_MC_NO : 1;
+ ///
+ /// [Bit 7] TSX_CTRL: If 1, indicates presence of IA32_TSX_CTRL MSR.
+ ///
+ UINT32 TSX_CTRL : 1;
+ ///
+ /// [Bit 8] TAA_NO: If 1, processor is not affected by TAA.
+ ///
+ UINT32 TAA_NO : 1;
+ UINT32 Reserved1 : 1;
+ ///
+ /// [Bit 10] MISC_PACKAGE_CTLS: The processor supports IA32_MISC_PACKAGE_CTLS MSR.
+ ///
+ UINT32 MISC_PACKAGE_CTLS : 1;
+ ///
+ /// [Bit 11] ENERGY_FILTERING_CTL: The processor supports setting and reading the
+ /// IA32_MISC_PACKAGE_CTLS[0] (ENERGY_FILTERING_ENABLE) bit.
+ ///
+ UINT32 ENERGY_FILTERING_CTL : 1;
+ ///
+ /// [Bit 12] DOITM: If 1, the processor supports Data Operand Independent Timing Mode.
+ ///
+ UINT32 DOITM : 1;
+ ///
+ /// [Bit 13] SBDR_SSDP_NO: The processor is not affected by either the Shared Buffers Data
+ /// Read (SBDR) vulnerability or the Sideband Stale Data Propagator (SSDP).
+ ///
+ UINT32 SBDR_SSDP_NO : 1;
+ ///
+ /// [Bit 14] FBSDP_NO: The processor is not affected by the Fill Buffer Stale Data Propagator (FBSDP).
+ ///
+ UINT32 FBSDP_NO : 1;
+ ///
+ /// [Bit 15] PSDP_NO: The processor is not affected by vulnerabilities involving the Primary Stale Data Propagator (PSDP).
+ ///
+ UINT32 PSDP_NO : 1;
+ UINT32 Reserved2 : 1;
+ ///
+ /// [Bit 17] FB_CLEAR: If 1, the processor supports overwrite of fill buffer values as part of MD_CLEAR operations
+ /// with the VERW instruction.
+ ///
+ UINT32 FB_CLEAR : 1;
+ ///
+ /// [Bit 18] FB_CLEAR_CTRL: If 1, the processor supports the IA32_MCU_OPT_CTRL MSR
+ /// and allows software to set bit 3 of that MSR (FB_CLEAR_DIS).
+ ///
+ UINT32 FB_CLEAR_CTRL : 1;
+ ///
+ /// [Bit 19] RRSBA: A value of 1 indicates the processor may have the RRSBA alternate prediction
+ /// behavior, if not disabled by RRSBA_DIS_U or RRSBA_DIS_S.
+ ///
+ UINT32 RRSBA : 1;
+ ///
+ /// [Bit 20] BHI_NO: A value of 1 indicates BHI_NO branch prediction behavior, regardless of
+ /// the value of IA32_SPEC_CTRL[BHI_DIS_S] MSR bit.
+ ///
+ UINT32 BHI_NO : 1;
+ //
+ /// [Bit 21] XAPIC_DISABLE_STATUS: Enumerates that the IA32_XAPIC_DISABLE_STATUS MSR exists,
+ /// and that bit 0 specifies whether the legacy xAPIC is disabled and APIC state is locked to x2APIC.
+ ///
+ UINT32 XAPIC_DISABLE_STATUS : 1;
+ UINT32 Reserved3 : 1;
+ ///
+ /// [Bit 23] OVERCLOCKING_STATUS: If set, the IA32_OVERCLOCKING_STATUS MSR exists.
+ ///
+ UINT32 OVERCLOCKING_STATUS : 1;
+ ///
+ /// [Bit 24] PBRSB_NO: If 1, the processor is not affected by issues related to Post-Barrier
+ /// Return Stack Buffer Predictions.
+ ///
+ UINT32 PBRSB_NO : 1;
+ UINT32 Reserved4 : 7;
+ UINT32 Reserved5 : 32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} IA32_ARCH_CAPABILITIES_REGISTER;
+
/**
SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@@ -1035,6 +1178,61 @@ typedef union {
UINT64 Uint64;
} MSR_IA32_PERFEVTSEL_REGISTER;
+/**
+ Overclocking Status (R/O) IA32_ARCH_CAPABILITIES[bit 23] enumerates support for this MSR.
+
+ @param ECX IA32_OVERCLOCKING_STATUS (0x00000195)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type IA32_OVERCLOCKING_STATUS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type IA32_OVERCLOCKING_STATUS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ IA32_OVERCLOCKING_STATUS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (IA32_OVERCLOCKING_STATUS);
+ @endcode
+ @note IA32_OVERCLOCKING_STATUS is defined as IA32_OVERCLOCKING_STATUS in SDM.
+**/
+#define IA32_OVERCLOCKING_STATUS 0x00000195
+
+/**
+ MSR information returned for MSR index #IA32_ARCH_CAPABILITIES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 0] Indicates if specific forms of overclocking have been enabled on this boot or reset
+ /// cycle: 0 indicates no, 1 indicates yes.
+ ///
+ UINT32 OverclockingUtilized : 1;
+ ///
+ /// [Bits 1] Indicates if the “Dynamic OC Undervolt Protection” security feature is active:
+ /// 0 indicates disabled, 1 indicates enabled.
+ ///
+ UINT32 UndervoltProtection : 1;
+ ///
+ /// [Bits 2] Indicates that overclocking capabilities have been unlocked by BIOS,
+ /// with or without overclocking: 0 indicates Not Secured, 1 indicates Secure.
+ ///
+ UINT32 OverclockingSecureStatus : 1;
+ UINT32 Reserved1 : 29;
+ UINT32 Reserved2 : 32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} IA32_OVERCLOCKING_STATUS_REGISTER;
+
/**
Current performance state(P-State) operating point (RO). Introduced at
Display Family / Display Model 0F_03H.
--
2.34.1.windows.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] Update Architecture MSR to follow latest SDM.
2023-01-13 8:22 [PATCH v2] Update Architecture MSR to follow latest SDM william2.wang
@ 2023-01-16 8:47 ` Donald Kuo
0 siblings, 0 replies; 3+ messages in thread
From: Donald Kuo @ 2023-01-16 8:47 UTC (permalink / raw)
To: Wang, William2, devel@edk2.groups.io
Cc: Kinney, Michael D, Gao, Liming, Ni, Ray, Kumar, Chandana C
Hi William
Looks good to me
Reviewed-by: Kuo, Donald donald.kuo@intel.com
-----Original Message-----
From: Wang, William2 <william2.wang@intel.com>
Sent: Friday, January 13, 2023 4:22 PM
To: devel@edk2.groups.io
Cc: Wang, William2 <william2.wang@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Ni, Ray <ray.ni@intel.com>; Kuo, Donald <donald.kuo@intel.com>; Kumar, Chandana C <chandana.c.kumar@intel.com>
Subject: [PATCH v2] Update Architecture MSR to follow latest SDM.
From: William2 Wang <william2.wang@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4263
Update Architecture MSR contains the MSR10A.BIT23 and
MSR195.BIT2-0 for overclocking undervolt protection.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Donald Kuo <Donald.Kuo@intel.com>
Cc: Chandana C Kumar <chandana.c.kumar@intel.com>
---
MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 198 ++++++++++++++++++++
1 file changed, 198 insertions(+)
diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
index 071a8c689c..f548b56672 100644
--- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
+++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
@@ -682,6 +682,149 @@ typedef union {
UINT64 Uint64;
} MSR_IA32_MTRRCAP_REGISTER;
+/**
+ Enumeration of Architectural Features (R/O). If CPUID.(EAX=07H, ECX=0):EDX[29]=1.
+
+ @param ECX IA32_ARCH_CAPABILITIES (0x0000010A)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type IA32_ARCH_CAPABILITIES_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type IA32_ARCH_CAPABILITIES_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ IA32_ARCH_CAPABILITIES_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (IA32_ARCH_CAPABILITIES);
+ @endcode
+ @note IA32_ARCH_CAPABILITIES is defined as IA32_ARCH_CAPABILITIES in SDM.
+**/
+#define IA32_ARCH_CAPABILITIES 0x0000010A
+
+/**
+ MSR information returned for MSR index #IA32_ARCH_CAPABILITIES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 0] RDCL_NO: The processor is not susceptible to Rogue Data Cache Load (RDCL).
+ ///
+ UINT32 RDCL_NO : 1;
+ ///
+ /// [Bit 1] IBRS_ALL: The processor supports enhanced IBRS.
+ ///
+ UINT32 IBRS_ALL : 1;
+ ///
+ /// [Bit 2] RSBA: The processor supports RSB Alternate. Alternative branch predictors
+ /// may be used by RET instructions when the RSB is empty. SW using retpoline may be
+ /// affected by this behavior.
+ ///
+ UINT32 RSBA : 1;
+ ///
+ /// [Bit 3] SKIP_L1DFL_VMENTRY: A value of 1 indicates the hypervisor need not flush the
+ /// L1D on VM entry.
+ ///
+ UINT32 SKIP_L1DFL_VMENTRY : 1;
+ ///
+ /// [Bit 4] SSB_NO: Processor is not susceptible to Speculative Store Bypass.
+ ///
+ UINT32 SSB_NO : 1;
+ ///
+ /// [Bit 5] MDS_NO: Processor is not susceptible to Microarchitectural Data Sampling (MDS).
+ ///
+ UINT32 MDS_NO : 1;
+ ///
+ /// [Bit 6] IF_PSCHANGE_MC_NO: The processor is not susceptible to a machine check error due to
+ /// modifying the size of a code page without TLB invalidation.
+ ///
+ UINT32 IF_PSCHANGE_MC_NO : 1;
+ ///
+ /// [Bit 7] TSX_CTRL: If 1, indicates presence of IA32_TSX_CTRL MSR.
+ ///
+ UINT32 TSX_CTRL : 1;
+ ///
+ /// [Bit 8] TAA_NO: If 1, processor is not affected by TAA.
+ ///
+ UINT32 TAA_NO : 1;
+ UINT32 Reserved1 : 1;
+ ///
+ /// [Bit 10] MISC_PACKAGE_CTLS: The processor supports IA32_MISC_PACKAGE_CTLS MSR.
+ ///
+ UINT32 MISC_PACKAGE_CTLS : 1;
+ ///
+ /// [Bit 11] ENERGY_FILTERING_CTL: The processor supports setting and reading the
+ /// IA32_MISC_PACKAGE_CTLS[0] (ENERGY_FILTERING_ENABLE) bit.
+ ///
+ UINT32 ENERGY_FILTERING_CTL : 1;
+ ///
+ /// [Bit 12] DOITM: If 1, the processor supports Data Operand Independent Timing Mode.
+ ///
+ UINT32 DOITM : 1;
+ ///
+ /// [Bit 13] SBDR_SSDP_NO: The processor is not affected by either the Shared Buffers Data
+ /// Read (SBDR) vulnerability or the Sideband Stale Data Propagator (SSDP).
+ ///
+ UINT32 SBDR_SSDP_NO : 1;
+ ///
+ /// [Bit 14] FBSDP_NO: The processor is not affected by the Fill Buffer Stale Data Propagator (FBSDP).
+ ///
+ UINT32 FBSDP_NO : 1;
+ ///
+ /// [Bit 15] PSDP_NO: The processor is not affected by vulnerabilities involving the Primary Stale Data Propagator (PSDP).
+ ///
+ UINT32 PSDP_NO : 1;
+ UINT32 Reserved2 : 1;
+ ///
+ /// [Bit 17] FB_CLEAR: If 1, the processor supports overwrite of fill buffer values as part of MD_CLEAR operations
+ /// with the VERW instruction.
+ ///
+ UINT32 FB_CLEAR : 1;
+ ///
+ /// [Bit 18] FB_CLEAR_CTRL: If 1, the processor supports the IA32_MCU_OPT_CTRL MSR
+ /// and allows software to set bit 3 of that MSR (FB_CLEAR_DIS).
+ ///
+ UINT32 FB_CLEAR_CTRL : 1;
+ ///
+ /// [Bit 19] RRSBA: A value of 1 indicates the processor may have the RRSBA alternate prediction
+ /// behavior, if not disabled by RRSBA_DIS_U or RRSBA_DIS_S.
+ ///
+ UINT32 RRSBA : 1;
+ ///
+ /// [Bit 20] BHI_NO: A value of 1 indicates BHI_NO branch prediction behavior, regardless of
+ /// the value of IA32_SPEC_CTRL[BHI_DIS_S] MSR bit.
+ ///
+ UINT32 BHI_NO : 1;
+ //
+ /// [Bit 21] XAPIC_DISABLE_STATUS: Enumerates that the IA32_XAPIC_DISABLE_STATUS MSR exists,
+ /// and that bit 0 specifies whether the legacy xAPIC is disabled and APIC state is locked to x2APIC.
+ ///
+ UINT32 XAPIC_DISABLE_STATUS : 1;
+ UINT32 Reserved3 : 1;
+ ///
+ /// [Bit 23] OVERCLOCKING_STATUS: If set, the IA32_OVERCLOCKING_STATUS MSR exists.
+ ///
+ UINT32 OVERCLOCKING_STATUS : 1;
+ ///
+ /// [Bit 24] PBRSB_NO: If 1, the processor is not affected by issues related to Post-Barrier
+ /// Return Stack Buffer Predictions.
+ ///
+ UINT32 PBRSB_NO : 1;
+ UINT32 Reserved4 : 7;
+ UINT32 Reserved5 : 32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} IA32_ARCH_CAPABILITIES_REGISTER;
+
/**
SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@@ -1035,6 +1178,61 @@ typedef union {
UINT64 Uint64;
} MSR_IA32_PERFEVTSEL_REGISTER;
+/**
+ Overclocking Status (R/O) IA32_ARCH_CAPABILITIES[bit 23] enumerates support for this MSR.
+
+ @param ECX IA32_OVERCLOCKING_STATUS (0x00000195)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type IA32_OVERCLOCKING_STATUS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type IA32_OVERCLOCKING_STATUS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ IA32_OVERCLOCKING_STATUS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (IA32_OVERCLOCKING_STATUS);
+ @endcode
+ @note IA32_OVERCLOCKING_STATUS is defined as IA32_OVERCLOCKING_STATUS in SDM.
+**/
+#define IA32_OVERCLOCKING_STATUS 0x00000195
+
+/**
+ MSR information returned for MSR index #IA32_ARCH_CAPABILITIES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 0] Indicates if specific forms of overclocking have been enabled on this boot or reset
+ /// cycle: 0 indicates no, 1 indicates yes.
+ ///
+ UINT32 OverclockingUtilized : 1;
+ ///
+ /// [Bits 1] Indicates if the “Dynamic OC Undervolt Protection” security feature is active:
+ /// 0 indicates disabled, 1 indicates enabled.
+ ///
+ UINT32 UndervoltProtection : 1;
+ ///
+ /// [Bits 2] Indicates that overclocking capabilities have been unlocked by BIOS,
+ /// with or without overclocking: 0 indicates Not Secured, 1 indicates Secure.
+ ///
+ UINT32 OverclockingSecureStatus : 1;
+ UINT32 Reserved1 : 29;
+ UINT32 Reserved2 : 32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} IA32_OVERCLOCKING_STATUS_REGISTER;
+
/**
Current performance state(P-State) operating point (RO). Introduced at
Display Family / Display Model 0F_03H.
--
2.34.1.windows.1
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