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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ankit Sinha > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Monday, June 6, 2022 3:51 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Sinha, Ankit > ; Kubacki, Michael > ; Luo, Heng > Subject: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate > width of CLK duty cycle in FADT >=20 > Set the location of the DUTY_CYCLE field in the P_CNT register and indica= te > the width of the clock duty cycle to OS power management >=20 > Cc: Sai Chaganty > Cc: Ankit Sinha > Cc: Michael Kubacki > Cc: Heng Luo > Signed-off-by: Nate DeSimone > --- > .../TigerlakeURvp/OpenBoardPkgPcd.dsc | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd > .dsc > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd > .dsc > index ebbbc7b9f9..aba3c8d6d0 100644 > --- > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd > .dsc > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd > +++ .dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the TigerlakeURvp board. > # > -# Copyright (c) 2021, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021 - 2022, Intel Corporation. All rights > +reserved.
> # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -118,6 +118,14 > @@ > gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 > #!endif > gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000 > + > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register # > + and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + > [PcdsFeatureFlag.common] > ###################################### > # Edk2 Configuration > -- > 2.27.0.windows.1