From: "Nate DeSimone" <nathaniel.l.desimone@intel.com>
To: Ling Jia <jialing@phytium.com.cn>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: Leif Lindholm <leif@nuviainc.com>,
Peng Xie <xiepeng@phytium.com.cn>,
"Yiqi Shu" <shuyiqi@phytium.com.cn>,
Takuto Naito <naitaku@gmail.com>,
"Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>,
"Luo, Heng" <heng.luo@intel.com>
Subject: Re: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5
Date: Thu, 1 Apr 2021 19:19:58 +0000 [thread overview]
Message-ID: <MWHPR1101MB21601498692499669672BB9ACD7B9@MWHPR1101MB2160.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210312105618.75605-2-jialing@phytium.com.cn>
Hi Ling,
This appears to be a duplicate of a patch that has already been applied:
https://edk2.groups.io/g/devel/message/71894
https://github.com/tianocore/edk2-platforms/commit/12ef75dc
Was this message sent in error?
Thanks,
Nate
> -----Original Message-----
> From: Ling Jia <jialing@phytium.com.cn>
> Sent: Friday, March 12, 2021 2:56 AM
> To: devel@edk2.groups.io
> Cc: Leif Lindholm <leif@nuviainc.com>; Peng Xie
> <xiepeng@phytium.com.cn>; Yiqi Shu <shuyiqi@phytium.com.cn>; Takuto
> Naito <naitaku@gmail.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Luo, Heng <heng.luo@intel.com>
> Subject: [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with
> GCC5
>
> From: Takuto Naito <naitaku@gmail.com>
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224
>
> - Fix the path of TigerLakeFspBinPkg
> - Fix misuse of RETURN_ERROR
> - Remove unused function CheckNationalSio.
>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Heng Luo <heng.luo@intel.com>
> Signed-off-by: Takuto Naito <naitaku@gmail.com>
> Reviewed-by: Heng Luo <heng.luo@intel.com>
> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>
> Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit
> Lib/PeiFspPolicyInitLib.inf | 2 +-
>
> Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl
> atformHookLib.c | 188 --------------------
>
> Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat
> eLib/DxeSiliconPolicyUpdateLate.c | 2 +-
> 3 files changed, 2 insertions(+), 190 deletions(-)
>
> diff --git
> a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI
> nitLib/PeiFspPolicyInitLib.inf
> b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI
> nitLib/PeiFspPolicyInitLib.inf
> index 9d85d855f501..708fbac08fd6 100644
> ---
> a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI
> nitLib/PeiFspPolicyInitLib.inf
> +++
> b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI
> nitLib/PeiFspPolicyInitLib.inf
> @@ -52,7 +52,7 @@ [Packages]
> MdeModulePkg/MdeModulePkg.dec
>
> IntelFsp2Pkg/IntelFsp2Pkg.dec
>
> TigerlakeSiliconPkg/SiPkg.dec
>
> - TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec
>
> + TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec
>
> TigerlakeOpenBoardPkg/OpenBoardPkg.dec
>
> UefiCpuPkg/UefiCpuPkg.dec
>
> IntelSiliconPkg/IntelSiliconPkg.dec
>
> diff --git
> a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas
> ePlatformHookLib.c
> b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas
> ePlatformHookLib.c
> index 6209e5045061..cc5337698b8a 100644
> ---
> a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas
> ePlatformHookLib.c
> +++
> b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Bas
> ePlatformHookLib.c
> @@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED
> EFI_SIO_TABLE mSioTableWinbond_x374[] = {
> {0x30, 0x01} // Enable it with Activation bit
>
> };
>
>
>
> -/**
>
> - Detect if a National 393 SIO is docked. If yes, enable the docked SIO
>
> - and its serial port, and disable the onboard serial port.
>
> -
>
> - @retval EFI_SUCCESS Operations performed successfully.
>
> -**/
>
> -STATIC
>
> -VOID
>
> -CheckNationalSio (
>
> - VOID
>
> - )
>
> -{
>
> - UINT8 Data8;
>
> -
>
> - //
>
> - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).
>
> - // We use (0x2e, 0x2f) which is determined by BADD default strapping
>
> - //
>
> -
>
> - //
>
> - // Read the Pc87393 signature
>
> - //
>
> - IoWrite8 (0x2e, 0x20);
>
> - Data8 = IoRead8 (0x2f);
>
> -
>
> - if (Data8 == 0xea) {
>
> - //
>
> - // Signature matches - National PC87393 SIO is docked
>
> - //
>
> -
>
> - //
>
> - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch
>
> - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated
> at
>
> - // SIO_BASE_ADDRESS + 0x10)
>
> - //
>
> - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) &
> (UINT16)~0x7F), 0x20);
>
> -
>
> - //
>
> - // Enable port switch
>
> - //
>
> - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);
>
> -
>
> - //
>
> - // Turn on docking power
>
> - //
>
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);
>
> -
>
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);
>
> -
>
> - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);
>
> -
>
> - //
>
> - // Enable port switch
>
> - //
>
> - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);
>
> -
>
> - //
>
> - // GPIO setting
>
> - //
>
> - IoWrite8 (0x2e, 0x24);
>
> - IoWrite8 (0x2f, 0x29);
>
> -
>
> - //
>
> - // Enable chip clock
>
> - //
>
> - IoWrite8 (0x2e, 0x29);
>
> - IoWrite8 (0x2f, 0x1e);
>
> -
>
> -
>
> - //
>
> - // Enable serial port
>
> - //
>
> -
>
> - //
>
> - // Select com1
>
> - //
>
> - IoWrite8 (0x2e, 0x7);
>
> - IoWrite8 (0x2f, 0x3);
>
> -
>
> - //
>
> - // Base address: 0x3f8
>
> - //
>
> - IoWrite8 (0x2e, 0x60);
>
> - IoWrite8 (0x2f, 0x03);
>
> - IoWrite8 (0x2e, 0x61);
>
> - IoWrite8 (0x2f, 0xf8);
>
> -
>
> - //
>
> - // Interrupt: 4
>
> - //
>
> - IoWrite8 (0x2e, 0x70);
>
> - IoWrite8 (0x2f, 0x04);
>
> -
>
> - //
>
> - // Enable bank selection
>
> - //
>
> - IoWrite8 (0x2e, 0xf0);
>
> - IoWrite8 (0x2f, 0x82);
>
> -
>
> - //
>
> - // Activate
>
> - //
>
> - IoWrite8 (0x2e, 0x30);
>
> - IoWrite8 (0x2f, 0x01);
>
> -
>
> - //
>
> - // Disable onboard serial port
>
> - //
>
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);
>
> -
>
> - //
>
> - // Power Down UARTs
>
> - //
>
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);
>
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);
>
> -
>
> - //
>
> - // Dissable COM1 decode
>
> - //
>
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);
>
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
>
> -
>
> - //
>
> - // Disable COM2 decode
>
> - //
>
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);
>
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
>
> -
>
> - //
>
> - // Disable interrupt
>
> - //
>
> - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);
>
> - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);
>
> -
>
> - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
>
> -
>
> - //
>
> - // Enable floppy
>
> - //
>
> -
>
> - //
>
> - // Select floppy
>
> - //
>
> - IoWrite8 (0x2e, 0x7);
>
> - IoWrite8 (0x2f, 0x0);
>
> -
>
> - //
>
> - // Base address: 0x3f0
>
> - //
>
> - IoWrite8 (0x2e, 0x60);
>
> - IoWrite8 (0x2f, 0x03);
>
> - IoWrite8 (0x2e, 0x61);
>
> - IoWrite8 (0x2f, 0xf0);
>
> -
>
> - //
>
> - // Interrupt: 6
>
> - //
>
> - IoWrite8 (0x2e, 0x70);
>
> - IoWrite8 (0x2f, 0x06);
>
> -
>
> - //
>
> - // DMA 2
>
> - //
>
> - IoWrite8 (0x2e, 0x74);
>
> - IoWrite8 (0x2f, 0x02);
>
> -
>
> - //
>
> - // Activate
>
> - //
>
> - IoWrite8 (0x2e, 0x30);
>
> - IoWrite8 (0x2f, 0x01);
>
> -
>
> - } else {
>
> -
>
> - //
>
> - // No National pc87393 SIO is docked, turn off dock power and
>
> - // disable port switch
>
> - //
>
> - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);
>
> - // IoWrite8 (0x690, 0);
>
> -
>
> - //
>
> - // If no National pc87393, just return
>
> - //
>
> - return ;
>
> - }
>
> -}
>
> -
>
> /**
>
> Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports
>
>
>
> diff --git
> a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd
> ateLib/DxeSiliconPolicyUpdateLate.c
> b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUp
> dateLib/DxeSiliconPolicyUpdateLate.c
> index 2eee9958beea..410a8d1073a9 100644
> ---
> a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd
> ateLib/DxeSiliconPolicyUpdateLate.c
> +++
> b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUp
> dateLib/DxeSiliconPolicyUpdateLate.c
> @@ -88,8 +88,8 @@ SiliconPolicyUpdateLate (
> // GOP Dxe Policy Initialization
>
> //
>
> Status = GopPolicyInitDxe (gImageHandle);
>
> - RETURN_ERROR (Status);
>
> DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
>
> + ASSERT_EFI_ERROR (Status);
>
> }
>
>
>
> return Policy;
>
> --
> 2.25.1
next prev parent reply other threads:[~2021-04-01 19:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-12 10:55 [PATCH v3 00/46] Added support for FT2000/4 chip Ling Jia
2021-03-12 10:55 ` [PATCH v3 01/46] TigerlakeOpenBoardPkg: Fix build errors with GCC5 Ling Jia
2021-04-01 19:19 ` Nate DeSimone [this message]
2021-04-02 8:46 ` Ling Jia
2021-03-12 10:55 ` [PATCH v3 14/46] Silicon/Phytium: Added Acpi support to FT2000/4 Ling Jia
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