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charset="Windows-1252" Content-Transfer-Encoding: quoted-printable Hi Everyone, We are pleased to announce that the FSP External Architecture Specification= v2.2 has been posted to https://www.intel.com/fsp!=20 Highlights * Multi-Phase Silicon Initialization =96 A new optional API has been added = to FSP-S to address some of the ongoing community feedback surrounding FSP-= S. In general, the feedback has been that FSP-S is too monolithic. FspSilic= onInit() does a large amount of initialization in one API call; so much tha= t it has made integration difficult in some cases. For example, firmware up= date/recovery flows. To address this, a new FspMultiPhaseSiInit() API has b= een added which splits FSP-S into multiple parts. This allows the bootloade= r to add board specific code throughout the SiliconInit flow as needed. The= breakdown of silicon initialization steps may vary per product and will be= detailed in the Integration Guide. FspMultiPhaseSiInit() is only used in A= PI mode. In dispatch mode, equivalent functionality can be achieved using P= PIs with less complexity. * FSP Event Handlers =96 This new feature enables FSP to generate events me= ssages to aid in the debugging of firmware issues. This eliminates the need= for FSP to directly write debug messages to the UART. Instead FSP signals = the bootloader to inform it of a new debug message. This allows the bootloa= der to provide board specific methods of reporting debug messages beyond th= e UART. This brings feature parity between dispatch mode and API mode as FS= P 2.1 defined a similar method for dispatch mode. This change also helps dispatch mode as well. Since it provides a means for= FSP-T and early PEI to output debug message before the status code service= s PEIMs are initialized. Roadmap TigerLakeFspBinPkg provides the first implementation of FSP 2.2. Tiger Lake= FSP implements 2 phases for FSP-S: FspSiliconInit() will return after TCSS= (=93Type-C Sub System=94 =96 Integrated USB-C & Thunderbolt 4) initializat= ion is complete. The second phase, invoked by FspMultiPhaseSiInit(), will i= nitialize the graphics framebuffer and lock SAI/SPI writes. This allows boa= rd specific USB-C programming to be done before FSP attempts to start early= video, and also provides a potentially convenient location for firmware up= date flows. Looking forward, our upcoming Alder Lake platform will also hav= e FSP 2.2 support.