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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Chasel, Thank you for the feedback. I have resolved it before push. Thanks, Nate -----Original Message----- From: Chiu, Chasel =20 Sent: Tuesday, July 20, 2021 9:07 PM To: Desimone, Nathaniel L ; devel@edk2.grou= ps.io Cc: Oram, Isaac W Subject: RE: [edk2-platforms] [PATCH V1] WhitleySiliconPkg: Improve comment= s for silicon policy structures Hi Nate, Just one small feedbacks inline, please check them. With that resolved: Reviewed-by: Chasel Chiu =20 Thanks, Chasel > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Wednesday, July 21, 2021 4:22 AM > To: devel@edk2.groups.io > Cc: Oram, Isaac W ; Chiu, Chasel=20 > > Subject: [edk2-platforms] [PATCH V1] WhitleySiliconPkg: Improve=20 > comments for silicon policy structures >=20 > Signed-off-by: Nate DeSimone > Cc: Isaac Oram > Cc: Chasel Chiu > --- > .../Include/Ppi/RasImcS3Data.h | 6 + > .../Include/Ppi/UpiPolicyPpi.h | 5 +- > .../WhitleySiliconPkg/Include/Upi/KtiHost.h | 250 +++++++++--------- > .../SouthClusterLbg/Include/PchPolicyCommon.h | 9 + > .../SecurityIp/SecurityIpMkTme1v0_Inputs.h | 8 +- > .../SecurityIp/SecurityIpMkTme1v0_Outputs.h | 12 +- > .../SecurityIp/SecurityIpSgxTem1v0_Inputs.h | 43 +-- > .../Guid/SecurityIp/SecurityIpTdx1v0_Inputs.h | 4 +- > .../Security/Include/Guid/SecurityPolicy.h | 29 ++ > .../Include/Guid/SecurityPolicy_Flat.h | 4 +- > .../Library/SecurityPolicyDefinitions.h | 28 ++ > 11 files changed, 245 insertions(+), 153 deletions(-) create mode=20 > 100644=20 > Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPolicy.h > create mode 100644 > Silicon/Intel/WhitleySiliconPkg/Security/Include/Library/SecurityPolic > yDefinition > s.h >=20 > diff --git=20 > a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h > b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h > index 82725bc84..2198f8516 100644 > --- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h > +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h > @@ -44,7 +44,13 @@ EFI_STATUS > OUT VOID *Data > ); >=20 > +/** > + RAS IMC S3 Data PPI > +**/ > struct _RAS_IMC_S3_DATA_PPI { > + /** > + Retrieves data for S3 saved memory RAS features from non-volatile st= orage. > + **/ > RAS_IMC_S3_DATA_PPI_GET_IMC_S3_RAS_DATA GetImcS3RasData; }; >=20 > diff --git=20 > a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h > b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h > index e355dcaba..503c5c0ae 100644 > --- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h > +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/UpiPolicyPpi.h > @@ -24,6 +24,9 @@ >=20 > typedef struct _UPI_POLICY_PPI UPI_POLICY_PPI; >=20 > +/** > + UPI Policy Structure > +**/ > struct _UPI_POLICY_PPI { > /** > This member specifies the revision of the UPI_POLICY_PPI. This=20 > field is used to @@ -32,7 +35,7 @@ struct _UPI_POLICY_PPI { > to correctly interpret the content of the INTERFACE fields. > **/ > UINT32 Revision; > - KTI_HOST_IN Upi; > + KTI_HOST_IN Upi; ///< KTIRC input structure > }; >=20 > #endif // _UPI_POLICY_PPI_H_ > diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h > b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h > index cf558b3d3..e793cc647 100644 > --- a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h > +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h > @@ -99,28 +99,31 @@ typedef struct { > KTI_RESERVED_2 Phy[MAX_FW_KTI_PORTS]; } KTI_RESERVED_4; >=20 > -// > -// PHY settings that are system dependent. Need 1 of these for each > socket/link/freq. > -// > +/** > + Per Lane PHY Configuration >=20 > + These PHY settings are system dependent. Every socket/link/freq=20 > + requires an > instance of this structure. > +**/ > typedef struct { > - UINT8 SocketID; > - UINT8 AllLanesUseSameTxeq; > - UINT8 Freq; > - UINT32 Link; > - UINT32 TXEQL[20]; > - UINT32 CTLEPEAK[5]; > + UINT8 SocketID; ///< Socket ID > + UINT8 AllLanesUseSameTxeq; ///< Use same TXEQ on all lanes > + UINT8 Freq; ///< The Link Speed these TXEQ settings = should be used > for > + UINT32 Link; ///< Port Number > + UINT32 TXEQL[20]; ///< TXEQ Settings > + UINT32 CTLEPEAK[5]; ///< CTLE Peaking Settings > } PER_LANE_EPARAM_LINK_INFO; >=20 > -// > -// This is for full speed mode, all lanes have the same TXEQ setting=20 > -// > +/** > + All Lanes PHY Configuration > + > + This is for full speed mode, all lanes have the same TXEQ setting=20 > + **/ > typedef struct { > - UINT8 SocketID; > - UINT8 Freq; > - UINT32 Link; > - UINT32 AllLanesTXEQ; > - UINT8 CTLEPEAK; > + UINT8 SocketID; ///< Socket ID > + UINT8 Freq; ///< The Link Speed these TXEQ settings = should be used > for > + UINT32 Link; ///< Port Number > + UINT32 AllLanesTXEQ; ///< TXEQ Setting > + UINT8 CTLEPEAK; ///< CTLE Peaking Setting > } ALL_LANES_EPARAM_LINK_INFO; >=20 > #define ADAPTIVE_CTLE 0x3f > @@ -173,130 +176,141 @@ typedef struct { > KTI_CPU_PHY_SETTING Phy[MAX_FW_KTI_PORTS]; > } KTI_CPU_SETTING; >=20 > -// > -// KTIRC input structure > -// > +/** > + KTIRC input structure > +**/ > typedef struct { > // > // Protocol layer and other general options; note that "Auto" is=20 > provided only options whose value will change depending > // on the topology, not for all options. > // >=20 > - // > - // Indicates the ratio of Bus/MMIOL/IO resource to be allocated for=20 > each CPU's IIO. > - // Value 0 indicates, that CPU is not relevant for the system. If=20 > resource is > - // requested for an CPU that is not currently populated, KTIRC will=20 > assume > - // that the ratio is 0 for that CPU and won't allocate any resources f= or it. > - // If resource is not requested for an CPU that is populated, KTIRC=20 > will force > - // the ratio for that CPU to 1. > - // > - > - > + /** > + Indicates the ratio of Bus/MMIOL/IO resource to be allocated for=20 > + each CPU's > IIO. Align indents for every lines in this blob. > + Value 0 indicates, that CPU is not relevant for the system. If resou= rce is > + requested for an CPU that is not currently populated, KTIRC will=20 > + assume For 'a' CPU > + that the ratio is 0 for that CPU and won't allocate any resources fo= r it. > + If resource is not requested for an CPU that is populated, KTIRC wil= l force > + the ratio for that CPU to 1. > + **/ > UINT8 BusRatio[MAX_SOCKET]; >=20 > - UINT8 D2KCreditConfig; // 1 - Min, 2 - Med (= Default), 3- Max > - UINT8 SnoopThrottleConfig; // 0 - Disabled (Default), 1= - Min, 2 - Med, > 3- Max > - UINT8 SnoopAllCores; // 0 - Disabled, 1 - Enabled= , 2 - Auto > - UINT8 LegacyVgaSoc; // Socket that claims the lega= cy VGA range; > valid values are 0-7; 0 is default. > - UINT8 LegacyVgaStack; // Stack that claims the legac= y VGA range; > valid values are 0-3; 0 is default. > - UINT8 ColdResetRequestStart; > - UINT8 P2pRelaxedOrdering; // 0 - Disable(default) 1 - En= able > - UINT8 DebugPrintLevel; // Bit 0 - Fatal, Bit1 - Warni= ng, Bit2 - Info > Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable > - UINT8 SncEn; // 0 - Disable, (default) 1 - = Enable > - UINT8 UmaClustering; // 0 - Disable, 2 - 2Clusters = UMA, 4 - > 4Clusters UMA > - UINT8 IoDcMode; // 0 - Disable IODC, 1 - AUTO= (default), 2 - > IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW > - // 4 - IODC_EN_REM_INVITOM_ALL= OC_NONALLOC, 5 - > IODC_EN_REM_INVITOM_AND_WCILF > - UINT8 DegradePrecedence; // Use DEGRADE_PRECEDENCE defi= nition; > TOPOLOGY_PRECEDENCE is default > - UINT8 Degrade4SPreference;// 4S1LFullConnect topology is= default; > another option is 4S2LRing topology. > - UINT8 DirectoryModeEn; // 0 - Disable; 1 - Enable (de= fault) > - UINT8 XptPrefetchEn; // Xpt Prefetch : 1 - Enable;= 0 - Disable; 2 - > Auto (default) > - UINT8 KtiPrefetchEn; // Kti Prefetch : 1 - Enable;= 0 - Disable; 2 - > Auto (default) > - UINT8 XptRemotePrefetchEn; // Xpt Remote Prefetch : = 1 - Enable; 0 > - Disable; 2 - Auto (default) (ICX only) > - UINT8 RdCurForXptPrefetchEn; // RdCur for XPT Prefetch= : 0 - Disable, > 1 - Enable, 2- Auto (default) > - UINT8 KtiFpgaEnable[MAX_SOCKET]; // Indicate if should = enable Fpga > device found in this socket : 0 - Disable, 1 - Enable, 2- Auto > - UINT8 DdrtQosMode; // DDRT QoS Feature: 0 - Di= sable (default), > 1 - M2M QoS Enable, Cha QoS Disable > - // 2 - M2M QoS Enable, Cha Q= oS Enable > + UINT8 D2KCreditConfig; ///< 1 - Min, 2 - = Med (Default), 3- > Max > + UINT8 SnoopThrottleConfig; ///< 0 - Disabled = (Default), 1 - Min, > 2 - Med, 3- Max > + UINT8 SnoopAllCores; ///< 0 - Disabled,= 1 - Enabled, 2 - Auto > + UINT8 LegacyVgaSoc; ///< Socket that c= laims the legacy > VGA range; valid values are 0-7; 0 is default. > + UINT8 LegacyVgaStack; ///< Stack that cl= aims the legacy VGA > range; valid values are 0-3; 0 is default. > + UINT8 ColdResetRequestStart; ///< @deprecated R= eserved. > + UINT8 P2pRelaxedOrdering; ///< 0 - Disable(d= efault) 1 - Enable > + UINT8 DebugPrintLevel; ///< Bit 0 - Fatal= , Bit1 - Warning, Bit2 > - Info Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable > + UINT8 SncEn; ///< 0 - Disable, = (default) 1 - Enable > + UINT8 UmaClustering; ///< 0 - Disable, = 2 - 2Clusters UMA, 4 - > 4Clusters UMA > + UINT8 IoDcMode; ///< 0 - Disable I= ODC, 1 - AUTO > (default), 2 - IODC_EN_REM_INVITOM_PUSH, 3 -=20 > IODC_EN_REM_INVITOM_ALLOCFLOW > + ///< 4 - > IODC_EN_REM_INVITOM_ALLOC_NONALLOC, 5 - IODC_EN_REM_INVITOM_AND_WCILF > + UINT8 DegradePrecedence; ///< Use DEGRADE_P= RECEDENCE > definition; TOPOLOGY_PRECEDENCE is default > + UINT8 Degrade4SPreference; ///< 4S1LFullConne= ct topology is > default; another option is 4S2LRing topology. > + UINT8 DirectoryModeEn; ///< 0 - Disable; = 1 - Enable (default) > + UINT8 XptPrefetchEn; ///< Xpt Prefetch = : 1 - Enable; 0 - > Disable; 2 - Auto (default) > + UINT8 KtiPrefetchEn; ///< Kti Prefetch = : 1 - Enable; 0 - > Disable; 2 - Auto (default) > + UINT8 XptRemotePrefetchEn; ///< Xpt Remote Pr= efetch : 1 - > Enable; 0 - Disable; 2 - Auto (default) (ICX only) > + UINT8 RdCurForXptPrefetchEn; ///< RdCur for XPT= Prefetch : 0 - > Disable, 1 - Enable, 2- Auto (default) > + UINT8 KtiFpgaEnable[MAX_SOCKET]; ///< Indicate if s= hould enable > Fpga device found in this socket : 0 - Disable, 1 - Enable, 2- Auto > + UINT8 DdrtQosMode; ///< DDRT QoS Feat= ure: 0 - Disable > (default), 1 - M2M QoS Enable, Cha QoS Disable > + ///< 2 - M2M=20 > + QoS Enable, Cha QoS Enable >=20 > // > // Phy/Link Layer Options (System-wide and per socket) > // > - UINT8 KtiLinkSpeedMode; // Link speed mode selection; = 0 - Slow > Speed; 1- Full Speed (default) > - UINT8 KtiLinkSpeed; // Use KTI_LINKSPEED definitio= n > - UINT8 KtiAdaptationEn; // 0 - Disable, 1 - Enable > - UINT8 KtiAdaptationSpeed; // Use KTI_LINK_SPEED definiti= on; > MAX_KTI_LINK_SPEED - Auto (i.e BIOS choosen speed) > - UINT8 KtiLinkL0pEn; // 0 - Disable, 1 - Enable, 2-= Auto (default) > - UINT8 KtiLinkL1En; // 0 - Disable, 1 - Enable, 2-= Auto (default) > - UINT8 KtiFailoverEn; // 0 - Disable, 1 - Enable, 2-= Auto (default) > - UINT8 KtiLbEn; // 0 - Disable(default), 1 - E= nable > - UINT8 KtiCrcMode; // CRC_MODE_16BIT, > CRC_MODE_ROLLING_32BIT, CRC_MODE_AUTO or CRC_MODE_PER_LINK > - > - UINT8 KtiCpuSktHotPlugEn; // 0 - Disable (default)= , 1 - Enable > - UINT8 KtiCpuSktHotPlugTopology; // 0 - 4S Topology (defa= ult), 1 - 8S > Topology > - UINT8 KtiSkuMismatchCheck; // 0 - No, 1 - Yes (defa= ult) > - UINT8 IrqThreshold; // IRQ Threshold setting > - UINT8 TorThresLoctoremNorm; // TOR threshold - Locto= rem > threshold normal > - UINT8 TorThresLoctoremEmpty; // TOR threshold - Locto= rem > threshold empty > - UINT8 MbeBwCal; // 0 - Linear, 1 - Biase= d, 2 - Legacy, 3 - > AUTO (default =3D Linear) > - UINT8 TscSyncEn; // TSC sync in sockets: = 0 - Disable, 1 - Enable, > 2 - AUTO (Default) > - UINT8 StaleAtoSOptEn; // HA A to S directory o= ptimization: 1 - > Enable; 0 - Disable; 2 - Auto (Default) > - UINT8 LLCDeadLineAlloc; // LLC dead line alloc: = 1 - > Enable(Default); 0 - Disable > - UINT8 SplitLock; > - UINT8 ColdResetRequestEnd; > - > - // > - // Phy/Link Layer Options (per Port) > - // > + UINT8 KtiLinkSpeedMode; ///< Link speed mo= de selection; 0 - > Slow Speed; 1- Full Speed (default) > + UINT8 KtiLinkSpeed; ///< Use KTI_LINKS= PEED definition > + UINT8 KtiAdaptationEn; ///< 0 - Disable, = 1 - Enable > + UINT8 KtiAdaptationSpeed; ///< Use KTI_LINK_= SPEED definition; > MAX_KTI_LINK_SPEED - Auto (i.e BIOS choosen speed) > + UINT8 KtiLinkL0pEn; ///< 0 - Disable, = 1 - Enable, 2- Auto > (default) > + UINT8 KtiLinkL1En; ///< 0 - Disable, = 1 - Enable, 2- Auto > (default) > + UINT8 KtiFailoverEn; ///< 0 - Disable, = 1 - Enable, 2- Auto > (default) > + UINT8 KtiLbEn; ///< 0 - Disable(d= efault), 1 - Enable > + UINT8 KtiCrcMode; ///< CRC_MODE_16BI= T, > CRC_MODE_ROLLING_32BIT, CRC_MODE_AUTO or CRC_MODE_PER_LINK > + > + UINT8 KtiCpuSktHotPlugEn; ///< 0 - Disable (= default), 1 - Enable > + UINT8 KtiCpuSktHotPlugTopology; ///< 0 - 4S Topolo= gy (default), 1 > - 8S Topology > + UINT8 KtiSkuMismatchCheck; ///< 0 - No, 1 - Y= es (default) > + UINT8 IrqThreshold; ///< IRQ Threshold= setting > + UINT8 TorThresLoctoremNorm; ///< TOR threshold= - Loctorem > threshold normal > + UINT8 TorThresLoctoremEmpty; ///< TOR threshold= - Loctorem > threshold empty > + UINT8 MbeBwCal; ///< 0 - Linear, 1= - Biased, 2 - Legacy, 3 > - AUTO (default =3D Linear) > + UINT8 TscSyncEn; ///< TSC sync in s= ockets: 0 - Disable, 1 - > Enable, 2 - AUTO (Default) > + UINT8 StaleAtoSOptEn; ///< HA A to S dir= ectory optimization: > 1 - Enable; 0 - Disable; 2 - Auto (Default) > + UINT8 LLCDeadLineAlloc; ///< LLC dead line= alloc: 1 - > Enable(Default); 0 - Disable > + UINT8 SplitLock; ///< @deprecated R= eserved, must be set > to 0. > + UINT8 ColdResetRequestEnd; ///< @deprecated R= eserved. > + > + /// > + /// Phy/Link Layer Options (per Port) /// > KTI_CPU_SETTING PhyLinkPerPortSetting[MAX_SOCKET]; >=20 >=20 > - UINT8 mmCfgBase; ///< MMCFG Base address, must be 64MB (= SKX, > HSX, BDX) / 256MB (GROVEPORT) aligned. Options: {0:1G, 1:1.5G,=20 > 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6: Auto} > - UINT8 mmCfgSize; ///< MMCFG Size address, must be 64M, 1= 28M or > 256M. Options: {0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto} > - UINT32 mmiolBase; ///< MMIOL Base address, must be 64MB a= ligned > - UINT32 mmiolSize; ///< MMIOL Size address > - UINT32 mmiohBase; ///< Address bits above 4GB, i,e, the h= ex value > here is address Bit[45:32] for SKX family, Bit[51:32] for ICX-SP > - UINT8 CpuPaLimit; ///< Limits the max address to 46bits.= This will take > precedence over mmiohBase > - UINT8 lowGap; > - UINT8 highGap; > - UINT16 mmiohSize; ////<< Number of 1GB contiguous regions= to be > assigned for MMIOH space per CPU. Range 1-1024 > - UINT8 isocEn; ///< 1 - Enable; 0 - Disable (BIOS will= force this for 4S) > - UINT8 dcaEn; ///< 1 - Enable; 0 - Disable > + UINT8 mmCfgBase; ///< MMCFG Base ad= dress, must be > 64MB (SKX, HSX, BDX) / 256MB (GROVEPORT) aligned. Options: {0:1G,=20 > 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6: Auto} > + UINT8 mmCfgSize; ///< MMCFG Size ad= dress, must be 64M, > 128M or 256M. Options: {0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6:=20 > Auto} > + UINT32 mmiolBase; ///< MMIOL Base ad= dress, must be > 64MB aligned > + UINT32 mmiolSize; ///< MMIOL Size ad= dress > + UINT32 mmiohBase; ///< Address bits = above 4GB, i,e, the > hex value here is address Bit[45:32] for SKX family, Bit[51:32] for=20 > ICX-SP > + UINT8 CpuPaLimit; ///< Limits the ma= x address to 46bits. > This will take precedence over mmiohBase > + UINT8 lowGap; ///< @deprecated R= eserved. > + UINT8 highGap; ///< @deprecated R= eserved. > + UINT16 mmiohSize; ///< Number of 1GB= contiguous > regions to be assigned for MMIOH space per CPU. Range 1-1024 > + UINT8 isocEn; ///< 1 - Enable; 0= - Disable (BIOS will force > this for 4S) > + UINT8 dcaEn; ///< 1 - Enable; 0= - Disable >=20 > - /* > + /** > BoardTypeBitmask: > - Bits[3:0] - Socket0 > - Bits[7:4] - Socket1 > - Bits[11:8] - Socket2 > - Bits[15:12] - Socket3 > - Bits[19:16] - Socket4 > - Bits[23:20] - Socket5 > - Bits[27:24] - Socket6 > - Bits[31:28] - Socket7 > + - Bits[3:0] - Socket0 > + - Bits[7:4] - Socket1 > + - Bits[11:8] - Socket2 > + - Bits[15:12] - Socket3 > + - Bits[19:16] - Socket4 > + - Bits[23:20] - Socket5 > + - Bits[27:24] - Socket6 > + - Bits[31:28] - Socket7 >=20 > Within each Socket-specific field, bits mean: > - Bit0 =3D CPU_TYPE_STD support; always 1 on Socket0 > - Bit1 =3D CPU_TYPE_F support > - Bit2 =3D CPU_TYPE_P support > - Bit3 =3D reserved > - */ > + - Bit0 =3D CPU_TYPE_STD support; always 1 on Socket0 > + - Bit1 =3D CPU_TYPE_F support > + - Bit2 =3D CPU_TYPE_P support > + - Bit3 =3D reserved > + **/ > UINT32 BoardTypeBitmask; > - UINT32 AllLanesPtr; > - UINT32 PerLanePtr; > - UINT32 AllLanesSizeOfTable; > - UINT32 PerLaneSizeOfTable; > - UINT32 WaitTimeForPSBP; // the wait time in units of 1000= us for PBSP > to check in. > - BOOLEAN IsKtiNvramDataReady; > - UINT32 OemHookPostTopologyDiscovery; > - UINT32 OemGetResourceMapUpdate; > - UINT32 OemGetAdaptedEqSettings; > - UINT32 OemCheckCpuPartsChangeSwap; > - > - BOOLEAN WaSerializationEn; // Enable BIOS serializati= on WA by > PcdWaSerializationEn > + UINT32 AllLanesPtr; ///< Pointer to an= array of > ALL_LANES_EPARAM_LINK_INFO structures. > + UINT32 PerLanePtr; ///< Pointer to an= array of > PER_LANE_EPARAM_LINK_INFO structures. > + UINT32 AllLanesSizeOfTable; ///< Number of ele= ments in array > pointed to by AllLanesPtr > + UINT32 PerLaneSizeOfTable; ///< Number of ele= ments in array > pointed to by PerLanePtr > + UINT32 WaitTimeForPSBP; ///< the wait time= in units of > 1000us for PBSP to check in. > + BOOLEAN IsKtiNvramDataReady; ///< Used internal= ly, Reserved. > + UINT32 OemHookPostTopologyDiscovery; ///< > OEM_HOOK_POST_TOPOLOGY_DISCOVERY function pointer. Invoked at the end=20 > of topology discovery, used for error reporting. > + UINT32 OemGetResourceMapUpdate; ///< > OEM_GET_RESOURCE_MAP_UPDATE function pointer. Allows platform code to=20 > adjust the resource map. > + UINT32 OemGetAdaptedEqSettings; ///< @deprecated R= eserved, > must be set to 0. > + UINT32 OemCheckCpuPartsChangeSwap; ///< @deprecated > Reserved, must be set to 0. > + > + BOOLEAN WaSerializationEn; ///< Enable BIOS s= erialization WA > by PcdWaSerializationEn > KTI_RESERVED_3 Reserved166; > KTI_RESERVED_4 Reserved167[MAX_SOCKET]; > - UINT8 KtiInEnableMktme; // 0 - Disabled; 1 - Enabl= ed; MkTme > status decides D2Kti feature state > + UINT8 KtiInEnableMktme; ///< 0 - Disabled;= 1 - Enabled; > MkTme status decides D2Kti feature state > + /** > + Pointers to the location of the CFR/SINIT binaries. > + > + Contains a pointer to a 24 byte fixed length array. > + The array contains the 3 instances of the following c-struct > + ~~~ > + typedef struct { > + UINT32 CfrImagePtr; > + UINT32 CfrImageSize; > + } > + ~~~ > + This allows a maximum of 3 CFR/SINIT binaries to be provided by=20 > + platform > code. > + **/ > UINT32 CFRImagePtr; > - UINT8 S3mCFRCommit; // 0 - Disable S3m CFR flo= w. 1 - > Provision S3m CFR but not Commit. 2 - Provsion and Commit S3M CFR. > - UINT8 PucodeCFRCommit; // 0 - Disable Pucode CFR = flow. 1 - > Provision Pucode CFR but not Commit. 2 - Provsion and Commit Pucode CFR. > + UINT8 S3mCFRCommit; ///< 0 - Disable S= 3m CFR flow. 1 - > Provision S3m CFR but not Commit. 2 - Provision and Commit S3M CFR. > + UINT8 PucodeCFRCommit; ///< 0 - Disable P= ucode CFR flow. 1 > - Provision Pucode CFR but not Commit. 2 - Provision and Commit Pucode CF= R. > } KTI_HOST_IN; >=20 > #pragma pack() > diff --git > a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolic > yComm > on.h > b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolic > yComm > on.h > index f5861ccaf..0e10d0b8f 100644 > --- > a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolic > yComm > on.h > +++ > b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolic > yComm > on.h > @@ -23,6 +23,9 @@ extern EFI_GUID gFlashProtectionConfigGuid; //=20 > ---------------------------- PCH General Config=20 > ------------------------------- // >=20 > +/** > + PCH General Configuration > +**/ > typedef struct { > /** > Subsystem Vendor ID and Subsystem ID of the PCH devices. > @@ -775,6 +778,9 @@ typedef enum { > PchHdaIDispMode1T =3D 1 > } PCH_HDAUDIO_IDISP_TMODE; >=20 > +/** > + This structure contains the policies which are related to HD Audio=20 > +device > (cAVS). > +**/ > typedef struct { > /** > This member describes whether or not Intel HD Audio (Azalia)=20 > should be enabled. > @@ -1674,6 +1680,9 @@ typedef struct { > UINT16 ProtectedRangeBase; > } PROTECTED_RANGE; >=20 > +/** > + PCH Flash Protection Configuration > +**/ > typedef struct { > PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; > } PCH_FLASH_PROTECTION_CONFIG; > diff --git > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpMk > Tme1v0_Inputs.h > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpMk > Tme1v0_Inputs.h > index 4c48ca19e..84197b8c8 100644 > --- > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpMk > Tme1v0_Inputs.h > +++ > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpMk > Tme1v0_Inputs.h > @@ -8,15 +8,15 @@ > **/ >=20 > // > -// TME > +// TME (Total Memory Encryption) > // > -UINT8 EnableTme; // TME Enable > -UINT8 EnableTmeCR; // Exclude Crystal Ridge memory f= rom > encryption. > +UINT8 EnableTme; ///< TME Enable > +UINT8 EnableTmeCR; ///< TME for Optane Pers= istent Memory. > Set to 0 exclude Optane from encryption. >=20 > // > // MK-TME > // > -UINT8 EnableMktme; // MK-TME Enable > +UINT8 EnableMktme; ///< MK-TME Enable >=20 > UINT8 ReservedS234; > UINT8 ReservedS235; > diff --git > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpMk > Tme1v0_Outputs.h > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpMk > Tme1v0_Outputs.h > index 3a6262a65..201cdd9a9 100644 > --- > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpMk > Tme1v0_Outputs.h > +++ > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpMk > Tme1v0_Outputs.h > @@ -10,9 +10,9 @@ > // > // MK-TME > // > -// NAK - Not a knob, used just for indication > -UINT8 TmeCapability; // TME Capable > -UINT8 TmeCrSupport; // Flag used to check if Crystal Ridge is=20 > supported in UEFI > -UINT8 MktmeCapability; // MK-TME Capable > -UINT16 MktmeMaxKeys; // Max number of keys used for encryption > -UINT8 MkTmeKeyIdBits; // Used to suppress setup menu key-splits \ No=20 > newline at end of file > +// NAK (Not a knob) - Used just for indication > +UINT8 TmeCapability; // NAK (Not a knob) - TM= E Capable > +UINT8 TmeCrSupport; // NAK (Not a knob) - Fl= ag used to check > if Crystal Ridge is supported in UEFI > +UINT8 MktmeCapability; // NAK (Not a knob) - MK= -TME Capable > +UINT16 MktmeMaxKeys; // NAK (Not a knob) - Ma= x number of > keys used for encryption > +UINT8 MkTmeKeyIdBits; // NAK (Not a knob) - Us= ed to suppress > setup menu key-splits > diff --git > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpSgx > Tem1v0_Inputs.h > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpSgx > Tem1v0_Inputs.h > index 2deabd0b5..c46434392 100644 > --- > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpSgx > Tem1v0_Inputs.h > +++ > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpSgx > Tem1v0_Inputs.h > @@ -10,27 +10,30 @@ > // > // SGX > // > -UINT8 EnableSgx; > -UINT8 SgxFactoryReset; // Delete all registration data, = if SGX enabled > force IPE/FirstBinding flow > -UINT64 PrmrrSize; // SGX PRMRR size > +UINT8 EnableSgx; ///< Enable SGX > +UINT8 SgxFactoryReset; ///< Delete all registra= tion data, if SGX > enabled force IPE/FirstBinding flow > +UINT64 PrmrrSize; ///< SGX PRMRR size > UINT64 ReservedS239; > -UINT8 SgxQoS; // SGX Quality of Service > -UINT8 SgxAutoRegistrationAgent; > -UINT8 SgxPackageInfoInBandAccess; // Expose Package Info to OS > -UINT8 EpochUpdate; > -UINT64 SgxEpoch0; // SGX EPOCH0 value {0 - 0xFFFFFF= FFFFFFFFFF} > -UINT64 SgxEpoch1; // SGX EPOCH1 value {0 - 0xFFFFFF= FFFFFFFFFF} > -UINT8 SgxLeWr; // Flexible Launch Enclave Policy= (Wr En) > -UINT64 SgxLePubKeyHash0; // Launch Enclave Hash 0 > -UINT64 SgxLePubKeyHash1; // Launch Enclave Hash 1 > -UINT64 SgxLePubKeyHash2; // Launch Enclave Hash 2 > -UINT64 SgxLePubKeyHash3; // Launch Enclave Hash 3 > -// Client SGX - unused in server > -UINT8 SgxSinitNvsData; // SGX NVS data from Flash passed= during > previous boot using CPU_INFO_PROTOCOL.SGX_INFO; > - // Pass value of zero if there is= not data saved or when > SGX is disabled. > -UINT8 SgxSinitDataFromTpm; // SGX SVN data from TPM; 0: when= SGX is > disabled or TPM is not present or no data > - // is present in TPM. > -UINT8 SgxDebugMode; > +UINT8 SgxQoS; ///< SGX Quality of Serv= ice > +UINT8 SgxAutoRegistrationAgent; ///< SGX Auto Registrati= on Agent > +UINT8 SgxPackageInfoInBandAccess; ///< SGX Expose Package = Info to > OS > +UINT8 EpochUpdate; ///< SGX EPOCH Update > +UINT64 SgxEpoch0; ///< SGX EPOCH0 value {0= - > 0xFFFFFFFFFFFFFFFF} > +UINT64 SgxEpoch1; ///< SGX EPOCH1 value {0= - > 0xFFFFFFFFFFFFFFFF} > +UINT8 SgxLeWr; ///< Flexible Launch Enc= lave Policy (Wr En) > +UINT64 SgxLePubKeyHash0; ///< Launch Enclave Hash= 0 > +UINT64 SgxLePubKeyHash1; ///< Launch Enclave Hash= 1 > +UINT64 SgxLePubKeyHash2; ///< Launch Enclave Hash= 2 > +UINT64 SgxLePubKeyHash3; ///< Launch Enclave Hash= 3 > + > +// > +// DEPRECATED > +// > +UINT8 SgxSinitNvsData; ///< @deprecated SGX NVS= data from > Flash passed during previous boot using CPU_INFO_PROTOCOL.SGX_INFO; > + /// Pass va= lue of zero if there is not data > saved or when SGX is disabled. > +UINT8 SgxSinitDataFromTpm; ///< @deprecated SGX SVN= data > from TPM; 0: when SGX is disabled or TPM is not present or no data > + /// is pres= ent in TPM. > +UINT8 SgxDebugMode; ///< @deprecated >=20 > UINT8 ReservedS240; > UINT8 ReservedS241; > diff --git > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpTdx > 1v0_Inputs.h > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpTdx > 1v0_Inputs.h > index db5081c0a..79369f989 100644 > --- > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpTdx > 1v0_Inputs.h > +++ > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/Sec > urityIpTdx > 1v0_Inputs.h > @@ -7,7 +7,7 @@ > SPDX-License-Identifier: BSD-2-Clause-Patent **/ >=20 > -UINT8 EnableTdx; // TDX Enable > -UINT8 KeySplit; // TDX/MK-TME key split > +UINT8 EnableTdx; ///< TDX Enable > +UINT8 KeySplit; ///< TDX/MK-TME key spli= t >=20 > UINT8 ReservedS245; > diff --git > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPolicy > .h=20 > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPolicy > .h > new file mode 100644 > index 000000000..0beb26704 > --- /dev/null > +++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPo > +++ licy.h > @@ -0,0 +1,29 @@ > +/** @file > + Provides data structure information used by ServerSecurity features=20 > +in Mtkme > etc. > + > + @copyright > + Copyright 2018 - 2021 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _SECURITY_POLICY_H_ > +#define _SECURITY_POLICY_H_ > + > +extern EFI_GUID gSecurityPolicyDataGuid; #include=20 > + > + > +#pragma pack(1) > + > +/** > + Security Policy > +**/ > +typedef struct { > + /** > + * Please put common definitions inside the SecurityPolicy_Flat.h * > + **/ > + #include "SecurityPolicy_Flat.h" > +} SECURITY_POLICY; > + > +#pragma pack() > +#endif > diff --git > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPolicy > _Flat.h=20 > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPolicy > _Flat.h > index ba62b8c3a..09dacdf62 100644 > ---=20 > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPolicy > _Flat.h > +++ > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityPolicy > _Flat.h > @@ -1,6 +1,6 @@ > /** @file > Provides data structure information used by ServerSecurity features=20 > in literally all products > - Header is flat and injected directly in SecurityPolicy sructuture=20 > and SOCKET_PROCESSORCORE_CONFIGURATION. > + Header is flat and injected directly in SecurityPolicy structure=20 > + and > SOCKET_PROCESSORCORE_CONFIGURATION. >=20 > @copyright > Copyright 2020 - 2021 Intel Corporation.
@@ -8,7 +8,7 @@ > SPDX-License-Identifier: BSD-2-Clause-Patent **/ >=20 > - // Header is flat and injected directly in SecurityPolicy=20 > sructuture and SOCKET_PROCESSORCORE_CONFIGURATION. > + // Header is flat and injected directly in SecurityPolicy structure=20 > + and > SOCKET_PROCESSORCORE_CONFIGURATION. > // Put common definitons here either directly or via intermediate head= er file.. >=20 > // SECURITY_IP_MKTME_1V0 MkTme; > diff --git > a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Library/SecurityPol > icyDefiniti > ons.h > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Library/SecurityPol > icyDefiniti > ons.h > new file mode 100644 > index 000000000..700f5abb4 > --- /dev/null > +++ > b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Library/SecurityPol > icyDefiniti > ons.h > @@ -0,0 +1,28 @@ > +/**@file > + @copyright > + Copyright 2020 - 2021 Intel Corporation.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef __SECURITY_POLICY_DEFINITIONS_H__ #define=20 > +__SECURITY_POLICY_DEFINITIONS_H__ > + > +// > +// Security Policy definitions > +// > + > +// > +// Values for capable/incapable =3D=3D supported/unsupported // > +#define SECURITY_POLICY_UNSUPPORTED 0 > +#define SECURITY_POLICY_SUPPORTED 1 > + > +// > +// Values for enable/disable options > +// > +#define SECURITY_POLICY_DISABLE 0 > +#define SECURITY_POLICY_ENABLE 1 > +#define SECURITY_POLICY_AUTO 2 > + > +#endif > -- > 2.27.0.windows.1