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15.20.4415.023; Mon, 16 Aug 2021 05:32:40 +0000 From: "Nate DeSimone" To: Benjamin Doron , "devel@edk2.groups.io" CC: "Chiu, Chasel" , Michael Kubacki Subject: Re: [edk2-platforms][PATCH v2 2/5] KabylakeOpenBoardPkg/AspireVn7Dash572G: Duplicate KabylakeRvp3 directory Thread-Topic: [edk2-platforms][PATCH v2 2/5] KabylakeOpenBoardPkg/AspireVn7Dash572G: Duplicate KabylakeRvp3 directory Thread-Index: AQHXkKLn4xqkWryx6ka+7cf9zxm+46t1nqCw Date: Mon, 16 Aug 2021 05:32:40 +0000 Message-ID: References: <20210804203630.7080-1-benjamin.doron00@gmail.com> <20210814002445.10084-1-benjamin.doron00@gmail.com> <20210814002445.10084-3-benjamin.doron00@gmail.com> In-Reply-To: <20210814002445.10084-3-benjamin.doron00@gmail.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=none action=none header.from=intel.com; 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fkc/sreqYUFU09WwsYkBK/w5G/I1zyJrXl3uLFRRwwO4gOlO7jRj77kdlvTW2XbbDIEkF2RfTPPr62bBrDLMEQY8BJOnUA2c7252BwbhliY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1101MB2255 Return-Path: nathaniel.l.desimone@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Benjamin Doron > Sent: Friday, August 13, 2021 5:25 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Michael Kubacki > > Subject: [edk2-platforms][PATCH v2 2/5] > KabylakeOpenBoardPkg/AspireVn7Dash572G: Duplicate KabylakeRvp3 > directory >=20 > This makes diffing the follow-up board changes easier. >=20 > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Michael Kubacki > Signed-off-by: Benjamin Doron > --- >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c | 115= ++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 87= +++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c | 186 > +++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c | 153= +++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h | 27= + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c | 248 > +++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c | 84= +++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h | 30= + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 79 > +++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Li > brary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 150 > ++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCom > mands.h | 46= ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/Fla > shMapInclude.fdf | 48 += + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePla > tformHookLib/BasePlatformHookLib.c | 662 > ++++++++++++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePla > tformHookLib/BasePlatformHookLib.inf | 51 += + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/DxeBoardAcpiTableLib.c | 36 = + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/DxeBoardAcpiTableLib.inf | 48 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/DxeKabylakeRvp3AcpiTableLib.c | 76 = +++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/DxeMultiBoardAcpiSupportLib.c | 43 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/DxeMultiBoardAcpiSupportLib.inf | 49 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/SmmBoardAcpiEnableLib.c | 62 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/SmmBoardAcpiEnableLib.inf | 47 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/SmmKabylakeRvp3AcpiEnableLib.c | 39 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/SmmMultiBoardAcpiSupportLib.c | 81 = +++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/SmmMultiBoardAcpiSupportLib.inf | 48 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardA > cpiLib/SmmSiliconAcpiEnableLib.c | 168 = +++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/KabylakeRvp3GpioTable.c | 381 = +++++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/KabylakeRvp3HdaVerbTables.c | 232 = +++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/KabylakeRvp3HsioPtssTables.c | 105 = +++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/KabylakeRvp3SpdTable.c | 541 = +++++++++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiBoardInitPostMemLib.c | 39 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiBoardInitPostMemLib.inf | 54 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiBoardInitPreMemLib.c | 108 = +++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiBoardInitPreMemLib.inf | 135 = ++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiKabylakeRvp3Detect.c | 124 = ++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiKabylakeRvp3InitLib.h | 44 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiKabylakeRvp3InitPostMemLib.c | 208 = ++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiKabylakeRvp3InitPreMemLib.c | 339 = ++++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiMultiBoardInitPostMemLib.c | 40 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiMultiBoardInitPostMemLib.inf | 56 = ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiMultiBoardInitPreMemLib.c | 82 = +++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardI > nitLib/PeiMultiBoardInitPreMemLib.inf | 137 = ++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg > .dsc | 52= 1 ++++++++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg > .fdf | 71= 5 ++++++++++++++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg > BuildOption.dsc | 15= 1 +++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg > Pcd.dsc | 46= 4 +++++++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/ > DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c | 175 += ++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/ > DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h | 39 += + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/ > DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h | 64 += + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/ > DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c | 66 += + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/ > DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c | 53 += + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/ > DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf | 51 += + >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/ > PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 601 > ++++++++++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/ > PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 92 += ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py > | 68 ++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cf > g | 36 + > 55 files changed, 8384 insertions(+) >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c > new file mode 100644 > index 000000000000..155dfdaf623f > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c > @@ -0,0 +1,115 @@ > +/** @file >=20 > + This file is SampleCode of the library for Intel PCH PEI Policy initia= lization. >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include "PeiPchPolicyUpdate.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define PCI_CLASS_NETWORK 0x02 >=20 > +#define PCI_CLASS_NETWORK_ETHERNET 0x00 >=20 > +#define PCI_CLASS_NETWORK_OTHER 0x80 >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE > mPcieDeviceTable[] =3D { >=20 > + // >=20 > + // Intel PRO/Wireless >=20 > + // >=20 > + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel WiMAX/WiFi Link >=20 > + // >=20 > + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override= , 0, > 0, 0, 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Crane Peak WLAN NIC >=20 > + // >=20 > + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Crane Peak w/BT WLAN NIC >=20 > + // >=20 > + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Kelsey Peak WiFi, WiMax >=20 > + // >=20 > + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Centrino Wireless-N 105 >=20 > + // >=20 > + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Centrino Wireless-N 135 >=20 > + // >=20 > + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Centrino Wireless-N 2200 >=20 > + // >=20 > + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Centrino Wireless-N 2230 >=20 > + // >=20 > + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Centrino Wireless-N 6235 >=20 > + // >=20 > + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel CampPeak 2 Wifi >=20 > + // >=20 > + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel WilkinsPeak 1 Wifi >=20 > + // >=20 > + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, > PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, > PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Wilkins Peak 2 Wifi >=20 > + // >=20 > + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, > PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, >=20 > + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, > PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, >=20 > + // >=20 > + // Intel Wilkins Peak PF Wifi >=20 > + // >=20 > + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, > PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, > 0, 0, 0, 0 }, >=20 > + >=20 > + // >=20 > + // End of Table >=20 > + // >=20 > + { 0 } >=20 > +}; >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c > new file mode 100644 > index 000000000000..d8aff1960f0b > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c > @@ -0,0 +1,87 @@ > +/** @file >=20 > + Implementation of Fsp Misc UPD Initialization. >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Performs FSP Misc UPD initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspMiscUpdUpdatePreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINTN VariableSize; >=20 > + VOID *MemorySavedData; >=20 > + UINT8 MorControl; >=20 > + VOID *MorControlPtr; >=20 > + >=20 > + // >=20 > + // Initialize S3 Data variable (S3DataPtr). It may be used for warm an= d fast > boot paths. >=20 > + // >=20 > + VariableSize =3D 0; >=20 > + MemorySavedData =3D NULL; >=20 > + Status =3D PeiGetVariable ( >=20 > + L"MemoryConfig", >=20 > + &gFspNonVolatileStorageHobGuid, >=20 > + &MemorySavedData, >=20 > + &VariableSize >=20 > + ); >=20 > + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" > gFspNonVolatileStorageHobGuid - %r\n", Status)); >=20 > + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); >=20 > + FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData; >=20 > + >=20 > + if (FspmUpd->FspmArchUpd.NvsBufferPtr !=3D NULL) { >=20 > + // >=20 > + // Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - > GEN_PMCON_A[23]), >=20 > + // after memory Data is saved to NVRAM. >=20 > + // >=20 > + PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, > PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A), > B_PCH_PMC_GEN_PMCON_A_DISB); >=20 > + } >=20 > + >=20 > + // >=20 > + // MOR >=20 > + // >=20 > + MorControl =3D 0; >=20 > + MorControlPtr =3D &MorControl; >=20 > + VariableSize =3D sizeof (MorControl); >=20 > + Status =3D PeiGetVariable ( >=20 > + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, >=20 > + &gEfiMemoryOverwriteControlDataGuid, >=20 > + &MorControlPtr, >=20 > + &VariableSize >=20 > + ); >=20 > + DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); >=20 > + if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { >=20 > + FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & > MOR_CLEAR_MEMORY_BIT_MASK); >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c > new file mode 100644 > index 000000000000..55be16265e99 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c > @@ -0,0 +1,186 @@ > +/** @file >=20 > + Provide FSP wrapper platform related function. >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Performs FSP Misc UPD initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspMiscUpdUpdatePreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP PCH PEI Policy pre mem initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspPchPolicyUpdatePreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP PCH PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspPchPolicyUpdate ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP SA PEI Policy initialization in pre-memory. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSaPolicyUpdatePreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP SA PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSaPolicyUpdate ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ); >=20 > + >=20 > +VOID >=20 > +InternalPrintVariableData ( >=20 > + IN UINT8 *Data8, >=20 > + IN UINTN DataSize >=20 > + ) >=20 > +{ >=20 > + UINTN Index; >=20 > + >=20 > + for (Index =3D 0; Index < DataSize; Index++) { >=20 > + if (Index % 0x10 =3D=3D 0) { >=20 > + DEBUG ((DEBUG_INFO, "\n%08X:", Index)); >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, " %02X", *Data8++)); >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "\n")); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs silicon pre-mem policy update. >=20 > + >=20 > + The meaning of Policy is defined by silicon code. >=20 > + It could be the raw data, a handle, a PPI, etc. >=20 > + >=20 > + The input Policy must be returned by SiliconPolicyDonePreMem(). >=20 > + >=20 > + 1) In FSP path, the input Policy should be FspmUpd. >=20 > + A platform may use this API to update the FSPM UPD policy initialized >=20 > + by the silicon module or the default UPD data. >=20 > + The output of FSPM UPD data from this API is the final UPD data. >=20 > + >=20 > + 2) In non-FSP path, the board may use additional way to get >=20 > + the silicon policy data field based upon the input Policy. >=20 > + >=20 > + @param[in, out] Policy Pointer to policy. >=20 > + >=20 > + @return the updated policy. >=20 > +**/ >=20 > +VOID * >=20 > +EFIAPI >=20 > +SiliconPolicyUpdatePreMem ( >=20 > + IN OUT VOID *FspmUpd >=20 > + ) >=20 > +{ >=20 > + FSPM_UPD *FspmUpdDataPtr; >=20 > + >=20 > + FspmUpdDataPtr =3D FspmUpd; >=20 > + PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr); >=20 > + PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr); >=20 > + PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr); >=20 > + >=20 > + InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD)); >=20 > + >=20 > + return FspmUpd; >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs silicon post-mem policy update. >=20 > + >=20 > + The meaning of Policy is defined by silicon code. >=20 > + It could be the raw data, a handle, a PPI, etc. >=20 > + >=20 > + The input Policy must be returned by SiliconPolicyDonePostMem(). >=20 > + >=20 > + 1) In FSP path, the input Policy should be FspsUpd. >=20 > + A platform may use this API to update the FSPS UPD policy initialized >=20 > + by the silicon module or the default UPD data. >=20 > + The output of FSPS UPD data from this API is the final UPD data. >=20 > + >=20 > + 2) In non-FSP path, the board may use additional way to get >=20 > + the silicon policy data field based upon the input Policy. >=20 > + >=20 > + @param[in, out] Policy Pointer to policy. >=20 > + >=20 > + @return the updated policy. >=20 > +**/ >=20 > +VOID * >=20 > +EFIAPI >=20 > +SiliconPolicyUpdatePostMem ( >=20 > + IN OUT VOID *FspsUpd >=20 > + ) >=20 > +{ >=20 > + FSPS_UPD *FspsUpdDataPtr; >=20 > + >=20 > + FspsUpdDataPtr =3D FspsUpd; >=20 > + PeiFspSaPolicyUpdate (FspsUpdDataPtr); >=20 > + PeiFspPchPolicyUpdate (FspsUpdDataPtr); >=20 > + >=20 > + InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD)); >=20 > + >=20 > + return FspsUpd; >=20 > +} >=20 > + >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c > new file mode 100644 > index 000000000000..b469720ac657 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c > @@ -0,0 +1,153 @@ > +/** @file >=20 > + This file is SampleCode of the library for Intel PCH PEI Policy initia= lization. >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include "PeiPchPolicyUpdate.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[]; >=20 > + >=20 > +/** >=20 > + Add verb table helper function. >=20 > + This function calculates verbtable number and shows verb table > information. >=20 > + >=20 > + @param[in,out] VerbTableEntryNum Input current VerbTable number > and output the number after adding new table >=20 > + @param[in,out] VerbTableArray Pointer to array of VerbTable >=20 > + @param[in] VerbTable VerbTable which is going to add = into array >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +InternalAddVerbTable ( >=20 > + IN OUT UINT8 *VerbTableEntryNum, >=20 > + IN OUT UINT32 *VerbTableArray, >=20 > + IN HDAUDIO_VERB_TABLE *VerbTable >=20 > + ) >=20 > +{ >=20 > + if (VerbTable =3D=3D NULL) { >=20 > + DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable > =3D=3D NULL\n")); >=20 > + return; >=20 > + } >=20 > + >=20 > + VerbTableArray[*VerbTableEntryNum] =3D (UINT32) VerbTable; >=20 > + *VerbTableEntryNum +=3D 1; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, >=20 > + "Add verb table for vendor =3D 0x%04X devId =3D 0x%04X (size =3D %d > DWords)\n", >=20 > + VerbTable->Header.VendorId, >=20 > + VerbTable->Header.DeviceId, >=20 > + VerbTable->Header.DataDwords) >=20 > + ); >=20 > +} >=20 > + >=20 > +enum HDAUDIO_CODEC_SELECT { >=20 > + PchHdaCodecPlatformOnboard =3D 0, >=20 > + PchHdaCodecExternalKit =3D 1 >=20 > +}; >=20 > + >=20 > +/** >=20 > + Add verb table function. >=20 > + This function update the verb table number and verb table ptr of polic= y. >=20 > + >=20 > + @param[in] HdAudioConfig HDAudie config block >=20 > + @param[in] CodecType Platform codec type indicator >=20 > + @param[in] AudioConnectorType Platform audio connector type >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +InternalAddPlatformVerbTables ( >=20 > + IN OUT FSPS_UPD *FspsUpd, >=20 > + IN UINT8 CodecType, >=20 > + IN UINT8 AudioConnectorType >=20 > + ) >=20 > +{ >=20 > + UINT8 VerbTableEntryNum; >=20 > + UINT32 VerbTableArray[32]; >=20 > + UINT32 *VerbTablePtr; >=20 > + >=20 > + VerbTableEntryNum =3D 0; >=20 > + >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable)); >=20 > + >=20 > + if (CodecType =3D=3D PchHdaCodecPlatformOnboard) { >=20 > + DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n")); >=20 > + if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) !=3D NULL) { >=20 > + if (AudioConnectorType =3D=3D 0) { //Type-C Audio connector select= ed in > Bios Setup menu >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID > *) (UINTN) PcdGet32 (PcdExtHdaVerbTable)); >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); >=20 > + DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n")); >=20 > + } else { //Stacked Jack Audio connector selected in Bios Setup men= u >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID > *) (UINTN) PcdGet32 (PcdHdaVerbTable)); >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID > *) (UINTN) PcdGet32 (PcdHdaVerbTable2)); >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); >=20 > + DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector > selected!\n")); >=20 > + } >=20 > + } else { >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdHdaVerbTable)); >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdHdaVerbTable2)); >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); >=20 > + } >=20 > + } else { >=20 > + DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n")); >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdCommonHdaVerbTable1)); >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdCommonHdaVerbTable2)); >=20 > + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdCommonHdaVerbTable3)); >=20 > + } >=20 > + >=20 > + FspsUpd->FspsConfig.PchHdaVerbTableEntryNum =3D VerbTableEntryNum; >=20 > + >=20 > + VerbTablePtr =3D (UINT32 *) AllocateZeroPool (sizeof (UINT32) * > VerbTableEntryNum); >=20 > + CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * > VerbTableEntryNum); >=20 > + FspsUpd->FspsConfig.PchHdaVerbTablePtr =3D (UINT32) VerbTablePtr; >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs FSP PCH PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspPchPolicyUpdate ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ) >=20 > +{ >=20 > + >=20 > + FspsUpd->FspsConfig.PchSubSystemVendorId =3D > V_PCH_INTEL_VENDOR_ID; >=20 > + FspsUpd->FspsConfig.PchSubSystemId =3D V_PCH_DEFAULT_SID; >=20 > + >=20 > + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D (UINT32) > mPcieDeviceTable; >=20 > + >=20 > + InternalAddPlatformVerbTables (FspsUpd, > PchHdaCodecPlatformOnboard, PcdGet8 (PcdAudioConnector)); >=20 > + >=20 > +DEBUG_CODE_BEGIN(); >=20 > +if ((PcdGet8 (PcdSerialIoUartDebugEnable) =3D=3D 1) && >=20 > + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + > PcdGet8 (PcdSerialIoUartNumber)] =3D=3D PchSerialIoDisabled ) { >=20 > + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 > (PcdSerialIoUartNumber)] =3D PchSerialIoLegacyUart; >=20 > + } >=20 > +DEBUG_CODE_END(); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h > new file mode 100644 > index 000000000000..30d2f99e1dde > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h > @@ -0,0 +1,27 @@ > +/** @file >=20 > + >=20 > +Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef _PEI_PCH_POLICY_UPDATE_H_ >=20 > +#define _PEI_PCH_POLICY_UPDATE_H_ >=20 > + >=20 > +// >=20 > +// External include files do NOT need to be explicitly specified in real= EDKII >=20 > +// environment >=20 > +// >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#endif >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c > new file mode 100644 > index 000000000000..f6390ee12c17 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c > @@ -0,0 +1,248 @@ > +/** @file >=20 > + This file is SampleCode of the library for Intel PCH PEI Policy initia= lization. >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include "PeiPchPolicyUpdate.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +VOID >=20 > +InstallPlatformHsioPtssTable ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + HSIO_PTSS_TABLES *UnknowPtssTables; >=20 > + HSIO_PTSS_TABLES *SpecificPtssTables; >=20 > + HSIO_PTSS_TABLES *PtssTables; >=20 > + UINT8 PtssTableIndex; >=20 > + UINT32 UnknowTableSize; >=20 > + UINT32 SpecificTableSize; >=20 > + UINT32 TableSize; >=20 > + UINT32 Entry; >=20 > + UINT8 LaneNum; >=20 > + UINT8 Index; >=20 > + UINT8 MaxSataPorts; >=20 > + UINT8 MaxPciePorts; >=20 > + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; >=20 > + UINT8 PciePort; >=20 > + UINTN RpBase; >=20 > + UINTN RpDevice; >=20 > + UINTN RpFunction; >=20 > + UINT32 StrapFuseCfg; >=20 > + UINT8 PcieControllerCfg; >=20 > + EFI_STATUS Status; >=20 > + >=20 > + UnknowPtssTables =3D NULL; >=20 > + UnknowTableSize =3D 0; >=20 > + SpecificPtssTables =3D NULL; >=20 > + SpecificTableSize =3D 0; >=20 > + >=20 > + if (GetPchGeneration () =3D=3D SklPch) { >=20 > + switch (PchStepping ()) { >=20 > + case PchLpB0: >=20 > + case PchLpB1: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowLpHsioPtssTable1); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable1Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificLpHsioPtssTable1); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable1Size)= ; >=20 > + break; >=20 > + case PchLpC0: >=20 > + case PchLpC1: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowLpHsioPtssTable2); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable2Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificLpHsioPtssTable2); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable2Size)= ; >=20 > + break; >=20 > + case PchHB0: >=20 > + case PchHC0: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowHHsioPtssTable1); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable1Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificHHsioPtssTable1); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable1Size); >=20 > + break; >=20 > + case PchHD0: >=20 > + case PchHD1: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowHHsioPtssTable2); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificHHsioPtssTable2); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size); >=20 > + break; >=20 > + default: >=20 > + UnknowPtssTables =3D NULL; >=20 > + UnknowTableSize =3D 0; >=20 > + SpecificPtssTables =3D NULL; >=20 > + SpecificTableSize =3D 0; >=20 > + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); >=20 > + } >=20 > + } else { >=20 > + switch (PchStepping ()) { >=20 > + case KblPchHA0: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowHHsioPtssTable2); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificHHsioPtssTable2); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size); >=20 > + break; >=20 > + default: >=20 > + UnknowPtssTables =3D NULL; >=20 > + UnknowTableSize =3D 0; >=20 > + SpecificPtssTables =3D NULL; >=20 > + SpecificTableSize =3D 0; >=20 > + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); >=20 > + } >=20 > + } >=20 > + >=20 > + PtssTableIndex =3D 0; >=20 > + MaxSataPorts =3D GetPchMaxSataPortNum (); >=20 > + MaxPciePorts =3D GetPchMaxPciePortNum (); >=20 > + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); >=20 > + >=20 > + //Populate PCIe topology based on lane configuration >=20 > + for (PciePort =3D 0; PciePort < MaxPciePorts; PciePort +=3D 4) { >=20 > + Status =3D GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + RpBase =3D MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) > RpDevice, (UINT32) RpFunction); >=20 > + StrapFuseCfg =3D MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); >=20 > + PcieControllerCfg =3D (UINT8) ((StrapFuseCfg & > B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); >=20 > + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value =3D %d\n", > PciePort, PcieControllerCfg)); >=20 > + } >=20 > + for (Index =3D 0; Index < MaxPciePorts; Index++) { >=20 > + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology =3D %d\n", > Index, PcieTopologyReal[Index])); >=20 > + } >=20 > + >=20 > + //Case 1: BoardId is known, Topology is known/unknown >=20 > + //Case 1a: SATA >=20 > + PtssTables =3D SpecificPtssTables; >=20 > + TableSize =3D SpecificTableSize; >=20 > + for (Index =3D 0; Index < MaxSataPorts; Index++) { >=20 > + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { >=20 > + for (Entry =3D 0; Entry < TableSize; Entry++) { >=20 > + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && >=20 > + (PtssTables[Entry].PtssTable.PhyMode =3D=3D > V_PCH_PCR_FIA_LANE_OWN_SATA) >=20 > + ) >=20 > + { >=20 > + PtssTableIndex++; >=20 > + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_RX_DWORD20) && >=20 > + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & > B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D > (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) > { >=20 > + FspmUpd- > >FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] =3D TRUE; >=20 > + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D > (PtssTables[Entry].PtssTable.Value & (UINT32) > ~PtssTables[Entry].PtssTable.BitMask) >> > N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; >=20 > + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_TX_DWORD8)) { >=20 > + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { >=20 > + FspmUpd- > >FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] =3D TRUE; >=20 > + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> > N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); >=20 > + } >=20 > + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { >=20 > + FspmUpd- > >FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] =3D TRUE; >=20 > + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> > N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); >=20 > + } >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + //Case 1b: PCIe >=20 > + for (Index =3D 0; Index < MaxPciePorts; Index++) { >=20 > + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { >=20 > + for (Entry =3D 0; Entry < TableSize; Entry++) { >=20 > + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && >=20 > + (PtssTables[Entry].PtssTable.PhyMode =3D=3D > V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && >=20 > + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology))= { >=20 > + PtssTableIndex++; >=20 > + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_RX_DWORD25) && >=20 > + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & > B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) > B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { >=20 > + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D TR= UE; >=20 > + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > ~PtssTables[Entry].PtssTable.BitMask) >> > N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + //Case 2: BoardId is unknown, Topology is known/unknown >=20 > + if (PtssTableIndex =3D=3D 0) { >=20 > + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be > applied\n")); >=20 > + >=20 > + PtssTables =3D UnknowPtssTables; >=20 > + TableSize =3D UnknowTableSize; >=20 > + >=20 > + for (Index =3D 0; Index < MaxSataPorts; Index++) { >=20 > + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { >=20 > + for (Entry =3D 0; Entry < TableSize; Entry++) { >=20 > + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && >=20 > + (PtssTables[Entry].PtssTable.PhyMode =3D=3D > V_PCH_PCR_FIA_LANE_OWN_SATA) >=20 > + ) >=20 > + { >=20 > + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_RX_DWORD20) && >=20 > + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & > B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D > (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) > { >=20 > + FspmUpd- > >FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] =3D TRUE; >=20 > + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D > (PtssTables[Entry].PtssTable.Value & (UINT32) > ~PtssTables[Entry].PtssTable.BitMask) >> > N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; >=20 > + } else if (PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32= ) > R_PCH_HSIO_TX_DWORD8) { >=20 > + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT= 32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { >=20 > + FspmUpd- > >FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] =3D TRUE; >=20 > + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] > =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> > N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); >=20 > + } >=20 > + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT= 32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { >=20 > + FspmUpd- > >FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] =3D TRUE; >=20 > + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] > =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> > N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); >=20 > + } >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + for (Index =3D 0; Index < MaxPciePorts; Index++) { >=20 > + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { >=20 > + for (Entry =3D 0; Entry < TableSize; Entry++) { >=20 > + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && >=20 > + (PtssTables[Entry].PtssTable.PhyMode =3D=3D > V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && >=20 > + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology= )) { >=20 > + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_RX_DWORD25) && >=20 > + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & > B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) > B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { >=20 > + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D = TRUE; >=20 > + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > ~PtssTables[Entry].PtssTable.BitMask) >> > N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs FSP PCH PEI Policy pre mem initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspPchPolicyUpdatePreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + InstallPlatformHsioPtssTable (FspmUpd); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c > new file mode 100644 > index 000000000000..d6ec3e38dd7e > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c > @@ -0,0 +1,84 @@ > +/** @file >=20 > +Do Platform Stage System Agent initialization. >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include "PeiSaPolicyUpdate.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Performs FSP SA PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSaPolicyUpdate ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ) >=20 > +{ >=20 > + VOID *Buffer; >=20 > + VOID *MemBuffer; >=20 > + UINT32 Size; >=20 > + >=20 > + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); >=20 > + >=20 > + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; >=20 > + >=20 > + Size =3D 0; >=20 > + Buffer =3D NULL; >=20 > + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), > EFI_SECTION_RAW, 0, &Buffer, &Size); >=20 > + if (Buffer =3D=3D NULL) { >=20 > + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); >=20 > + } else { >=20 > + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES > ((UINTN)Size)); >=20 > + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { >=20 > + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); >=20 > + FspsUpd->FspsConfig.GraphicsConfigPtr =3D > (UINT32)(UINTN)MemBuffer; >=20 > + } else { >=20 > + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); >=20 > + FspsUpd->FspsConfig.GraphicsConfigPtr =3D 0; >=20 > + } >=20 > + } >=20 > + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is > 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr)); >=20 > + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", > Size)); >=20 > + >=20 > + Size =3D 0; >=20 > + Buffer =3D NULL; >=20 > + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, > &Buffer, &Size); >=20 > + if (Buffer =3D=3D NULL) { >=20 > + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); >=20 > + } else { >=20 > + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES > ((UINTN)Size)); >=20 > + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { >=20 > + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); >=20 > + FspsUpd->FspsConfig.LogoPtr =3D (UINT32)(UINTN)MemBuffer; >=20 > + FspsUpd->FspsConfig.LogoSize =3D Size; >=20 > + } else { >=20 > + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); >=20 > + FspsUpd->FspsConfig.LogoPtr =3D 0; >=20 > + FspsUpd->FspsConfig.LogoSize =3D 0; >=20 > + } >=20 > + } >=20 > + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", > FspsUpd->FspsConfig.LogoPtr)); >=20 > + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", > FspsUpd->FspsConfig.LogoSize)); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h > new file mode 100644 > index 000000000000..3abf3fc8fd2f > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h > @@ -0,0 +1,30 @@ > +/** @file >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef _PEI_SA_POLICY_UPDATE_H_ >=20 > +#define _PEI_SA_POLICY_UPDATE_H_ >=20 > + >=20 > +// >=20 > +// External include files do NOT need to be explicitly specified in real= EDKII >=20 > +// environment >=20 > +// >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "PeiPchPolicyUpdate.h" >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern EFI_GUID gTianoLogoGuid; >=20 > + >=20 > +#endif >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c > new file mode 100644 > index 000000000000..f95f82a25ca5 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c > @@ -0,0 +1,79 @@ > +/** @file >=20 > +Do Platform Stage System Agent initialization. >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include "PeiSaPolicyUpdate.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > + >=20 > +/** >=20 > + Performs FSP SA PEI Policy initialization in pre-memory. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSaPolicyUpdatePreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + VOID *Buffer; >=20 > + >=20 > + // >=20 > + // If SpdAddressTable are not all 0, it means DIMM slots implemented a= nd >=20 > + // MemorySpdPtr* already updated by reading SPD from DIMM in > SiliconPolicyInitPreMem. >=20 > + // >=20 > + // If SpdAddressTable all 0, this is memory down design and hardcoded > SpdData >=20 > + // should be applied to MemorySpdPtr*. >=20 > + // >=20 > + if ((PcdGet8 (PcdMrcSpdAddressTable0) =3D=3D 0) && (PcdGet8 > (PcdMrcSpdAddressTable1) =3D=3D 0) >=20 > + && (PcdGet8 (PcdMrcSpdAddressTable2) =3D=3D 0) && (PcdGet8 > (PcdMrcSpdAddressTable3) =3D=3D 0)) { >=20 > + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n")); >=20 > + CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, > (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 > (PcdMrcSpdDataSize)); >=20 > + CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, > (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 > (PcdMrcSpdDataSize)); >=20 > + } >=20 > + >=20 > + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling > Settings...\n")); >=20 > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); >=20 > + if (Buffer) { >=20 > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); >=20 > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) > Buffer + 12, 12); >=20 > + } >=20 > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); >=20 > + if (Buffer) { >=20 > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, > Buffer, 8); >=20 > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, > (UINT8*) Buffer + 8, 8); >=20 > + } >=20 > + >=20 > + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & > Rcomp Target Settings...\n")); >=20 > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); >=20 > + if (Buffer) { >=20 > + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); >=20 > + } >=20 > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); >=20 > + if (Buffer) { >=20 > + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/ > Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > new file mode 100644 > index 000000000000..f8bec0c852d6 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper > /Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > @@ -0,0 +1,150 @@ > +## @file >=20 > +# Provide FSP wrapper platform related function. >=20 > +# >=20 > +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# Defines Section - statements that will be processed to create a Makefi= le. >=20 > +# >=20 > +######################################################### > ####################### >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D SiliconPolicyUpdateLibFsp >=20 > + FILE_GUID =3D 4E83003B-49A9-459E-AAA6-1CA3C6D04FB= 2 >=20 > + MODULE_TYPE =3D PEIM >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D SiliconPolicyUpdateLib >=20 > + >=20 > + >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 >=20 > +# >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# Sources Section - list of files that are required for the build to suc= ceed. >=20 > +# >=20 > +######################################################### > ####################### >=20 > + >=20 > +[Sources] >=20 > + PeiFspPolicyUpdateLib.c >=20 > + PeiPchPolicyUpdatePreMem.c >=20 > + PeiPchPolicyUpdate.c >=20 > + PeiSaPolicyUpdatePreMem.c >=20 > + PeiSaPolicyUpdate.c >=20 > + PeiFspMiscUpdUpdateLib.c >=20 > + PcieDeviceTable.c >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# Package Dependency Section - list of Package files that are required f= or >=20 > +# this module. >=20 > +# >=20 > +######################################################### > ####################### >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + IntelFsp2Pkg/IntelFsp2Pkg.dec >=20 > + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + KabylakeFspBinPkg/KabylakeFspBinPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + >=20 > +[LibraryClasses.IA32] >=20 > + FspWrapperApiLib >=20 > + OcWdtLib >=20 > + PchResetLib >=20 > + FspWrapperPlatformLib >=20 > + BaseMemoryLib >=20 > + CpuPlatformLib >=20 > + DebugLib >=20 > + HobLib >=20 > + IoLib >=20 > + PcdLib >=20 > + PostCodeLib >=20 > + SmbusLib >=20 > + MmPciLib >=20 > + ConfigBlockLib >=20 > + PeiSaPolicyLib >=20 > + PchGbeLib >=20 > + PchInfoLib >=20 > + PchHsioLib >=20 > + PchPcieRpLib >=20 > + MemoryAllocationLib >=20 > + CpuMailboxLib >=20 > + DebugPrintErrorLevelLib >=20 > + SiPolicyLib >=20 > + PchGbeLib >=20 > + TimerLib >=20 > + GpioLib >=20 > + PeiLib >=20 > + >=20 > +[Pcd] >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## > CONSUMES >=20 > + >=20 > + # SPD Address Table >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 ## > CONSUMES >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize >=20 > + >=20 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES >=20 > + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES >=20 > + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES >=20 > + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## > CONSUMES >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid >=20 > + >=20 > +[Guids] >=20 > + gFspNonVolatileStorageHobGuid ## CONSUMES >=20 > + gTianoLogoGuid ## CONSUMES >=20 > + gEfiMemoryOverwriteControlDataGuid >=20 > + >=20 > +[Depex] >=20 > + gEdkiiVTdInfoPpiGuid >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCo > mmands.h > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCo > mmands.h > new file mode 100644 > index 000000000000..a4ab192d8ce1 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCo > mmands.h > @@ -0,0 +1,46 @@ > +/** @file >=20 > + Definition for supported EC commands. >=20 > + >=20 > +Copyright (c) 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef EC_COMMANDS_H_ >=20 > +#define EC_COMMANDS_H_ >=20 > + >=20 > +// >=20 > +// Timeout if EC command/data fails >=20 > +// >=20 > +#define EC_TIME_OUT 0x20000 >=20 > + >=20 > +// >=20 > +// The EC implements an embedded controller interface at ports 0x60/0x64 > and a ACPI compliant >=20 > +// system management controller at ports 0x62/0x66. Port 0x66 is the > command and status port, >=20 > +// port 0x62 is the data port. >=20 > +// >=20 > +#define EC_D_PORT 0x62 >=20 > +#define EC_C_PORT 0x66 >=20 > + >=20 > +// >=20 > +// Status Port 0x62 >=20 > +// >=20 > +#define EC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the > threshold >=20 > +#define EC_S_SMI_EVT 0x40 // SMI event is pending >=20 > +#define EC_S_SCI_EVT 0x20 // SCI event is pending >=20 > +#define EC_S_BURST 0x10 // EC is in burst mode or normal mode >=20 > +#define EC_S_CMD 0x08 // Byte in data register is command/dat= a >=20 > +#define EC_S_IGN 0x04 // Ignored >=20 > +#define EC_S_IBF 0x02 // Input buffer is full/empty >=20 > +#define EC_S_OBF 0x01 // Output buffer is full/empty >=20 > + >=20 > +// >=20 > +// EC commands that are issued to the EC through the command port > (0x66). >=20 > +// New commands and command parameters should only be written by the > host when IBF=3D0. >=20 > +// Data read from the EC data port is valid only when OBF=3D1. >=20 > +// >=20 > +#define EC_C_FAB_ID 0x0D // Get the board fab ID i= n the lower > 3 bits >=20 > +#define EC_C_ACPI_READ 0x80 // Read a byte of EC RAM >=20 > +#define EC_C_ACPI_WRITE 0x81 // Write a byte of EC RAM >=20 > + >=20 > +#endif // EC_COMMANDS_H_ >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/ > FlashMapInclude.fdf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/ > FlashMapInclude.fdf > new file mode 100644 > index 000000000000..b5e3f66ceafc > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/ > FlashMapInclude.fdf > @@ -0,0 +1,48 @@ > +## @file >=20 > +# FDF file for the KabylakeRvp3 board. >=20 > +# >=20 > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D# >=20 > +# 8 M BIOS - for FSP wrapper >=20 > +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D# >=20 > +DEFINE FLASH_BASE =3D = 0xFF800000 # >=20 > +DEFINE FLASH_SIZE =3D = 0x00800000 # >=20 > +DEFINE FLASH_BLOCK_SIZE =3D = 0x00010000 # >=20 > +DEFINE FLASH_NUM_BLOCKS =3D = 0x00000080 # >=20 > +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D# >=20 > + >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D > 0x00000000 # Flash addr (0xFF800000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D > 0x00040000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D > 0x00000000 # Flash addr (0xFF800000) >=20 > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > =3D 0x0001E000 # >=20 > +SET > gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D > 0x0001E000 # Flash addr (0xFF81E000) >=20 > +SET > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D > 0x00002000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset > =3D 0x00020000 # Flash addr (0xFF820000) >=20 > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > =3D 0x00020000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D > 0x00040000 # Flash addr (0xFF840000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D > 0x00050000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D > 0x00090000 # Flash addr (0xFF890000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D > 0x00070000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D > 0x00100000 # Flash addr (0xFF900000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D > 0x00090000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D > 0x00190000 # Flash addr (0xFF990000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D > 0x001E0000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D > 0x00370000 # Flash addr (0xFFB70000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D > 0x00180000 # >=20 > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D > 0x004F0000 # Flash addr (0xFFCF0000) >=20 > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > 0x000A0000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D > 0x00590000 # Flash addr (0xFFD90000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D > 0x00060000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D > 0x005F0000 # Flash addr (0xFFDF0000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D > 0x000BC000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D > 0x006AC000 # Flash addr (0xFFEAC000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D > 0x00014000 # >=20 > +SET > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =3D > 0x006C0000 # Flash addr (0xFFEC0000) >=20 > +SET > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize =3D > 0x00010000 # >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D > 0x006D0000 # Flash addr (0xFFED0000) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D > 0x00130000 # >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Base > PlatformHookLib/BasePlatformHookLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Base > PlatformHookLib/BasePlatformHookLib.c > new file mode 100644 > index 000000000000..c7fc6986f547 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Base > PlatformHookLib/BasePlatformHookLib.c > @@ -0,0 +1,662 @@ > +/** @file >=20 > + Platform Hook Library instances >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define COM1_BASE 0x3f8 >=20 > +#define COM2_BASE 0x2f8 >=20 > + >=20 > +#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690 >=20 > + >=20 > +#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E >=20 > +#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F >=20 > +#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20 >=20 > + >=20 > +#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E >=20 > +#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F >=20 > +#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E >=20 > +#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F >=20 > + >=20 > +typedef struct { >=20 > + UINT8 Register; >=20 > + UINT8 Value; >=20 > +} EFI_SIO_TABLE; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] =3D { >=20 > + {0x002, 0x88}, // Power On UARTs >=20 > + {0x024, COM1_BASE >> 2}, >=20 > + {0x025, COM2_BASE >> 2}, >=20 > + {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3D3,UART1 IRQ=3D4, >=20 > + {0x029, 0x080}, // SIRQ_CLKRUN_EN >=20 > + {0x02A, 0x000}, >=20 > + {0x02B, 0x0DE}, >=20 > + {0x00A, 0x040}, >=20 > + {0x00C, 0x00E}, >=20 > + {0x02c, 0x002}, >=20 > + {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4}, >=20 > + {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8}, >=20 > + {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff}, >=20 > + {0x03a, 0x00A}, // LPC Docking Enabling >=20 > + {0x031, 0x01f}, >=20 > + {0x032, 0x000}, >=20 > + {0x033, 0x004}, >=20 > + {0x038, 0x0FB}, >=20 > + {0x035, 0x0FE}, >=20 > + {0x036, 0x000}, >=20 > + {0x037, 0x0FF}, >=20 > + {0x039, 0x000}, >=20 > + {0x034, 0x001}, >=20 > + {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF}, = // > Relocate configuration ports base address >=20 > + {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF} = // to > ensure SIO config address can be accessed in OS >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE > mSioTableSmsc1000[] =3D { >=20 > + {0x002, 0x88}, // Power On UARTs >=20 > + {0x007, 0x00}, >=20 > + {0x024, COM1_BASE >> 2}, >=20 > + {0x025, COM2_BASE >> 2}, >=20 > + {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3D3,UART1 IRQ=3D4, >=20 > + {0x029, 0x080}, // SIRQ_CLKRUN_EN >=20 > + {0x02A, 0x000}, >=20 > + {0x02B, 0x0DE}, >=20 > + {0x00A, 0x040}, >=20 > + {0x00C, 0x00E}, >=20 > + {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4}, >=20 > + {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8}, >=20 > + {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff}, >=20 > + {0x03a, 0x00A}, // LPC Docking Enabling >=20 > + {0x031, 0x01f}, >=20 > + {0x032, 0x000}, >=20 > + {0x033, 0x004}, >=20 > + {0x038, 0x0FB}, >=20 > + {0x035, 0x0FE}, >=20 > + {0x036, 0x000}, >=20 > + {0x037, 0x0FE}, >=20 > + {0x039, 0x000}, >=20 > + {0x034, 0x001} >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE > mSioTableWpcn381u[] =3D { >=20 > + {0x29, 0x0A0}, // Enable super I/O clock and set to 4= 8MHz >=20 > + {0x22, 0x003}, // >=20 > + {0x07, 0x003}, // Select UART0 device >=20 > + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB >=20 > + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB >=20 > + {0x70, 0x004}, // Set to IRQ4 >=20 > + {0x30, 0x001}, // Enable it with Activation bit >=20 > + {0x07, 0x002}, // Select UART1 device >=20 > + {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB >=20 > + {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB >=20 > + {0x70, 0x003}, // Set to IRQ3 >=20 > + {0x30, 0x001}, // Enable it with Activation bit >=20 > + {0x07, 0x007}, // Select GPIO device >=20 > + {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base > Address MSB >=20 > + {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base > Address LSB >=20 > + {0x30, 0x001}, // Enable it with Activation bit >=20 > + {0x21, 0x001}, // Global Device Enable >=20 > + {0x26, 0x000} // Fast Enable UART 0 & 1 as their ena= ble & > activation bit >=20 > +}; >=20 > + >=20 > +// >=20 > +// National PC8374L >=20 > +// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] > =3D { >=20 > + {0x007, 0x03}, // Select Com1 >=20 > + {0x061, 0xF8}, // 0x3F8 >=20 > + {0x060, 0x03}, // 0x3F8 >=20 > + {0x070, 0x04}, // IRQ4 >=20 > + {0x030, 0x01} // Active >=20 > +}; >=20 > + >=20 > +// >=20 > +// IT8628 >=20 > +// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE > mSioIt8628TableSerialPort[] =3D { >=20 > + {0x023, 0x09}, // Clock Selection register >=20 > + {0x007, 0x01}, // Com1 Logical Device Number select >=20 > + {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register >=20 > + {0x060, 0x03}, // Serial Port 1 Base Address LSB Register >=20 > + {0x070, 0x04}, // Serial Port 1 Interrupt Level Select >=20 > + {0x030, 0x01}, // Serial Port 1 Activate >=20 > + {0x007, 0x02}, // Com1 Logical Device Number select >=20 > + {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register >=20 > + {0x060, 0x02}, // Serial Port 2 Base Address MSB Register >=20 > + {0x070, 0x03}, // Serial Port 2 Interrupt Level Select >=20 > + {0x030, 0x01} // Serial Port 2 Activate >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE > mSioIt8628TableParallelPort[] =3D { >=20 > + {0x007, 0x03}, // Parallel Port Logical Device Number select >=20 > + {0x030, 0x00}, // Parallel port Activate >=20 > + {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register >=20 > + {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register >=20 > + {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register >=20 > + {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register >=20 > + {0x0F0, 0x03} // Special Configuration register >=20 > +}; >=20 > + >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE > mSioTableWinbondX374[] =3D { >=20 > + {0x07, 0x03}, // Select UART0 device >=20 > + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB >=20 > + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB >=20 > + {0x70, 0x04}, // Set to IRQ4 >=20 > + {0x30, 0x01} // Enable it with Activation bit >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] =3D { >=20 > + {0x07, 0x02}, // Set logical device SP Serial port Com0 >=20 > + {0x61, 0xF8}, // Write Base Address LSB register 0x3F8 >=20 > + {0x60, 0x03}, // Write Base Address MSB register 0x3F8 >=20 > + {0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard >=20 > + {0x30, 0x01} // Enable serial port with Activation bit >=20 > +}; >=20 > + >=20 > +/** >=20 > + Detect if a National 393 SIO is docked. If yes, enable the docked SIO >=20 > + and its serial port, and disable the onboard serial port. >=20 > + >=20 > + @retval EFI_SUCCESS Operations performed successfully. >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +CheckNationalSio ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT8 Data8; >=20 > + >=20 > + // >=20 > + // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). >=20 > + // We use (0x2e, 0x2f) which is determined by BADD default strapping >=20 > + // >=20 > + >=20 > + // >=20 > + // Read the Pc87393 signature >=20 > + // >=20 > + IoWrite8 (0x2e, 0x20); >=20 > + Data8 =3D IoRead8 (0x2f); >=20 > + >=20 > + if (Data8 =3D=3D 0xea) { >=20 > + // >=20 > + // Signature matches - National PC87393 SIO is docked >=20 > + // >=20 > + >=20 > + // >=20 > + // Enlarge the LPC decode scope to accommodate the Docking LPC Switc= h >=20 > + // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated > at >=20 > + // SIO_BASE_ADDRESS + 0x10) >=20 > + // >=20 > + PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & > (UINT16)~0x7F), 0x20); >=20 > + >=20 > + // >=20 > + // Enable port switch >=20 > + // >=20 > + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); >=20 > + >=20 > + // >=20 > + // Turn on docking power >=20 > + // >=20 > + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); >=20 > + >=20 > + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); >=20 > + >=20 > + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); >=20 > + >=20 > + // >=20 > + // Enable port switch >=20 > + // >=20 > + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); >=20 > + >=20 > + // >=20 > + // GPIO setting >=20 > + // >=20 > + IoWrite8 (0x2e, 0x24); >=20 > + IoWrite8 (0x2f, 0x29); >=20 > + >=20 > + // >=20 > + // Enable chip clock >=20 > + // >=20 > + IoWrite8 (0x2e, 0x29); >=20 > + IoWrite8 (0x2f, 0x1e); >=20 > + >=20 > + >=20 > + // >=20 > + // Enable serial port >=20 > + // >=20 > + >=20 > + // >=20 > + // Select com1 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x7); >=20 > + IoWrite8 (0x2f, 0x3); >=20 > + >=20 > + // >=20 > + // Base address: 0x3f8 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x60); >=20 > + IoWrite8 (0x2f, 0x03); >=20 > + IoWrite8 (0x2e, 0x61); >=20 > + IoWrite8 (0x2f, 0xf8); >=20 > + >=20 > + // >=20 > + // Interrupt: 4 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x70); >=20 > + IoWrite8 (0x2f, 0x04); >=20 > + >=20 > + // >=20 > + // Enable bank selection >=20 > + // >=20 > + IoWrite8 (0x2e, 0xf0); >=20 > + IoWrite8 (0x2f, 0x82); >=20 > + >=20 > + // >=20 > + // Activate >=20 > + // >=20 > + IoWrite8 (0x2e, 0x30); >=20 > + IoWrite8 (0x2f, 0x01); >=20 > + >=20 > + // >=20 > + // Disable onboard serial port >=20 > + // >=20 > + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); >=20 > + >=20 > + // >=20 > + // Power Down UARTs >=20 > + // >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); >=20 > + >=20 > + // >=20 > + // Dissable COM1 decode >=20 > + // >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); >=20 > + >=20 > + // >=20 > + // Disable COM2 decode >=20 > + // >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); >=20 > + >=20 > + // >=20 > + // Disable interrupt >=20 > + // >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); >=20 > + >=20 > + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); >=20 > + >=20 > + // >=20 > + // Enable floppy >=20 > + // >=20 > + >=20 > + // >=20 > + // Select floppy >=20 > + // >=20 > + IoWrite8 (0x2e, 0x7); >=20 > + IoWrite8 (0x2f, 0x0); >=20 > + >=20 > + // >=20 > + // Base address: 0x3f0 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x60); >=20 > + IoWrite8 (0x2f, 0x03); >=20 > + IoWrite8 (0x2e, 0x61); >=20 > + IoWrite8 (0x2f, 0xf0); >=20 > + >=20 > + // >=20 > + // Interrupt: 6 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x70); >=20 > + IoWrite8 (0x2f, 0x06); >=20 > + >=20 > + // >=20 > + // DMA 2 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x74); >=20 > + IoWrite8 (0x2f, 0x02); >=20 > + >=20 > + // >=20 > + // Activate >=20 > + // >=20 > + IoWrite8 (0x2e, 0x30); >=20 > + IoWrite8 (0x2f, 0x01); >=20 > + >=20 > + } else { >=20 > + >=20 > + // >=20 > + // No National pc87393 SIO is docked, turn off dock power and >=20 > + // disable port switch >=20 > + // >=20 > + // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); >=20 > + // IoWrite8 (0x690, 0); >=20 > + >=20 > + // >=20 > + // If no National pc87393, just return >=20 > + // >=20 > + return; >=20 > + } >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > +Check whether the IT8628 SIO present on LPC. If yes, enable its serial >=20 > +ports, parallel port, and port 80. >=20 > + >=20 > +@retval EFI_SUCCESS Operations performed successfully. >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +It8628SioSerialPortInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT8 ChipId0 =3D 0; >=20 > + UINT8 ChipId1 =3D 0; >=20 > + UINT16 LpcIoDecondeRangeSet =3D 0; >=20 > + UINT16 LpcIoDecoodeSet =3D 0; >=20 > + UINT8 Index; >=20 > + UINTN LpcBaseAddr; >=20 > + >=20 > + >=20 > + // >=20 > + // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port > 2Eh/2Fh. >=20 > + // >=20 > + LpcBaseAddr =3D MmPciBase ( >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + PCI_DEVICE_NUMBER_PCH_LPC, >=20 > + PCI_FUNCTION_NUMBER_PCH_LPC >=20 > + ); >=20 > + >=20 > + LpcIoDecondeRangeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + > R_PCH_LPC_IOD); >=20 > + LpcIoDecoodeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + > R_PCH_LPC_IOE); >=20 > + MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet > | ((V_PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8))); >=20 > + MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | > (B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE))); >=20 > + >=20 > + // >=20 > + // Enter MB PnP Mode >=20 > + // >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87); >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01); >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55); >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55); >=20 > + >=20 > + // >=20 > + // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21) >=20 > + // >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20); >=20 > + ChipId0 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); >=20 > + >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21); >=20 > + ChipId1 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); >=20 > + >=20 > + // >=20 > + // Enable Serial Port 1, Port 2 >=20 > + // >=20 > + if ((ChipId0 =3D=3D 0x86) && (ChipId1 =3D=3D 0x28)) { >=20 > + for (Index =3D 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeo= f > (EFI_SIO_TABLE); Index++) { >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, > mSioIt8628TableSerialPort[Index].Register); >=20 > + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, > mSioIt8628TableSerialPort[Index].Value); >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Exit MB PnP Mode >=20 > + // >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02); >=20 > + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02); >=20 > + >=20 > + return; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Performs platform specific initialization required for the CPU to acce= ss >=20 > + the hardware associated with a SerialPortLib instance. This function = does >=20 > + not initialize the serial port hardware itself. Instead, it initializ= es >=20 > + hardware devices that are required for the CPU to access the serial po= rt >=20 > + hardware. This function may be called more than once. >=20 > + >=20 > + @retval RETURN_SUCCESS The platform specific initialization > succeeded. >=20 > + @retval RETURN_DEVICE_ERROR The platform specific initialization coul= d > not be completed. >=20 > + >=20 > +**/ >=20 > +RETURN_STATUS >=20 > +EFIAPI >=20 > +PlatformHookSerialPortInitialize ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT16 ConfigPort; >=20 > + UINT16 IndexPort; >=20 > + UINT16 DataPort; >=20 > + UINT16 DeviceId; >=20 > + UINT8 Index; >=20 > + UINT16 AcpiBase; >=20 > + >=20 > + // >=20 > + // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit >=20 > + // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use. >=20 > + // >=20 > + IndexPort =3D 0; >=20 > + DataPort =3D 0; >=20 > + Index =3D 0; >=20 > + AcpiBase =3D 0; >=20 > + PchAcpiBaseGet (&AcpiBase); >=20 > + if (AcpiBase =3D=3D 0) { >=20 > + PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress)); >=20 > + } >=20 > + >=20 > + // >=20 > + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port > 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. >=20 > + // >=20 > + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); >=20 > + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); >=20 > + >=20 > + // Configure Sio IT8628 >=20 > + It8628SioSerialPortInit (); >=20 > + >=20 > + DeviceId =3D MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + > R_SA_MC_DEVICE_ID); >=20 > + if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) { >=20 > + // >=20 > + // if no EC, it is SV Bidwell Bar board >=20 > + // >=20 > + if ((IoRead8 (0x66) !=3D 0xFF) && (IoRead8 (0x62) !=3D 0xFF)) { >=20 > + // >=20 > + // Super I/O initialization for SMSC SI1007 >=20 > + // >=20 > + ConfigPort =3D FixedPcdGet16 (PcdLpcSioConfigDefaultPort); >=20 > + DataPort =3D PcdGet16 (PcdLpcSioDataDefaultPort); >=20 > + IndexPort =3D PcdGet16 (PcdLpcSioIndexDefaultPort); >=20 > + >=20 > + // >=20 > + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF; >=20 > + // >=20 > + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), > 0x10); >=20 > + >=20 > + // >=20 > + // Program and Enable Default Super IO Configuration Port Addresse= s > and range >=20 > + // >=20 > + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & > (~0xF), 0x10); >=20 > + >=20 > + // >=20 > + // Enter Config Mode >=20 > + // >=20 > + IoWrite8 (ConfigPort, 0x55); >=20 > + >=20 > + // >=20 > + // Check for SMSC SIO1007 >=20 > + // >=20 > + IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register i= s 0x0D >=20 > + if (IoRead8 (DataPort) =3D=3D 0x20) { // SMSC SIO1007 Device ID = is 0x20 >=20 > + // >=20 > + // Configure SIO >=20 > + // >=20 > + for (Index =3D 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_T= ABLE); > Index++) { >=20 > + IoWrite8 (IndexPort, mSioTable[Index].Register); >=20 > + IoWrite8 (DataPort, mSioTable[Index].Value); >=20 > + } >=20 > + >=20 > + // >=20 > + // Exit Config Mode >=20 > + // >=20 > + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); >=20 > + >=20 > + // >=20 > + // GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of CRB_SC= H >=20 > + // >=20 > + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f); >=20 > + } >=20 > + >=20 > + // >=20 > + // Check if a National Pc87393 SIO is docked >=20 > + // >=20 > + CheckNationalSio (); >=20 > + >=20 > + // >=20 > + // Super I/O initialization for SMSC SIO1000 >=20 > + // >=20 > + ConfigPort =3D PcdGet16 (PcdLpcSioIndexPort); >=20 > + IndexPort =3D PcdGet16 (PcdLpcSioIndexPort); >=20 > + DataPort =3D PcdGet16 (PcdLpcSioDataPort); >=20 > + >=20 > + // >=20 > + // Enter Config Mode >=20 > + // >=20 > + IoWrite8 (ConfigPort, 0x55); >=20 > + >=20 > + // >=20 > + // Check for SMSC SIO1000 >=20 > + // >=20 > + if (IoRead8 (ConfigPort) !=3D 0xFF) { >=20 > + // >=20 > + // Configure SIO >=20 > + // >=20 > + for (Index =3D 0; Index < sizeof (mSioTableSmsc1000) / sizeof > (EFI_SIO_TABLE); Index++) { >=20 > + IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register); >=20 > + IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value); >=20 > + } >=20 > + >=20 > + // >=20 > + // Exit Config Mode >=20 > + // >=20 > + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); >=20 > + } >=20 > + >=20 > + // >=20 > + // Super I/O initialization for Winbond WPCN381U >=20 > + // >=20 > + IndexPort =3D LPC_SIO_INDEX_DEFAULT_PORT_2; >=20 > + DataPort =3D LPC_SIO_DATA_DEFAULT_PORT_2; >=20 > + >=20 > + // >=20 > + // Check for Winbond WPCN381U >=20 > + // >=20 > + IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID > register is 0x20 >=20 > + if (IoRead8 (DataPort) =3D=3D 0xF4) { // Winbond WPCN381U Device= ID is > 0xF4 >=20 > + // >=20 > + // Configure SIO >=20 > + // >=20 > + for (Index =3D 0; Index < sizeof (mSioTableWpcn381u) / sizeof > (EFI_SIO_TABLE); Index++) { >=20 > + IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register); >=20 > + IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value); >=20 > + } >=20 > + } >=20 > + } //EC is not exist, skip mobile board detection for SV board >=20 > + >=20 > + // >=20 > + //add for SV Bidwell Bar board >=20 > + // >=20 > + if (IoRead8 (COM1_BASE) =3D=3D 0xFF) { >=20 > + // >=20 > + // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (L= DC) >=20 > + // Looking for LDC2 card first >=20 > + // >=20 > + IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55); >=20 > + if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) =3D=3D 0x55) { >=20 > + IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; >=20 > + DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT; >=20 > + } else { >=20 > + IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT; >=20 > + DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT; >=20 > + } >=20 > + >=20 > + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID regi= ster is > 0x20 >=20 > + if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID = is 0xF1 >=20 > + for (Index =3D 0; Index < sizeof (mSioTableWinbondX374) / sizeof > (EFI_SIO_TABLE); Index++) { >=20 > + IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register); >=20 > + IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value); >=20 > + } >=20 > + } >=20 > + }// end of Bidwell Bar SIO initialization >=20 > + } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || > IS_SA_DEVICE_ID_SERVER (DeviceId)) { >=20 > + // >=20 > + // If we are in debug mode, we will allow serial status codes >=20 > + // >=20 > + >=20 > + // >=20 > + // National PC8374 SIO & Winbond WPCD374 (LDC2) >=20 > + // >=20 > + IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; >=20 > + >=20 > + IoWrite8 (IndexPort, 0x55); >=20 > + if (IoRead8 (IndexPort) =3D=3D 0x55) { >=20 > + IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; >=20 > + DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT; >=20 > + } else { >=20 > + IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT; >=20 > + DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT; >=20 > + } >=20 > + >=20 > + // >=20 > + // Configure SIO >=20 > + // >=20 > + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID regist= er is 0x20 >=20 > + if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID is= 0xF1 >=20 > + for (Index =3D 0; Index < sizeof (mDesktopSioTable) / sizeof > (EFI_SIO_TABLE); Index++) { >=20 > + IoWrite8 (IndexPort, mDesktopSioTable[Index].Register); >=20 > + //PrePpiStall (200); >=20 > + IoWrite8 (DataPort, mDesktopSioTable[Index].Value); >=20 > + //PrePpiStall (200); >=20 > + } >=20 > + return RETURN_SUCCESS; >=20 > + } >=20 > + // >=20 > + // Configure Pilot3 SIO >=20 > + // >=20 > + IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config > mode. >=20 > + IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); // Pil= ot3 > SIO Device ID register is 0x20. >=20 > + if (IoRead8 (PILOTIII_SIO_DATA_PORT) =3D=3D PILOTIII_CHIP_ID) { /= / Pilot3 > SIO Device ID register is 0x03. >=20 > + // >=20 > + // Configure SIO >=20 > + // >=20 > + for (Index =3D 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_S= IO_TABLE); > Index++) { >=20 > + IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Regist= er); >=20 > + IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value); >=20 > + } >=20 > + } >=20 > + IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mo= de. >=20 > + } >=20 > + >=20 > + >=20 > + return RETURN_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Base > PlatformHookLib/BasePlatformHookLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Base > PlatformHookLib/BasePlatformHookLib.inf > new file mode 100644 > index 000000000000..7a5e290657f2 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Base > PlatformHookLib/BasePlatformHookLib.inf > @@ -0,0 +1,51 @@ > +### @file >=20 > +# Platform Hook Library instance for Kaby Lake RVP3. >=20 > +# >=20 > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +### >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D BasePlatformHookLib >=20 > + FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963= D >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D BASE >=20 > + LIBRARY_CLASS =3D PlatformHookLib >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + MmPciLib >=20 > + PciLib >=20 > + PchCycleDecodingLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Pcd] >=20 > + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CON= SUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort ## > CONSUMES >=20 > + >=20 > +[FixedPcd] >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## > CONSUMES >=20 > + >=20 > +[Sources] >=20 > + BasePlatformHookLib.c >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeBoardAcpiTableLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeBoardAcpiTableLib.c > new file mode 100644 > index 000000000000..8699f8d4033f > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeBoardAcpiTableLib.c > @@ -0,0 +1,36 @@ > +/** @file >=20 > + Kaby Lake RVP 3 Board ACPI library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardUpdateAcpiTable ( >=20 > + IN OUT EFI_ACPI_COMMON_HEADER *Table, >=20 > + IN OUT EFI_ACPI_TABLE_VERSION *Version >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardUpdateAcpiTable ( >=20 > + IN OUT EFI_ACPI_COMMON_HEADER *Table, >=20 > + IN OUT EFI_ACPI_TABLE_VERSION *Version >=20 > + ) >=20 > +{ >=20 > + KabylakeRvp3BoardUpdateAcpiTable (Table, Version); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeBoardAcpiTableLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeBoardAcpiTableLib.inf > new file mode 100644 > index 000000000000..e0bf5823d8c6 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeBoardAcpiTableLib.inf > @@ -0,0 +1,48 @@ > +### @file >=20 > +# Kaby Lake RVP 3 Board ACPI library >=20 > +# >=20 > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +### >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D DxeBoardAcpiTableLib >=20 > + FILE_GUID =3D 6562E0AE-90D8-4D41-8C97-81286B4BE7D= 2 >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D BASE >=20 > + LIBRARY_CLASS =3D BoardAcpiTableLib >=20 > + >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + PciLib >=20 > + AslUpdateLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + BoardModulePkg/BoardModulePkg.dec >=20 > + >=20 > +[Pcd] >=20 > + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress >=20 > + >=20 > +[Sources] >=20 > + DxeKabylakeRvp3AcpiTableLib.c >=20 > + DxeBoardAcpiTableLib.c >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeKabylakeRvp3AcpiTableLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeKabylakeRvp3AcpiTableLib.c > new file mode 100644 > index 000000000000..d66283f7e830 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeKabylakeRvp3AcpiTableLib.c > @@ -0,0 +1,76 @@ > +/** @file >=20 > + Kaby Lake RVP 3 Board ACPI Library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED > EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea; >=20 > + >=20 > +VOID >=20 > +KabylakeRvp3UpdateGlobalNvs ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + >=20 > + // >=20 > + // Allocate and initialize the NVS area for SMM and ASL communication. >=20 > + // >=20 > + mGlobalNvsArea.Area =3D (VOID *)(UINTN)PcdGet64 > (PcdAcpiGnvsAddress); >=20 > + >=20 > + // >=20 > + // Update global NVS area for ASL and SMM init code to use >=20 > + // >=20 > + >=20 > + // >=20 > + // Enable PowerState >=20 > + // >=20 > + mGlobalNvsArea.Area->PowerState =3D 1; // AC =3D1; for mobile platform= , will > update this value in SmmPlatform.c >=20 > + >=20 > + mGlobalNvsArea.Area->NativePCIESupport =3D PcdGet8 > (PcdPciExpNative); >=20 > + >=20 > + // >=20 > + // Enable APIC >=20 > + // >=20 > + mGlobalNvsArea.Area->ApicEnable =3D GLOBAL_NVS_DEVICE_ENABLE; >=20 > + >=20 > + // >=20 > + // Low Power S0 Idle - Enabled/Disabled >=20 > + // >=20 > + mGlobalNvsArea.Area->LowPowerS0Idle =3D PcdGet8 > (PcdLowPowerS0Idle); >=20 > + >=20 > + mGlobalNvsArea.Area->Ps2MouseEnable =3D FALSE; >=20 > + mGlobalNvsArea.Area->Ps2KbMsEnable =3D PcdGet8 > (PcdPs2KbMsEnable); >=20 > + >=20 > + mGlobalNvsArea.Area->BoardId =3D (UINT8) LibPcdGetSku (); >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardUpdateAcpiTable ( >=20 > + IN OUT EFI_ACPI_COMMON_HEADER *Table, >=20 > + IN OUT EFI_ACPI_TABLE_VERSION *Version >=20 > + ) >=20 > +{ >=20 > + if (Table->Signature =3D=3D > EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE > ) { >=20 > + KabylakeRvp3UpdateGlobalNvs (); >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeMultiBoardAcpiSupportLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeMultiBoardAcpiSupportLib.c > new file mode 100644 > index 000000000000..dfb1b028f18f > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeMultiBoardAcpiSupportLib.c > @@ -0,0 +1,43 @@ > +/** @file >=20 > + Kaby Lake RVP 3 Multi-Board ACPI Support library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardUpdateAcpiTable ( >=20 > + IN OUT EFI_ACPI_COMMON_HEADER *Table, >=20 > + IN OUT EFI_ACPI_TABLE_VERSION *Version >=20 > + ); >=20 > + >=20 > +BOARD_ACPI_TABLE_FUNC mKabylakeRvp3BoardAcpiTableFunc =3D { >=20 > + KabylakeRvp3BoardUpdateAcpiTable >=20 > +}; >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetS= ku () > =3D=3D BoardIdSkylakeRvp3)) { >=20 > + return RegisterBoardAcpiTableFunc > (&mKabylakeRvp3BoardAcpiTableFunc); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeMultiBoardAcpiSupportLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeMultiBoardAcpiSupportLib.inf > new file mode 100644 > index 000000000000..e5de9268e71e > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/DxeMultiBoardAcpiSupportLib.inf > @@ -0,0 +1,49 @@ > +### @file >=20 > +# Kaby Lake RVP 3 Multi-Board ACPI Support library >=20 > +# >=20 > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +### >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D DxeKabylakeRvp3MultiBoardAcpiTableL= ib >=20 > + FILE_GUID =3D 8E6A3B38-53E0-48C0-970F-058F380FCB8= 0 >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D BASE >=20 > + LIBRARY_CLASS =3D NULL >=20 > + CONSTRUCTOR =3D > DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor >=20 > + >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + PciLib >=20 > + AslUpdateLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + BoardModulePkg/BoardModulePkg.dec >=20 > + >=20 > +[Pcd] >=20 > + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress >=20 > + >=20 > +[Sources] >=20 > + DxeKabylakeRvp3AcpiTableLib.c >=20 > + DxeMultiBoardAcpiSupportLib.c >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmBoardAcpiEnableLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmBoardAcpiEnableLib.c > new file mode 100644 > index 000000000000..e89624ea0372 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmBoardAcpiEnableLib.c > @@ -0,0 +1,62 @@ > +/** @file >=20 > + Kaby Lake RVP 3 SMM Board ACPI Enable library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ) >=20 > +{ >=20 > + SiliconEnableAcpi (EnableSci); >=20 > + return KabylakeRvp3BoardEnableAcpi (EnableSci); >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ) >=20 > +{ >=20 > + SiliconDisableAcpi (DisableSci); >=20 > + return KabylakeRvp3BoardDisableAcpi (DisableSci); >=20 > +} >=20 > + >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmBoardAcpiEnableLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmBoardAcpiEnableLib.inf > new file mode 100644 > index 000000000000..46a714dc1d97 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmBoardAcpiEnableLib.inf > @@ -0,0 +1,47 @@ > +### @file >=20 > +# Kaby Lake RVP 3 SMM Board ACPI Enable library >=20 > +# >=20 > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +### >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D SmmBoardAcpiEnableLib >=20 > + FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58A= D >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D BASE >=20 > + LIBRARY_CLASS =3D BoardAcpiEnableLib >=20 > + >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + PciLib >=20 > + MmPciLib >=20 > + PchCycleDecodingLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Pcd] >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## > CONSUMES >=20 > + >=20 > +[Protocols] >=20 > + >=20 > +[Sources] >=20 > + SmmKabylakeRvp3AcpiEnableLib.c >=20 > + SmmSiliconAcpiEnableLib.c >=20 > + SmmBoardAcpiEnableLib.c >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c > new file mode 100644 > index 000000000000..54755dd17695 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c > @@ -0,0 +1,39 @@ > +/** @file >=20 > + Kaby Lake RVP 3 SMM Board ACPI Enable library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ) >=20 > +{ >=20 > + // enable additional board register >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ) >=20 > +{ >=20 > + // enable additional board register >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmMultiBoardAcpiSupportLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmMultiBoardAcpiSupportLib.c > new file mode 100644 > index 000000000000..fb678a19bcf9 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmMultiBoardAcpiSupportLib.c > @@ -0,0 +1,81 @@ > +/** @file >=20 > + Kaby Lake RVP 3 SMM Multi-Board ACPI Support library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3MultiBoardEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ) >=20 > +{ >=20 > + SiliconEnableAcpi (EnableSci); >=20 > + return KabylakeRvp3BoardEnableAcpi (EnableSci); >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3MultiBoardDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ) >=20 > +{ >=20 > + SiliconDisableAcpi (DisableSci); >=20 > + return KabylakeRvp3BoardDisableAcpi (DisableSci); >=20 > +} >=20 > + >=20 > +BOARD_ACPI_ENABLE_FUNC mKabylakeRvp3BoardAcpiEnableFunc =3D { >=20 > + KabylakeRvp3MultiBoardEnableAcpi, >=20 > + KabylakeRvp3MultiBoardDisableAcpi, >=20 > +}; >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGet= Sku () > =3D=3D BoardIdSkylakeRvp3)) { >=20 > + return RegisterBoardAcpiEnableFunc > (&mKabylakeRvp3BoardAcpiEnableFunc); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmMultiBoardAcpiSupportLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmMultiBoardAcpiSupportLib.inf > new file mode 100644 > index 000000000000..fca63c831431 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmMultiBoardAcpiSupportLib.inf > @@ -0,0 +1,48 @@ > +### @file >=20 > +# Kaby Lake RVP 3 SMM Multi-Board ACPI Support library >=20 > +# >=20 > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +### >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D SmmKabylakeRvp3MultiBoardAcpiSuppor= tLib >=20 > + FILE_GUID =3D 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF= 5 >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D BASE >=20 > + LIBRARY_CLASS =3D NULL >=20 > + CONSTRUCTOR =3D > SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor >=20 > + >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + PciLib >=20 > + MmPciLib >=20 > + PchCycleDecodingLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Pcd] >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## > CONSUMES >=20 > + >=20 > +[Protocols] >=20 > + >=20 > +[Sources] >=20 > + SmmKabylakeRvp3AcpiEnableLib.c >=20 > + SmmSiliconAcpiEnableLib.c >=20 > + SmmMultiBoardAcpiSupportLib.c >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmSiliconAcpiEnableLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmSiliconAcpiEnableLib.c > new file mode 100644 > index 000000000000..7f63a12bf461 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dAcpiLib/SmmSiliconAcpiEnableLib.c > @@ -0,0 +1,168 @@ > +/** @file >=20 > + Kaby Lake RVP 3 SMM Silicon ACPI Enable library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Clear Port 80h >=20 > + >=20 > + SMI handler to enable ACPI mode >=20 > + >=20 > + Dispatched on reads from APM port with value > EFI_ACPI_ENABLE_SW_SMI >=20 > + >=20 > + Disables the SW SMI Timer. >=20 > + ACPI events are disabled and ACPI event status is cleared. >=20 > + SCI mode is then enabled. >=20 > + >=20 > + Clear SLP SMI status >=20 > + Enable SLP SMI >=20 > + >=20 > + Disable SW SMI Timer >=20 > + >=20 > + Clear all ACPI event status and disable all ACPI events >=20 > + >=20 > + Disable PM sources except power button >=20 > + Clear status bits >=20 > + >=20 > + Disable GPE0 sources >=20 > + Clear status bits >=20 > + >=20 > + Disable GPE1 sources >=20 > + Clear status bits >=20 > + >=20 > + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) >=20 > + >=20 > + Enable SCI >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ) >=20 > +{ >=20 > + UINT32 OutputValue; >=20 > + UINT32 SmiEn; >=20 > + UINT32 SmiSts; >=20 > + UINT32 ULKMC; >=20 > + UINTN LpcBaseAddress; >=20 > + UINT16 AcpiBaseAddr; >=20 > + UINT32 Pm1Cnt; >=20 > + >=20 > + LpcBaseAddress =3D MmPciBase ( >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + PCI_DEVICE_NUMBER_PCH_LPC, >=20 > + PCI_FUNCTION_NUMBER_PCH_LPC >=20 > + ); >=20 > + >=20 > + // >=20 > + // Get the ACPI Base Address >=20 > + // >=20 > + PchAcpiBaseGet (&AcpiBaseAddr); >=20 > + >=20 > + // >=20 > + // BIOS must also ensure that CF9GR is cleared and locked before handi= ng > control to the >=20 > + // OS in order to prevent the host from issuing global resets and rese= tting > ME >=20 > + // >=20 > + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global > Reset >=20 > + // MmioWrite32 ( >=20 > + // PmcBaseAddress + R_PCH_PMC_ETR3), >=20 > + // PmInit); >=20 > + >=20 > + // >=20 > + // Clear Port 80h >=20 > + // >=20 > + IoWrite8 (0x80, 0); >=20 > + >=20 > + // >=20 > + // Disable SW SMI Timer and clean the status >=20 > + // >=20 > + SmiEn =3D IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN); >=20 > + SmiEn &=3D ~(B_PCH_SMI_EN_LEGACY_USB2 | > B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB); >=20 > + IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn); >=20 > + >=20 > + SmiSts =3D IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS); >=20 > + SmiSts |=3D B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR > | B_PCH_SMI_EN_LEGACY_USB; >=20 > + IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts); >=20 > + >=20 > + // >=20 > + // Disable port 60/64 SMI trap if they are enabled >=20 > + // >=20 > + ULKMC =3D MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) & > ~(B_PCH_LPC_ULKMC_60REN | B_PCH_LPC_ULKMC_60WEN | > B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC_64WEN | > B_PCH_LPC_ULKMC_A20PASSEN); >=20 > + MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC); >=20 > + >=20 > + // >=20 > + // Disable PM sources except power button >=20 > + // >=20 > + IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN, > B_PCH_ACPI_PM1_EN_PWRBTN); >=20 > + >=20 > + // >=20 > + // Clear PM status except Power Button status for RapidStart Resume >=20 > + // >=20 > + IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF); >=20 > + >=20 > + // >=20 > + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) >=20 > + // >=20 > + IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD); >=20 > + IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0); >=20 > + >=20 > + // >=20 > + // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#) >=20 > + // >=20 > + OutputValue =3D IoRead32 (AcpiBaseAddr + 0x38); >=20 > + OutputValue =3D OutputValue & ~(1 << (UINTN) PcdGet8 > (PcdSmcExtSmiBitPosition)); >=20 > + IoWrite32 (AcpiBaseAddr + 0x38, OutputValue); >=20 > + >=20 > + >=20 > + // >=20 > + // Enable SCI >=20 > + // >=20 > + if (EnableSci) { >=20 > + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT); >=20 > + Pm1Cnt |=3D B_PCH_ACPI_PM1_CNT_SCI_EN; >=20 > + IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt); >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ) >=20 > +{ >=20 > + UINT16 AcpiBaseAddr; >=20 > + UINT32 Pm1Cnt; >=20 > + >=20 > + // >=20 > + // Get the ACPI Base Address >=20 > + // >=20 > + PchAcpiBaseGet (&AcpiBaseAddr); >=20 > + >=20 > + // >=20 > + // Disable SCI >=20 > + // >=20 > + if (DisableSci) { >=20 > + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT); >=20 > + Pm1Cnt &=3D ~B_PCH_ACPI_PM1_CNT_SCI_EN; >=20 > + IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt); >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3GpioTable.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3GpioTable.c > new file mode 100644 > index 000000000000..2439c6bc1edc > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3GpioTable.c > @@ -0,0 +1,381 @@ > +/** @file >=20 > + GPIO definition table for KabylakeRvp3 >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef _KABYLAKE_RVP3_GPIO_TABLE_H_ >=20 > +#define _KABYLAKE_RVP3_GPIO_TABLE_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > + >=20 > +#define END_OF_GPIO_TABLE 0xFFFFFFFF >=20 > + >=20 > +GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =3D >=20 > +{ >=20 > +//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermNone}},//H_RCIN_N >=20 > +//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0 >=20 > +//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1 >=20 > +//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2 >=20 > +//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3 >=20 > +//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N >=20 > +//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ >=20 > + {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//PM_SLP_S0ix_R_N >=20 > +// skip for PM_CLKRUN_N {GPIO_SKL_LP_GPP_A8, > {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, > GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N >=20 > +//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK >=20 > +// skip for PCH_CLK_PCI_TPM {GPIO_SKL_LP_GPP_A10, > {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, > GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM >=20 > + {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, > GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR >=20 > + {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, > GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N >=20 > +//skip for SUS_PWR_ACK_R {GPIO_SKL_LP_GPP_A13, > {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, > GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R >=20 > +//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N >=20 > +//skip for SUSACK_R_N {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, > GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, > GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N >=20 > + {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_1P8_SEL >=20 > + {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_PWR_EN_N >=20 > + {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_GP_0_SENSOR >=20 > + {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_GP_1_SENSOR >=20 > + {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_GP_2_SENSOR >=20 > + {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//GNSS_CHUB_IRQ >=20 > + {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//FPS_SLP_N >=20 > + {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, > GpioHostDeepReset, GpioTermNone}},//FPS_DRDY >=20 > + {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//V0.85A_VID0 >=20 > + {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//V0.85A_VID1 >=20 > + {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//GP_VRALERTB >=20 > + {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformRes= et, > GpioTermNone}},//TCH_PAD_INTR_R_N >=20 > + {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//BT_RF_KILL_N >=20 > + {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, > GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N >=20 > + // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//CLK_REQ_SLOT1_N >=20 > + // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//CLK_REQ_SLOT2_LAN_N >=20 > + // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N >=20 > + // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//CLK_REQ_M.2_WIGIG_N >=20 > + // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//CLK_REQ_M.2_WLAN_N >=20 > + {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//MPHY_EXT_PWR_GATEB >=20 > + {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//PCH_SLP_S0_N >=20 > + {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//PLT_RST_N >=20 > + {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//TCH_PNL_PWREN >=20 > + // {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//PCH_NFC_DFU, NOT OWNED BY BIOS >=20 > + {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformRese= t, > GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N >=20 > + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset= , > GpioTermWpu20K}},//TBT_CIO_PLUG_EVENT_N >=20 > + {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformRese= t, > GpioTermWpu20K}},//PCH_SLOT1_WAKE_N >=20 > + {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//FPS_GSPI1_CS_R1_N >=20 > + {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//FPS_GSPI1_CLK_R1 >=20 > + {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//FPS_GSPI1_MISO_R1 >=20 > + {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1 >=20 > + {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N >=20 > + {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SMB_CLK >=20 > + {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//SMB_DATA >=20 > + {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N >=20 > + {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SML0_CLK >=20 > + {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SML0_DATA >=20 > + {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, > GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N >=20 > + {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SML1_CLK, OWNED BY ME >=20 > + {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//SML1_DATA, OWNED BY ME >=20 > + {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART0_RXD >=20 > + {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART0_TXD >=20 > + {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART0_RTS_N >=20 > + {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART0_CTS_N >=20 > + {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD >=20 > + {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD >=20 > + {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N >=20 > + {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N >=20 > + {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_I2C0_SDA >=20 > + {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_I2C0_SCL >=20 > + {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_I2C1_SDA >=20 > + {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_I2C1_SCL >=20 > + {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART2_RXD >=20 > + {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART2_TXD >=20 > + {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART2_RTS_N >=20 > + {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SERIALIO_UART2_CTS_N >=20 > + {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SPI1_TCHPNL_CS_N >=20 > + {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SPI1_TCHPNL_CLK >=20 > + {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SPI1_TCHPNL_MISO >=20 > + {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SPI1_TCHPNL_MOSI >=20 > + {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//CSI2_FLASH_STROBE >=20 > + {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_I2C0_SDA >=20 > + {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_I2C0_SCL >=20 > + {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_I2C1_SDA >=20 > + {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_I2C1_SCL >=20 > + {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepRese= t, > GpioTermNone}},//HOME_BTN >=20 > + {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepRese= t, > GpioTermNone}},//SCREEN_LOCK_PCH >=20 > + {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepRese= t, > GpioTermNone}},//VOL_UP_PCH >=20 > + {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepRese= t, > GpioTermNone}},//VOL_DOWN_PCH >=20 > + {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA >=20 > + {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK >=20 > + {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_UART0_RTS_N >=20 > + {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N >=20 > + {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//DMIC_CLK_1 >=20 > + {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//DMIC_DATA_1 >=20 > + {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//DMIC_CLK_0 >=20 > + {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//DMIC_DATA_0 >=20 > + {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SPI1_TCHPNL_IO2 >=20 > + {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SPI1_TCHPNL_IO3 >=20 > + {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SSP_MCLK >=20 > + {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, > GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N >=20 > + {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SATA_ODD_PRSNT_N >=20 > + {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, > GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N >=20 > + {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, > GpioTermNone}},//EINK_SSR_DFU_N >=20 > + {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//PCH_NFC_RESET >=20 > + {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R >=20 > + // {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R, NOT OWNED BY BIOS >=20 > + {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//PCH_SATA_LED_N >=20 > + {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//USB_OC_0_WP1_OTG_N >=20 > + {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//USB_OC_1_WP4_N >=20 > + {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N >=20 > + // {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepRese= t, > GpioTermNone}},//PCH_NFC_IRQ, NOT OWNED BY BIOS >=20 > + {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//DDI1_HPD_Q >=20 > + {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//DDI2_HPD_Q >=20 > + {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, > GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N >=20 > + {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformRese= t, > GpioTermNone}},//SMC_RUNTIME_SCI_R_N >=20 > + {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EDP_HPD >=20 > + {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//DDI1_CTRL_CLK >=20 > + {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//DDI1_CTRL_DATA >=20 > + {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//DDI2_CTRL_CLK >=20 > + {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//DDI2_CTRL_DATA >=20 > + {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, > GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ >=20 > + {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermWpd20K}},//TCH_PNL_RST_N >=20 > + {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SSP2_SCLK >=20 > + {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SSP2_SFRM >=20 > + {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SSP2_TXD >=20 > + {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SSP2_RXD >=20 > + {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA >=20 > + {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL >=20 > + {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA >=20 > + {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL >=20 > + {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA >=20 > + {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL >=20 > + {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA >=20 > + {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL >=20 > + {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_CMD >=20 > + {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_DATA0 >=20 > + {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_DATA1 >=20 > + {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_DATA2 >=20 > + {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_DATA3 >=20 > + {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_DATA4 >=20 > + {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_DATA5 >=20 > + {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_DATA6 >=20 > + {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_DATA7 >=20 > + {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_RCLK >=20 > + {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//EMMC_CLK >=20 > + {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, > GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET >=20 > + {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_CMD >=20 > + {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_DATA0 >=20 > + {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_DATA1 >=20 > + {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_DATA2 >=20 > + {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_DATA3 >=20 > + {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_CDB >=20 > + {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_CLK >=20 > + {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone}},//SD_WP >=20 > + {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//PM_BATLOW_R_N >=20 > + {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//AC_PRESENT_R >=20 > + {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, > GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N >=20 > + {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermWpu20K}},//PM_PWRBTN_R_N >=20 > + {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//SLP_S3_R_N >=20 > + {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//SLP_S4_R_N >=20 > + {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//SLP_M_R_N >=20 > + {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//USB_WAKEOUT_INTRUDET_N >=20 > + {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//SUS_CLK >=20 > + {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//PCH_SLP_WLAN_N >=20 > + {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//SLP_S5_R_N >=20 > + {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//PM_LANPHY_ENABLE >=20 > + {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, > GpioTermNone}},//Marking End of Table >=20 > +}; >=20 > + >=20 > +UINT16 mGpioTableLpDdr3Rvp3Size =3D sizeof (mGpioTableLpDdr3Rvp3) / > sizeof (GPIO_INIT_CONFIG) - 1; >=20 > + >=20 > +GPIO_INIT_CONFIG mGpioTableKabyLakeYLpddr3Rvp3[] =3D >=20 > +{ >=20 > + { GPIO_SKL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioResumeReset, > GpioTermNone } },//REALSENSE_ISH_WAKE >=20 > + { GPIO_SKL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone } },//IRIS_PROXI_INTR >=20 > + { GPIO_SKL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, > GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N >=20 > + { GPIO_SKL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntApic, > GpioHostDeepReset, GpioTermNone } },//SD_CARD_WAKE >=20 > + { GPIO_SKL_LP_GPP_D11, { GpioPadModeNative2, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone } },//TYPEC_P1_DCI_CLK >=20 > + { GPIO_SKL_LP_GPP_D12, { GpioPadModeNative2, GpioHostOwnGpio, > GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, > GpioTermNone } },//TYPEC_P1_DCI_DATA >=20 > +}; >=20 > + >=20 > +UINT16 mGpioTableKabyLakeYLpddr3Rvp3Size =3D sizeof > (mGpioTableKabyLakeYLpddr3Rvp3) / sizeof (GPIO_INIT_CONFIG); >=20 > + >=20 > +GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[] =3D >=20 > +{ >=20 > + { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, > GpioTermNone } }, //GPP_B0 >=20 > + { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, > GpioTermNone } }, //GPP_B1 >=20 > +}; >=20 > + >=20 > +UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize =3D sizeof > (mGpioTableLpddr3Rvp3UcmcDevice) / sizeof (GPIO_INIT_CONFIG); >=20 > + >=20 > +GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel =3D >=20 > + {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformRes= et, > GpioTermNone}}; >=20 > + >=20 > +GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3SdhcSidebandCardDetect =3D >=20 > + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirIn, GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset, > GpioTermNone}}; //SD_CDB D3 >=20 > + >=20 > +//IO Expander Table for SKL RVP7, RVP13 and RVP15 >=20 > +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] =3D >=20 > +{ >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26 >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27 >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOE > XP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED}//M.2_WIGIG_PWREN_IOEXP >=20 > +}; >=20 > + >=20 > +UINT16 mGpioTableIoExpanderSize =3D sizeof (mGpioTableIoExpander) / > sizeof (IO_EXPANDER_GPIO_CONFIG); >=20 > + >=20 > +//IO Expander Table for KBL -Refresh >=20 > +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] =3D >=20 > +{ >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//Unused pin >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//RTD3_USB_PD1_PWR_EN >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//HRESET_PD1_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N >=20 > + //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R >=20 > + // We want the initial state to be high. >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_RST_CNTRL_R >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_WAKE_CTRL_R_N >=20 > + // Turn off WWAN power and will turn it on later. >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//RSVD >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//RSVD >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOE > XP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP >=20 > +}; >=20 > +UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 =3D sizeof > (mGpioTableIoExpanderKabylakeRDdr4) / sizeof > (IO_EXPANDER_GPIO_CONFIG); >=20 > + >=20 > +//IO Expander Table for KBL -kc >=20 > +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] =3D >=20 > +{ >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//RSVD >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//RSVD >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26 >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27 >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOE > XP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_8, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_9, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_FLEX_PWREN >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB_UART_SEL >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_DOCK_PWREN_IOEXP_R >=20 > +}; >=20 > +UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 =3D sizeof > (mGpioTableIoExpanderKabylakeKcDdr3) / sizeof > (IO_EXPANDER_GPIO_CONFIG); >=20 > +//IO Expander Table Full table for KBL RVP3 >=20 > +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRvp3[] =3D >=20 > +{ >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_3.3_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SNSR_HUB_DFU_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SATA_PWR_EN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WLAN_WAKE_CTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//GFX_CRB_DET_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//MFG_MODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//FLIP_TO_TABLET_MODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCH_SLOT1_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB3_CAM_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//RSVD_TESTMODE_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//BIOS_REC_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//EINK_PWREN_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TBT_FORCE_PWR_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIFI_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//DGPU_PRSNT_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED > },//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD) >=20 > +//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN_IOEXP > (SKL_RVP3_BOARD) >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//IMAGING_DFU_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//SW_GFX_PWERGD_IOEXP >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_WAKE_CTRL_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_LOW, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_SSD_RST_IOEXP_N >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P26 >=20 > + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//TP_IOEXP1_P27 >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WWAN_DISABLE_IOEXP_N >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_WP4_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, > IO_EXPANDER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED },//Not Connected (KBK_RVP3_BOARD) >=20 > +//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_OTG_WP1_PWREN_IOEXP > (SKL_RVP3_BOARD) >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB32_WP2_WP3_WP5_PWREN_R_IOE > XP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//PCH_AUDIO_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_GNSS_DISABLE_IOEXP_N >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//M.2_WIGIG_PWREN_IOEXP >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//USB2_CAM_PWREN (KBL_RVP3_BOARD) >=20 > + {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, > IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDER_GPO_LEVEL_HIGH, > IO_EXPANDER_GPI_INV_DISABLED, > IO_EXPANDER_GPIO_RESERVED},//FPS_LOCK_N (KBL_RVP3_BOARD) >=20 > +}; >=20 > + >=20 > +UINT16 mGpioTableIoExpanderKabylakeRvp3Size =3D sizeof > (mGpioTableIoExpanderKabylakeRvp3) / sizeof > (IO_EXPANDER_GPIO_CONFIG); >=20 > + >=20 > +#endif // _KABYLAKE_RVP3_GPIO_TABLE_H_ >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3HdaVerbTables.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3HdaVerbTables.c > new file mode 100644 > index 000000000000..92afcbab0653 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3HdaVerbTables.c > @@ -0,0 +1,232 @@ > +/** @file >=20 > + HDA Verb table for KabylakeRvp3 >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef _KABYLAKE_RVP3_HDA_VERB_TABLES_H_ >=20 > +#define _KABYLAKE_RVP3_HDA_VERB_TABLES_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 =3D > HDAUDIO_VERB_TABLE_INIT ( >=20 > + // >=20 > + // VerbTable: (Realtek ALC286) for RVP3 >=20 > + // Revision ID =3D 0xff >=20 > + // Codec Verb Table for SKL PCH boards >=20 > + // Codec Address: CAd value (0/1/2) >=20 > + // Codec Vendor: 0x10EC0286 >=20 > + // >=20 > + 0x10EC, 0x0286, >=20 > + 0xFF, 0xFF, >=20 > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > + // >=20 > + // Realtek Semiconductor Corp. >=20 > + // >=20 > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > + >=20 > + //Realtek High Definition Audio Configuration - Version : 5.0.2.9 >=20 > + //Realtek HD Audio Codec : ALC286 >=20 > + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 >=20 > + //HDA Codec PnP ID : > HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E >=20 > + //The number of verb command block : 16 >=20 > + >=20 > + // NID 0x12 : 0x411111F0 >=20 > + // NID 0x13 : 0x40000000 >=20 > + // NID 0x14 : 0x9017011F >=20 > + // NID 0x17 : 0x90170110 >=20 > + // NID 0x18 : 0x03A11040 >=20 > + // NID 0x19 : 0x411111F0 >=20 > + // NID 0x1A : 0x411111F0 >=20 > + // NID 0x1D : 0x4066A22D >=20 > + // NID 0x1E : 0x411111F0 >=20 > + // NID 0x21 : 0x03211020 >=20 > + >=20 > + >=20 > + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D >=20 > + //HDA Codec Subsystem ID : 0x10EC108E >=20 > + 0x0017208E, >=20 > + 0x00172110, >=20 > + 0x001722EC, >=20 > + 0x00172310, >=20 > + >=20 > + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D >=20 > + //Widget node 0x01 : >=20 > + 0x0017FF00, >=20 > + 0x0017FF00, >=20 > + 0x0017FF00, >=20 > + 0x0017FF00, >=20 > + //Pin widget 0x12 - DMIC >=20 > + 0x01271CF0, >=20 > + 0x01271D11, >=20 > + 0x01271E11, >=20 > + 0x01271F41, >=20 > + //Pin widget 0x13 - DMIC >=20 > + 0x01371C00, >=20 > + 0x01371D00, >=20 > + 0x01371E00, >=20 > + 0x01371F40, >=20 > + //Pin widget 0x14 - SPEAKER-OUT (Port-D) >=20 > + 0x01771C1F, >=20 > + 0x01771D01, >=20 > + 0x01771E17, >=20 > + 0x01771F90, >=20 > + //Pin widget 0x17 - I2S-OUT >=20 > + 0x01771C10, >=20 > + 0x01771D01, >=20 > + 0x01771E17, >=20 > + 0x01771F90, >=20 > + //Pin widget 0x18 - MIC1 (Port-B) >=20 > + 0x01871C40, >=20 > + 0x01871D10, >=20 > + 0x01871EA1, >=20 > + 0x01871F03, >=20 > + //Pin widget 0x19 - I2S-IN >=20 > + 0x01971CF0, >=20 > + 0x01971D11, >=20 > + 0x01971E11, >=20 > + 0x01971F41, >=20 > + //Pin widget 0x1A - LINE1 (Port-C) >=20 > + 0x01A71CF0, >=20 > + 0x01A71D11, >=20 > + 0x01A71E11, >=20 > + 0x01A71F41, >=20 > + //Pin widget 0x1D - PC-BEEP >=20 > + 0x01D71C2D, >=20 > + 0x01D71DA2, >=20 > + 0x01D71E66, >=20 > + 0x01D71F40, >=20 > + //Pin widget 0x1E - S/PDIF-OUT >=20 > + 0x01E71CF0, >=20 > + 0x01E71D11, >=20 > + 0x01E71E11, >=20 > + 0x01E71F41, >=20 > + //Pin widget 0x21 - HP-OUT (Port-A) >=20 > + 0x02171C20, >=20 > + 0x02171D10, >=20 > + 0x02171E21, >=20 > + 0x02171F03, >=20 > + //Widget node 0x20 : >=20 > + 0x02050071, >=20 > + 0x02040014, >=20 > + 0x02050010, >=20 > + 0x02040C22, >=20 > + //Widget node 0x20 - 1 : >=20 > + 0x0205004F, >=20 > + 0x02045029, >=20 > + 0x0205004F, >=20 > + 0x02045029, >=20 > + //Widget node 0x20 - 2 : >=20 > + 0x0205002B, >=20 > + 0x02040DD0, >=20 > + 0x0205002D, >=20 > + 0x02047020, >=20 > + //Widget node 0x20 - 3 : >=20 > + 0x0205000E, >=20 > + 0x02046C80, >=20 > + 0x01771F90, >=20 > + 0x01771F90, >=20 > + //TI AMP settings : >=20 > + 0x02050022, >=20 > + 0x0204004C, >=20 > + 0x02050023, >=20 > + 0x02040000, >=20 > + 0x02050025, >=20 > + 0x02040000, >=20 > + 0x02050026, >=20 > + 0x0204B010, >=20 > + >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + >=20 > + 0x02050022, >=20 > + 0x0204004C, >=20 > + 0x02050023, >=20 > + 0x02040002, >=20 > + 0x02050025, >=20 > + 0x02040011, >=20 > + 0x02050026, >=20 > + 0x0204B010, >=20 > + >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + >=20 > + 0x02050022, >=20 > + 0x0204004C, >=20 > + 0x02050023, >=20 > + 0x0204000D, >=20 > + 0x02050025, >=20 > + 0x02040010, >=20 > + 0x02050026, >=20 > + 0x0204B010, >=20 > + >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + >=20 > + 0x02050022, >=20 > + 0x0204004C, >=20 > + 0x02050023, >=20 > + 0x02040025, >=20 > + 0x02050025, >=20 > + 0x02040008, >=20 > + 0x02050026, >=20 > + 0x0204B010, >=20 > + >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + >=20 > + 0x02050022, >=20 > + 0x0204004C, >=20 > + 0x02050023, >=20 > + 0x02040002, >=20 > + 0x02050025, >=20 > + 0x02040000, >=20 > + 0x02050026, >=20 > + 0x0204B010, >=20 > + >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + 0x000F0000, >=20 > + >=20 > + 0x02050022, >=20 > + 0x0204004C, >=20 > + 0x02050023, >=20 > + 0x02040003, >=20 > + 0x02050025, >=20 > + 0x02040000, >=20 > + 0x02050026, >=20 > + 0x0204B010 >=20 > +); >=20 > + >=20 > +#endif // _KABYLAKE_RVP3_HDA_VERB_TABLES_H_ >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3HsioPtssTables.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3HsioPtssTables.c > new file mode 100644 > index 000000000000..8a9048fa4c88 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3HsioPtssTables.c > @@ -0,0 +1,105 @@ > +/** @file >=20 > + KabylakeRvp3 HSIO PTSS H File >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef KABYLAKE_RVP3_HSIO_PTSS_H_ >=20 > +#define KABYLAKE_RVP3_HSIO_PTSS_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#ifndef HSIO_PTSS_TABLE_SIZE >=20 > +#define HSIO_PTSS_TABLE_SIZE(A) A##_Size =3D sizeof (A) / sizeof > (HSIO_PTSS_TABLES) >=20 > +#endif >=20 > + >=20 > +//BoardId KabylakeRvp3 >=20 > +HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[] =3D { >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoM2}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopoM2}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopox4}, >=20 > + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) > ~0x3F000000}, PchSataTopoDirectConnect}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopoM2}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopox4}, >=20 > + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopox4}, >=20 > + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopox4}, >=20 > + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopoM2}, >=20 > + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopox1}, >=20 > + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) > ~0x3F3F00}, PchSataTopoM2}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) > ~0x3F3F00}, PchSataTopoDirectConnect}, >=20 > + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopoM2}, >=20 > + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopox1}, >=20 > + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown} >=20 > +}; >=20 > + >=20 > +UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size =3D > sizeof(PchLpHsioPtss_Cx_KabylakeRvp3) / sizeof(HSIO_PTSS_TABLES); >=20 > + >=20 > +HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[] =3D { >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchPcieTopoUnknown}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopox4}, >=20 > + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) > ~0x3F000000}, PchSataTopoDirectConnect}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopox4}, >=20 > + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopox4}, >=20 > + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) > ~0x3F000000}, PchSataTopoUnknown}, >=20 > + {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopox4}, >=20 > + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopox1}, >=20 > + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) > ~0x3F3F00}, PchPcieTopoUnknown}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) > ~0x3F3F00}, PchSataTopoDirectConnect}, >=20 > + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopox1}, >=20 > + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) > ~0x1F0000}, PchPcieTopoUnknown}, >=20 > + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) > ~0x3F3F00}, PchSataTopoUnknown}, >=20 > +}; >=20 > + >=20 > +UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size =3D > sizeof(PchLpHsioPtss_Bx_KabylakeRvp3) / sizeof(HSIO_PTSS_TABLES); >=20 > + >=20 > +#endif // KABYLAKE_RVP3_HSIO_PTSS_H_ >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3SpdTable.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3SpdTable.c > new file mode 100644 > index 000000000000..e4ad785bda20 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/KabylakeRvp3SpdTable.c > @@ -0,0 +1,541 @@ > +/** @file >=20 > + GPIO definition table for KabylakeRvp3 >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef _KABYLAKE_RVP3_SPD_TABLE_H_ >=20 > +#define _KABYLAKE_RVP3_SPD_TABLE_H_ >=20 > + >=20 > +// >=20 > +// DQByteMap[0] - ClkDQByteMap: >=20 > +// If clock is per rank, program to [0xFF, 0xFF] >=20 > +// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] >=20 > +// If clock is shared by 2 ranks but does not go to all bytes, >=20 > +// Entry[i] defines which DQ bytes Group i services >=20 > +// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is > CmdN/CAB >=20 > +// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is > CmdS/CAB >=20 > +// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is > CKE /CAB >=20 > +// For DDR, DQByteMap[3:1] =3D [0xFF, 0] >=20 > +// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we > have 1 CTL / rank >=20 > +// Variable only exists to make the code e= asier to use >=20 > +// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we > have 1 CA Vref >=20 > +// Variable only exists to make the code e= asier to use >=20 > +// >=20 > +// >=20 > +// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL > SDS - used by SKL/KBL MRC >=20 > +// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 > mDqByteMapSklRvp3[2][6][2] =3D { >=20 > + // Channel 0: >=20 > + { >=20 > + { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to > package 1 - Bytes[7:4] >=20 > + { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4] >=20 > + { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to > Byte[7:4] >=20 > + { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB >=20 > + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes >=20 > + { 0xFF, 0x00 } // CA Vref is one for all bytes >=20 > + }, >=20 > + // Channel 1: >=20 > + { >=20 > + { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to > package 1 - Bytes[7:4] >=20 > + { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4] >=20 > + { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to > Byte[7:4] >=20 > + { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB >=20 > + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes >=20 > + { 0xFF, 0x00 } // CA Vref is one for all bytes >=20 > + } >=20 > +}; >=20 > + >=20 > +// >=20 > +// DQS byte swizzling between CPU and DRAM - for SKL DOE RVP >=20 > +// >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 > mDqsMapCpu2DramSklRvp3[2][8] =3D { >=20 > + { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0 >=20 > + { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1 >=20 > +}; >=20 > + >=20 > +// Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16 >=20 > +// or Hynix H9CCNNNBLTALAR-NUD >=20 > +// or similar >=20 > +// 1867, 14-17-17-40 >=20 > +// 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb =3D 4GB total per chann= el >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] =3D > { >=20 > + 0x24, ///< 0 Number of Serial PD Byt= es Written / SPD > Device Size >=20 > + 0x20, ///< 1 SPD Revision >=20 > + 0x0F, ///< 2 DRAM Device Type >=20 > + 0x0E, ///< 3 Module Type >=20 > + 0x14, ///< 4 SDRAM Density and Banks= : 8 Banks, 4 Gb > SDRAM density >=20 > + 0x12, ///< 5 SDRAM Addressing: 14 Ro= ws, 11 Columns >=20 > + 0xB5, ///< 6 SDRAM Package Type: QDP= , 1 Channel per > die, Signal Loading Matrix 1 >=20 > + 0x00, ///< 7 SDRAM Optional Features >=20 > + 0x00, ///< 8 SDRAM Thermal and Refre= sh Options >=20 > + 0x00, ///< 9 Other SDRAM Optional Fe= atures >=20 > + 0x00, ///< 10 Reserved - must be code= d as 0x00 >=20 > + 0x03, ///< 11 Module Nominal Voltage,= VDD >=20 > + 0x0A, ///< 12 Module Organization, SD= RAM width: 16 bits, > 2 Ranks >=20 > + 0x23, ///< 13 Module Memory Bus Width= : 2 channels, 64 > bit channel bus width >=20 > + 0x00, ///< 14 Module Thermal Sensor >=20 > + 0x00, ///< 15 Extended Module Type >=20 > + 0x00, ///< 16 Reserved - must be code= d as 0x00 >=20 > + 0x00, ///< 17 Timebases >=20 > + 0x09, ///< 18 SDRAM Minimum Cycle Tim= e (tCKmin): > tCKmin =3D 1.071ns (LPDDR3-1867) >=20 > + 0xFF, ///< 19 SDRAM Minimum Cycle Tim= e (tCKmax) >=20 > + 0xD4, ///< 20 CAS Latencies Supported= , First Byte (tCK): > 14, 12, 10, 8 >=20 > + 0x00, ///< 21 CAS Latencies Supported= , Second Byte >=20 > + 0x00, ///< 22 CAS Latencies Supported= , Third Byte >=20 > + 0x00, ///< 23 CAS Latencies Supported= , Fourth Byte >=20 > + 0x78, ///< 24 Minimum CAS Latency Tim= e (tAAmin) =3D > 14.994 ns >=20 > + 0x00, ///< 25 Read and Write Latency = Set Options >=20 > + 0x90, ///< 26 Minimum RAS# to CAS# De= lay Time > (tRCDmin) >=20 > + 0xA8, ///< 27 Minimum Row Precharge D= elay Time for all > banks (tRPab) >=20 > + 0x90, ///< 28 Minimum Row Precharge D= elay Time per > bank (tRPpb) >=20 > + 0x10, ///< 29 Minimum Refresh Recover= y Delay Time for > all banks (tRFCab), Least Significant Byte >=20 > + 0x04, ///< 30 Minimum Refresh Recover= y Delay Time for > all banks (tRFCab), Most Significant Byte >=20 > + 0xE0, ///< 31 Minimum Refresh Recover= y Delay Time for > per bank (tRFCpb), Least Significant Byte >=20 > + 0x01, ///< 32 Minimum Refresh Recover= y Delay Time for > per bank (tRFCpb), Most Significant Byte >=20 > + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM = Bit Mapping >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM = Bit Mapping >=20 > + 0, 0, ///< 78 - 79 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 >=20 > + 0x00, ///< 120 Fine Offset for Minimum= Row Precharge > Delay Time per bank (tRPpb) >=20 > + 0x00, ///< 121 Fine Offset for Minimum= Row Precharge > Delay Time for all banks (tRPab) >=20 > + 0x00, ///< 122 Fine Offset for Minimum= RAS# to CAS# > Delay Time (tRCDmin) >=20 > + 0xFA, ///< 123 Fine Offset for Minimum= CAS Latency Time > (tAAmin): 14.994 ns (LPDDR3-1867) >=20 > + 0x7F, ///< 124 Fine Offset for SDRAM M= inimum Cycle Time > (tCKmax): 32.002 ns >=20 > + 0xCA, ///< 125 Fine Offset for SDRAM M= inimum Cycle Time > (tCKmin): 1.071 ns (LPDDR-1867) >=20 > + 0x00, ///< 126 CRC A >=20 > + 0x00, ///< 127 CRC B >=20 > + 0, 0, ///< 128 - 129 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 >=20 > + 0x00, ///< 320 Module Manufacturer ID = Code, Least > Significant Byte >=20 > + 0x00, ///< 321 Module Manufacturer ID = Code, Most > Significant Byte >=20 > + 0x00, ///< 322 Module Manufacturing Lo= cation >=20 > + 0x00, ///< 323 Module Manufacturing Da= te Year >=20 > + 0x00, ///< 324 Module Manufacturing Da= te Week >=20 > + 0x55, ///< 325 Module Serial Number A >=20 > + 0x00, ///< 326 Module Serial Number B >=20 > + 0x00, ///< 327 Module Serial Number C >=20 > + 0x00, ///< 328 Module Serial Number D >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Numbe= r: > Unused bytes coded as ASCII Blanks (0x20) >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Numbe= r >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Numbe= r >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Numbe= r >=20 > + 0x00, ///< 349 Module Revision Code >=20 > + 0x00, ///< 350 DRAM Manufacturer ID Co= de, Least > Significant Byte >=20 > + 0x00, ///< 351 DRAM Manufacturer ID Co= de, Most > Significant Byte >=20 > + 0x00, ///< 352 DRAM Stepping >=20 > + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 >=20 > + 0, 0 ///< 510 - 511 >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 > mSkylakeRvp16SpdSize =3D sizeof (mSkylakeRvp16Spd); >=20 > + >=20 > +//Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die >=20 > +//1867 >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] > =3D { >=20 > + 0x91, ///< 0 Number of Serial PD B= ytes Written / SPD > Device Size / CRC Coverage 1, 2 >=20 > + 0x20, ///< 1 SPD Revision >=20 > + 0xF1, ///< 2 DRAM Device Type >=20 > + 0x03, ///< 3 Module Type >=20 > + 0x05, ///< 4 SDRAM Density and Ban= ks, 8Gb >=20 > + 0x19, ///< 5 SDRAM Addressing: 15 = Rows, 10 Columns >=20 > + 0x05, ///< 6 Module Nominal Voltag= e >=20 > + 0x0B, ///< 7 Module Organization: = 32 bits, 2 Ranks >=20 > + 0x03, ///< 8 Module Memory Bus Wid= th >=20 > + 0x11, ///< 9 Fine Timebase (FTB) D= ividend / Divisor >=20 > + 0x01, ///< 10 Medium Timebase (MTB)= Dividend >=20 > + 0x08, ///< 11 Medium Timebase (MTB)= Divisor >=20 > + 0x09, ///< 12 SDRAM Minimum Cycle T= ime (tCKmin): > tCKmin =3D 1.071 ns (LPDDR3-1867) >=20 > + 0x00, ///< 13 Reserved0 >=20 > + 0x50, ///< 14 CAS Latencies support= ed (tCK): 14, 12, 10, 8 > (LSB) >=20 > + 0x05, ///< 15 CAS Latencies support= ed (tCK): 14, 12, 10, 8 > (LSB) >=20 > + 0x78, ///< 16 Minimum CAS Latency (= tAAmin) =3D 14.994 ns >=20 > + 0x78, ///< 17 Minimum Write Recover= y Time (tWRmin) >=20 > + 0x90, ///< 18 Minimum RAS# to CAS# = Delay Time > (tRCDmin) >=20 > + 0x50, ///< 19 Minimum Row Active to= Row Active Delay > Time (tRRDmin) >=20 > + 0x90, ///< 20 Minimum Row Precharge= Delay Time > (tRPmin) >=20 > + 0x11, ///< 21 Upper Nibbles for tRA= S and tRC >=20 > + 0x50, ///< 22 Minimum Active to Pre= charge Delay Time > (tRASmin), Least Significant Byte >=20 > + 0xE0, ///< 23 Minimum Active to Act= ive/Refresh Delay > Time (tRCmin), Least Significant Byte >=20 > + 0x90, ///< 24 Minimum Refresh Recov= ery Delay Time > (tRFCmin), Least Significant Byte >=20 > + 0x06, ///< 25 Minimum Refresh Recov= ery Delay Time > (tRFCmin), Most Significant Byte >=20 > + 0x3C, ///< 26 Minimum Internal Writ= e to Read Command > Delay Time (tWTRmin) >=20 > + 0x3C, ///< 27 Minimum Internal Read= to Precharge > Command Delay Time (tRTPmin) >=20 > + 0x01, ///< 28 Upper Nibble for tFAW >=20 > + 0x90, ///< 29 Minimum Four Activate= Window Delay Time > (tFAWmin) >=20 > + 0x00, ///< 30 SDRAM Optional Featur= es >=20 > + 0x00, ///< 31 SDRAMThermalAndRefres= hOptions >=20 > + 0x00, ///< 32 ModuleThermalSensor >=20 > + 0x00, ///< 33 SDRAM Device Type >=20 > + 0xCA, ///< 34 Fine Offset for SDRAM= Minimum Cycle > Time (tCKmin): 1.071 ns (LPDDR3-1867) >=20 > + 0xFA, ///< 35 Fine Offset for Minim= um CAS Latency Time > (tAAmin): 14.994 ns (LPDDR3-1867) >=20 > + 0x00, ///< 36 Fine Offset for Minim= um RAS# to CAS# > Delay Time (tRCDmin) >=20 > + 0x00, ///< 37 Fine Offset for Minim= um Row Precharge > Delay Time (tRPmin) >=20 > + 0x00, ///< 38 Fine Offset for Minim= um Active to > Active/Refresh Delay Time (tRCmin) >=20 > + 0xA8, ///< 39 Row precharge time fo= r all banks (tRPab) >=20 > + 0x00, ///< 40 FTB for Row precharge= time for all banks > (tRPab) >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 >=20 > + 0, 0, ///< 60 - 61 >=20 > + 0x00, ///< 62 Reference Raw Card Us= ed >=20 > + 0x00, ///< 63 Address Mapping from = Edge Connector to > DRAM >=20 > + 0x00, ///< 64 ThermalHeatSpreaderSo= lution >=20 > + 0, 0, 0, 0, 0, ///< 65 - 69 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 >=20 > + 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116 >=20 > + 0x00, ///< 117 Module Manufacturer I= D Code, Least > Significant Byte >=20 > + 0x00, ///< 118 Module Manufacturer I= D Code, Most > Significant Byte >=20 > + 0x00, ///< 119 Module Manufacturing = Location >=20 > + 0x00, ///< 120 Module Manufacturing = Date Year >=20 > + 0x00, ///< 121 Module Manufacturing = Date creation work > week >=20 > + 0x55, ///< 122 Module Serial Number = A >=20 > + 0x00, ///< 123 Module Serial Number = B >=20 > + 0x00, ///< 124 Module Serial Number = C >=20 > + 0x00, ///< 125 Module Serial Number = D >=20 > + 0x00, ///< 126 CRC A >=20 > + 0x00 ///< 127 CRC B >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 > mSkylakeRvp3Spd110Size =3D sizeof (mSkylakeRvp3Spd110); >=20 > + >=20 > +// >=20 > +// Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32 >=20 > +// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] > =3D { >=20 > + 0x91, ///< 0 128 SPD bytes used, 2= 56 total, CRC covers > 0..116 >=20 > + 0x20, ///< 1 SPD Revision 2.0 >=20 > + 0xF1, ///< 2 DRAM Type: LPDDR3 SDR= AM >=20 > + 0x03, ///< 3 Module Type: SO-DIMM >=20 > + 0x05, ///< 4 8 Banks, 8 Gb SDRAM d= ensity >=20 > + 0x19, ///< 5 SDRAM Addressing: 15 = Rows, 10 Columns >=20 > + 0x05, ///< 6 Module Nominal Voltag= e VDD: 1.2v >=20 > + 0x0B, ///< 7 SDRAM width: 32 bits,= 2 Ranks >=20 > + 0x03, ///< 8 SDRAM bus width: 64 b= its, no ECC >=20 > + 0x11, ///< 9 Fine Timebase (FTB) g= ranularity: 1 ps >=20 > + 0x01, ///< 10 Medium Timebase (MTB)= : 0.125 ns >=20 > + 0x08, ///< 11 Medium Timebase Divis= or >=20 > + 0x08, ///< 12 tCKmin =3D 0.938 ns (= LPDDR3-2133) >=20 > + 0x00, ///< 13 Reserved >=20 > + 0x50, ///< 14 CAS Latencies support= ed (tCK): 16, 14, 12, > 10, 8 (LSB) >=20 > + 0x15, ///< 15 CAS Latencies support= ed (tCK): 16, 14, 12, > 10, 8 (MSB) >=20 > + 0x78, ///< 16 Minimum CAS Latency (= tAAmin) =3D 15.008 ns >=20 > + 0x78, ///< 17 tWR =3D 15 ns >=20 > + 0x90, ///< 18 Minimum RAS-to-CAS de= lay (tRCDmin) =3D 18 > ns >=20 > + 0x50, ///< 19 tRRD =3D 10 ns >=20 > + 0x90, ///< 20 Minimum row precharge= time (tRPmin) =3D 18 > ns >=20 > + 0x11, ///< 21 Upper nibbles for tRA= S and tRC >=20 > + 0x50, ///< 22 tRASmin =3D 42 ns >=20 > + 0xE0, ///< 23 tRCmin =3D (tRASmin = + tRPmin) =3D 60 ns >=20 > + 0x90, ///< 24 tRFCmin =3D (tRFCab) = =3D 210 ns (8Gb) >=20 > + 0x06, ///< 25 tRFCmin MSB >=20 > + 0x3C, ///< 26 tWTRmin =3D 7.5 ns >=20 > + 0x3C, ///< 27 tRTPmin =3D 7.5 ns >=20 > + 0x01, ///< 28 tFAWmin upper nibble >=20 > + 0x90, ///< 29 tFAWmin =3D 50 ns >=20 > + 0x00, ///< 30 SDRAM Optional Featur= es - none >=20 > + 0x00, ///< 31 SDRAM Thermal / Refre= sh options - none >=20 > + 0x00, ///< 32 ModuleThermalSensor >=20 > + 0x00, ///< 33 SDRAM Device Type >=20 > + 0xC2, ///< 34 FTB for tCKmin =3D 0.= 938 ns (LPDDR3-2133) >=20 > + 0x08, ///< 35 FTB for tAAmin =3D 15= .008 ns (LPDDR3-2133) >=20 > + 0x00, ///< 36 Fine Offset for Minim= um RAS# to CAS# > Delay Time (tRCDmin) >=20 > + 0x00, ///< 37 Fine Offset for Minim= um Row Precharge > Delay Time (tRPmin) >=20 > + 0x00, ///< 38 Fine Offset for Minim= um Active to > Active/Refresh Delay Time (tRCmin) >=20 > + 0xA8, ///< 39 Row precharge time fo= r all banks (tRPab)=3D > 21 ns >=20 > + 0x00, ///< 40 FTB for Row precharge= time for all banks > (tRPab) =3D 0 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 >=20 > + 0, 0, ///< 60 - 61 >=20 > + 0x00, ///< 62 Reference Raw Card Us= ed >=20 > + 0x00, ///< 63 Rank1 Mapping: Standa= rd >=20 > + 0x00, ///< 64 ThermalHeatSpreaderSo= lution >=20 > + 0, 0, 0, 0, 0, ///< 65 - 69 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 >=20 > + 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116 >=20 > + 0x00, ///< 117 Module Manufacturer I= D Code, Least > Significant Byte >=20 > + 0x00, ///< 118 Module Manufacturer I= D Code, Most > Significant Byte >=20 > + 0x00, ///< 119 Module Manufacturing = Location >=20 > + 0x00, ///< 120 Module Manufacturing = Date Year >=20 > + 0x00, ///< 121 Module Manufacturing = Date creation work > week >=20 > + 0x55, ///< 122 Module ID: Module Ser= ial Number >=20 > + 0x00, ///< 123 Module Serial Number = B >=20 > + 0x00, ///< 124 Module Serial Number = C >=20 > + 0x00, ///< 125 Module Serial Number = D >=20 > + 0x00, ///< 126 CRC A >=20 > + 0x00 ///< 127 CRC B >=20 > +}; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 > mKblRSpdLpddr32133Size =3D sizeof (mKblRSpdLpddr32133); >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] =3D { >=20 > + 0x24, ///< 0 Number of Serial PD Byt= es Written / SPD > Device Size >=20 > + 0x01, ///< 1 SPD Revision >=20 > + 0x0F, ///< 2 DRAM Device Type >=20 > + 0x0E, ///< 3 Module Type >=20 > + 0x15, ///< 4 SDRAM Density and Banks= : 8 Banks, 8 Gb > SDRAM density >=20 > + 0x19, ///< 5 SDRAM Addressing: 15 Ro= ws, 10 Columns >=20 > + 0x90, ///< 6 SDRAM Package Type: QDP= , 1 Channel per > die, Signal Loading Matrix 1 >=20 > + 0x00, ///< 7 SDRAM Optional Features >=20 > + 0x00, ///< 8 SDRAM Thermal and Refre= sh Options >=20 > + 0x00, ///< 9 Other SDRAM Optional Fe= atures >=20 > + 0x00, ///< 10 Reserved - must be code= d as 0x00 >=20 > + 0x0B, ///< 11 Module Nominal Voltage,= VDD >=20 > + 0x0B, ///< 12 Module Organization, SD= RAM width: 32 bits, > 2 Ranks >=20 > + 0x03, ///< 13 Module Memory Bus Width= : 2 channels, 64 > bit channel bus width >=20 > + 0x00, ///< 14 Module Thermal Sensor >=20 > + 0x00, ///< 15 Extended Module Type >=20 > + 0x00, ///< 16 Reserved - must be code= d as 0x00 >=20 > + 0x00, ///< 17 Timebases >=20 > + 0x08, ///< 18 SDRAM Minimum Cycle Tim= e (tCKmin) >=20 > + 0xFF, ///< 19 SDRAM Minimum Cycle Tim= e (tCKmax) >=20 > + 0xD4, ///< 20 CAS Latencies Supported= , First Byte >=20 > + 0x01, ///< 21 CAS Latencies Supported= , Second Byte >=20 > + 0x00, ///< 22 CAS Latencies Supported= , Third Byte >=20 > + 0x00, ///< 23 CAS Latencies Supported= , Fourth Byte >=20 > + 0x78, ///< 24 Minimum CAS Latency Tim= e (tAAmin) >=20 > + 0x00, ///< 25 Read and Write Latency = Set Options >=20 > + 0x90, ///< 26 Minimum RAS# to CAS# De= lay Time > (tRCDmin) >=20 > + 0xA8, ///< 27 Minimum Row Precharge D= elay Time for all > banks (tRPab) >=20 > + 0x90, ///< 28 Minimum Row Precharge D= elay Time per > bank (tRPpb) >=20 > + 0x90, ///< 29 Minimum Refresh Recover= y Delay Time for > all banks (tRFCab), Least Significant Byte >=20 > + 0x06, ///< 30 Minimum Refresh Recover= y Delay Time for > all banks (tRFCab), Most Significant Byte >=20 > + 0xD0, ///< 31 Minimum Refresh Recover= y Delay Time for > per bank (tRFCpb), Least Significant Byte >=20 > + 0x02, ///< 32 Minimum Refresh Recover= y Delay Time for > per bank (tRFCpb), Most Significant Byte >=20 > + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM = Bit Mapping >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM = Bit Mapping >=20 > + 0, 0, ///< 78 - 79 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 >=20 > + 0x00, ///< 120 Fine Offset for Minimum= Row Precharge > Delay Time per bank (tRPpb) >=20 > + 0x00, ///< 121 Fine Offset for Minimum= Row Precharge > Delay Time for all banks (tRPab) >=20 > + 0x00, ///< 122 Fine Offset for Minimum= RAS# to CAS# > Delay Time (tRCDmin) >=20 > + 0x08, ///< 123 Fine Offset for Minimum= CAS Latency Time > (tAAmin) >=20 > + 0x7F, ///< 124 Fine Offset for SDRAM M= inimum Cycle Time > (tCKmax) >=20 > + 0xC2, ///< 125 Fine Offset for SDRAM M= inimum Cycle Time > (tCKmin) >=20 > + 0x00, ///< 126 CRC A >=20 > + 0x00, ///< 127 CRC B >=20 > + 0, 0, ///< 128 - 129 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 >=20 > + 0x00, ///< 320 Module Manufacturer ID = Code, Least > Significant Byte >=20 > + 0x00, ///< 321 Module Manufacturer ID = Code, Most > Significant Byte >=20 > + 0x00, ///< 322 Module Manufacturing Lo= cation >=20 > + 0x00, ///< 323 Module Manufacturing Da= te Year >=20 > + 0x00, ///< 324 Module Manufacturing Da= te Week >=20 > + 0x55, ///< 325 Module Serial Number A >=20 > + 0x00, ///< 326 Module Serial Number B >=20 > + 0x00, ///< 327 Module Serial Number C >=20 > + 0x00, ///< 328 Module Serial Number D >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Numbe= r: > Unused bytes coded as ASCII Blanks (0x20) >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Numbe= r >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Numbe= r >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Numbe= r >=20 > + 0x00, ///< 349 Module Revision Code >=20 > + 0x00, ///< 350 DRAM Manufacturer ID Co= de, Least > Significant Byte >=20 > + 0x00, ///< 351 DRAM Manufacturer ID Co= de, Most > Significant Byte >=20 > + 0x00, ///< 352 DRAM Stepping >=20 > + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 >=20 > + 0, 0 ///< 510 - 511 >=20 > +}; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size > =3D sizeof (mSpdLpddr32133); >=20 > + >=20 > +/** >=20 > + Hynix H9CCNNN8JTMLAR-NTM_178b_DDP LPDDR3, 4Gb die (128Mx32), > x32 >=20 > + or Elpida EDF8132A1MC-GD-F >=20 > + or Samsung K4E8E304EB-EGCE >=20 > + 1600, 12-15-15-34 >=20 > + 2 rank per channel, 2 SDRAMs per rank, 4x4Gb =3D 2GB total per channel >=20 > +**/ >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd[] =3D { >=20 > + 0x24, ///< 0 Number of Serial PD Byt= es Written / SPD > Device Size >=20 > + 0x20, ///< 1 SPD Revision >=20 > + 0x0F, ///< 2 DRAM Device Type >=20 > + 0x0E, ///< 3 Module Type >=20 > + 0x14, ///< 4 SDRAM Density and Banks= : 8 Banks, 4 Gb > SDRAM density >=20 > + 0x11, ///< 5 SDRAM Addressing: 14 Ro= ws, 10 Columns >=20 > + 0x95, ///< 6 SDRAM Package Type: DDP= , 1 Channel per > die, Signal Loading Matrix 1 >=20 > + 0x00, ///< 7 SDRAM Optional Features >=20 > + 0x00, ///< 8 SDRAM Thermal and Refre= sh Options >=20 > + 0x00, ///< 9 Other SDRAM Optional Fe= atures >=20 > + 0x00, ///< 10 Reserved - must be code= d as 0x00 >=20 > + 0x03, ///< 11 Module Nominal Voltage,= VDD >=20 > + 0x0B, ///< 12 Module Organization, SD= RAM width: 32 bits, > 2 Ranks >=20 > + 0x23, ///< 13 Module Memory Bus Width= : 2 channels, 64 > bit channel bus width >=20 > + 0x00, ///< 14 Module Thermal Sensor >=20 > + 0x00, ///< 15 Extended Module Type >=20 > + 0x00, ///< 16 Reserved - must be code= d as 0x00 >=20 > + 0x00, ///< 17 Timebases >=20 > + 0x0A, ///< 18 SDRAM Minimum Cycle Tim= e (tCKmin) >=20 > + 0xFF, ///< 19 SDRAM Minimum Cycle Tim= e (tCKmax) >=20 > + 0x54, ///< 20 CAS Latencies Supported= , First Byte (tCk): 12 > 10 8 >=20 > + 0x00, ///< 21 CAS Latencies Supported= , Second Byte >=20 > + 0x00, ///< 22 CAS Latencies Supported= , Third Byte >=20 > + 0x00, ///< 23 CAS Latencies Supported= , Fourth Byte >=20 > + 0x78, ///< 24 Minimum CAS Latency Tim= e (tAAmin) >=20 > + 0x00, ///< 25 Read and Write Latency = Set Options >=20 > + 0x90, ///< 26 Minimum RAS# to CAS# De= lay Time > (tRCDmin) >=20 > + 0xA8, ///< 27 Minimum Row Precharge D= elay Time for all > banks (tRPab) >=20 > + 0x90, ///< 28 Minimum Row Precharge D= elay Time per > bank (tRPpb) >=20 > + 0x10, ///< 29 Minimum Refresh Recover= y Delay Time for > all banks (tRFCab), Least Significant Byte >=20 > + 0x04, ///< 30 Minimum Refresh Recover= y Delay Time for > all banks (tRFCab), Most Significant Byte >=20 > + 0xE0, ///< 31 Minimum Refresh Recover= y Delay Time for > per bank (tRFCpb), Least Significant Byte >=20 > + 0x01, ///< 32 Minimum Refresh Recover= y Delay Time for > per bank (tRFCpb), Most Significant Byte >=20 > + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM = Bit Mapping >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM = Bit Mapping >=20 > + 0, 0, ///< 78 - 79 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 >=20 > + 0x00, ///< 120 Fine Offset for Minimum= Row Precharge > Delay Time per bank (tRPpb) >=20 > + 0x00, ///< 121 Fine Offset for Minimum= Row Precharge > Delay Time for all banks (tRPab) >=20 > + 0x00, ///< 122 Fine Offset for Minimum= RAS# to CAS# > Delay Time (tRCDmin) >=20 > + 0x00, ///< 123 Fine Offset for Minimum= CAS Latency Time > (tAAmin) >=20 > + 0x7F, ///< 124 Fine Offset for SDRAM M= inimum Cycle Time > (tCKmax) >=20 > + 0x00, ///< 125 Fine Offset for SDRAM M= inimum Cycle Time > (tCKmin) >=20 > + 0x00, ///< 126 CRC A >=20 > + 0x00, ///< 127 CRC B >=20 > + 0, 0, ///< 128 - 129 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 >=20 > + 0x00, ///< 320 Module Manufacturer ID = Code, Least > Significant Byte >=20 > + 0x00, ///< 321 Module Manufacturer ID = Code, Most > Significant Byte >=20 > + 0x00, ///< 322 Module Manufacturing Lo= cation >=20 > + 0x00, ///< 323 Module Manufacturing Da= te Year >=20 > + 0x00, ///< 324 Module Manufacturing Da= te Week >=20 > + 0x55, ///< 325 Module Serial Number A >=20 > + 0x00, ///< 326 Module Serial Number B >=20 > + 0x00, ///< 327 Module Serial Number C >=20 > + 0x00, ///< 328 Module Serial Number D >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Numbe= r: > Unused bytes coded as ASCII Blanks (0x20) >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Numbe= r >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Numbe= r >=20 > + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Numbe= r >=20 > + 0x00, ///< 349 Module Revision Code >=20 > + 0x00, ///< 350 DRAM Manufacturer ID Co= de, Least > Significant Byte >=20 > + 0x00, ///< 351 DRAM Manufacturer ID Co= de, Most > Significant Byte >=20 > + 0x00, ///< 352 DRAM Stepping >=20 > + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 >=20 > + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 >=20 > + 0, 0 ///< 510 - 511 >=20 > +}; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3SpdSize > =3D sizeof (mSkylakeRvp3Spd); >=20 > +#endif // _KABYLAKE_RVP3_SPD_TABLE_H_ >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPostMemLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPostMemLib.c > new file mode 100644 > index 000000000000..2e079a0387a5 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPostMemLib.c > @@ -0,0 +1,39 @@ > +/** @file >=20 > + Kaby Lake RVP 3 Board Initialization Post-Memory library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardInitBeforeSiliconInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardInitBeforeSiliconInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + KabylakeRvp3BoardInitBeforeSiliconInit (); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardInitAfterSiliconInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPostMemLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPostMemLib.inf > new file mode 100644 > index 000000000000..bdf481b9805c > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPostMemLib.inf > @@ -0,0 +1,54 @@ > +## @file >=20 > +# Component information file for KabylakeRvp3InitLib in PEI post memory > phase. >=20 > +# >=20 > +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiBoardPostMemInitLib >=20 > + FILE_GUID =3D 7fcc3900-d38d-419f-826b-72481e8b550= 9 >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D BoardInitLib >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + DebugLib >=20 > + BaseMemoryLib >=20 > + MemoryAllocationLib >=20 > + GpioExpanderLib >=20 > + PcdLib >=20 > + SiliconInitLib >=20 > + >=20 > +[Packages] >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Sources] >=20 > + PeiKabylakeRvp3InitPostMemLib.c >=20 > + KabylakeRvp3GpioTable.c >=20 > + KabylakeRvp3HdaVerbTables.c >=20 > + PeiBoardInitPostMemLib.c >=20 > + >=20 > +[FixedPcd] >=20 > + >=20 > +[Pcd] >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPreMemLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPreMemLib.c > new file mode 100644 > index 000000000000..f5c695ecff86 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPreMemLib.c > @@ -0,0 +1,108 @@ > +/** @file >=20 > + Kaby Lake RVP 3 Board Initialization Pre-Memory library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardDetect ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_BOOT_MODE >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardBootModeDetect ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardDebugInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardInitBeforeMemoryInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardDetect ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + KabylakeRvp3BoardDetect (); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardDebugInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + KabylakeRvp3BoardDebugInit (); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_BOOT_MODE >=20 > +EFIAPI >=20 > +BoardBootModeDetect ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return KabylakeRvp3BoardBootModeDetect (); >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardInitBeforeMemoryInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetS= ku () > =3D=3D BoardIdSkylakeRvp3)) { >=20 > + KabylakeRvp3BoardInitBeforeMemoryInit (); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardInitAfterMemoryInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardInitBeforeTempRamExit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +BoardInitAfterTempRamExit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPreMemLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPreMemLib.inf > new file mode 100644 > index 000000000000..850fc514188b > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiBoardInitPreMemLib.inf > @@ -0,0 +1,135 @@ > +## @file >=20 > +# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem > Library >=20 > +# >=20 > +# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiBoardInitPreMemLib >=20 > + FILE_GUID =3D ec3675bc-1470-417d-826e-37378140213= d >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D BoardInitLib >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + DebugLib >=20 > + BaseMemoryLib >=20 > + MemoryAllocationLib >=20 > + PcdLib >=20 > + SiliconInitLib >=20 > + EcLib >=20 > + PchResetLib >=20 > + >=20 > +[Packages] >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Sources] >=20 > + PeiKabylakeRvp3Detect.c >=20 > + PeiKabylakeRvp3InitPreMemLib.c >=20 > + KabylakeRvp3HsioPtssTables.c >=20 > + KabylakeRvp3SpdTable.c >=20 > + PeiBoardInitPreMemLib.c >=20 > + >=20 > +[Pcd] >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort >=20 > + >=20 > + # PCH-LP HSIO PTSS Table >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size >=20 > + >=20 > + # PCH-H HSIO PTSS Table >=20 > + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 >=20 > + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 >=20 > + > #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size >=20 > + > #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size >=20 > + >=20 > + # SA Misc Config >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize >=20 > + >=20 > + # PEG Reset By GPIO >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive >=20 > + >=20 > + >=20 > + # SPD Address Table >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 >=20 > + >=20 > + # CA Vref Configuration >=20 > + >=20 > + # Root Port Clock Info >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo >=20 > + >=20 > + # USB 2.0 Port AFE >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe >=20 > + >=20 > + # USB 2.0 Port Over Current Pin >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 >=20 > + >=20 > + # USB 3.0 Port Over Current Pin >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 >=20 > + >=20 > + # Misc >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent >=20 > + >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3Detect.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3Detect.c > new file mode 100644 > index 000000000000..429f4316dd64 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3Detect.c > @@ -0,0 +1,124 @@ > +/** @file >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include "PeiKabylakeRvp3InitLib.h" >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define BOARD_ID_MASK_8BIT 0xff >=20 > + >=20 > +/** >=20 > + Get board fab ID. >=20 > + >=20 > + @param[out] DataBuffer >=20 > + >=20 > + @retval EFI_SUCCESS Command success >=20 > + @retval EFI_DEVICE_ERROR Command error >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GetBoardFabId ( >=20 > + OUT UINT8 *DataBuffer >=20 > + ) >=20 > +{ >=20 > + UINT8 DataSize; >=20 > + >=20 > + // >=20 > + // For 'EC_C_FAB_ID' command NumberOfSendData =3D 0, > NumberOfReceiveData =3D2. >=20 > + // >=20 > + DataSize =3D 2; >=20 > + return (LpcEcInterface (EC_C_FAB_ID, &DataSize, DataBuffer)); >=20 > +} >=20 > + >=20 > +/** >=20 > + Get RVP3 board ID. >=20 > + There are 2 different RVP3 boards having different ID. >=20 > + This function will return board ID to caller. >=20 > + >=20 > + @param[out] DataBuffer >=20 > + >=20 > + @retval EFI_SUCCESS Command success >=20 > + @retval EFI_DEVICE_ERROR Command error >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GetRvp3BoardId ( >=20 > + UINT8 *BoardId >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT16 EcBoardInfo; >=20 > + UINT8 DataBuffer[2]; >=20 > + >=20 > + Status =3D GetBoardFabId (DataBuffer); >=20 > + if (Status =3D=3D EFI_SUCCESS) { >=20 > + EcBoardInfo =3D DataBuffer[0]; >=20 > + EcBoardInfo =3D (EcBoardInfo << 8) | DataBuffer[1]; >=20 > + // >=20 > + // Get the following data: >=20 > + // [7:0] - BOARD_IDx >=20 > + // [8] - GEN_ID >=20 > + // [11:9] - REV_FAB_IDx >=20 > + // [12] - TP_SPD_PRSNT >=20 > + // [15:13] - BOM_IDx >=20 > + // >=20 > + *BoardId =3D (UINT8) (EcBoardInfo & BOARD_ID_MASK_8BIT); >=20 > + DEBUG ((DEBUG_INFO, "BoardId =3D %X\n", *BoardId)); >=20 > + } >=20 > + return Status; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardDetect ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT8 BoardId; >=20 > + >=20 > + if (LibPcdGetSku () !=3D 0) { >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "KabylakeRvp3DetectionCallback\n")); >=20 > + if (GetRvp3BoardId (&BoardId) =3D=3D EFI_SUCCESS) { >=20 > + if (BoardId =3D=3D BoardIdKabyLakeYLpddr3Rvp3) { >=20 > + LibPcdSetSku (BoardIdKabyLakeYLpddr3Rvp3); >=20 > + ASSERT (LibPcdGetSku() =3D=3D BoardIdKabyLakeYLpddr3Rvp3); >=20 > + } else if (BoardId =3D=3D BoardIdSkylakeRvp3) { >=20 > + LibPcdSetSku (BoardIdSkylakeRvp3); >=20 > + ASSERT (LibPcdGetSku() =3D=3D BoardIdSkylakeRvp3); >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3InitLib.h > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3InitLib.h > new file mode 100644 > index 000000000000..5b2ccf6b0dea > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3InitLib.h > @@ -0,0 +1,44 @@ > +/** @file >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#ifndef _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_ >=20 > +#define _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +extern const UINT8 mDqByteMapSklRvp3[2][6][2]; >=20 > +extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8]; >=20 > +extern const UINT8 mSkylakeRvp3Spd110[]; >=20 > +extern const UINT16 mSkylakeRvp3Spd110Size; >=20 > +extern const UINT8 mSkylakeRvp3Spd[]; >=20 > +extern const UINT16 mSkylakeRvp3SpdSize; >=20 > +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[]; >=20 > +extern UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size; >=20 > +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[]; >=20 > +extern UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size; >=20 > + >=20 > +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3; >=20 > +extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[]; >=20 > +extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize; >=20 > + >=20 > +extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[]; >=20 > +extern UINT16 mGpioTableIoExpanderSize; >=20 > +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel; >=20 > +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[]; >=20 > +extern UINT16 mGpioTableLpDdr3Rvp3Size; >=20 > + >=20 > +#endif // _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_ >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3InitPostMemLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3InitPostMemLib.c > new file mode 100644 > index 000000000000..5d398ab6654e > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3InitPostMemLib.c > @@ -0,0 +1,208 @@ > +/** @file >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include "PeiKabylakeRvp3InitLib.h" >=20 > + >=20 > +/** >=20 > + SkylaeA0Rvp3 board configuration init function for PEI post memory pha= se. >=20 > + >=20 > + PEI_BOARD_CONFIG_PCD_INIT >=20 > + >=20 > + @param Content pointer to the buffer contain init information for bo= ard > init. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > + @retval EFI_INVALID_PARAMETER The parameter is NULL. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3Init ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3); >=20 > + >=20 > + // >=20 > + // Assign the GPIO table with pin configs to be used for UCMC >=20 > + // >=20 > + PcdSet32S (PcdBoardUcmcGpioTable, > (UINTN)mGpioTableLpddr3Rvp3UcmcDevice); >=20 > + PcdSet16S (PcdBoardUcmcGpioTableSize, > mGpioTableLpddr3Rvp3UcmcDeviceSize); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +#define EXPANDERS 2 /= / defines expander's > quantity >=20 > + >=20 > +/** >=20 > + Configures GPIO >=20 > + >=20 > + @param[in] GpioTable Point to Platform Gpio table >=20 > + @param[in] GpioTableCount Number of Gpio table entries >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +ConfigureGpio ( >=20 > + IN GPIO_INIT_CONFIG *GpioDefinition, >=20 > + IN UINT16 GpioTableCount >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); >=20 > + >=20 > + Status =3D GpioConfigurePads (GpioTableCount, GpioDefinition); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); >=20 > +} >=20 > + >=20 > +VOID >=20 > +SetBit ( >=20 > + IN OUT UINT32 *Value, >=20 > + IN UINT32 BitNumber, >=20 > + IN BOOLEAN NewBitValue >=20 > + ) >=20 > +{ >=20 > + if (NewBitValue) { >=20 > + *Value |=3D 1 << BitNumber; >=20 > + } else { >=20 > + *Value &=3D ~(1 << BitNumber); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Configures IO Expander GPIO device >=20 > + >=20 > + @param[in] IOExpGpioDefinition Point to IO Expander Gpio table >=20 > + @param[in] IOExpGpioTableCount Number of Gpio table entries >=20 > + >=20 > +**/ >=20 > +void >=20 > +ConfigureIoExpanderGpio ( >=20 > + IN IO_EXPANDER_GPIO_CONFIG *IoExpGpioDefinition, >=20 > + IN UINT16 IoExpGpioTableCount >=20 > + ) >=20 > +{ >=20 > + UINT8 Index; >=20 > + UINT32 Direction[EXPANDERS] =3D {0x00FFFFFF, 0x00FFFFFF}; >=20 > + UINT32 Level[EXPANDERS] =3D {0}; >=20 > + UINT32 Polarity[EXPANDERS] =3D {0}; >=20 > + >=20 > + // IoExpander {TCA6424A} >=20 > + DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n")); >=20 > + for (Index =3D 0; Index < IoExpGpioTableCount; Index++) { //Program = IO > Expander as per the table defined in PeiPlatformHooklib.c >=20 > + SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber], > IoExpGpioDefinition[Index].GpioPinNumber, > (BOOLEAN)IoExpGpioDefinition[Index].GpioDirection); >=20 > + SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber], > IoExpGpioDefinition[Index].GpioPinNumber, > (BOOLEAN)IoExpGpioDefinition[Index].GpioLevel); >=20 > + SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber], > IoExpGpioDefinition[Index].GpioPinNumber, > (BOOLEAN)IoExpGpioDefinition[Index].GpioInversion); >=20 > + } >=20 > + for (Index =3D 0; Index < EXPANDERS; Index++) { >=20 > + GpioExpBulkConfig(Index, Direction[Index], Polarity[Index], > Level[Index]); >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n")); >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure GPIO behind IoExpander. >=20 > + >=20 > + @param[in] PeiServices General purpose services available to ev= ery > PEIM. >=20 > + @param[in] NotifyDescriptor >=20 > + @param[in] Interface >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > +**/ >=20 > +VOID >=20 > +ExpanderGpioInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + ConfigureIoExpanderGpio(mGpioTableIoExpander, > mGpioTableIoExpanderSize); >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure single GPIO pad for touchpanel interrupt >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +TouchpanelGpioInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + GPIO_INIT_CONFIG* TouchpanelPad; >=20 > + GPIO_PAD_OWN PadOwnVal; >=20 > + >=20 > + PadOwnVal =3D 0; >=20 > + TouchpanelPad =3D &mGpioTableLpDdr3Rvp3Touchpanel; >=20 > + >=20 > + GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal); >=20 > + if (PadOwnVal =3D=3D GpioPadOwnHost) { >=20 > + GpioConfigurePads (1, TouchpanelPad); >=20 > + } >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Configure GPIO >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +GpioInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + ConfigureGpio (mGpioTableLpDdr3Rvp3, mGpioTableLpDdr3Rvp3Size); >=20 > + >=20 > + TouchpanelGpioInit(); >=20 > + >=20 > + return; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Configure GPIO and SIO >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardInitBeforeSiliconInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + KabylakeRvp3Init (); >=20 > + >=20 > + GpioInit (); >=20 > + ExpanderGpioInit (); >=20 > + >=20 > + /// >=20 > + /// Do Late PCH init >=20 > + /// >=20 > + LateSiliconInit (); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3InitPreMemLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3InitPreMemLib.c > new file mode 100644 > index 000000000000..d34b0be3c7f6 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiKabylakeRvp3InitPreMemLib.c > @@ -0,0 +1,339 @@ > +/** @file >=20 > + >=20 > +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include "PeiKabylakeRvp3InitLib.h" >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +// >=20 > +// Reference RCOMP resistors on motherboard - for SKL RVP1 >=20 > +// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 > RcompResistorSklRvp1[SA_MRC_MAX_RCOMP] =3D { 200, 81, 162 }; >=20 > +// >=20 > +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for > SKL RVP1 >=20 > +// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 > RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] =3D { 100, 40, 40, 23, > 40 }; >=20 > + >=20 > +/** >=20 > + SkylaeA0Rvp3 board configuration init function for PEI pre-memory phas= e. >=20 > + >=20 > + PEI_BOARD_CONFIG_PCD_INIT >=20 > + >=20 > + @param Content pointer to the buffer contain init information for bo= ard > init. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > + @retval EFI_INVALID_PARAMETER The parameter is NULL. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3InitPreMem ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + PcdSet32S (PcdPcie0WakeGpioNo, 0); >=20 > + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); >=20 > + PcdSet32S (PcdPcie0HoldRstGpioNo, 8); >=20 > + PcdSetBoolS (PcdPcie0HoldRstActive, TRUE); >=20 > + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); >=20 > + PcdSet32S (PcdPcie0PwrEnableGpioNo, 16); >=20 > + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); >=20 > + >=20 > + // >=20 > + // HSIO PTSS Table >=20 > + // >=20 > + PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) > PchLpHsioPtss_Bx_KabylakeRvp3); >=20 > + PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) > PchLpHsioPtss_Bx_KabylakeRvp3_Size); >=20 > + PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) > PchLpHsioPtss_Cx_KabylakeRvp3); >=20 > + PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) > PchLpHsioPtss_Cx_KabylakeRvp3_Size); >=20 > + >=20 > + // >=20 > + // DRAM related definition >=20 > + // >=20 > + PcdSet8S (PcdSaMiscUserBd, 5); >=20 > + >=20 > + PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3); >=20 > + PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3)); >=20 > + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) > mDqsMapCpu2DramSklRvp3); >=20 > + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof > (mDqsMapCpu2DramSklRvp3)); >=20 > + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1); >=20 > + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1); >=20 > + // >=20 > + // Example policy for DIMM slots implementation boards: >=20 > + // 1. Assign Smbus address of DIMMs and SpdData will be updated later >=20 > + // by reading from DIMM SPD. >=20 > + // 2. No need to apply hardcoded SpdData buffers here for such board. >=20 > + // Example: >=20 > + // PcdMrcSpdAddressTable0 =3D 0xA0 >=20 > + // PcdMrcSpdAddressTable1 =3D 0xA2 >=20 > + // PcdMrcSpdAddressTable2 =3D 0xA4 >=20 > + // PcdMrcSpdAddressTable3 =3D 0xA6 >=20 > + // PcdMrcSpdData =3D 0 >=20 > + // PcdMrcSpdDataSize =3D 0 >=20 > + // >=20 > + // Kabylake RVP3 has 8GB Memory down implementation withouit SPD, >=20 > + // So assign all SpdAddress to 0 and apply static SpdData buffers: >=20 > + // PcdMrcSpdAddressTable0 =3D 0 >=20 > + // PcdMrcSpdAddressTable1 =3D 0 >=20 > + // PcdMrcSpdAddressTable2 =3D 0 >=20 > + // PcdMrcSpdAddressTable3 =3D 0 >=20 > + // PcdMrcSpdData =3D static data buffer >=20 > + // PcdMrcSpdDataSize =3D sizeof (static data buffer) >=20 > + // >=20 > + PcdSet8S (PcdMrcSpdAddressTable0, 0); >=20 > + PcdSet8S (PcdMrcSpdAddressTable1, 0); >=20 > + PcdSet8S (PcdMrcSpdAddressTable2, 0); >=20 > + PcdSet8S (PcdMrcSpdAddressTable3, 0); >=20 > + PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110); >=20 > + PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size); >=20 > + >=20 > + PcdSetBoolS (PcdIoExpanderPresent, TRUE); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + SkylaeA0Rvp3 board configuration init function for PEI pre-memory phas= e. >=20 > + >=20 > + PEI_BOARD_CONFIG_PCD_INIT >=20 > + >=20 > + @param Content pointer to the buffer contain init information for bo= ard > init. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > + @retval EFI_INVALID_PARAMETER The parameter is NULL. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SkylakeRvp3InitPreMem ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + PcdSet32S (PcdPcie0WakeGpioNo, 0); >=20 > + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); >=20 > + PcdSet32S (PcdPcie0HoldRstGpioNo, 8); >=20 > + PcdSetBoolS (PcdPcie0HoldRstActive, TRUE); >=20 > + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); >=20 > + PcdSet32S (PcdPcie0PwrEnableGpioNo, 16); >=20 > + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); >=20 > + >=20 > + // >=20 > + // HSIO PTSS Table >=20 > + // >=20 > + PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) > PchLpHsioPtss_Bx_KabylakeRvp3); >=20 > + PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) > PchLpHsioPtss_Bx_KabylakeRvp3_Size); >=20 > + PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) > PchLpHsioPtss_Cx_KabylakeRvp3); >=20 > + PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) > PchLpHsioPtss_Cx_KabylakeRvp3_Size); >=20 > + >=20 > + // >=20 > + // DRAM related definition >=20 > + // >=20 > + PcdSet8S (PcdSaMiscUserBd, 5); >=20 > + >=20 > + PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3); >=20 > + PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3)); >=20 > + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) > mDqsMapCpu2DramSklRvp3); >=20 > + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof > (mDqsMapCpu2DramSklRvp3)); >=20 > + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1); >=20 > + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1); >=20 > + // >=20 > + // Example policy for DIMM slots implementation boards: >=20 > + // 1. Assign Smbus address of DIMMs and SpdData will be updated later >=20 > + // by reading from DIMM SPD. >=20 > + // 2. No need to apply hardcoded SpdData buffers here for such board. >=20 > + // Example: >=20 > + // PcdMrcSpdAddressTable0 =3D 0xA0 >=20 > + // PcdMrcSpdAddressTable1 =3D 0xA2 >=20 > + // PcdMrcSpdAddressTable2 =3D 0xA4 >=20 > + // PcdMrcSpdAddressTable3 =3D 0xA6 >=20 > + // PcdMrcSpdData =3D 0 >=20 > + // PcdMrcSpdDataSize =3D 0 >=20 > + // >=20 > + // Skylake RVP3 has 4GB Memory down implementation withouit SPD, >=20 > + // So assign all SpdAddress to 0 and apply static SpdData buffers: >=20 > + // PcdMrcSpdAddressTable0 =3D 0 >=20 > + // PcdMrcSpdAddressTable1 =3D 0 >=20 > + // PcdMrcSpdAddressTable2 =3D 0 >=20 > + // PcdMrcSpdAddressTable3 =3D 0 >=20 > + // PcdMrcSpdData =3D static data buffer >=20 > + // PcdMrcSpdDataSize =3D sizeof (static data buffer) >=20 > + // >=20 > + PcdSet8S (PcdMrcSpdAddressTable0, 0); >=20 > + PcdSet8S (PcdMrcSpdAddressTable1, 0); >=20 > + PcdSet8S (PcdMrcSpdAddressTable2, 0); >=20 > + PcdSet8S (PcdMrcSpdAddressTable3, 0); >=20 > + PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd); >=20 > + PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3SpdSize); >=20 > + >=20 > + PcdSetBoolS (PcdIoExpanderPresent, TRUE); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680 >=20 > + >=20 > +/** >=20 > + Configures GPIO. >=20 > + >=20 > + @param[in] GpioTable Point to Platform Gpio table >=20 > + @param[in] GpioTableCount Number of Gpio table entries >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +ConfigureGpio ( >=20 > + IN GPIO_INIT_CONFIG *GpioDefinition, >=20 > + IN UINT16 GpioTableCount >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); >=20 > + >=20 > + Status =3D GpioConfigurePads (GpioTableCount, GpioDefinition); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure GPIO Before Memory is not ready. >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +GpioInitPreMem ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // ConfigureGpio (); >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure Super IO. >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SioInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Program and Enable Default Super IO Configuration Port Addresses an= d > range >=20 > + // >=20 > + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), > 0x10); >=20 > + >=20 > + // >=20 > + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF; >=20 > + // >=20 > + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), > 0x10); >=20 > + >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + Configues the IC2 Controller on which GPIO Expander Communicates. >=20 > + This Function is to enable the I2CGPIOExapanderLib to programm the > Gpios >=20 > + Complete intilization will be done in later Stage >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +I2CGpioExpanderInitPreMem( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidd= en); >=20 > + SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, > PchSerialIoIs33V); >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure GPIO and SIO before memory ready. >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardInitBeforeMemoryInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + if (LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) { >=20 > + KabylakeRvp3InitPreMem (); >=20 > + } else if (LibPcdGetSku () =3D=3D BoardIdSkylakeRvp3) { >=20 > + SkylakeRvp3InitPreMem (); >=20 > + } >=20 > + >=20 > + // >=20 > + // Configures the I2CGpioExpander >=20 > + // >=20 > + if (PcdGetBool (PcdIoExpanderPresent)) { >=20 > + I2CGpioExpanderInitPreMem(); >=20 > + } >=20 > + >=20 > + GpioInitPreMem (); >=20 > + SioInit (); >=20 > + >=20 > + /// >=20 > + /// Do basic PCH init >=20 > + /// >=20 > + SiliconInit (); >=20 > + >=20 > + // >=20 > + // Install PCH RESET PPI and EFI RESET2 PeiService >=20 > + // >=20 > + Status =3D PchInitializeReset (); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardDebugInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + /// >=20 > + /// Do Early PCH init >=20 > + /// >=20 > + EarlySiliconInit (); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_BOOT_MODE >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardBootModeDetect ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return BOOT_WITH_FULL_CONFIGURATION; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPostMemLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPostMemLib.c > new file mode 100644 > index 000000000000..70e93e94da11 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPostMemLib.c > @@ -0,0 +1,40 @@ > +/** @file >=20 > + Kaby Lake RVP 3 Multi-Board Initialization Post-Memory library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardInitBeforeSiliconInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +BOARD_POST_MEM_INIT_FUNC mKabylakeRvp3BoardInitFunc =3D { >=20 > + KabylakeRvp3BoardInitBeforeSiliconInit, >=20 > + NULL, // BoardInitAfterSiliconInit >=20 > +}; >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiKabylakeRvp3MultiBoardInitLibConstructor ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetS= ku () > =3D=3D BoardIdSkylakeRvp3)) { >=20 > + return RegisterBoardPostMemInit (&mKabylakeRvp3BoardInitFunc); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPostMemLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPostMemLib.inf > new file mode 100644 > index 000000000000..f955dd4ea966 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPostMemLib.inf > @@ -0,0 +1,56 @@ > +## @file >=20 > +# Component information file for KabylakeRvp3InitLib in PEI post memory > phase. >=20 > +# >=20 > +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiKabylakeRvp3MultiBoardInitLib >=20 > + FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF901749928= 0 >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D NULL >=20 > + CONSTRUCTOR =3D PeiKabylakeRvp3MultiBoardInitLibCon= structor >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + DebugLib >=20 > + BaseMemoryLib >=20 > + MemoryAllocationLib >=20 > + GpioExpanderLib >=20 > + PcdLib >=20 > + SiliconInitLib >=20 > + MultiBoardInitSupportLib >=20 > + >=20 > +[Packages] >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Sources] >=20 > + PeiKabylakeRvp3InitPostMemLib.c >=20 > + KabylakeRvp3GpioTable.c >=20 > + KabylakeRvp3HdaVerbTables.c >=20 > + PeiMultiBoardInitPostMemLib.c >=20 > + >=20 > +[FixedPcd] >=20 > + >=20 > +[Pcd] >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPreMemLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPreMemLib.c > new file mode 100644 > index 000000000000..59b3177201db > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPreMemLib.c > @@ -0,0 +1,82 @@ > +/** @file >=20 > + Kaby Lake RVP 3 Multi-Board Initialization Pre-Memory library >=20 > + >=20 > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardDetect ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3MultiBoardDetect ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_BOOT_MODE >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardBootModeDetect ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardDebugInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3BoardInitBeforeMemoryInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +BOARD_DETECT_FUNC mKabylakeRvp3BoardDetectFunc =3D { >=20 > + KabylakeRvp3MultiBoardDetect >=20 > +}; >=20 > + >=20 > +BOARD_PRE_MEM_INIT_FUNC mKabylakeRvp3BoardPreMemInitFunc =3D { >=20 > + KabylakeRvp3BoardDebugInit, >=20 > + KabylakeRvp3BoardBootModeDetect, >=20 > + KabylakeRvp3BoardInitBeforeMemoryInit, >=20 > + NULL, // BoardInitAfterMemoryInit >=20 > + NULL, // BoardInitBeforeTempRamExit >=20 > + NULL, // BoardInitAfterTempRamExit >=20 > +}; >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +KabylakeRvp3MultiBoardDetect ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + KabylakeRvp3BoardDetect (); >=20 > + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetS= ku () > =3D=3D BoardIdSkylakeRvp3)) { >=20 > + RegisterBoardPreMemInit (&mKabylakeRvp3BoardPreMemInitFunc); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return RegisterBoardDetect (&mKabylakeRvp3BoardDetectFunc); >=20 > +} > \ No newline at end of file > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPreMemLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPreMemLib.inf > new file mode 100644 > index 000000000000..23fe6b6f03c5 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar > dInitLib/PeiMultiBoardInitPreMemLib.inf > @@ -0,0 +1,137 @@ > +## @file >=20 > +# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem > Library >=20 > +# >=20 > +# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiKabylakeRvp3MultiBoardInitPreMem= Lib >=20 > + FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574= F >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D NULL >=20 > + CONSTRUCTOR =3D > PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + DebugLib >=20 > + BaseMemoryLib >=20 > + MemoryAllocationLib >=20 > + PcdLib >=20 > + SiliconInitLib >=20 > + MultiBoardInitSupportLib >=20 > + EcLib >=20 > + PchResetLib >=20 > + >=20 > +[Packages] >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Sources] >=20 > + PeiKabylakeRvp3InitPreMemLib.c >=20 > + KabylakeRvp3HsioPtssTables.c >=20 > + KabylakeRvp3SpdTable.c >=20 > + PeiMultiBoardInitPreMemLib.c >=20 > + PeiKabylakeRvp3Detect.c >=20 > + >=20 > +[Pcd] >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort >=20 > + >=20 > + # PCH-LP HSIO PTSS Table >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size >=20 > + >=20 > + # PCH-H HSIO PTSS Table >=20 > + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 >=20 > + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 >=20 > + > #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size >=20 > + > #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size >=20 > + >=20 > + # SA Misc Config >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize >=20 > + >=20 > + # PEG Reset By GPIO >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive >=20 > + >=20 > + >=20 > + # SPD Address Table >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 >=20 > + >=20 > + # CA Vref Configuration >=20 > + >=20 > + # Root Port Clock Info >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo >=20 > + >=20 > + # USB 2.0 Port AFE >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe >=20 > + >=20 > + # USB 2.0 Port Over Current Pin >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 >=20 > + >=20 > + # USB 3.0 Port Over Current Pin >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 >=20 > + >=20 > + # Misc >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent >=20 > + >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kg.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kg.dsc > new file mode 100644 > index 000000000000..f64555e3910f > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kg.dsc > @@ -0,0 +1,521 @@ > +## @file >=20 > +# The main build description file for the KabylakeRvp3 board. >=20 > +# >=20 > +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > +[Defines] >=20 > + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg >=20 > + DEFINE PLATFORM_SI_PACKAGE =3D KabylakeSiliconPkg >=20 > + DEFINE PLATFORM_SI_BIN_PACKAGE =3D KabylakeSiliconBinPkg >=20 > + DEFINE PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg >=20 > + DEFINE BOARD =3D KabylakeRvp3 >=20 > + DEFINE PROJECT =3D > $(PLATFORM_BOARD_PACKAGE)/$(BOARD) >=20 > + DEFINE PEI_ARCH =3D IA32 >=20 > + DEFINE DXE_ARCH =3D X64 >=20 > + DEFINE TOP_MEMORY_ADDRESS =3D 0x0 >=20 > + >=20 > + # >=20 > + # Default value for OpenBoardPkg.fdf use >=20 > + # >=20 > + DEFINE BIOS_SIZE_OPTION =3D SIZE_70 >=20 > + >=20 > + PLATFORM_NAME =3D $(PLATFORM_PACKAGE) >=20 > + PLATFORM_GUID =3D 8470676C-18E8-467F-B12= 6- > 28DB1941AA5A >=20 > + PLATFORM_VERSION =3D 0.1 >=20 > + DSC_SPECIFICATION =3D 0x00010005 >=20 > + OUTPUT_DIRECTORY =3D Build/$(PROJECT) >=20 > + SUPPORTED_ARCHITECTURES =3D IA32|X64 >=20 > + BUILD_TARGETS =3D DEBUG|RELEASE >=20 > + SKUID_IDENTIFIER =3D ALL >=20 > + FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPk= g.fdf >=20 > + >=20 > + FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 >=20 > + >=20 > + # >=20 > + # Include PCD configuration for this board. >=20 > + # >=20 > + !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc >=20 > + >=20 > + !include OpenBoardPkgPcd.dsc >=20 > + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc >=20 > + >=20 > +[Defines] >=20 > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 >=20 > + # >=20 > + # For backward compatibility API mode will use KabylakeFspBinPkg. >=20 > + # KabylakeFspBinPkg only supports API mode. >=20 > + # >=20 > + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D KabylakeFspBinPkg >=20 > +!else >=20 > + # >=20 > + # AmberLakeFspBinPkg supports both API and Dispatch modes >=20 > + # >=20 > + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D AmberLakeFspBinPkg >=20 > +!endif >=20 > + >=20 > +[PcdsDynamicExDefault.common.DEFAULT] >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D TRUE >=20 > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 0 >=20 > + # >=20 > + # Include FSP DynamicEx PCD settings in Dispatch mode >=20 > + # >=20 > + !include $(PLATFORM_FSP_BIN_PACKAGE)/FspPcds.dsc >=20 > + >=20 > + # >=20 > + # Override some FSP consumed PCD default value to match platform > requirement. >=20 > + # >=20 > + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress > |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress >=20 > + > gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgToke > nSpaceGuid.PcdPciExpressRegionLength >=20 > +!endif >=20 > +!endif >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# SKU Identification section - list of all SKU IDs supported by this boa= rd. >=20 > +# >=20 > +######################################################### > ####################### >=20 > +[SkuIds] >=20 > + 0x00|DEFAULT # 0|DEFAULT is reserved and always require= d. >=20 > + 0x04|KabylakeRvp3 >=20 > + 0x60|KabyLakeYLpddr3Rvp3 >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# Includes section - other DSC file contents included for this board bui= ld. >=20 > +# >=20 > +######################################################### > ####################### >=20 > + >=20 > +####################################### >=20 > +# Library Includes >=20 > +####################################### >=20 > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc >=20 > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc >=20 > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc >=20 > + >=20 > +####################################### >=20 > +# Component Includes >=20 > +####################################### >=20 > + >=20 > +# @todo: Change below line to [Components.$(PEI_ARCH)] after > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2308 >=20 > +# is completed >=20 > +[Components.IA32] >=20 > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc >=20 > + >=20 > +# @todo: Change below line to [Components.$(DXE_ARCH)] after > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2308 >=20 > +# is completed >=20 > +[Components.X64] >=20 > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc >=20 > + >=20 > +####################################### >=20 > +# Build Option Includes >=20 > +####################################### >=20 > +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc >=20 > +!include OpenBoardPkgBuildOption.dsc >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# Library Class section - list of all Library Classes needed by this boa= rd. >=20 > +# >=20 > +######################################################### > ####################### >=20 > + >=20 > +[LibraryClasses.common] >=20 > + ####################################### >=20 > + # Edk2 Packages >=20 > + ####################################### >=20 > + > FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/Ba > seFspWrapperApiLib.inf >=20 > + > FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTest > Lib/PeiFspWrapperApiTestLib.inf >=20 > + >=20 > + ####################################### >=20 > + # Silicon Initialization Package >=20 > + ####################################### >=20 > + > ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlock= Li > b.inf >=20 > + > SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilico= nI > nitLib.inf >=20 > + >=20 > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 >=20 > + # >=20 > + # FSP API mode >=20 > + # >=20 > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitL= ib > Fsp/PeiSiliconPolicyInitLibFsp.inf >=20 > +!else >=20 > + # >=20 > + # FSP Dispatch mode and non-FSP build (EDK2 build) >=20 > + # >=20 > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitL= ib > Fsp/PeiSiliconPolicyInitLibFspAml.inf >=20 > +!endif >=20 > + >=20 > + ##################################### >=20 > + # Platform Package >=20 > + ##################################### >=20 > + > BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/ > BoardInitLibNull.inf >=20 > + > FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/P > eiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf >=20 > + > FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFs > pWrapperPlatformLib/PeiFspWrapperPlatformLib.inf >=20 > + > PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimpl > e/PciHostBridgeLibSimple.inf >=20 > + > PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibS > imple/PciSegmentInfoLibSimple.inf >=20 > + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf >=20 > + > PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatfor > mBootManagerLib/DxePlatformBootManagerLib.inf >=20 > + > ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/P > eiReportFvLib.inf >=20 > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib > Null/TestPointCheckLibNull.inf >=20 > + >=20 > + ####################################### >=20 > + # Board Package >=20 > + ####################################### >=20 > + EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf >=20 > + > GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpan > derLib/BaseGpioExpanderLib.inf >=20 > + > I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2 > cAccessLib.inf >=20 > + > PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapp > erPlatformSecLib/SecFspWrapperPlatformSecLib.inf >=20 > + >=20 > + # Thunderbolt >=20 > +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE >=20 > + > DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Dxe > TbtPolicyLib/DxeTbtPolicyLib.inf >=20 > + > TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Pei > DxeSmmTbtCommonLib/TbtCommonLib.inf >=20 > +!endif >=20 > + >=20 > + ####################################### >=20 > + # Board-specific >=20 > + ####################################### >=20 > + > PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHo > okLib.inf >=20 > + >=20 > +[LibraryClasses.IA32.SEC] >=20 > + ####################################### >=20 > + # Platform Package >=20 > + ####################################### >=20 > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib > /SecTestPointCheckLib.inf >=20 > + > SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitL > ibNull/SecBoardInitLibNull.inf >=20 > + > SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyU= p > dateLibNull/SiliconPolicyUpdateLibNull.inf >=20 > + >=20 > +[LibraryClasses.common.PEIM] >=20 > + ####################################### >=20 > + # Silicon Package >=20 > + ####################################### >=20 > + > ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLi > b.inf >=20 > + >=20 > + ####################################### >=20 > + # Platform Package >=20 > + ####################################### >=20 > + > BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSu > pportLib/PeiMultiBoardInitSupportLib.inf >=20 > + > FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFs > pWrapperPlatformLib/PeiFspWrapperPlatformLib.inf >=20 > + > MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mul > tiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf >=20 > + > TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPoi > ntLib.inf >=20 > +!if $(TARGET) =3D=3D DEBUG >=20 > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib > /PeiTestPointCheckLib.inf >=20 > +!endif >=20 > + > SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCac > heMtrrLibNull.inf >=20 > + >=20 > + ####################################### >=20 > + # Board Package >=20 > + ####################################### >=20 > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 >=20 > + # >=20 > + # FSP API mode >=20 > + # >=20 > + > SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd > ateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf >=20 > +!else >=20 > + # >=20 > + # FSP Dispatch mode and non-FSP build (EDK2 build) >=20 > + # >=20 > + > SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateLi= b/ > PeiSiliconPolicyUpdateLib.inf >=20 > +!endif >=20 > + >=20 > + # Thunderbolt >=20 > +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE >=20 > + > PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Privat > e/PeiDTbtInitLib/PeiDTbtInitLib.inf >=20 > + > PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiT > btPolicyLib/PeiTbtPolicyLib.inf >=20 > +!endif >=20 > + >=20 > +[LibraryClasses.common.DXE_DRIVER] >=20 > + ####################################### >=20 > + # Silicon Initialization Package >=20 > + ####################################### >=20 > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInitL= i > b/DxeSiliconPolicyInitLib.inf >=20 > + >=20 > + ####################################### >=20 > + # Platform Package >=20 > + ####################################### >=20 > + > BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSu > pportLib/DxeMultiBoardAcpiSupportLib.inf >=20 > + > BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSu > pportLib/DxeMultiBoardInitSupportLib.inf >=20 > + > FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeF > spWrapperPlatformLib/DxeFspWrapperPlatformLib.inf >=20 > + > MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoar > dAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf >=20 > + > MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mul > tiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf >=20 > + > TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPoi > ntLib.inf >=20 > + >=20 > +!if $(TARGET) =3D=3D DEBUG >=20 > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib > /DxeTestPointCheckLib.inf >=20 > +!endif >=20 > + ####################################### >=20 > + # Board Package >=20 > + ####################################### >=20 > + > BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHoo > kLib.inf >=20 > + > BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/Boa > rdBootManagerLib.inf >=20 > + >=20 > + ####################################### >=20 > + # Board-specific >=20 > + ####################################### >=20 > + > SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateLi= b > /DxeSiliconPolicyUpdateLib.inf >=20 > + >=20 > +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] >=20 > + ####################################### >=20 > + # Silicon Initialization Package >=20 > + ####################################### >=20 > + > ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeReset > SystemLib/DxeRuntimeResetSystemLib.inf >=20 > + >=20 > +[LibraryClasses.X64.DXE_SMM_DRIVER] >=20 > + ####################################### >=20 > + # Silicon Initialization Package >=20 > + ####################################### >=20 > + > SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashC > ommonLib/SmmSpiFlashCommonLib.inf >=20 > + >=20 > + ####################################### >=20 > + # Platform Package >=20 > + ####################################### >=20 > + > BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiS > upportLib/SmmMultiBoardAcpiSupportLib.inf >=20 > + > MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoar > dAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf >=20 > + > TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestP > ointLib.inf >=20 > +!if $(TARGET) =3D=3D DEBUG >=20 > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib > /SmmTestPointCheckLib.inf >=20 > +!endif >=20 > + >=20 > +####################################### >=20 > +# PEI Components >=20 > +####################################### >=20 > +# @todo: Change below line to [Components.$(PEI_ARCH)] after > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2308 >=20 > +# is completed >=20 > +[Components.IA32] >=20 > + ####################################### >=20 > + # Edk2 Packages >=20 > + ####################################### >=20 > + UefiCpuPkg/SecCore/SecCore.inf { >=20 > + >=20 > + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf >=20 > + } >=20 > + >=20 > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 >=20 > + # >=20 > + # In FSP API mode the policy has to be installed before FSP Wrapper > updating UPD. >=20 > + # Add policy as dependency for FSP Wrapper >=20 > + # >=20 > + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { >=20 > + >=20 > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitL= ib > Dependency/PeiPreMemSiliconPolicyInitLibDependency.inf >=20 > + } >=20 > + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { >=20 > + >=20 > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitL= ib > Dependency/PeiPostMemSiliconPolicyInitLibDependency.inf >=20 > + } >=20 > +!else >=20 > + # >=20 > + # In FSP Dispatch mode the policy will be installed after FSP-M dispat= ched > (only PrePolicy silicon-init executed). >=20 > + # Do not add policy dependency and let FspmWrapper report FSP-M FV to > dispatcher. >=20 > + # >=20 > + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { >=20 > + >=20 > + > SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyIni= tLibN > ull/SiliconPolicyInitLibNull.inf >=20 > + } >=20 > + # >=20 > + # In FSP Dispatch mode the policy will be installed after FSP-S dispat= ched > (only PrePolicy silicon-init executed). >=20 > + # Do not add policy dependency and let FspsWrapper report FSP-S FV to > dispatcher. >=20 > + # >=20 > + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { >=20 > + >=20 > + > SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyIni= tLibN > ull/SiliconPolicyInitLibNull.inf >=20 > + } >=20 > +!endif >=20 > + >=20 > + ####################################### >=20 > + # Silicon Initialization Package >=20 > + ####################################### >=20 > + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf >=20 > + > IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSa > mplePei.inf >=20 > + >=20 > + ####################################### >=20 > + # Platform Package >=20 > + ####################################### >=20 > + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf >=20 > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.i > nf { >=20 > + >=20 > + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D= =3D > FALSE >=20 > + > BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf >=20 > + !else >=20 > + > NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf >=20 > + !endif >=20 > + } >=20 > + >=20 > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem > .inf { >=20 > + >=20 > + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D= =3D > FALSE >=20 > + > BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf >=20 > + !else >=20 > + > NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf >=20 > + !endif >=20 > + } >=20 > + >=20 > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 >=20 > + > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe > m.inf { >=20 > + >=20 > + # >=20 > + # Hook a library constructor to update some policy fields when polic= y is > installed. >=20 > + # >=20 > + > NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicy > NotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf >=20 > + } >=20 > + > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostM > em.inf >=20 > +!else >=20 > + # >=20 > + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP= to > install a default policy PPI. >=20 > + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch mo= de > can generate different policy structure >=20 > + # for different FSP revisions, but they must maintain backward > compatibility. >=20 > + # >=20 > + > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe > m.inf { >=20 > + >=20 > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitL= ib > /PeiPreMemSiliconPolicyInitLib.inf >=20 > + } >=20 > + > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostM > em.inf { >=20 > + >=20 > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitL= ib > /PeiPostMemSiliconPolicyInitLib.inf >=20 > + } >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE >=20 > + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf >=20 > +!endif >=20 > + >=20 > + ####################################### >=20 > + # Board Package >=20 > + ####################################### >=20 > + # Thunderbolt >=20 > +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE >=20 > + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf >=20 > +!endif >=20 > + $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf >=20 > + >=20 > +####################################### >=20 > +# DXE Components >=20 > +####################################### >=20 > +# @todo: Change below line to [Components.$(DXE_ARCH)] after > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2308 >=20 > +# is completed >=20 > +[Components.X64] >=20 > + ####################################### >=20 > + # Edk2 Packages >=20 > + ####################################### >=20 > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf >=20 > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf >=20 > + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf >=20 > + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf >=20 > + > MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDx > e.inf >=20 > + MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf >=20 > + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf{ >=20 > + >=20 > + NULL|BoardModulePkg/Library/BdsPs2KbcLib/BdsPs2KbcLib.inf >=20 > + } >=20 > + UefiCpuPkg/CpuDxe/CpuDxe.inf >=20 > + >=20 > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 >=20 > + # >=20 > + # FSP API mode >=20 > + # >=20 > + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf >=20 > +!endif >=20 > + >=20 > + ShellPkg/Application/Shell/Shell.inf { >=20 > + >=20 > + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE >=20 > + >=20 > + > NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma > ndsLib.inf >=20 > + > NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma > ndsLib.inf >=20 > + > NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma > ndsLib.inf >=20 > + > NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com > mandsLib.inf >=20 > + > NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Com > mandsLib.inf >=20 > + > NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com > mandsLib.inf >=20 > + > NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1 > CommandsLib.inf >=20 > + > NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2 > CommandsLib.inf >=20 > + > ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma > ndLib.inf >=20 > + > HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingL > ib.inf >=20 > + > BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg > CommandLib.inf >=20 > + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryL= ib.inf >=20 > + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf >=20 > + } >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE >=20 > + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { >=20 > + >=20 > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 >=20 > + >=20 > + !if $(TARGET) =3D=3D DEBUG >=20 > + > DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort. > inf >=20 > + !endif >=20 > + } >=20 > +!endif >=20 > + >=20 > + ####################################### >=20 > + # Silicon Initialization Package >=20 > + ####################################### >=20 > + IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf >=20 > + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf >=20 > + >=20 > + ####################################### >=20 > + # Platform Package >=20 > + ####################################### >=20 > + > $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryCo > nfig.inf >=20 > + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf >=20 > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf >=20 > + > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf >=20 > + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf >=20 > + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE >=20 > + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE >=20 > + >=20 > + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf >=20 > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.in > f >=20 > + >=20 > + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { >=20 > + >=20 > + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D= =3D > FALSE >=20 > + > BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnable > Lib.inf >=20 > + !else >=20 > + > NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf >=20 > + !endif >=20 > + } >=20 > + >=20 > + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { >=20 > + >=20 > + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D= =3D > FALSE >=20 > + > BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.i > nf >=20 > + !else >=20 > + > NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf >=20 > + !endif >=20 > + } >=20 > + >=20 > +!endif >=20 > + >=20 > + ####################################### >=20 > + # Board Package >=20 > + ####################################### >=20 > + # Thunderbolt >=20 > +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE >=20 > + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf >=20 > + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf >=20 > + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE >=20 > + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { >=20 > + >=20 > + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D= =3D > FALSE >=20 > + > BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.i > nf >=20 > + !else >=20 > + > NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf >=20 > + !endif >=20 > + } >=20 > +!endif >=20 > + BoardModulePkg/LegacySioDxe/LegacySioDxe.inf >=20 > + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kg.fdf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kg.fdf > new file mode 100644 > index 000000000000..6cdf4e2f9f1f > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kg.fdf > @@ -0,0 +1,715 @@ > +## @file >=20 > +# FDF file of Platform. >=20 > +# >=20 > +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# FD Section >=20 > +# The [FD] Section is made up of the definition statements and a >=20 > +# description of what goes into the Flash Device Image. Each FD sectio= n >=20 > +# defines one flash "device" image. A flash device image may be one of >=20 > +# the following: Removable media bootable image (like a boot floppy >=20 > +# image,) an Option ROM image (that would be "flashed" into an add-in >=20 > +# card,) a System "Flash" image (that would be burned into a system's >=20 > +# flash) or an Update ("Capsule") image that will be used to update and >=20 > +# existing system flash. >=20 > +# >=20 > +######################################################### > ####################### >=20 > +[FD.KabylakeRvp3] >=20 > +# >=20 > +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, > cannot be >=20 > +# assigned with PCD values. Instead, it uses the definitions for its var= iety, > which >=20 > +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and > FLASH_NUM_BLOCKS. >=20 > +# >=20 > +BaseAddress =3D $(FLASH_BASE) | > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of > the FLASH Device. >=20 > +Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize > #The size in bytes of the FLASH Device >=20 > +ErasePolarity =3D 1 >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +NumBlocks =3D $(FLASH_NUM_BLOCKS) >=20 > + >=20 > +DEFINE SIPKG_DXE_SMM_BIN =3D INF >=20 > +DEFINE SIPKG_PEI_BIN =3D INF >=20 > + >=20 > +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, > because macro expression is not supported. >=20 > +# So, PlatformSecLib uses PcdFlashAreaBaseAddress + > PcdNemCodeCacheBase to get the real CodeCache base address. >=20 > +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset) >=20 > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) >=20 > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) >=20 > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 >=20 > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset >=20 > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress >=20 > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaSize >=20 > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) >=20 > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) >=20 > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress >=20 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaSize >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# Following are lists of FD Region layout which correspond to the locati= ons > of different >=20 > +# images within the flash device. >=20 > +# >=20 > +# Regions must be defined in ascending order and may not overlap. >=20 > +# >=20 > +# A Layout Region start with a eight digit hex offset (leading "0x" requ= ired) > followed by >=20 > +# the pipe "|" character, followed by the size of the region, also in he= x with > the leading >=20 > +# "0x" characters. Like: >=20 > +# Offset|Size >=20 > +# PcdOffsetCName|PcdSizeCName >=20 > +# RegionType >=20 > +# Fv Size can be adjusted >=20 > +# >=20 > +######################################################### > ####################### >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiM > deModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize >=20 > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfi > MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize >=20 > +#NV_VARIABLE_STORE >=20 > +DATA =3D { >=20 > + ## This is the EFI_FIRMWARE_VOLUME_HEADER >=20 > + # ZeroVector [] >=20 > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, >=20 > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, >=20 > + # FileSystemGuid >=20 > + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, >=20 > + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, >=20 > + # FvLength: 0x40000 >=20 > + 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, >=20 > + #Signature "_FVH" #Attributes >=20 > + 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00, >=20 > + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision >=20 > + # >=20 > + # Be careful on CheckSum field. >=20 > + # >=20 > + 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02, >=20 > + #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block >=20 > + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, >=20 > + #Blockmap[1]: End >=20 > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, >=20 > + ## This is the VARIABLE_STORE_HEADER >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE >=20 > + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, > 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} >=20 > + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, >=20 > + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, >=20 > +!else >=20 > + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x9= 8, 0xb6, > 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} >=20 > + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, >=20 > + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, >=20 > +!endif >=20 > + #Size: 0x1E000 > (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 > (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x1DFB8 >=20 > + # This can speed up the Variable Dispatch a bit. >=20 > + 0xB8, 0xDF, 0x01, 0x00, >=20 > + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: > UINT32 >=20 > + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 >=20 > +} >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|g > EfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize >=20 > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|g > EfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize >=20 > +#NV_FTW_WORKING >=20 > +DATA =3D { >=20 > + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D > gEdkiiWorkingBlockSignatureGuid =3D >=20 > + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f,= 0x1b, > 0x95 }} >=20 > + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, >=20 > + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, >=20 > + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, R= eserved >=20 > + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, >=20 > + # WriteQueueSize: UINT64 >=20 > + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 >=20 > +} >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfi > MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize >=20 > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfi > MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize >=20 > +#NV_FTW_SPARE >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatfor > mPkgTokenSpaceGuid.PcdFlashFvAdvancedSize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatform > PkgTokenSpaceGuid.PcdFlashFvAdvancedSize >=20 > +FV =3D FvAdvanced >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatform > PkgTokenSpaceGuid.PcdFlashFvSecuritySize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformP > kgTokenSpaceGuid.PcdFlashFvSecuritySize >=20 > +FV =3D FvSecurity >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatform > PkgTokenSpaceGuid.PcdFlashFvOsBootSize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPk > gTokenSpaceGuid.PcdFlashFvOsBootSize >=20 > +FV =3D FvOsBoot >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatfor > mPkgTokenSpaceGuid.PcdFlashFvUefiBootSize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatform > PkgTokenSpaceGuid.PcdFlashFvUefiBootSize >=20 > +FV =3D FvUefiBoot >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlat > formPkgTokenSpaceGuid.PcdFlashFvPostMemorySize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatf > ormPkgTokenSpaceGuid.PcdFlashFvPostMemorySize >=20 > +FV =3D FvPostMemory >=20 > + >=20 > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGui > d.PcdFlashMicrocodeFvSize >=20 > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid. > PcdFlashMicrocodeFvSize >=20 > +#Microcode >=20 > +FV =3D FvMicrocode >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkg > TokenSpaceGuid.PcdFlashFvFspSSize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgT > okenSpaceGuid.PcdFlashFvFspSSize >=20 > +# FSP_S Section >=20 > +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPk > gTokenSpaceGuid.PcdFlashFvFspMSize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkg > TokenSpaceGuid.PcdFlashFvFspMSize >=20 > +# FSP_M Section >=20 > +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkg > TokenSpaceGuid.PcdFlashFvFspTSize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgT > okenSpaceGuid.PcdFlashFvFspTSize >=20 > +# FSP_T Section >=20 > +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset| > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|g > MinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize >=20 > +FV =3D FvAdvancedPreMemory >=20 > + >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatf > ormPkgTokenSpaceGuid.PcdFlashFvPreMemorySize >=20 > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatfor > mPkgTokenSpaceGuid.PcdFlashFvPreMemorySize >=20 > +FV =3D FvPreMemory >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# FV Section >=20 > +# >=20 > +# [FV] section is used to define what components or modules are placed > within a flash >=20 > +# device file. This section also defines order the components and modul= es > are positioned >=20 > +# within the image. The [FV] section consists of define statements, set > statements and >=20 > +# module statements. >=20 > +# >=20 > +######################################################### > ####################### >=20 > +[FV.FvMicrocode] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D FALSE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D FALSE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > + >=20 > +INF RuleOverride =3D MICROCODE > $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf >=20 > + >=20 > +[FV.FvPreMemory] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D >=20 > + >=20 > +INF UefiCpuPkg/SecCore/SecCore.inf >=20 > +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) > || (gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain > =3D=3D FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D= =3D > 1) >=20 > +# >=20 > +# PeiMain is needed only for FSP API mode or EDK2 build, >=20 > +# in FSP dispatch mode the one inside FSP Binary is launched >=20 > +# unless requested otherwise (PcdFspDispatchModeUseFspPeiMain =3D=3D > FALSE). >=20 > +# >=20 > +INF MdeModulePkg/Core/Pei/PeiMain.inf >=20 > +!endif >=20 > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf >=20 > + >=20 > +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf >=20 > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.i > nf >=20 > +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf >=20 > +INF > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe > m.inf >=20 > +INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf >=20 > + >=20 > +[FV.FvPostMemoryUncompact] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7 >=20 > + >=20 > +!include > $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf >=20 > + >=20 > +# Init Board Config PCD >=20 > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem > .inf >=20 > +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf >=20 > +INF > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostM > em.inf >=20 > + >=20 > +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable =3D=3D TRUE >=20 > +FILE FREEFORM =3D 4ad46122-ffeb-4a52-bfb0-518cfca02db0 { >=20 > + SECTION RAW =3D > $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin >=20 > + SECTION UI =3D "Vbt" >=20 > +} >=20 > +FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D { >=20 > + SECTION RAW =3D MdeModulePkg/Logo/Logo.bmp >=20 > +} >=20 > +!endif # PcdPeiDisplayEnable >=20 > + >=20 > +[FV.FvPostMemory] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D 9DFE49DB-8EF0-4D9C-B273-0036144DE917 >=20 > + >=20 > +FILE FV_IMAGE =3D 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 { >=20 > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { >=20 > + SECTION FV_IMAGE =3D FvPostMemoryUncompact >=20 > + } >=20 > +} >=20 > + >=20 > +[FV.FvUefiBootUncompact] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D A881D567-6CB0-4eee-8435-2E72D33E45B5 >=20 > + >=20 > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf >=20 > + >=20 > +INF UefiCpuPkg/CpuDxe/CpuDxe.inf >=20 > +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf >=20 > + >=20 > +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf >=20 > +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf >=20 > +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf >=20 > +INF > MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDx > e.inf >=20 > +INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf >=20 > +INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf >=20 > +INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf >=20 > + >=20 > +INF ShellPkg/Application/Shell/Shell.inf >=20 > + >=20 > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf >=20 > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 >=20 > + # >=20 > + # Below module is used by FSP API mode >=20 > + # >=20 > + INF > IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf >=20 > +!endif >=20 > + >=20 > +INF > $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf >=20 > + >=20 > +[FV.FvUefiBoot] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D 0496D33D-EA79-495C-B65D-ABF607184E3B >=20 > + >=20 > +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { >=20 > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { >=20 > + SECTION FV_IMAGE =3D FvUefiBootUncompact >=20 > + } >=20 > + } >=20 > + >=20 > +[FV.FvOsBootUncompact] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D A0F04529-B715-44C6-BCA4-2DEBDD01EEEC >=20 > + >=20 > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf >=20 > + >=20 > +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE >=20 > +INF > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf >=20 > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.in > f >=20 > +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf >=20 > + >=20 > +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf >=20 > +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf >=20 > + >=20 > +INF RuleOverride =3D DRIVER_ACPITABLE > $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf >=20 > + >=20 > +INF > $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryCo > nfig.inf >=20 > + >=20 > +!endif >=20 > + >=20 > +[FV.FvLateSilicon] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE >=20 > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf >=20 > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf >=20 > + >=20 > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf >=20 > + >=20 > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher. > inf >=20 > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf >=20 > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf >=20 > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf >=20 > + >=20 > +INF RuleOverride =3D ACPITABLE > $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf >=20 > +INF RuleOverride =3D ACPITABLE > $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf >=20 > + >=20 > +!endif >=20 > + >=20 > +[FV.FvOsBoot] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D 13BF8810-75FD-4B1A-91E6-E16C4201F80A >=20 > + >=20 > +FILE FV_IMAGE =3D B9020753-84A8-4BB6-947C-CE7D41F5CE39 { >=20 > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { >=20 > + SECTION FV_IMAGE =3D FvOsBootUncompact >=20 > + } >=20 > + } >=20 > + >=20 > +FILE FV_IMAGE =3D D4632741-510C-44E3-BE21-C3D6D7881485 { >=20 > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { >=20 > + SECTION FV_IMAGE =3D FvLateSilicon >=20 > + } >=20 > + } >=20 > + >=20 > +[FV.FvSecurityPreMemory] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 #FV alignment and FV attributes settin= g. >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B >=20 > + >=20 > +!include > $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf >=20 > + >=20 > +INF > IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSa > mplePei.inf >=20 > + >=20 > +INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf >=20 > + >=20 > +[FV.FvSecurityPostMemory] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 #FV alignment and FV attributes settin= g. >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D 4199E560-54AE-45E5-91A4-F7BC3804E14A >=20 > + >=20 > +!include > $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE >=20 > +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf >=20 > +!endif >=20 > + >=20 > +[FV.FvSecurityLate] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D F753FE9A-EEFD-485B-840B-E032D538102C >=20 > + >=20 > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf >=20 > + >=20 > +INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE >=20 > + >=20 > +INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf >=20 > + >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE >=20 > + >=20 > +INF > $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE >=20 > +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf >=20 > +!endif >=20 > + >=20 > +!endif >=20 > + >=20 > +[FV.FvSecurity] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF >=20 > + >=20 > +FILE FV_IMAGE =3D 757CC075-1428-423D-A73C-22639706C119 { >=20 > + SECTION FV_IMAGE =3D FvSecurityPreMemory >=20 > + } >=20 > + >=20 > +FILE FV_IMAGE =3D 80BB8482-44D5-4BEC-82B5-8D87A933830B { >=20 > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { >=20 > + SECTION FV_IMAGE =3D FvSecurityPostMemory >=20 > + } >=20 > + } >=20 > + >=20 > +FILE FV_IMAGE =3D C83522D9-80A1-4D95-8C25-3F1370497406 { >=20 > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { >=20 > + SECTION FV_IMAGE =3D FvSecurityLate >=20 > + } >=20 > + } >=20 > + >=20 > +# >=20 > +# Pre-memory Advanced Features >=20 > +# >=20 > +[FV.FvAdvancedPreMemory] >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305 >=20 > + >=20 > +!include AdvancedFeaturePkg/Include/PreMemory.fdf >=20 > + >=20 > +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE >=20 > +INF > $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf >=20 > +!endif >=20 > + >=20 > +# >=20 > +# Post-Memory Advanced Features >=20 > +# >=20 > +[FV.FvAdvancedUncompact] >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D BE3DF86F-E464-44A3-83F7-0D27E6B88C27 >=20 > + >=20 > +!include AdvancedFeaturePkg/Include/PostMemory.fdf >=20 > + >=20 > +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE >=20 > +INF > $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf >=20 > +INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf >=20 > +INF > $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf >=20 > +!endif >=20 > + >=20 > +# >=20 > +# Compressed FV with Post-Memory Advanced Features >=20 > +# >=20 > +[FV.FvAdvanced] >=20 > +BlockSize =3D $(FLASH_BLOCK_SIZE) >=20 > +FvAlignment =3D 16 >=20 > +ERASE_POLARITY =3D 1 >=20 > +MEMORY_MAPPED =3D TRUE >=20 > +STICKY_WRITE =3D TRUE >=20 > +LOCK_CAP =3D TRUE >=20 > +LOCK_STATUS =3D TRUE >=20 > +WRITE_DISABLED_CAP =3D TRUE >=20 > +WRITE_ENABLED_CAP =3D TRUE >=20 > +WRITE_STATUS =3D TRUE >=20 > +WRITE_LOCK_CAP =3D TRUE >=20 > +WRITE_LOCK_STATUS =3D TRUE >=20 > +READ_DISABLED_CAP =3D TRUE >=20 > +READ_ENABLED_CAP =3D TRUE >=20 > +READ_STATUS =3D TRUE >=20 > +READ_LOCK_CAP =3D TRUE >=20 > +READ_LOCK_STATUS =3D TRUE >=20 > +FvNameGuid =3D B23E7388-9953-45C7-9201-0473DDE5487A >=20 > + >=20 > +FILE FV_IMAGE =3D 5248467B-B87B-4E74-AC02-398AF4BCB712 { >=20 > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { >=20 > + SECTION FV_IMAGE =3D FvAdvancedUncompact >=20 > + } >=20 > + } >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# Rules are use with the [FV] section's module INF type to define >=20 > +# how an FFS file is created for a given INF file. The following Rule ar= e the > default >=20 > +# rules for the different module type. User can add the customized rules= to > define the >=20 > +# content of the FFS file. >=20 > +# >=20 > +######################################################### > ####################### >=20 > + >=20 > +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kgBuildOption.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kgBuildOption.dsc > new file mode 100644 > index 000000000000..8e885cc6a4b8 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kgBuildOption.dsc > @@ -0,0 +1,151 @@ > +## @file >=20 > +# platform build option configuration file. >=20 > +# >=20 > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[BuildOptions] >=20 > +# Define Build Options both for EDK and EDKII drivers. >=20 > + >=20 > + >=20 > + DEFINE DSC_S3_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE DSC_CSM_BUILD_OPTIONS =3D >=20 > + >=20 > +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE >=20 > + DEFINE DSC_ACPI_BUILD_OPTIONS =3D -DACPI_SUPPORT=3D1 >=20 > +!else >=20 > + DEFINE DSC_ACPI_BUILD_OPTIONS =3D >=20 > +!endif >=20 > + >=20 > + DEFINE BIOS_GUARD_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE OVERCLOCKING_BUILD_OPTION =3D >=20 > + >=20 > + DEFINE FSP_BINARY_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE FSP_WRAPPER_BUILD_OPTIONS =3D -DFSP_WRAPPER_FLAG >=20 > + >=20 > + DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =3D >=20 > + >=20 > + DEFINE RESTRICTED_OPTION =3D >=20 > + >=20 > + >=20 > + DEFINE SV_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE TEST_MENU_BUILD_OPTION =3D >=20 > + >=20 > +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE >=20 > + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL- >=20 > +!else >=20 > + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D >=20 > +!endif >=20 > + >=20 > + DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =3D >=20 > + >=20 > + >=20 > + DEFINE TPM_BUILD_OPTION =3D >=20 > + >=20 > + DEFINE TPM2_BUILD_OPTION =3D >=20 > + >=20 > + DEFINE DSC_TBT_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE DSC_DCTT_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE EMB_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =3D - > DMEM_DOWN_FLAG=3D1 >=20 > + >=20 > + DEFINE DSC_KBCEMUL_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE BOOT_GUARD_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE SECURE_BOOT_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE USBTYPEC_BUILD_OPTION =3D >=20 > + >=20 > + DEFINE CAPSULE_BUILD_OPTIONS =3D >=20 > + >=20 > + DEFINE PERFORMANCE_BUILD_OPTION =3D >=20 > + >=20 > + DEFINE DEBUGUSEUSB_BUILD_OPTION =3D >=20 > + >=20 > + DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =3D - > DDISABLE_NEW_DEPRECATED_INTERFACES=3D1 >=20 > + >=20 > + DEFINE SINITBIN_BUILD_OPTION =3D >=20 > + >=20 > + DEFINE MINTREE_FLAG_BUILD_OPTION =3D -DMINTREE_FLAG=3D1 >=20 > + >=20 > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) > $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) > $(EMB_BUILD_OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) > $(DSC_TBT_BUILD_OPTIONS) >=20 > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > $(BOOT_GUARD_BUILD_OPTIONS) > $(DSC_MEMORY_DOWN_BUILD_OPTIONS) > $(DEBUGUSEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS) >=20 > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) > $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS) >=20 > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) > $(SECURE_BOOT_BUILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) > $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION) >=20 > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION) > $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS) >=20 > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) > $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION) > $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION) >=20 > + >=20 > +[BuildOptions.Common.EDKII] >=20 > + >=20 > +# >=20 > +# For IA32 Global Build Flag >=20 > +# >=20 > + *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - > D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI >=20 > + *_*_IA32_VFRPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_IA32_NASM_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + >=20 > +# >=20 > +# For IA32 Specific Build Flag >=20 > +# >=20 > +GCC: *_*_IA32_PP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > +GCC: *_*_IA32_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI -Wno-unused -Wl,-- > allow-multiple-definition >=20 > +MSFT: *_*_IA32_ASM_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > +MSFT: *_*_IA32_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI >=20 > +MSFT: *_*_IA32_VFRPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_IA32_APP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_IA32_ASLPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_IA32_ASLCC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > + >=20 > +# >=20 > +# For X64 Global Build Flag >=20 > +# >=20 > + *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - > D PI_SPECIFICATION_VERSION=3D0x00010015 >=20 > + *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + *_*_X64_NASM_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + >=20 > + >=20 > +# >=20 > +# For X64 Specific Build Flag >=20 > +# >=20 > +GCC: *_*_X64_PP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > +GCC: *_*_X64_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 -Wno-unused -Wl,--allow- > multiple-definition >=20 > +MSFT: *_*_X64_ASM_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > +MSFT: *_*_X64_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > -D PI_SPECIFICATION_VERSION=3D0x00010015 >=20 > +MSFT: *_*_X64_VFRPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_X64_APP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) >=20 > +MSFT: *_*_X64_ASLPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > +MSFT: *_*_X64_ASLCC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) >=20 > + >=20 > + >=20 > +# Force PE/COFF sections to be aligned at 4KB boundaries to support page > level protection >=20 > +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, > BuildOptions.common.EDKII.SMM_CORE] >=20 > + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 >=20 > + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 >=20 > + >=20 > +# Force PE/COFF sections to be aligned at 4KB boundaries to support > MemoryAttribute table >=20 > +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] >=20 > + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 >=20 > + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 >=20 > + >=20 > +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX > protection >=20 > +[BuildOptions.common.EDKII.DXE_DRIVER, > BuildOptions.common.EDKII.DXE_CORE, > BuildOptions.common.EDKII.UEFI_DRIVER, > BuildOptions.common.EDKII.UEFI_APPLICATION] >=20 > + #MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 >=20 > + #GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kgPcd.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kgPcd.dsc > new file mode 100644 > index 000000000000..725596cbf71e > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP > kgPcd.dsc > @@ -0,0 +1,464 @@ > +## @file >=20 > +# PCD configuration build description file for the KabylakeRvp3 board. >=20 > +# >=20 > +# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +######################################################### > ####################### >=20 > +# >=20 > +# Pcd Section - list of all PCD Entries used by this board. >=20 > +# >=20 > +######################################################### > ####################### >=20 > + >=20 > +[PcdsFixedAtBuild.common] >=20 > + ###################################### >=20 > + # Key Boot Stage and FSP configuration >=20 > + ###################################### >=20 > + # >=20 > + # Please select the Boot Stage here. >=20 > + # Stage 1 - enable debug (system deadloop after debug init) >=20 > + # Stage 2 - mem init (system deadloop after mem init) >=20 > + # Stage 3 - boot to shell only >=20 > + # Stage 4 - boot to OS >=20 > + # Stage 5 - boot to OS with security boot enabled >=20 > + # Stage 6 - boot with advanced features enabled >=20 > + # >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 >=20 > + >=20 > + # >=20 > + # 0: FSP Wrapper is running in Dispatch mode. >=20 > + # 1: FSP Wrapper is running in API mode. >=20 > + # >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 >=20 > + >=20 > + # >=20 > + # FALSE: The board is not a FSP wrapper (FSP binary not used) >=20 > + # TRUE: The board is a FSP wrapper (FSP binary is used) >=20 > + # >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE >=20 > + >=20 > + # >=20 > + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all > PEIMs >=20 > + # (both inside FSP and outside FSP). >=20 > + # Pros: >=20 > + # * PEI Main is re-built from source and is always the latest= version >=20 > + # * Platform code can link any desired LibraryClass to PEI Ma= in >=20 > + # (Ex: Custom DebugLib instance, SerialPortLib, etc.) >=20 > + # Cons: >=20 > + # * The PEI Main being used to execute FSP PEIMs is not the P= EI Main >=20 > + # that the FSP PEIMs were tested with, adding risk of break= age. >=20 > + # * Two copies of PEI Main will exist in the final binary, >=20 > + # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is neve= r >=20 > + # executed, wasting space. >=20 > + # >=20 > + # TRUE: The PEI Main included in FSP is used to dispatch all P= EIMs >=20 > + # (both inside FSP and outside FSP). PEI Main will not be inclu= ded in >=20 > + # FvPreMemory. This is the default and is the recommended choic= e. >=20 > + # >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TR > UE >=20 > + >=20 > + # >=20 > + # FSP Base address PCD will be updated in FDF basing on flash map. >=20 > + # >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 >=20 > + >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 >=20 > + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 >=20 > + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 >=20 > + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 >=20 > + >=20 > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 >=20 > + # >=20 > + # FSP API mode does not share stack with the boot loader, >=20 > + # so FSP needs more temporary memory for FSP heap + stack size. >=20 > + # >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 >=20 > + # >=20 > + # FSP API mode does not need to enlarge the boot loader stack size >=20 > + # since the stacks are separate. >=20 > + # >=20 > + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 >=20 > +!else >=20 > + # >=20 > + # In FSP Dispatch mode boot loader stack size must be large >=20 > + # enough for executing both boot loader and FSP. >=20 > + # >=20 > + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 >=20 > +!endif >=20 > + >=20 > +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) > || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1) >=20 > + > gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpac > eGuid.PcdPciExpressBaseAddress >=20 > + > gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgToke > nSpaceGuid.PcdPciExpressRegionLength >=20 > +!else >=20 > + # >=20 > + # FSP Dispatch mode requires more platform memory as boot loader and > FSP sharing the same >=20 > + # platform memory. >=20 > + # >=20 > + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 >=20 > +!endif >=20 > + >=20 > +[PcdsFeatureFlag.common] >=20 > + ###################################### >=20 > + # Edk2 Configuration >=20 > + ###################################### >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSecti > onFirst|FALSE >=20 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE >=20 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE >=20 > + >=20 > + ###################################### >=20 > + # Silicon Configuration >=20 > + ###################################### >=20 > + # Build switches >=20 > + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE >=20 > + >=20 > + # CPU >=20 > + gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE >=20 > + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE >=20 > + >=20 > + # SA >=20 > + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE >=20 > + >=20 > + # ME >=20 > + gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE >=20 > + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE >=20 > + >=20 > + # Others >=20 > + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE >=20 > + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE >=20 > + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE >=20 > + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE >=20 > + gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE >=20 > + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE >=20 > + >=20 > + ###################################### >=20 > + # Platform Configuration >=20 > + ###################################### >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE >=20 > +!endif >=20 > + >=20 > +!if $(TARGET) =3D=3D DEBUG >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE >=20 > +!else >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE >=20 > +!endif >=20 > + >=20 > + ###################################### >=20 > + # Board Configuration >=20 > + ###################################### >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE >=20 > + >=20 > +[PcdsFixedAtBuild.common] >=20 > + ###################################### >=20 > + # Edk2 Configuration >=20 > + ###################################### >=20 > +!if $(TARGET) =3D=3D RELEASE >=20 > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 >=20 > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 >=20 > +!else >=20 > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F >=20 > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 >=20 > +!endif >=20 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE >=20 > + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 >=20 > +!endif >=20 > + >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$( > TOP_MEMORY_ADDRESS) >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x4 > 00 >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 >=20 > +!endif >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe| > TRUE >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x > 1 >=20 > +!endif >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE >=20 > +!if $(TARGET) =3D=3D DEBUG >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FAL > SE >=20 > +!endif >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE >=20 > +!if $(TARGET) =3D=3D RELEASE >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE >=20 > +!else >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE >=20 > +!endif >=20 > + >=20 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 >=20 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40 >=20 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 >=20 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F >=20 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 >=20 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 >=20 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 >=20 > + > gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC >=20 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 >=20 > + >=20 > + # Specifies timeout value in microseconds for the BSP to detect all AP= s for > the first time. >=20 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 >=20 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 >=20 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 >=20 > +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) > || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1) >=20 > + # >=20 > + # In non-FSP build (EDK2 build) or FSP API mode below PCD are > FixedAtBuild >=20 > + # (They will be DynamicEx in FSP Dispatch mode) >=20 > + # >=20 > + ## Specifies max supported number of Logical Processors. >=20 > + # @Prompt Configure max supported number of Logical Processors >=20 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 >=20 > + >=20 > + ## Specifies the size of the microcode Region. >=20 > + # @Prompt Microcode Region size. >=20 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 >=20 > + >=20 > + ## Specifies the AP wait loop state during POST phase. >=20 > + # The value is defined as below. >=20 > + # 1: Place AP in the Hlt-Loop state. >=20 > + # 2: Place AP in the Mwait-Loop state. >=20 > + # 3: Place AP in the Run-Loop state. >=20 > + # @Prompt The AP wait loop state. >=20 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 >=20 > +!endif >=20 > + >=20 > + ###################################### >=20 > + # Silicon Configuration >=20 > + ###################################### >=20 > + >=20 > + # Refer to HstiFeatureBit.h for bit definitions >=20 > + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 >=20 > + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 >=20 > + >=20 > + ###################################### >=20 > + # Platform Configuration >=20 > + ###################################### >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 >=20 > + >=20 > + # >=20 > + # The PCDs are used to control the Windows SMM Security Mitigations > Table - Protection Flags >=20 > + # >=20 > + # BIT0: If set, expresses that for all synchronous SMM entries,SMM wil= l > validate that input and output buffers lie entirely within the expected f= ixed > memory regions. >=20 > + # BIT1: If set, expresses that for all synchronous SMM entries, SMM wi= ll > validate that input and output pointers embedded within the fixed > communication buffer only refer to address ranges \ >=20 > + # that lie entirely within the expected fixed memory regions. >=20 > + # BIT2: Firmware setting this bit is an indication that it will not al= low > reconfiguration of system resources via non-architectural mechanisms. >=20 > + # BIT3-31: Reserved >=20 > + # >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 >=20 > + >=20 > +!if $(TARGET) =3D=3D RELEASE >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x4 > 02 >=20 > +!else >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x1 > 88B >=20 > +!endif >=20 > + >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b >=20 > +!if $(TARGET) =3D=3D RELEASE >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 >=20 > +!else >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1 >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, > 0x00, 0x00} >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 2 >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, > 0x00, 0x00} >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 3 >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, > 0x00, 0x00} >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 4 >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, > 0x00, 0x00} >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5 >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, > 0x00, 0x00} >=20 > +!endif >=20 > + >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6 >=20 > + > gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0= x00, > 0x00, 0x00} >=20 > +!endif >=20 > + >=20 > + >=20 > + ###################################### >=20 > + # Board Configuration >=20 > + ###################################### >=20 > + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|1 >=20 > + gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, > 0x00, 0x1F, 0x00} >=20 > + >=20 > +[PcdsFixedAtBuild.IA32] >=20 > + ###################################### >=20 > + # Edk2 Configuration >=20 > + ###################################### >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 >=20 > + >=20 > + ###################################### >=20 > + # Platform Configuration >=20 > + ###################################### >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 >=20 > + >=20 > +[PcdsFixedAtBuild.X64] >=20 > + ###################################### >=20 > + # Edk2 Configuration >=20 > + ###################################### >=20 > + >=20 > + # Default platform supported RFC 4646 languages: (American) English >=20 > + > gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"e > n-US" >=20 > + >=20 > +[PcdsPatchableInModule.common] >=20 > + ###################################### >=20 > + # Edk2 Configuration >=20 > + ###################################### >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 >=20 > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 >=20 > + >=20 > + ###################################### >=20 > + # Silicon Configuration >=20 > + ###################################### >=20 > +!if $(TARGET) =3D=3D DEBUG >=20 > + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 >=20 > +!endif >=20 > + >=20 > +[PcdsDynamicDefault] >=20 > + ###################################### >=20 > + # Edk2 Configuration >=20 > + ###################################### >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x > 0 >=20 > + >=20 > + # >=20 > + # Set video to native resolution as Windows 8 WHCK requirement. >=20 > + # >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 >=20 > + >=20 > + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0 >=20 > + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F >=20 > + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 >=20 > + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, > 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0= x17} >=20 > + >=20 > + # >=20 > + # FSP Base address PCD will be updated in FDF basing on flash map. >=20 > + # >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 >=20 > + # Platform will pre-allocate UPD buffer and pass it to FspWrapper >=20 > + # Those dummy address will be patched before FspWrapper executing >=20 > + > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF >=20 > + >=20 > + ###################################### >=20 > + # Board Configuration >=20 > + ###################################### >=20 > + >=20 > + # Thunderbolt Configuration >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting > |0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x > 02010011 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerEn|0x1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerType|0x1 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioAccessType|0x2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|2 > 6 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemRsvd|100 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax| > 28 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode|0x1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWin10Support|0x0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExpander|0x0 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000 > 001 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtOffDelay|5000 >=20 > + >=20 > +[PcdsDynamicHii.X64.DEFAULT] >=20 > + ###################################### >=20 > + # Edk2 Configuration >=20 > + ###################################### >=20 > + > gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSup > port"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" >=20 > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE >=20 > + > gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlo > balVariableGuid|0x0|1 # Variable: L"Timeout" >=20 > +!else >=20 > + > gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlo > balVariableGuid|0x0|5 # Variable: L"Timeout" >=20 > +!endif >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c > new file mode 100644 > index 000000000000..7744af6b3cfc > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c > @@ -0,0 +1,175 @@ > +/** @file >=20 > + This file initialises and Installs GopPolicy Protocol. >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include "DxeGopPolicyInit.h" >=20 > +#include >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL > mGOPPolicy; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize =3D 0; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS > mVbtAddress =3D 0; >=20 > + >=20 > +// >=20 > +// Function implementations >=20 > +// >=20 > + >=20 > +/** >=20 > + >=20 > + @param[out] CurrentLidStatus >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_UNSUPPORTED >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetPlatformLidStatus ( >=20 > + OUT LID_STATUS *CurrentLidStatus >=20 > + ) >=20 > +{ >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > +/** >=20 > + >=20 > + @param[out] CurrentDockStatus >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_UNSUPPORTED >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetPlatformDockStatus ( >=20 > + OUT DOCK_STATUS CurrentDockStatus >=20 > + ) >=20 > +{ >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + >=20 > + @param[out] VbtAddress >=20 > + @param[out] VbtSize >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_NOT_FOUND >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetVbtData ( >=20 > + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, >=20 > + OUT UINT32 *VbtSize >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINTN FvProtocolCount; >=20 > + EFI_HANDLE *FvHandles; >=20 > + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; >=20 > + UINTN Index; >=20 > + UINT32 AuthenticationStatus; >=20 > + UINT8 *Buffer; >=20 > + UINTN VbtBufferSize; >=20 > + >=20 > + >=20 > + Status =3D EFI_NOT_FOUND; >=20 > + if ( mVbtAddress =3D=3D 0) { >=20 > + Fv =3D NULL; >=20 > + >=20 > + Buffer =3D 0; >=20 > + FvHandles =3D NULL; >=20 > + Status =3D gBS->LocateHandleBuffer ( >=20 > + ByProtocol, >=20 > + &gEfiFirmwareVolume2ProtocolGuid, >=20 > + NULL, >=20 > + &FvProtocolCount, >=20 > + &FvHandles >=20 > + ); >=20 > + if (!EFI_ERROR (Status)) { >=20 > + for (Index =3D 0; Index < FvProtocolCount; Index++) { >=20 > + Status =3D gBS->HandleProtocol ( >=20 > + FvHandles[Index], >=20 > + &gEfiFirmwareVolume2ProtocolGuid, >=20 > + (VOID **) &Fv >=20 > + ); >=20 > + VbtBufferSize =3D 0; >=20 > + Status =3D Fv->ReadSection ( >=20 > + Fv, >=20 > + PcdGetPtr (PcdGraphicsVbtGuid), >=20 > + EFI_SECTION_RAW, >=20 > + 0, >=20 > + (VOID **) &Buffer, >=20 > + &VbtBufferSize, >=20 > + &AuthenticationStatus >=20 > + ); >=20 > + if (!EFI_ERROR (Status)) { >=20 > + *VbtAddress =3D (EFI_PHYSICAL_ADDRESS)Buffer; >=20 > + *VbtSize =3D (UINT32)VbtBufferSize; >=20 > + mVbtAddress =3D *VbtAddress; >=20 > + mVbtSize =3D *VbtSize; >=20 > + Status =3D EFI_SUCCESS; >=20 > + break; >=20 > + } >=20 > + } >=20 > + } else { >=20 > + Status =3D EFI_NOT_FOUND; >=20 > + } >=20 > + >=20 > + if (FvHandles !=3D NULL) { >=20 > + FreePool (FvHandles); >=20 > + FvHandles =3D NULL; >=20 > + } >=20 > + } else { >=20 > + *VbtAddress =3D mVbtAddress; >=20 > + *VbtSize =3D mVbtSize; >=20 > + Status =3D EFI_SUCCESS; >=20 > + } >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > + >=20 > + >=20 > +/** >=20 > +Initialize GOP DXE Policy >=20 > + >=20 > +@param[in] ImageHandle Image handle of this driver. >=20 > + >=20 > +@retval EFI_SUCCESS Initialization complete. >=20 > +@retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r. >=20 > +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver. >=20 > +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. >=20 > +**/ >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GopPolicyInitDxe ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + // >=20 > + // Initialize the EFI Driver Library >=20 > + // >=20 > + SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0); >=20 > + >=20 > + mGOPPolicy.Revision =3D GOP_POLICY_PROTOCOL_REVISION_03= ; >=20 > + mGOPPolicy.GetPlatformLidStatus =3D GetPlatformLidStatus; >=20 > + mGOPPolicy.GetVbtData =3D GetVbtData; >=20 > + mGOPPolicy.GetPlatformDockStatus =3D GetPlatformDockStatus; >=20 > + >=20 > + // >=20 > + // Install protocol to allow access to this Policy. >=20 > + // >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &ImageHandle, >=20 > + &gGopPolicyProtocolGuid, >=20 > + &mGOPPolicy, >=20 > + NULL >=20 > + ); >=20 > + >=20 > + return Status; >=20 > +} >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h > new file mode 100644 > index 000000000000..17f9b545fcfb > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h > @@ -0,0 +1,39 @@ > +/** @file >=20 > +Header file for the GopPolicyInitDxe Driver. >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > +#ifndef _GOP_POLICY_INIT_DXE_H_ >=20 > +#define _GOP_POLICY_INIT_DXE_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > + >=20 > +/** >=20 > +Initialize GOP DXE Policy >=20 > + >=20 > +@param[in] ImageHandle Image handle of this driver. >=20 > + >=20 > +@retval EFI_SUCCESS Initialization complete. >=20 > +@retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r. >=20 > +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver. >=20 > +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GopPolicyInitDxe( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ); >=20 > + >=20 > +#endif >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h > new file mode 100644 > index 000000000000..b49e13da54c1 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h > @@ -0,0 +1,64 @@ > +/** @file >=20 > + Header file for the SaPolicyInitDxe Driver. >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > +#ifndef _SA_POLICY_INIT_DXE_H_ >=20 > +#define _SA_POLICY_INIT_DXE_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > + >=20 > +/** >=20 > + SA DXE Policy Driver Entry Point \n >=20 > + - Introduction \n >=20 > + System Agent DXE drivers behavior can be controlled by platform poli= cy > without modifying reference code directly. >=20 > + Platform policy Protocol is initialized with default settings in thi= s funciton. >=20 > + This policy Protocol has to be initialized prior to System Agent ini= tialization > DXE drivers execution. >=20 > + >=20 > + - @pre >=20 > + - Runtime variable service should be ready if policy initialization = required. >=20 > + >=20 > + - @result >=20 > + SA_POLICY_PROTOCOL will be installed successfully and ready for Syst= em > Agent reference code use. >=20 > + >=20 > + - Porting Recommendations \n >=20 > + Policy should be initialized basing on platform design or user selec= tion > (like BIOS Setup Menu) >=20 > + >=20 > + @param[in] ImageHandle - Image handle of this driver. >=20 > + >=20 > + @retval EFI_SUCCESS Initialization complete. >=20 > + @exception EFI_UNSUPPORTED The chipset is unsupported by this > driver. >=20 > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver. >=20 > + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaPolicyInitDxe ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Get data for platform policy from setup options. >=20 > + >=20 > + @param[in] SaPolicy The pointer to get SA Policy prot= ocol instance >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +UpdateDxeSaPolicy ( >=20 > + IN OUT SA_POLICY_PROTOCOL *SaPolicy >=20 > + ); >=20 > + >=20 > +#endif >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c > new file mode 100644 > index 000000000000..fcd248fdf5cf > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c > @@ -0,0 +1,66 @@ > +/** @file >=20 > + This file is the library for SA DXE Policy initialization. >=20 > + >=20 > +Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include "DxeSaPolicyInit.h" >=20 > +#include >=20 > + >=20 > +#define SA_VTD_RMRR_USB_LENGTH 0x20000 >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS > mAddress; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSiz= e; >=20 > + >=20 > +/** >=20 > + Update RMRR Base and Limit Address for USB. >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +UpdateRmrrUsbAddress ( >=20 > + IN OUT SA_POLICY_PROTOCOL *SaPolicy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + MISC_DXE_CONFIG *MiscDxeConfig; >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOI= D > *)&MiscDxeConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + if (1) { >=20 > + mSize =3D EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH); >=20 > + mAddress =3D SIZE_4GB; >=20 > + >=20 > + Status =3D (gBS->AllocatePages) ( >=20 > + AllocateMaxAddress, >=20 > + EfiReservedMemoryType, >=20 > + mSize, >=20 > + &mAddress >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + MiscDxeConfig->RmrrUsbBaseAddress[0] =3D mAddress; >=20 > + MiscDxeConfig->RmrrUsbBaseAddress[1] =3D mAddress + > SA_VTD_RMRR_USB_LENGTH - 1; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Get data for platform policy from setup options. >=20 > + >=20 > + @param[in] SaPolicy The pointer to get SA Policy prot= ocol instance >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +UpdateDxeSaPolicy ( >=20 > + IN OUT SA_POLICY_PROTOCOL *SaPolicy >=20 > + ) >=20 > +{ >=20 > + UpdateRmrrUsbAddress (SaPolicy); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c > new file mode 100644 > index 000000000000..d4dbb414a26f > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c > @@ -0,0 +1,53 @@ > +/** @file >=20 > + >=20 > +Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include "DxeSaPolicyInit.h" >=20 > +#include "DxeGopPolicyInit.h" >=20 > + >=20 > +/** >=20 > + Performs silicon late policy update. >=20 > + >=20 > + The meaning of Policy is defined by silicon code. >=20 > + It could be the raw data, a handle, a Protocol, etc. >=20 > + >=20 > + The input Policy must be returned by SiliconPolicyDoneLate(). >=20 > + >=20 > + In FSP or non-FSP path, the board may use additional way to get >=20 > + the silicon policy data field based upon the input Policy. >=20 > + >=20 > + @param[in, out] Policy Pointer to policy. >=20 > + >=20 > + @return the updated policy. >=20 > +**/ >=20 > +VOID * >=20 > +EFIAPI >=20 > +SiliconPolicyUpdateLate ( >=20 > + IN VOID *Policy >=20 > + ) >=20 > +{ >=20 > + SA_POLICY_PROTOCOL *SaPolicy; >=20 > + EFI_STATUS Status; >=20 > + >=20 > + SaPolicy =3D Policy; >=20 > + UpdateDxeSaPolicy (SaPolicy); >=20 > + >=20 > + if (PcdGetBool(PcdIntelGopEnable)) { >=20 > + // >=20 > + // GOP Dxe Policy Initialization >=20 > + // >=20 > + Status =3D GopPolicyInitDxe(gImageHandle); >=20 > + DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); >=20 > + ASSERT_EFI_ERROR(Status); >=20 > + } >=20 > + >=20 > + return Policy; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf > new file mode 100644 > index 000000000000..2abf1aef805a > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf > @@ -0,0 +1,51 @@ > +## @file >=20 > +# Component information file for Silicon Update Library >=20 > +# >=20 > +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D DxeSiliconUpdateLib >=20 > + FILE_GUID =3D C523609D-E354-416B-B24F-33468D4BD21= D >=20 > + MODULE_TYPE =3D DXE_DRIVER >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D SiliconUpdateLib >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + PcdLib >=20 > + DebugLib >=20 > + ConfigBlockLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Sources] >=20 > + DxeSiliconPolicyUpdateLib.c >=20 > + DxeGopPolicyInit.c >=20 > + DxeSaPolicyUpdate.c >=20 > + >=20 > +[Pcd] >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid >=20 > + >=20 > +[Protocols] >=20 > + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES >=20 > + gSaPolicyProtocolGuid ## CONSUMES >=20 > + gDxeSiPolicyProtocolGuid ## PRODUCES >=20 > + gGopPolicyProtocolGuid ## PRODUCES >=20 > + >=20 > +[Guids] >=20 > + gMiscDxeConfigGuid >=20 > + >=20 > +[Depex] >=20 > + gEfiVariableArchProtocolGuid >=20 > + >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c > new file mode 100644 > index 000000000000..2dce9be63c58 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c > @@ -0,0 +1,601 @@ > +/** @file >=20 > + Provides silicon policy update library functions. >=20 > + >=20 > +Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
>=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > + >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Get the next microcode patch pointer. >=20 > + >=20 > + @param[in, out] MicrocodeData - Input is a pointer to the last microco= de > patch address found, >=20 > + and output points to the next patch ad= dress found. >=20 > + >=20 > + @retval EFI_SUCCESS - Patch found. >=20 > + @retval EFI_NOT_FOUND - Patch not found. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +RetrieveMicrocode ( >=20 > + IN OUT CPU_MICROCODE_HEADER **MicrocodeData >=20 > + ) >=20 > +{ >=20 > + UINTN MicrocodeStart; >=20 > + UINTN MicrocodeEnd; >=20 > + UINTN TotalSize; >=20 > + >=20 > + if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) =3D=3D 0) || (FixedPcdGet= 32 > (PcdFlashMicrocodeFvSize) =3D=3D 0)) { >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Microcode binary in SEC >=20 > + /// >=20 > + MicrocodeStart =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + >=20 > + ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 > (PcdFlashMicrocodeFvBase))->HeaderLength + >=20 > + sizeof (EFI_FFS_FILE_HEADER); >=20 > + >=20 > + MicrocodeEnd =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + > (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); >=20 > + >=20 > + if (*MicrocodeData =3D=3D NULL) { >=20 > + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) (UINTN) > MicrocodeStart; >=20 > + } else { >=20 > + if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) > MicrocodeStart) { >=20 > + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart > \n")); >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + >=20 > + TotalSize =3D (UINTN) ((*MicrocodeData)->TotalSize); >=20 > + if (TotalSize =3D=3D 0) { >=20 > + TotalSize =3D 2048; >=20 > + } >=20 > + >=20 > + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) > ((UINTN)*MicrocodeData + TotalSize); >=20 > + if (*MicrocodeData >=3D (CPU_MICROCODE_HEADER *) (UINTN) > (MicrocodeEnd) || (*MicrocodeData)->TotalSize =3D=3D (UINT32) -1) { >=20 > + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >=3D MicrocodeEnd > \n")); >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Get the microcode patch pointer. >=20 > + >=20 > + @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or > NULL if not found. >=20 > +**/ >=20 > +EFI_PHYSICAL_ADDRESS >=20 > +PlatformCpuLocateMicrocodePatch ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + CPU_MICROCODE_HEADER *MicrocodeData; >=20 > + EFI_CPUID_REGISTER Cpuid; >=20 > + UINT32 UcodeRevision; >=20 > + UINTN MicrocodeBufferSize; >=20 > + VOID *MicrocodeBuffer =3D NULL; >=20 > + >=20 > + AsmCpuid ( >=20 > + CPUID_VERSION_INFO, >=20 > + &Cpuid.RegEax, >=20 > + &Cpuid.RegEbx, >=20 > + &Cpuid.RegEcx, >=20 > + &Cpuid.RegEdx >=20 > + ); >=20 > + >=20 > + UcodeRevision =3D GetCpuUcodeRevision (); >=20 > + MicrocodeData =3D NULL; >=20 > + while (TRUE) { >=20 > + /// >=20 > + /// Find the next patch address >=20 > + /// >=20 > + Status =3D RetrieveMicrocode (&MicrocodeData); >=20 > + DEBUG ((DEBUG_INFO, "MicrocodeData =3D %x\n", MicrocodeData)); >=20 > + >=20 > + if (Status !=3D EFI_SUCCESS) { >=20 > + break; >=20 > + } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, > &UcodeRevision)) { >=20 > + break; >=20 > + } >=20 > + } >=20 > + >=20 > + if (EFI_ERROR (Status)) { >=20 > + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Check that microcode patch size is <=3D 128K max size, >=20 > + /// then copy the patch from FV to temp buffer for faster access. >=20 > + /// >=20 > + MicrocodeBufferSize =3D (UINTN) MicrocodeData->TotalSize; >=20 > + >=20 > + if (MicrocodeBufferSize <=3D MAX_MICROCODE_PATCH_SIZE) { >=20 > + MicrocodeBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES > (MicrocodeBufferSize)); >=20 > + if (MicrocodeBuffer !=3D NULL) { >=20 > + DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); >=20 > + CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); >=20 > + >=20 > + return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; >=20 > + } else { >=20 > + DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for > Microcode Patch.\n")); >=20 > + } >=20 > + } else { >=20 > + DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max > allowed size of 128K.\n")); >=20 > + } >=20 > + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; >=20 > +} >=20 > + >=20 > +/** >=20 > + Update HSIO policy per board. >=20 > + >=20 > + @param[in] Policy - Policy PPI pointer (caller should ensure it is val= id > pointer) >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +InstallPlatformHsioPtssTable ( >=20 > + IN VOID *Policy >=20 > + ) >=20 > +{ >=20 > + HSIO_PTSS_TABLES *UnknowPtssTables; >=20 > + HSIO_PTSS_TABLES *SpecificPtssTables; >=20 > + HSIO_PTSS_TABLES *PtssTables; >=20 > + UINT8 PtssTableIndex; >=20 > + UINT32 UnknowTableSize; >=20 > + UINT32 SpecificTableSize; >=20 > + UINT32 TableSize; >=20 > + UINT32 Entry; >=20 > + UINT8 LaneNum; >=20 > + UINT8 Index; >=20 > + UINT8 MaxSataPorts; >=20 > + UINT8 MaxPciePorts; >=20 > + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; >=20 > + UINT8 PciePort; >=20 > + UINTN RpBase; >=20 > + UINTN RpDevice; >=20 > + UINTN RpFunction; >=20 > + UINT32 StrapFuseCfg; >=20 > + UINT8 PcieControllerCfg; >=20 > + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; >=20 > + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; >=20 > + EFI_STATUS Status; >=20 > + >=20 > + Status =3D GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *= ) > &HsioPciePreMemConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + Status =3D GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *= ) > &HsioSataPreMemConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + UnknowPtssTables =3D NULL; >=20 > + UnknowTableSize =3D 0; >=20 > + SpecificPtssTables =3D NULL; >=20 > + SpecificTableSize =3D 0; >=20 > + >=20 > + if (GetPchGeneration () =3D=3D SklPch) { >=20 > + switch (PchStepping ()) { >=20 > + case PchLpB0: >=20 > + case PchLpB1: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowLpHsioPtssTable1); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable1Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificLpHsioPtssTable1); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable1Size)= ; >=20 > + break; >=20 > + case PchLpC0: >=20 > + case PchLpC1: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowLpHsioPtssTable2); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable2Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificLpHsioPtssTable2); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable2Size)= ; >=20 > + break; >=20 > + case PchHB0: >=20 > + case PchHC0: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowHHsioPtssTable1); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable1Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificHHsioPtssTable1); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable1Size); >=20 > + break; >=20 > + case PchHD0: >=20 > + case PchHD1: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowHHsioPtssTable2); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificHHsioPtssTable2); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size); >=20 > + break; >=20 > + default: >=20 > + UnknowPtssTables =3D NULL; >=20 > + UnknowTableSize =3D 0; >=20 > + SpecificPtssTables =3D NULL; >=20 > + SpecificTableSize =3D 0; >=20 > + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); >=20 > + } >=20 > + } else { >=20 > + switch (PchStepping ()) { >=20 > + case KblPchHA0: >=20 > + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdUnknowHHsioPtssTable2); >=20 > + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size); >=20 > + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 > (PcdSpecificHHsioPtssTable2); >=20 > + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size); >=20 > + break; >=20 > + default: >=20 > + UnknowPtssTables =3D NULL; >=20 > + UnknowTableSize =3D 0; >=20 > + SpecificPtssTables =3D NULL; >=20 > + SpecificTableSize =3D 0; >=20 > + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); >=20 > + } >=20 > + } >=20 > + >=20 > + PtssTableIndex =3D 0; >=20 > + MaxSataPorts =3D GetPchMaxSataPortNum (); >=20 > + MaxPciePorts =3D GetPchMaxPciePortNum (); >=20 > + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); >=20 > + // >=20 > + //Populate PCIe topology based on lane configuration >=20 > + // >=20 > + for (PciePort =3D 0; PciePort < MaxPciePorts; PciePort +=3D 4) { >=20 > + Status =3D GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + RpBase =3D MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) > RpDevice, (UINT32) RpFunction); >=20 > + StrapFuseCfg =3D MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); >=20 > + PcieControllerCfg =3D (UINT8) ((StrapFuseCfg & > B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); >=20 > + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value =3D %d\n", > PciePort, PcieControllerCfg)); >=20 > + } >=20 > + for (Index =3D 0; Index < MaxPciePorts; Index++) { >=20 > + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology =3D %d\n", > Index, PcieTopologyReal[Index])); >=20 > + } >=20 > + // >=20 > + //Case 1: BoardId is known, Topology is known/unknown >=20 > + //Case 1a: SATA >=20 > + // >=20 > + PtssTables =3D SpecificPtssTables; >=20 > + TableSize =3D SpecificTableSize; >=20 > + for (Index =3D 0; Index < MaxSataPorts; Index++) { >=20 > + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { >=20 > + for (Entry =3D 0; Entry < TableSize; Entry++) { >=20 > + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && >=20 > + (PtssTables[Entry].PtssTable.PhyMode =3D=3D > V_PCH_PCR_FIA_LANE_OWN_SATA) >=20 > + ) >=20 > + { >=20 > + PtssTableIndex++; >=20 > + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_RX_DWORD20) && >=20 > + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & > B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D > (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) > { >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioRxGen3EqBoostMagEnable =3D TRUE; >=20 > + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag > =3D (PtssTables[Entry].PtssTable.Value & (UINT32) > ~PtssTables[Entry].PtssTable.BitMask) >> > N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; >=20 > + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_TX_DWORD8)) { >=20 > + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioTxGen1DownscaleAmpEnable =3D TRUE; >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioTxGen1DownscaleAmp =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> > N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); >=20 > + } >=20 > + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioTxGen2DownscaleAmpEnable =3D TRUE; >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioTxGen2DownscaleAmp =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> > N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); >=20 > + } >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + // >=20 > + //Case 1b: PCIe >=20 > + // >=20 > + for (Index =3D 0; Index < MaxPciePorts; Index++) { >=20 > + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { >=20 > + for (Entry =3D 0; Entry < TableSize; Entry++) { >=20 > + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && >=20 > + (PtssTables[Entry].PtssTable.PhyMode =3D=3D > V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && >=20 > + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology))= { >=20 > + PtssTableIndex++; >=20 > + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_RX_DWORD25) && >=20 > + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & > B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) > B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { >=20 > + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = =3D > TRUE; >=20 > + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > ~PtssTables[Entry].PtssTable.BitMask) >> > N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); >=20 > + >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + // >=20 > + //Case 2: BoardId is unknown, Topology is known/unknown >=20 > + // >=20 > + if (PtssTableIndex =3D=3D 0) { >=20 > + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be > applied\n")); >=20 > + >=20 > + PtssTables =3D UnknowPtssTables; >=20 > + TableSize =3D UnknowTableSize; >=20 > + >=20 > + for (Index =3D 0; Index < MaxSataPorts; Index++) { >=20 > + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { >=20 > + for (Entry =3D 0; Entry < TableSize; Entry++) { >=20 > + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && >=20 > + (PtssTables[Entry].PtssTable.PhyMode =3D=3D > V_PCH_PCR_FIA_LANE_OWN_SATA) >=20 > + ) >=20 > + { >=20 > + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_RX_DWORD20) && >=20 > + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & > B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D > (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) > { >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioRxGen3EqBoostMagEnable =3D TRUE; >=20 > + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag > =3D (PtssTables[Entry].PtssTable.Value & (UINT32) > ~PtssTables[Entry].PtssTable.BitMask) >> > N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; >=20 > + >=20 > + } else if (PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32= ) > R_PCH_HSIO_TX_DWORD8) { >=20 > + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT= 32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioTxGen1DownscaleAmpEnable =3D TRUE; >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioTxGen1DownscaleAmp =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> > N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); >=20 > + >=20 > + } >=20 > + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT= 32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioTxGen2DownscaleAmpEnable =3D TRUE; >=20 > + HsioSataPreMemConfig- > >PortLane[Index].HsioTxGen2DownscaleAmp =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> > N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); >=20 > + } >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + for (Index =3D 0; Index < MaxPciePorts; Index++) { >=20 > + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { >=20 > + for (Entry =3D 0; Entry < TableSize; Entry++) { >=20 > + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && >=20 > + (PtssTables[Entry].PtssTable.PhyMode =3D=3D > V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && >=20 > + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology= )) { >=20 > + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) > R_PCH_HSIO_RX_DWORD25) && >=20 > + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & > B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) > B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { >=20 > + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = =3D > TRUE; >=20 > + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = =3D > (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) > ~PtssTables[Entry].PtssTable.BitMask) >> > N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); >=20 > + } else { >=20 > + ASSERT (FALSE); >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Update PreMem phase silicon policy per board. >=20 > + >=20 > + @param[in] Policy - Policy PPI pointer. >=20 > + >=20 > + @retval Policy - Policy PPI pointer. >=20 > + >=20 > +**/ >=20 > +VOID * >=20 > +EFIAPI >=20 > +SiliconPolicyUpdatePreMem ( >=20 > + IN VOID *Policy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; >=20 > + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; >=20 > + VOID *Buffer; >=20 > + UINTN VariableSize; >=20 > + VOID *MemorySavedData; >=20 > + UINT8 SpdAddressTable[4]; >=20 > + >=20 > + DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n")); >=20 > + >=20 > + if (Policy !=3D NULL) { >=20 > + SpdAddressTable[0] =3D PcdGet8 (PcdMrcSpdAddressTable0); >=20 > + SpdAddressTable[1] =3D PcdGet8 (PcdMrcSpdAddressTable1); >=20 > + SpdAddressTable[2] =3D PcdGet8 (PcdMrcSpdAddressTable2); >=20 > + SpdAddressTable[3] =3D PcdGet8 (PcdMrcSpdAddressTable3); >=20 > + >=20 > + MiscPeiPreMemConfig =3D NULL; >=20 > + Status =3D GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOI= D > *) &MiscPeiPreMemConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + if (MiscPeiPreMemConfig !=3D NULL) { >=20 > + // >=20 > + // Pass board specific SpdAddressTable to policy >=20 > + // >=20 > + CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID > *) SpdAddressTable, (sizeof (UINT8) * 4)); >=20 > + >=20 > + // >=20 > + // Set size of SMRAM >=20 > + // >=20 > + MiscPeiPreMemConfig->TsegSize =3D PcdGet32 (PcdTsegSize); >=20 > + >=20 > + // >=20 > + // Initialize S3 Data variable (S3DataPtr). It may be used for war= m and > fast boot paths. >=20 > + // Note: AmberLake FSP does not implement the > FSPM_ARCH_CONFIG_PPI added in FSP 2.1, hence >=20 > + // the platform specific S3DataPtr must be used instead. >=20 > + // >=20 > + VariableSize =3D 0; >=20 > + MemorySavedData =3D NULL; >=20 > + Status =3D PeiGetVariable ( >=20 > + L"MemoryConfig", >=20 > + &gFspNonVolatileStorageHobGuid, >=20 > + &MemorySavedData, >=20 > + &VariableSize >=20 > + ); >=20 > + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" > gFspNonVolatileStorageHobGuid - %r\n", Status)); >=20 > + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); >=20 > + if (!EFI_ERROR (Status)) { >=20 > + MiscPeiPreMemConfig->S3DataPtr =3D MemorySavedData; >=20 > + } >=20 > + >=20 > + // >=20 > + // In FSP Dispatch Mode these BAR values are initialized by > SiliconPolicyInitPreMem() in >=20 > + // > KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c;= this > function calls >=20 > + // PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI->PeiPreMemPolicyInit() > to initialize all Config Blocks >=20 > + // with default policy values (including these BAR values.) > PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI >=20 > + // is implemented in the FSP. Make sure the value that FSP is usin= g > matches the value we are using. >=20 > + // >=20 > + ASSERT (PcdGet64 (PcdMchBaseAddress) <=3D 0xFFFFFFFF); >=20 > + ASSERT (MiscPeiPreMemConfig->MchBar =3D=3D (UINT32) PcdGet64 > (PcdMchBaseAddress)); >=20 > + ASSERT (MiscPeiPreMemConfig->SmbusBar =3D=3D PcdGet16 > (PcdSmbusBaseAddress)); >=20 > + } >=20 > + MemConfigNoCrc =3D NULL; >=20 > + Status =3D GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) > &MemConfigNoCrc); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + if (MemConfigNoCrc !=3D NULL) { >=20 > + MemConfigNoCrc->PlatformMemorySize =3D PcdGet32 > (PcdPeiMinMemorySize); >=20 > + >=20 > + // >=20 > + // Only if SpdAddressTables are all zero we need to pass hard-code= d SPD > data buffer. >=20 > + // Otherwise FSP will retrieve SPD from DIMM basing on > SpdAddressTables policy. >=20 > + // >=20 > + if (*((UINT32 *) (UINTN) SpdAddressTable) =3D=3D 0) { >=20 > + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n")); >=20 > + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], > (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 > (PcdMrcSpdDataSize)); >=20 > + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], > (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 > (PcdMrcSpdDataSize)); >=20 > + } >=20 > + >=20 > + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling > Settings...\n")); >=20 > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); >=20 > + if (Buffer) { >=20 > + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], > Buffer, 12); >=20 > + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], > (UINT8*) Buffer + 12, 12); >=20 > + } >=20 > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); >=20 > + if (Buffer) { >=20 > + CopyMem ((VOID *) MemConfigNoCrc->DqsMap- > >DqsMapCpu2Dram[0], Buffer, 8); >=20 > + CopyMem ((VOID *) MemConfigNoCrc->DqsMap- > >DqsMapCpu2Dram[1], (UINT8*) Buffer + 8, 8); >=20 > + } >=20 > + >=20 > + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & > Rcomp Target Settings...\n")); >=20 > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); >=20 > + if (Buffer) { >=20 > + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData- > >RcompResistor[0]), Buffer, 6); >=20 > + } >=20 > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); >=20 > + if (Buffer) { >=20 > + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData- > >RcompTarget[0]), Buffer, 10); >=20 > + } >=20 > + } >=20 > + // >=20 > + // Update PCD policy >=20 > + // >=20 > + InstallPlatformHsioPtssTable (Policy); >=20 > + } >=20 > + >=20 > + return Policy; >=20 > +} >=20 > + >=20 > +/** >=20 > + Update PostMem phase silicon policy per board. >=20 > + >=20 > + @param[in] Policy - Policy PPI pointer. >=20 > + >=20 > + @retval Policy - Policy PPI pointer. >=20 > + >=20 > +**/ >=20 > +VOID * >=20 > +EFIAPI >=20 > +SiliconPolicyUpdatePostMem ( >=20 > + IN VOID *Policy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + VOID *Buffer; >=20 > + VOID *MemBuffer; >=20 > + UINT32 Size; >=20 > + GRAPHICS_PEI_CONFIG *GtConfig; >=20 > + CPU_CONFIG *CpuConfig; >=20 > + >=20 > + DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); >=20 > + >=20 > + GtConfig =3D NULL; >=20 > + Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (= VOID > *)&GtConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + if (GtConfig !=3D NULL) { >=20 > + // >=20 > + // Always enable PEI graphics initialization. >=20 > + // >=20 > + GtConfig->PeiGraphicsPeimInit =3D 1; >=20 > + Size =3D 0; >=20 > + Buffer =3D NULL; >=20 > + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), > EFI_SECTION_RAW, 0, &Buffer, &Size); >=20 > + if (Buffer =3D=3D NULL) { >=20 > + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); >=20 > + } else { >=20 > + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES > ((UINTN)Size)); >=20 > + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { >=20 > + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); >=20 > + GtConfig->GraphicsConfigPtr =3D MemBuffer; >=20 > + } else { >=20 > + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); >=20 > + GtConfig->GraphicsConfigPtr =3D 0; >=20 > + } >=20 > + } >=20 > + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is > 0x%x\n", GtConfig->GraphicsConfigPtr)); >=20 > + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", > Size)); >=20 > + Size =3D 0; >=20 > + Buffer =3D NULL; >=20 > + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, > &Buffer, &Size); >=20 > + if (Buffer =3D=3D NULL) { >=20 > + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); >=20 > + } else { >=20 > + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES > ((UINTN)Size)); >=20 > + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { >=20 > + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); >=20 > + GtConfig->LogoPtr =3D MemBuffer; >=20 > + GtConfig->LogoSize =3D Size; >=20 > + } else { >=20 > + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); >=20 > + GtConfig->LogoPtr =3D 0; >=20 > + GtConfig->LogoSize =3D 0; >=20 > + } >=20 > + } >=20 > + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", > GtConfig->LogoPtr)); >=20 > + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", > GtConfig->LogoSize)); >=20 > + } >=20 > + >=20 > + CpuConfig =3D NULL; >=20 > + Status =3D GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID > *)&CpuConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + if (CpuConfig !=3D NULL) { >=20 > + CpuConfig->MicrocodePatchAddress =3D > PlatformCpuLocateMicrocodePatch (); >=20 > + } >=20 > + return Policy; >=20 > +} >=20 > + >=20 > +/** >=20 > + Update late phase silicon policy per board. >=20 > + >=20 > + @param[in] Policy - Policy PPI pointer. >=20 > + >=20 > + @retval Policy - Policy PPI pointer. >=20 > + >=20 > +**/ >=20 > +VOID * >=20 > +EFIAPI >=20 > +SiliconPolicyUpdateLate ( >=20 > + IN VOID *Policy >=20 > + ) >=20 > +{ >=20 > + return Policy; >=20 > +} >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > new file mode 100644 > index 000000000000..5c2da68bf935 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar > y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf > @@ -0,0 +1,92 @@ > +### @file >=20 > +# Component information file for silicon policy update library >=20 > +# >=20 > +# Copyright (c) 2019 - 2021 Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiSiliconPolicyUpdateLib >=20 > + FILE_GUID =3D 14F5D83D-76A5-4241-BEC5-987E70E233D= 5 >=20 > + MODULE_TYPE =3D PEIM >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D SiliconPolicyUpdateLib >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + PcdLib >=20 > + DebugLib >=20 > + ConfigBlockLib >=20 > + BaseMemoryLib >=20 > + MemoryAllocationLib >=20 > + PeiLib >=20 > + CpuPlatformLib >=20 > + PchPcieRpLib >=20 > + PchInfoLib >=20 > + MmPciLib >=20 > + IoLib >=20 > + PchHsioLib >=20 > + >=20 > +[Packages] >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + MdePkg/MdePkg.dec >=20 > + IntelFsp2Pkg/IntelFsp2Pkg.dec >=20 > + UefiCpuPkg/UefiCpuPkg.dec >=20 > + KabylakeSiliconPkg/SiPkg.dec >=20 > + KabylakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Sources] >=20 > + PeiSiliconPolicyUpdateLib.c >=20 > + >=20 > +[Guids] >=20 > + gMemoryConfigNoCrcGuid >=20 > + gTianoLogoGuid ## CONSUMES >=20 > + gGraphicsPeiConfigGuid ## CONSUMES >=20 > + gCpuConfigGuid ## CONSUMES >=20 > + gHsioPciePreMemConfigGuid ## CONSUMES >=20 > + gHsioSataPreMemConfigGuid ## CONSUMES >=20 > + gSaMiscPeiPreMemConfigGuid ## CONSUMES >=20 > + gFspNonVolatileStorageHobGuid ## CONSUMES >=20 > + >=20 > +[Pcd] >=20 > + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize >=20 > + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase >=20 > + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize >=20 > + gSiPkgTokenSpaceGuid.PcdMchBaseAddress >=20 > + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress >=20 > + gSiPkgTokenSpaceGuid.PcdTsegSize >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## > CONSUMES >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size >=20 > + >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size >=20 > + > gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size >=20 > + >=20 > + # SPD Address Table >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 >=20 > + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board. > py > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board. > py > new file mode 100644 > index 000000000000..41668120f109 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board. > py > @@ -0,0 +1,68 @@ > +# @ build_board.py >=20 > +# This is a sample code provides Optional dynamic imports >=20 > +# of build functions to the BuildBios.py script >=20 > +# >=20 > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > + >=20 > +""" >=20 > +This module serves as a sample implementation of the build extension >=20 > +scripts >=20 > +""" >=20 > + >=20 > + >=20 > +def pre_build_ex(config, functions): >=20 > + """Additional Pre BIOS build function >=20 > + >=20 > + :param config: The environment variables to be used in the build pro= cess >=20 > + :type config: Dictionary >=20 > + :param functions: A dictionary of function pointers >=20 > + :type functions: Dictionary >=20 > + :returns: nothing >=20 > + """ >=20 > + print("pre_build_ex") >=20 > + return None >=20 > + >=20 > + >=20 > +def build_ex(config, functions): >=20 > + """Additional BIOS build function >=20 > + >=20 > + :param config: The environment variables to be used in the build pro= cess >=20 > + :type config: Dictionary >=20 > + :param functions: A dictionary of function pointers >=20 > + :type functions: Dictionary >=20 > + :returns: config dictionary >=20 > + :rtype: Dictionary >=20 > + """ >=20 > + print("build_ex") >=20 > + return None >=20 > + >=20 > + >=20 > +def post_build_ex(config, functions): >=20 > + """Additional Post BIOS build function >=20 > + >=20 > + :param config: The environment variables to be used in the post >=20 > + build process >=20 > + :type config: Dictionary >=20 > + :param functions: A dictionary of function pointers >=20 > + :type functions: Dictionary >=20 > + :returns: config dictionary >=20 > + :rtype: Dictionary >=20 > + """ >=20 > + print("post_build_ex") >=20 > + return None >=20 > + >=20 > + >=20 > +def clean_ex(config, functions): >=20 > + """Additional clean function >=20 > + >=20 > + :param config: The environment variables to be used in the build pro= cess >=20 > + :type config: Dictionary >=20 > + :param functions: A dictionary of function pointers >=20 > + :type functions: Dictionary >=20 > + :returns: config dictionary >=20 > + :rtype: Dictionary >=20 > + """ >=20 > + print("clean_ex") >=20 > + return None >=20 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config. > cfg > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config. > cfg > new file mode 100644 > index 000000000000..f6ae4b342aa0 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config. > cfg > @@ -0,0 +1,36 @@ > +# @ build_config.cfg >=20 > +# This is the KabylakeRvp3 board specific build settings >=20 > +# >=20 > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > + >=20 > + >=20 > +[CONFIG] >=20 > +WORKSPACE_PLATFORM_BIN =3D >=20 > +EDK_SETUP_OPTION =3D >=20 > +openssl_path =3D >=20 > +PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg >=20 > +PROJECT =3D KabylakeOpenBoardPkg/KabylakeRvp3 >=20 > +BOARD =3D KabylakeRvp3 >=20 > +FLASH_MAP_FDF =3D > KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapInclude.fdf >=20 > +PROJECT_DSC =3D KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc >=20 > +BOARD_PKG_PCD_DSC =3D > KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc >=20 > +ADDITIONAL_SCRIPTS =3D > KabylakeOpenBoardPkg/KabylakeRvp3/build_board.py >=20 > +PrepRELEASE =3D DEBUG >=20 > +SILENT_MODE =3D FALSE >=20 > +EXT_CONFIG_CLEAR =3D >=20 > +CapsuleBuild =3D FALSE >=20 > +EXT_BUILD_FLAGS =3D >=20 > +CAPSULE_BUILD =3D 0 >=20 > +TARGET =3D DEBUG >=20 > +TARGET_SHORT =3D D >=20 > +PERFORMANCE_BUILD =3D FALSE >=20 > +FSP_WRAPPER_BUILD =3D TRUE >=20 > +FSP_BIN_PKG =3D AmberLakeFspBinPkg >=20 > +FSP_BIN_PKG_FOR_API_MODE =3D KabylakeFspBinPkg >=20 > +FSP_PKG_NAME =3D AmberLakeFspPkg >=20 > +FSP_BINARY_BUILD =3D FALSE >=20 > +FSP_TEST_RELEASE =3D FALSE >=20 > +SECURE_BOOT_ENABLE =3D FALSE >=20 > +BIOS_INFO_GUID =3D C83BCE0E-6F16-4D3C-8D9F-4D6F5A032929 >=20 > -- > 2.31.1