It shouldn’t be because if it were then it would be impossible to access MCHBAR from 32-bit mode… but fair point. I’ve added an error check for that case, please see patch v2.

Thanks,

Nate

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Benjamin Doron
Sent: Monday, August 16, 2021 10:16 AM
To: Michael Kubacki <mikuback@linux.microsoft.com>
Cc: devel@edk2.groups.io; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Michael Kubacki <michael.kubacki@microsoft.com>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V1] KabylakeSiliconPkg: Default for PeciC10Reset should be 1

The MCH BAR field is the 38:15 bit range. Are the higher bits guaranteed to be clear, so that a 32 bit read is sufficient?

Best regards,

Benjamin

On Mon, Aug 16, 2021 at 11:53 AM Michael Kubacki <mikuback@linux.microsoft.com> wrote:

Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>

On 8/16/2021 12:02 AM, Nate DeSimone wrote:
> The default value for CpuConfigLibPreMemConfig->PeciC10Reset
> should be 1 so that Peci Reset on C10 exit is disabled.
>
> Other bug fixes in
> KabylakeSiliconPkg\Cpu\Library\PeiCpuPolicyLibPreMem\PeiCpuPolicyLib.c
>
>   1. PCI configuration space can only be read 32-bits at a time.
>      Converted MmioRead64 to MmioRead32.
>   2. Added a RShiftU64() call to prevent compiler instrinsics from
>      being inserted. Since this is a 64-bit integer shift done in
>      IA-32 mode it is possible for intrinsic calls to be added.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Benjamin Doron <benjamin.doron00@gmail.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>   .../Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c  | 9 ++++++---
>   1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c
> index 35041322a7..85baa46208 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c
> @@ -1,7 +1,7 @@
>   /** @file
>     This file is PeiCpuPolicy library.
>   
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
>   SPDX-License-Identifier: BSD-2-Clause-Patent
>   
>   **/
> @@ -45,13 +45,14 @@ LoadCpuConfigLibPreMemConfigDefault (
>     CpuConfigLibPreMemConfig->BootFrequency           = 1;    // Maximum non-turbo Performance
>     CpuConfigLibPreMemConfig->ActiveCoreCount         = 0;    // All cores active
>     CpuConfigLibPreMemConfig->VmxEnable               = CPU_FEATURE_ENABLE;
> -  CpuConfigLibPreMemConfig->CpuRatio = ((AsmReadMsr64 (MSR_PLATFORM_INFO) >> N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK);
> +  CpuConfigLibPreMemConfig->CpuRatio = RShiftU64 (AsmReadMsr64 (MSR_PLATFORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK;
> +
>     ///
>     /// FCLK Frequency
>     ///
>     CpuFamily  = GetCpuFamily();
>     CpuSku     = GetCpuSku();
> -  MchBar = MmioRead64 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0;
> +  MchBar = MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0;
>     if (IsPchLinkDmi (CpuFamily) && (MmioRead16 (MmPciBase (SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG10_FUN_NUM) + PCI_VENDOR_ID_OFFSET) != 0xFFFF)) {
>       PegDisabled = MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET) & BIT3;
>     } else {
> @@ -67,6 +68,8 @@ LoadCpuConfigLibPreMemConfigDefault (
>     } else {
>       CpuConfigLibPreMemConfig->FClkFrequency = 0;  // 800MHz
>     }
> +
> +  CpuConfigLibPreMemConfig->PeciC10Reset = 1;  // Disables Peci Reset on C10 exit
>   }
>   
>   /**