From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mga14.intel.com (mga14.intel.com [192.55.52.115])
 by mx.groups.io with SMTP id smtpd.web12.30928.1629149077674918608
 for <devel@edk2.groups.io>;
 Mon, 16 Aug 2021 14:24:38 -0700
Authentication-Results: mx.groups.io;
 dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=tsN6Du0E;
 spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: nathaniel.l.desimone@intel.com)
X-IronPort-AV: E=McAfee;i="6200,9189,10078"; a="215671234"
X-IronPort-AV: E=Sophos;i="5.84,327,1620716400"; 
   d="scan'208";a="215671234"
Received: from fmsmga003.fm.intel.com ([10.253.24.29])
  by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 14:24:36 -0700
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.84,327,1620716400"; 
   d="scan'208";a="519906509"
Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81])
  by FMSMGA003.fm.intel.com with ESMTP; 16 Aug 2021 14:24:36 -0700
Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by
 fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id
 15.1.2242.10; Mon, 16 Aug 2021 14:24:35 -0700
Received: from fmsmsx607.amr.corp.intel.com (10.18.126.87) by
 fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id
 15.1.2242.10; Mon, 16 Aug 2021 14:24:35 -0700
Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by
 fmsmsx607.amr.corp.intel.com (10.18.126.87) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id
 15.1.2242.10 via Frontend Transport; Mon, 16 Aug 2021 14:24:35 -0700
Received: from NAM10-DM6-obe.outbound.protection.outlook.com (104.47.58.101)
 by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server
 (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
 15.1.2242.10; Mon, 16 Aug 2021 14:24:34 -0700
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
 b=FSal5vnPPyfkV2x3l5ezLOYPakSOYt1egsb+cgho5zUM/VIKM8FcPumsj02OHPT7EAHYihorSxUobMo9q/rEn7ll3Qjjsigm0OLrODxqel2oSjcMUtukb8KfqLloNwIVMh5LKKKhekUfTM0yQTPOHZURfDdZGwmAH8JeYhxx4BhKy+XsOiOsNLkT9+Yclf3ORmrF3qOn433d32e2Hwbhbv8Qf9BCHZmJpMlQ2U+YZ28p/jby9lzDBqeoVG8zey4xTOYzYPKiKVC6f2jP9rrZy4exgOpW8mkX7aeYN8s7iN4Xqh47OupuFr4IZCQeLXu7mOhHxcqOEWPRj8JhdaRdZQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;
 s=arcselector9901;
 h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
 bh=mpmTtoO3jmAvq0Ny4Eab3v/3ou4gij83FsLxlgoVbD8=;
 b=AysqL1cWg6GN+YApeIagCNqvGfzq+M3MQhjrvQvw5lEfwJOTDkKAcTP3MuFtHcxzyGKaGxQtI01GaxDEpzn1D1VlUvK+g+2u8wHLAPg7+pZW0IkOeL+MgIZ5uisDMBJtUbSqrLyt4rFFmK/PXPmNm5fOnvjrjD0bgydGo+U1zpyaLUJRvje4YgD3UrN6DmX6C9Pphk0auYAWCzKLlX4xUR+oJ+0FzcCy9+yvBwe0eUAUz6a3Huvy7l9FVBjUditbHXucMJ7qQL0DAK8/JNENFEU8g33L4ordFYkPUOkU5gdneMgaFCLg42idLQKdREcAx6ruq6Z/U6BXS+U5LGDK0A==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass
 smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com;
 dkim=pass header.d=intel.com; arc=none
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com;
 s=selector2-intel-onmicrosoft-com;
 h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
 bh=mpmTtoO3jmAvq0Ny4Eab3v/3ou4gij83FsLxlgoVbD8=;
 b=tsN6Du0E/Qy0Sxq6YmGSHVi93EZn9x6TabDVffNfZtiemsJppNwh3rNhzfVv8j5qwkJQXNCQK2jFppLhva1wm7PuEk+GW2nN4qT5R8zQj2xVKZQPEZ4cbbVDHoyqoLz6C+051mInFb/3G5oILnNCPiiNECxSCOAe0RxIq6bTPFg=
Received: from MWHPR1101MB2160.namprd11.prod.outlook.com
 (2603:10b6:301:5b::12) by MW3PR11MB4617.namprd11.prod.outlook.com
 (2603:10b6:303:59::24) with Microsoft SMTP Server (version=TLS1_2,
 cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4415.19; Mon, 16 Aug
 2021 21:24:26 +0000
Received: from MWHPR1101MB2160.namprd11.prod.outlook.com
 ([fe80::546c:f20e:35d2:65a7]) by MWHPR1101MB2160.namprd11.prod.outlook.com
 ([fe80::546c:f20e:35d2:65a7%5]) with mapi id 15.20.4415.023; Mon, 16 Aug 2021
 21:24:26 +0000
From: "Nate DeSimone" <nathaniel.l.desimone@intel.com>
To: "Oram, Isaac W" <isaac.w.oram@intel.com>, "devel@edk2.groups.io"
	<devel@edk2.groups.io>
CC: "Chiu, Chasel" <chasel.chiu@intel.com>, "KARPAGAVINAYAGAM, MANICKAVASAKAM"
	<manickavasakamk@ami.com>, "Jha, Manish" <manishj@ami.com>
Subject: Re: [edk2-devel][edk2-platforms][PATCH V1 1/1] WhitleyOpenBoardPkg/Uba: Add WilsonCitySMT board support
Thread-Topic: [edk2-devel][edk2-platforms][PATCH V1 1/1]
 WhitleyOpenBoardPkg/Uba:  Add WilsonCitySMT board support
Thread-Index: AQHXkthER8jRCUUAmUKvlev5StUoL6t2pGRQ
Date: Mon, 16 Aug 2021 21:24:25 +0000
Message-ID: <MWHPR1101MB2160F86EA8AED203C5C9DACACDFD9@MWHPR1101MB2160.namprd11.prod.outlook.com>
References: <b7efc90885bbf5867a849b49ce9aa93d9079515f.1629143420.git.isaac.w.oram@intel.com>
In-Reply-To: <b7efc90885bbf5867a849b49ce9aa93d9079515f.1629143420.git.isaac.w.oram@intel.com>
Accept-Language: en-US
X-MS-Has-Attach: 
X-MS-TNEF-Correlator: 
dlp-reaction: no-action
dlp-version: 11.5.1.3
dlp-product: dlpe-windows
authentication-results: intel.com; dkim=none (message not signed)
 header.d=none;intel.com; dmarc=none action=none header.from=intel.com;
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: c11093bf-c008-4b87-7dc1-08d960fc3974
x-ms-traffictypediagnostic: MW3PR11MB4617:
x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr
x-ms-exchange-transport-forked: True
x-microsoft-antispam-prvs: <MW3PR11MB46177400F7C5784BB0356FC7CDFD9@MW3PR11MB4617.namprd11.prod.outlook.com>
x-ms-oob-tlc-oobclassifiers: OLM:2150;
x-ms-exchange-senderadcheck: 1
x-ms-exchange-antispam-relay: 0
x-microsoft-antispam: BCL:0;
x-microsoft-antispam-message-info: l1PXAgN3Hwyq9yi5qvZ8gYNi+KrshQji5K2wEfvYHROlaD2facrLm/L00uCPsdi99NeuajwADkwlYSpA3APN57aEguAGswe7ZKSp4Y3zXrjncj5zDi66ZlOCOc/VueAiPt5SVLVFAQ9yK2VFroQz3KVlPANFsPRRUqpvC+MGb3lp6DMvBz6Icb6tXiC0/5gJLRAEIgF0bkUbfWp7WF5vJWTqIf6iBch2H9owGxonav4BOEGwlOQkDKp0+gJJBWVcwJFPqGrXoFF7IW7WCU9wOfwnNWqNSGMWQ8eY6gymm53SeLYi3wsqfH9Dcc7oZlQG02tpDp+2un1EM+Nm47fXhw/rfYDVyl/kwtaSmRfMgbzsrpcBFeDKKQAmC0Z9wByanos/HT7+ASt1zQYwyEQPrBhnIpjqN7rQTkIrrjoIneQALC9iIWhoazRR9oaZxyHtUiYQC9FZsCt+geu6pSSpumkVFMIxwelM34hkIWgOHyZuO6H0jS4nSwx6nBq7l07Ox0F44O8Z3Cb13cHGJMj8xrYndxcGhwBZPEzWMfKEzBbBdmjFmhTtViGJLHRkiGMSre19ZfatGZc6zxWFDu/ytG4vpLYbIgbf8UYsAkBCzGZO8bIlhzX8hNnYIXMT86UG413au4ash11uRZOKwzb1JK1da/8OfrYymKQ4eIpKtFRI06d7PPZZf50vTvjMrrY0HO8u81PxIUnCUmAqXs5t9g==
x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1101MB2160.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(376002)(39860400002)(346002)(396003)(136003)(366004)(30864003)(186003)(86362001)(66446008)(66556008)(66946007)(19627235002)(64756008)(4326008)(66476007)(53546011)(8936002)(83380400001)(33656002)(8676002)(55016002)(2906002)(9686003)(110136005)(54906003)(7696005)(76116006)(316002)(38100700002)(26005)(5660300002)(38070700005)(52536014)(6506007)(478600001)(122000001)(71200400001)(579004)(569008)(559001);DIR:OUT;SFP:1102;
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?sn/t00+D8hcYrk5K5pxGt25IwYW8vD0ST/dTI246yl7qrjyYz4wAcntj9UMe?=
 =?us-ascii?Q?BZCazHezqfQLQnB0YLDxs2QayMdo4BFFoJddt2aG9ArSkMIYF8a7mmYgeqHh?=
 =?us-ascii?Q?04e8DVUiGOl/K6x+hR4sP87rCxGdof8WkxziffTAGXL4fu3fFhO1r2HTDGY9?=
 =?us-ascii?Q?uDiPMWH6ikc36/F+NilLzolKnTuIEyTMyb5JucesqXATuBEZYMd5FO6Ac4pw?=
 =?us-ascii?Q?2oUYaMyV0u89Zp68/aPU2/xmtcYPGnmvv16tom7QrzE7sc4VHCgBFtdb9C49?=
 =?us-ascii?Q?NRTqpgbjLLOJbLT1t3ASkxYTW4EWovp2K6MphW0VNNgGyaWWANKR2XzgC03q?=
 =?us-ascii?Q?g7KYrpLlmHqmqEyxMxIVOrlEvT/O38oLtYPEKUgr8KLH+3s+K1qtYk8yheE8?=
 =?us-ascii?Q?zokZttB3PKzdAi9Yw//qWQ6tV7hR+nY8jSEe54bmGJwll5VE+6l5gAwJ9Kz4?=
 =?us-ascii?Q?NEIuV1dHaUuid7pNyoyQvZtqm0+5exOvg/TI8mJPYnQ6AOlwVzx2LiM/vUGS?=
 =?us-ascii?Q?PjrNyN11m8nyCuLpyH1a+keYkj2OI4UWyqkPD2KgHLL4HEpv/TASXSyr8TCe?=
 =?us-ascii?Q?tuo6CnOn8FmqrQiWV/bgtY+K7030WJrPWFUHQKOX8k0EyXGYrfsXKSt/exty?=
 =?us-ascii?Q?6S0ap/LzzvQ5lKP9NEjW4WXcz9O36p620YLNnyBFJVxVL3D33iVMzBLnA/5C?=
 =?us-ascii?Q?TWXCqhKz8tXdXgx4qsfyKT1PrTSyCmcjKfIK6dNCg7EenSZ3ijiWFQPtJm7C?=
 =?us-ascii?Q?ETXOgKh0lVDNF6CBLe1Rz7wEx1NlQVEYrY67+CJ6NUQ5pHZ1G2n4PCeMNwqv?=
 =?us-ascii?Q?35qAKTvo/Oe3Ovb/KhYl1nUpiZ5AvoSfxCFqNb3xsy2WUlBMLjWeG8Ddve3c?=
 =?us-ascii?Q?QjjV54Bmt9MbsLrwrtR6s7J5J0Sp2pApu2Dsf2YB9ik/nROh6WSXNDsjSFwM?=
 =?us-ascii?Q?SafhNnxbv/O3VoxzPpvELTrGJr7YhbKUNxz49riHsPr/pAcn0UdjBochjavU?=
 =?us-ascii?Q?/XloTGiIXAdsgFHpqygeh2c6eaZceHacFldgoB8WZ3CwRjPZGR/QBNSUedo2?=
 =?us-ascii?Q?J8+nn+1snih0Dsdg6P5n6nqf6bwJzJno4r487o943tzQWtbkOPm9Eg914wXB?=
 =?us-ascii?Q?mhLkSDy9o03f+ESMps1kRsePkbhKkBjSxTf09+RLrI7+Rw31Wvq9OfsjTtXl?=
 =?us-ascii?Q?WOK727A6UAHs2Iq0lLUO8aRfwcM6fgB63K07t65pfsHfZzQF/eznfTVb/S/1?=
 =?us-ascii?Q?SKtU226rAIcg1usoWghP7goFPd4ERLT2Li2exkaG/A+vpe8PTZIWfUzJr7jX?=
 =?us-ascii?Q?ygNaBA1FKyFkmFoL59G6cK+8?=
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: MWHPR1101MB2160.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: c11093bf-c008-4b87-7dc1-08d960fc3974
X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Aug 2021 21:24:25.8458
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: gCoO94Ovf6BMjx96bGFX5XP2R3uRhCAKUpSCEnyjZdsAwLv6VFw0h0QM626BFMh3k38c025quya3e9JYfng4lJxWH1I3Lqrq+L6gpYnSKgY=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR11MB4617
Return-Path: nathaniel.l.desimone@intel.com
X-OriginatorOrg: intel.com
Content-Language: en-US
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram@intel.com>
> Sent: Monday, August 16, 2021 12:52 PM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; KARPAGAVINAYAGAM, MANICKAVASAKAM
> <manickavasakamk@ami.com>; Jha, Manish <manishj@ami.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 1/1]
> WhitleyOpenBoardPkg/Uba: Add WilsonCitySMT board support
>=20
> Add support for another commonly used Whitley reference platform
> motherboard
>=20
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
> Cc: Manish Jha <manishj@ami.com>
> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
> ---
>  Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
> |   7 +
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei
> /IioBifurInit.c                           | 141 ---------
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei
> /KtiEparam.c                              |  39 ---
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/D
> xe/IioCfgUpdateDxe/IioCfgUpdateDxe.c       |  99 ++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/D
> xe/IioCfgUpdateDxe/IioCfgUpdateDxe.h       | 118 +++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/D
> xe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf     |  48 +++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/D
> xe/SlotDataUpdateDxe/SlotDataUpdateDxe.c   | 115 +++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/D
> xe/SlotDataUpdateDxe/SlotDataUpdateDxe.h   |  57 ++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/D
> xe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf |  48 +++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/D
> xe/UsbOcUpdateDxe/UsbOcUpdateDxe.c         | 127 ++++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/D
> xe/UsbOcUpdateDxe/UsbOcUpdateDxe.h         |  27 ++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/D
> xe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf       |  44 +++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/AcpiTablePcds.c                         |  51 +++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/GpioTable.c                             | 327 ++++++++++++++++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/IioBifurInit.c                          | 249 +++++++++++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/KtiEparam.c                             |  79 +++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/PcdData.c                               | 273 ++++++++++++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/PchEarlyUpdate.c                        | 103 ++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/PeiBoardInit.h                          |  79 +++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/PeiBoardInitLib.c                       | 123 ++++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/PeiBoardInitLib.inf                     | 166 ++++++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/SlotTable.c                             | 171 ++++++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/SoftStrapFixup.c                        | 120 +++++++
>=20
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/P
> ei/UsbOC.c                                 | 126 ++++++++
>  Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
> |   8 +
>  25 files changed, 2565 insertions(+), 180 deletions(-)
>=20
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
> index cb40d6da78..fcf147885f 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
> @@ -20,3 +20,10 @@ INF
> $(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/SlotDataUpdateDxe/Slot
> DataUpdate
>  INF
> $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/UsbOcUpdateDxe/UsbO
> cUpdateDxe.inf
>  INF
> $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/IioCfgUpdateDxe/IioCfg
> UpdateDxe.inf
>  INF
> $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/Slot
> DataUpdateDxe.inf
> +
> +#
> +# Platform TypeWilsonCitySMT
> +#
> +INF
> $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/Usb
> OcUpdateDxe.inf
> +INF
> $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfg
> UpdateDxe.inf
> +INF
> $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/Slo
> tDataUpdateDxe.inf
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/P
> ei/IioBifurInit.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/P
> ei/IioBifurInit.c
> index c9e1be13ec..dc8fe7cc63 100644
> ---
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/P
> ei/IioBifurInit.c
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/P
> ei/IioBifurInit.c
> @@ -148,135 +148,6 @@ static IIO_SLOT_CONFIG_DATA_ENTRY_EX
> IioSlotTable[] =3D {
>      PORT_5D_INDEX, 17         , DISABLE , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_1   , 0x4E         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , ENABLE  , 0x20         , 2      =
      , 16        ,
> 0xe2         , 4            , ENABLE  , VPP_PORT_0   , 0x74         , ENA=
BLE  ,
> SMB_ADDR_MAX   , NOT_EXIST      , ENABLE  , VPP_PORT_1     , 0x42        =
   , 0x1
> }
>  };
>=20
> -
> -//
> -//  Tables below are generated by script. Please do not change it direct=
ly.
> -//
> -//  config file: Wilson_City_PCIe_Slot_Config_1p71.xlsx
> -//  config sheet: WilsonCity_CPX
> -//  sheet notes: WilsonCity for CPX4 Rev0.5, 11/07/2019
> -//
> -static IIO_BIFURCATION_DATA_ENTRY_EX   IioBifurcationTable_CPX[] =3D
> -{
> -  { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, 0           ,        =
 0x76, 0xE2
> , 4            },
> -  { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -
> -  { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_x4x4x4x4, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -
> -  { Iio_Socket2, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0           ,        =
 0x7C, 0xE2
> , 4            },
> -  { Iio_Socket2, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket2, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket2, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket2, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -
> -  { Iio_Socket3, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket3, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0           ,        =
 0x70, 0xE2
> , 4            },
> -  { Iio_Socket3, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
> -  { Iio_Socket3, Iio_Iou3, IIO_BIFURCATE_x4x4x4x4, 0           ,        =
 0x74, 0xE2
> , 4            },
> -  { Iio_Socket3, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }
> -};
> -
> -static IIO_SLOT_CONFIG_DATA_ENTRY_EX   IioSlotTable_CPX[] =3D {
> -  // Port Index                   | Slot      |Inter   |Power       |Pow=
er       |Hotplug |Vpp
> Port     |Vpp Addr     |PCIeSSD |PCIeSSD      |PCIeSSD      |Hidden   |Co=
mmon  |
> SRIS  |Uplink  |Retimer |Retimer      |Retimer      |Retimer   |Mux      =
    |Mux
> |ExtnCard|ExtnCard     |ExtnCard     |ExtnCard|Ex.C. Retimer|Ex.C. Ret-
> |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max    |
> -  //                              |           |lock    |Limit Scale |Lim=
it Value |Cap     |             |
> |Cap     |Port         |Address      |         |Clock   |        |Port   =
 |        |Address
> |Channel      |Width     |Address      |Channel      |Support |SMBus Port
> |SMBus Addr   |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port
> |Vpp Address  |Retimer|
> -  { SOCKET_0_INDEX + PORT_1A_INDEX, 7         , DISABLE, 0          , 75=
         ,
> DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE,
> SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX,
> SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE,
> SMB_ADDR_MAX, NOT_EXIST  , DISABLE, VPP_PORT_MAX,
> SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_2A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_4A_INDEX, 2         , DISABLE, 0          , 20=
0        ,
> DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE,
> SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2        , 4           , ENABLE=
 ,
> VPP_PORT_0  , 0x76        , ENABLE , SMB_ADDR_MAX, NOT_EXIST  , ENABLE ,
> VPP_PORT_0  , 0x40        , 0x1     },
> -  { SOCKET_0_INDEX + PORT_4B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, 0xe2        , 4           , ENABLE , VPP_PORT_0  , 0x76       =
 , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_1  , 0x40        , 0x1     }=
,
> -  { SOCKET_0_INDEX + PORT_4C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, 0xe2        , 4           , ENABLE , VPP_PORT_0  , 0x76       =
 , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_0  , 0x42        , 0x1     }=
,
> -  { SOCKET_0_INDEX + PORT_4D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, 0xe2        , 4           , ENABLE , VPP_PORT_0  , 0x76       =
 , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_1  , 0x42        , 0x1     }=
,
> -  { SOCKET_0_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_0_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  // Port Index                   | Slot      |Inter   |Power       |Pow=
er       |Hotplug |Vpp
> Port     |Vpp Addr     |PCIeSSD |PCIeSSD      |PCIeSSD      |Hidden   |Co=
mmon  |
> SRIS  |Uplink  |Retimer |Retimer      |Retimer      |Retimer   |Mux      =
    |Mux
> |ExtnCard|ExtnCard     |ExtnCard     |ExtnCard|Ex.C. Retimer|Ex.C. Ret-
> |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max    |
> -  //                              |           |lock    |Limit Scale |Lim=
it Value |Cap     |             |
> |Cap     |Port         |Address      |         |Clock   |        |Port   =
 |        |Address
> |Channel      |Width     |Address      |Channel      |Support |SMBus Port
> |SMBus Addr   |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port
> |Vpp Address  |Retimer|
> -  { SOCKET_1_INDEX + PORT_1A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_2A_INDEX, 6         , DISABLE, 0          , 75=
         ,
> DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE,
> SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX,
> SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE,
> SMB_ADDR_MAX, NOT_EXIST  , DISABLE, VPP_PORT_MAX,
> SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_4A_INDEX, 10        , DISABLE, 0          , 25=
         ,
> ENABLE , VPP_PORT_0  , 0x4C        , DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26        ,
> 2           , 16       , 0xe2        , SMB_DATA_MAX, DISABLE, VPP_PORT_MA=
X,
> SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST  , DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, 0x1     },
> -  { SOCKET_1_INDEX + PORT_4B_INDEX, 11        , DISABLE, 0          , 25=
         ,
> ENABLE , VPP_PORT_1  , 0x4C        , DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26        ,
> 2           , 16       , 0xe2        , SMB_DATA_MAX, DISABLE, VPP_PORT_MA=
X,
> SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST  , DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, 0x1     },
> -  { SOCKET_1_INDEX + PORT_4C_INDEX, 12        , DISABLE, 0          , 25=
         ,
> ENABLE , VPP_PORT_0  , 0x4E        , DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26        ,
> 2           , 16       , 0xe2        , SMB_DATA_MAX, DISABLE, VPP_PORT_MA=
X,
> SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST  , DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, 0x1     },
> -  { SOCKET_1_INDEX + PORT_4D_INDEX, 13        , DISABLE, 0          , 25=
         ,
> ENABLE , VPP_PORT_1  , 0x4E        , DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26        ,
> 2           , 16       , 0xe2        , SMB_DATA_MAX, DISABLE, VPP_PORT_MA=
X,
> SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST  , DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, 0x1     },
> -  { SOCKET_1_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_1_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  // Port Index                   | Slot      |Inter   |Power       |Pow=
er       |Hotplug |Vpp
> Port     |Vpp Addr     |PCIeSSD |PCIeSSD      |PCIeSSD      |Hidden   |Co=
mmon  |
> SRIS  |Uplink  |Retimer |Retimer      |Retimer      |Retimer   |Mux      =
    |Mux
> |ExtnCard|ExtnCard     |ExtnCard     |ExtnCard|Ex.C. Retimer|Ex.C. Ret-
> |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max    |
> -  //                              |           |lock    |Limit Scale |Lim=
it Value |Cap     |             |
> |Cap     |Port         |Address      |         |Clock   |        |Port   =
 |        |Address
> |Channel      |Width     |Address      |Channel      |Support |SMBus Port
> |SMBus Addr   |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port
> |Vpp Address  |Retimer|
> -  { SOCKET_2_INDEX + PORT_1A_INDEX, 9         , DISABLE, 0          , 25=
         ,
> DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE,
> SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2        , 4           , ENABLE=
 ,
> VPP_PORT_0  , 0x7C        , ENABLE , SMB_ADDR_MAX, NOT_EXIST  , ENABLE ,
> VPP_PORT_0  , 0x44        , 0x1     },
> -  { SOCKET_2_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, 0xe2        , 4           , ENABLE , VPP_PORT_0  , 0x7C       =
 , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_1  , 0x44        , 0x1     }=
,
> -  { SOCKET_2_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, 0xe2        , 4           , ENABLE , VPP_PORT_0  , 0x7C       =
 , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_0  , 0x46        , 0x1     }=
,
> -  { SOCKET_2_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, 0xe2        , 4           , ENABLE , VPP_PORT_0  , 0x7C       =
 , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_1  , 0x46        , 0x1     }=
,
> -  { SOCKET_2_INDEX + PORT_2A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_4A_INDEX, 8         , DISABLE, 0          , 25=
         ,
> DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE,
> SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX,
> SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE,
> SMB_ADDR_MAX, NOT_EXIST  , DISABLE, VPP_PORT_MAX,
> SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_4B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_4C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_4D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_2_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  // Port Index                   | Slot      |Inter   |Power       |Pow=
er       |Hotplug |Vpp
> Port     |Vpp Addr     |PCIeSSD |PCIeSSD      |PCIeSSD      |Hidden   |Co=
mmon  |
> SRIS  |Uplink  |Retimer |Retimer      |Retimer      |Retimer   |Mux      =
    |Mux
> |ExtnCard|ExtnCard     |ExtnCard     |ExtnCard|Ex.C. Retimer|Ex.C. Ret-
> |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max    |
> -  //                              |           |lock    |Limit Scale |Lim=
it Value |Cap     |             |
> |Cap     |Port         |Address      |         |Clock   |        |Port   =
 |        |Address
> |Channel      |Width     |Address      |Channel      |Support |SMBus Port
> |SMBus Addr   |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port
> |Vpp Address  |Retimer|
> -  { SOCKET_3_INDEX + PORT_1A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_2A_INDEX, 4         , DISABLE, 0          , 25=
         ,
> ENABLE , VPP_PORT_0  , 0x4A        , DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE,
> SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2        , 4           , ENABLE=
 ,
> VPP_PORT_0  , 0x70        , ENABLE , SMB_ADDR_MAX, NOT_EXIST  , ENABLE ,
> VPP_PORT_0  , 0x40        , 0x1     },
> -  { SOCKET_3_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, ENABLE , VPP_PORT_0  , 0x4A        ,
> DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE,
> DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2
> , 4           , ENABLE , VPP_PORT_0  , 0x70        , ENABLE , SMB_ADDR_MA=
X,
> NOT_EXIST  , ENABLE , VPP_PORT_1  , 0x40        , 0x1     },
> -  { SOCKET_3_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, ENABLE , VPP_PORT_0  , 0x4A        ,
> DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE,
> DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2
> , 4           , ENABLE , VPP_PORT_0  , 0x70        , ENABLE , SMB_ADDR_MA=
X,
> NOT_EXIST  , ENABLE , VPP_PORT_0  , 0x42        , 0x1     },
> -  { SOCKET_3_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, ENABLE , VPP_PORT_0  , 0x4A        ,
> DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE,
> DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2
> , 4           , ENABLE , VPP_PORT_0  , 0x70        , ENABLE , SMB_ADDR_MA=
X,
> NOT_EXIST  , ENABLE , VPP_PORT_1  , 0x42        , 0x1     },
> -  { SOCKET_3_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_4A_INDEX, 14        , DISABLE, 0          , 25=
         ,
> ENABLE , VPP_PORT_0  , 0x4C        , DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20        ,
> 2           , 16       , 0xe2        , 4           , ENABLE , VPP_PORT_0 =
 , 0x74        , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_0  , 0x40        , 0x1     }=
,
> -  { SOCKET_3_INDEX + PORT_4B_INDEX, 15        , DISABLE, 0          , 25=
         ,
> ENABLE , VPP_PORT_1  , 0x4C        , DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20        ,
> 2           , 16       , 0xe2        , 4           , ENABLE , VPP_PORT_0 =
 , 0x74        , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_1  , 0x40        , 0x1     }=
,
> -  { SOCKET_3_INDEX + PORT_4C_INDEX, 16        , DISABLE, 0          , 25=
         ,
> ENABLE , VPP_PORT_0  , 0x4E        , DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20        ,
> 2           , 16       , 0xe2        , 4           , ENABLE , VPP_PORT_0 =
 , 0x74        , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_0  , 0x42        , 0x1     }=
,
> -  { SOCKET_3_INDEX + PORT_4D_INDEX, 17        , DISABLE, 0          , 25=
         ,
> ENABLE , VPP_PORT_1  , 0x4E        , DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20        ,
> 2           , 16       , 0xe2        , 4           , ENABLE , VPP_PORT_0 =
 , 0x74        , ENABLE ,
> SMB_ADDR_MAX, NOT_EXIST  , ENABLE , VPP_PORT_1  , 0x42        , 0x1     }=
,
> -  { SOCKET_3_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     },
> -  { SOCKET_3_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE,
> PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX,
> VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE,
> ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX,
> NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE,
> VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST
> , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0     }
> -  // Port Index                   | Slot      |Inter   |Power       |Pow=
er       |Hotplug |Vpp
> Port     |Vpp Addr     |PCIeSSD |PCIeSSD      |PCIeSSD      |Hidden   |Co=
mmon  |
> SRIS  |Uplink  |Retimer |Retimer      |Retimer      |Retimer   |Mux      =
    |Mux
> |ExtnCard|ExtnCard     |ExtnCard     |ExtnCard|Ex.C. Retimer|Ex.C. Ret-
> |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max    |
> -  //                              |           |lock    |Limit Scale |Lim=
it Value |Cap     |             |
> |Cap     |Port         |Address      |         |Clock   |        |Port   =
 |        |Address
> |Channel      |Width     |Address      |Channel      |Support |SMBus Port
> |SMBus Addr   |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port
> |Vpp Address  |Retimer|
> -};
> -
> -
>  EFI_STATUS
>  UpdateWilsonCityRPIioConfig (
>    IN  IIO_GLOBALS             *IioGlobalData
> @@ -297,18 +168,6 @@ PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX
> TypeWilsonCityRPIioConfigTable =3D
>    sizeof(IioSlotTable)
>  };
>=20
> -PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX
> TypeWilsonCityRPIioConfigTable_CPX =3D
> -{
> -  PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
> -  PLATFORM_IIO_CONFIG_UPDATE_VERSION_2,
> -
> -  IioBifurcationTable_CPX,
> -  sizeof(IioBifurcationTable_CPX),
> -  UpdateWilsonCityRPIioConfig,
> -  IioSlotTable_CPX,
> -  sizeof(IioSlotTable_CPX)
> -};
> -
>  /**
>    Entry point function for the PEIM
>=20
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/P
> ei/KtiEparam.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/P
> ei/KtiEparam.c
> index dd67a65a54..63a0111750 100644
> ---
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/P
> ei/KtiEparam.c
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/P
> ei/KtiEparam.c
> @@ -41,45 +41,6 @@ PLATFORM_KTI_EPARAM_UPDATE_TABLE
> TypeWilsonCityRPIcxKtiEparamUpdate =3D {
>  };
>=20
>=20
> -ALL_LANES_EPARAM_LINK_INFO
> KtiWilsonCityRPCpxAllLanesEparamTable[] =3D {
> -  //
> -  // SocketID, Freq, Link, TXEQL, CTLEPEAK
> -  //
> -  //
> -  // Socket 0
> -  //
> -  {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE},
> -  {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK5), 0x2F39353F, ADAPTIVE_CTLE},
> -  //
> -  // Socket 1
> -  //
> -  {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE},
> -  {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK5), 0x2F3A343F, ADAPTIVE_CTLE},
> -
> -  //
> -  // Socket 2
> -  //
> -  {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE},
> -  {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK5), 0x2F39353F, ADAPTIVE_CTLE},
> -
> -  //
> -  // Socket 3
> -  //
> -  {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE},
> -  {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK5), 0x2F3A343F, ADAPTIVE_CTLE}
> -};
> -
> -PLATFORM_KTI_EPARAM_UPDATE_TABLE
> TypeWilsonCityRPCpxKtiEparamUpdate =3D
> -{
> -  PLATFORM_KTIEP_UPDATE_SIGNATURE,
> -  PLATFORM_KTIEP_UPDATE_VERSION,
> -  KtiWilsonCityRPCpxAllLanesEparamTable,
> -  sizeof (KtiWilsonCityRPCpxAllLanesEparamTable),
> -  NULL,
> -  0
> -};
> -
> -
>  EFI_STATUS
>  TypeWilsonCityRPInstallKtiEparamData (
>    IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
> new file mode 100644
> index 0000000000..fea80ce49e
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
> @@ -0,0 +1,99 @@
> +/** @file
> +  IIO Config Update.
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "IioCfgUpdateDxe.h"
> +
> +EFI_STATUS
> +UpdateWilsonCitySMTIioConfig (
> +  IN  IIO_GLOBALS             *IioGlobalData
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +PLATFORM_IIO_CONFIG_UPDATE_TABLE
> TypeWilsonCitySMTIioConfigTable =3D
> +{
> +  PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
> +  PLATFORM_IIO_CONFIG_UPDATE_VERSION,
> +
> +  IioBifurcationTable,
> +  sizeof(IioBifurcationTable),
> +  UpdateWilsonCitySMTIioConfig,
> +  IioSlotTable,
> +  sizeof(IioSlotTable)
> +
> +};
> +
> +/**
> +  The Driver Entry Point.
> +
> +  The function is the driver Entry point.
> +
> +  @param ImageHandle   A handle for the image that is initializing this =
driver
> +  @param SystemTable   A pointer to the EFI system table
> +
> +  @retval EFI_SUCCESS:              Driver initialized successfully
> +  @retval EFI_LOAD_ERROR:           Failed to Initialize or has been loa=
ded
> +  @retval EFI_OUT_OF_RESOURCES      Could not allocate needed resources
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +IioCfgUpdateEntry (
> +  IN EFI_HANDLE                            ImageHandle,
> +  IN EFI_SYSTEM_TABLE                      *SystemTable
> +)
> +{
> +  EFI_STATUS                               Status;
> +  UBA_CONFIG_DATABASE_PROTOCOL             *UbaConfigProtocol =3D NULL;
> +
> +  DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeWilsonCitySMT\n"));
> +  Status =3D gBS->LocateProtocol (
> +                  &gUbaConfigDatabaseProtocolGuid,
> +                  NULL,
> +                  &UbaConfigProtocol
> +                  );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigProtocol->AddData (
> +                                     UbaConfigProtocol,
> +                                     &gPlatformIioConfigDataDxeGuid,
> +                                     &TypeWilsonCitySMTIioConfigTable,
> +                                     sizeof(TypeWilsonCitySMTIioConfigTa=
ble)
> +                                     );
> +
> +  Status =3D UbaConfigProtocol->AddData (
> +                                     UbaConfigProtocol,
> +                                     &gPlatformIioConfigDataDxeGuid_1,
> +                                     &TypeWilsonCitySMTIioConfigTable,
> +                                     sizeof(TypeWilsonCitySMTIioConfigTa=
ble)
> +                                     );
> +
> +  Status =3D UbaConfigProtocol->AddData (
> +                                     UbaConfigProtocol,
> +                                     &gPlatformIioConfigDataDxeGuid_2,
> +                                     &TypeWilsonCitySMTIioConfigTable,
> +                                     sizeof(TypeWilsonCitySMTIioConfigTa=
ble)
> +                                     );
> +
> +  Status =3D UbaConfigProtocol->AddData (
> +                                     UbaConfigProtocol,
> +                                     &gPlatformIioConfigDataDxeGuid_3,
> +                                     &TypeWilsonCitySMTIioConfigTable,
> +                                     sizeof(TypeWilsonCitySMTIioConfigTa=
ble)
> +                                     );
> +
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  return Status;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
> new file mode 100644
> index 0000000000..662fa2c650
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
> @@ -0,0 +1,118 @@
> +/** @file
> +
> +  @copyright
> +  Copyright 2016 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _IIOCFG_UPDATE_DXE_H_
> +#define _IIOCFG_UPDATE_DXE_H_
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +#include <Protocol/UbaCfgDb.h>
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PciLib.h>
> +#include <Library/UbaIioConfigLib.h>
> +#include <IioPlatformData.h>
> +
> +typedef enum {
> +  Iio_Socket0 =3D 0,
> +  Iio_Socket1,
> +  Iio_Socket2,
> +  Iio_Socket3,
> +  Iio_Socket4,
> +  Iio_Socket5,
> +  Iio_Socket6,
> +  Iio_Socket7
> +} IIO_SOCKETS;
> +
> +typedef enum {
> +  Iio_Iou0 =3D0,
> +  Iio_Iou1,
> +  Iio_Iou2,
> +  Iio_Mcp0,
> +  Iio_Mcp1,
> +  Iio_IouMax
> +} IIO_IOUS;
> +
> +typedef enum {
> +  VPP_PORT_0 =3D 0,
> +  VPP_PORT_1,
> +  VPP_PORT_2,
> +  VPP_PORT_3
> +} VPP_PORT;
> +
> +#define ENABLE            1
> +#define DISABLE           0
> +#define NO_SLT_IMP        0xFF
> +#define SLT_IMP           1
> +#define HIDE              1
> +#define NOT_HIDE          0
> +#define VPP_PORT_0        0
> +#define VPP_PORT_1        1
> +#define VPP_PORT_MAX      0xFF
> +#define VPP_ADDR_MAX      0xFF
> +#define PWR_VAL_MAX       0xFF
> +#define PWR_SCL_MAX       0xFF
> +
> +static IIO_BIFURCATION_DATA_ENTRY   IioBifurcationTable[] =3D
> +{
> +  // Neon City IIO bifurcation table (Based on Neon City Block Diagram r=
ev
> 0.6)
> +  { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 },
> +  { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
> +  { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
> +  { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
> +  { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
> +  { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 },
> +  { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
> +  { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 },
> +  { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
> +  { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
> +};
> +
> +static IIO_SLOT_CONFIG_DATA_ENTRY   IioSlotTable[] =3D {
> +  // Port        |  Slot      | Inter      | Power Limit | Power Limit |=
 Hot     | Vpp
> | Vpp          | PcieSSD | PcieSSD     | PcieSSD       | Hidden
> +  // Index       |            | lock       | Scale       |  Value      |=
 Plug    | Port         | Addr
> | Cap     | VppPort     | VppAddr       |
> +  { PORT_1A_INDEX, NO_SLT_IMP , DISABLE    , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_0  , 0x4C          , HIDE    },//Oculink
> +  { PORT_1B_INDEX, NO_SLT_IMP , DISABLE    , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_1  , 0x4C          , HIDE    },//Oculink
> +  { PORT_1C_INDEX,  1         , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX ,
> DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX ,
> VPP_ADDR_MAX , NOT_HIDE },
> +  { PORT_2A_INDEX, NO_SLT_IMP , DISABLE    , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
> +  // Slot 2 supports HP:  PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P =
118
> (MRL in J65)
> +  { PORT_3A_INDEX,  2         , ENABLE     , PWR_SCL_MAX , PWR_VAL_MAX ,
> ENABLE  , VPP_PORT_0   , 0x40         , ENABLE  , VPP_PORT_0    , 0x40   =
      ,
> NOT_HIDE },
> +  { PORT_3B_INDEX, NO_SLT_IMP , DISABLE    , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_1    , 0x40         , HIDE    },
> +  { PORT_3C_INDEX, NO_SLT_IMP , DISABLE    , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_0    , 0x42         , HIDE    },
> +  { PORT_3D_INDEX, NO_SLT_IMP , DISABLE    , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_1    , 0x42         , HIDE    },
> +  { SOCKET_1_INDEX +
> +    PORT_0_INDEX ,   6        , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX ,
> DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX ,
> VPP_ADDR_MAX , NOT_HIDE },
> +  // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P =
121
> (MRL in J287)
> +  { SOCKET_1_INDEX +
> +    PORT_1A_INDEX,   4        , ENABLE     , PWR_SCL_MAX , PWR_VAL_MAX ,
> ENABLE  , VPP_PORT_1   , 0x40         , ENABLE  , VPP_PORT_0    , 0x40   =
      ,
> NOT_HIDE },
> +  { SOCKET_1_INDEX +
> +    PORT_1B_INDEX, NO_SLT_IMP , ENABLE     , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_1    , 0x40         , HIDE    },
> +  { SOCKET_1_INDEX +
> +    PORT_1C_INDEX, NO_SLT_IMP , ENABLE     , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_0    , 0x42         , HIDE    },
> +  { SOCKET_1_INDEX +
> +    PORT_1D_INDEX, NO_SLT_IMP , ENABLE     , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_1    , 0x42         , HIDE    },
> +  { SOCKET_1_INDEX +
> +    PORT_2A_INDEX,  8         , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX ,
> DISABLE , VPP_PORT_1   , VPP_ADDR_MAX , ENABLE  , VPP_PORT_0    , 0x44
> , NOT_HIDE },
> +  { SOCKET_1_INDEX +
> +    PORT_2B_INDEX, NO_SLT_IMP , DISABLE    , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_1    , 0x44         , HIDE    },
> +  { SOCKET_1_INDEX +
> +    PORT_2C_INDEX, NO_SLT_IMP , DISABLE    , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_0    , 0x46         , HIDE    },
> +  { SOCKET_1_INDEX +
> +    PORT_2D_INDEX, NO_SLT_IMP , DISABLE    , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE  ,
> VPP_PORT_1    , 0x46         , HIDE    },
> +  { SOCKET_1_INDEX +
> +    PORT_3A_INDEX,  5         , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX ,
> DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX ,
> VPP_ADDR_MAX , NOT_HIDE },
> +  { SOCKET_1_INDEX +
> +    PORT_3C_INDEX,  7         , DISABLE    , PWR_SCL_MAX , PWR_VAL_MAX ,
> DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX ,
> VPP_ADDR_MAX , NOT_HIDE },
> +  // Note: On Neon  City, Slot 3 is assigned to PCH's PCIE port
> +};
> +
> +#endif   //_IIOCFG_UPDATE_DXE_H_
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
> new file mode 100644
> index 0000000000..b34810f76c
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
> @@ -0,0 +1,48 @@
> +## @file
> +#
> +# @copyright
> +# Copyright 2019 Intel Corporation. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +[defines]
> +  INF_VERSION                    =3D 0x00010005
> +  BASE_NAME                      =3D IioCfgUpdateDxeWilsonCitySMT
> +  FILE_GUID                      =3D 7934B6C8-4090-C8BD-48F5-3C8F1F0E84D=
A
> +  MODULE_TYPE                    =3D DXE_DRIVER
> +  VERSION_STRING                 =3D 1.0
> +  ENTRY_POINT                    =3D IioCfgUpdateEntry
> +
> +[Sources]
> +  IioCfgUpdateDxe.c
> +  IioCfgUpdateDxe.h
> +
> +[LibraryClasses]
> +  BaseLib
> +  BaseMemoryLib
> +  MemoryAllocationLib
> +  DebugLib
> +  UefiBootServicesTableLib
> +  UefiDriverEntryPoint
> +  UefiRuntimeServicesTableLib
> +  UefiLib
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  WhitleySiliconPkg/WhitleySiliconPkg.dec
> +  WhitleySiliconPkg/CpRcPkg.dec
> +  WhitleySiliconPkg/SiliconPkg.dec
> +  WhitleyOpenBoardPkg/PlatformPkg.dec
> +
> +[Guids]
> +
> +[FixedPcd]
> +  gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
> +
> +[Protocols]
> +  gUbaConfigDatabaseProtocolGuid
> +
> +[Depex]
> +  gEfiPlatformTypeWilsonCitySMTProtocolGuid
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
> new file mode 100644
> index 0000000000..bdedb48316
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
> @@ -0,0 +1,115 @@
> +/** @file
> +  Slot Data Update.
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "SlotDataUpdateDxe.h"
> +
> +UINT8
> +GetTypeWilsonCitySMTIOU0Setting (
> +  UINT8  IOU0Data
> +)
> +{
> +  //
> +  // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
> +  //
> +  IOU0Data =3D IIO_BIFURCATE_xxx8xxx8;
> +  return IOU0Data;
> +}
> +
> +UINT8
> +GetTypeWilsonCitySMTIOU2Setting (
> +  UINT8  SkuPersonalityType,
> +  UINT8  IOU2Data
> +)
> +{
> +  return IOU2Data;
> +}
> +
> +static IIO_BROADWAY_ADDRESS_DATA_ENTRY
> SlotTypeWilsonCitySMTBroadwayTable[] =3D {
> +    {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
> +    {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
> +    {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
> +};
> +
> +
> +PLATFORM_SLOT_UPDATE_TABLE  TypeWilsonCitySMTSlotTable =3D
> +{
> +  PLATFORM_SLOT_UPDATE_SIGNATURE,
> +  PLATFORM_SLOT_UPDATE_VERSION,
> +
> +  SlotTypeWilsonCitySMTBroadwayTable,
> +  GetTypeWilsonCitySMTIOU0Setting,
> +  0
> +};
> +
> +PLATFORM_SLOT_UPDATE_TABLE2  TypeWilsonCitySMTSlotTable2 =3D
> +{
> +  PLATFORM_SLOT_UPDATE_SIGNATURE,
> +  PLATFORM_SLOT_UPDATE_VERSION,
> +
> +  SlotTypeWilsonCitySMTBroadwayTable,
> +  GetTypeWilsonCitySMTIOU0Setting,
> +  0,
> +  GetTypeWilsonCitySMTIOU2Setting
> +};
> +
> +/**
> +  The Driver Entry Point.
> +
> +  The function is the driver Entry point.
> +
> +  @param ImageHandle   A handle for the image that is initializing this =
driver
> +  @param SystemTable   A pointer to the EFI system table
> +
> +  @retval EFI_SUCCESS:              Driver initialized successfully
> +  @retval EFI_LOAD_ERROR:           Failed to Initialize or has been loa=
ded
> +  @retval EFI_OUT_OF_RESOURCES      Could not allocate needed resources
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SlotDataUpdateEntry (
> +  IN EFI_HANDLE                            ImageHandle,
> +  IN EFI_SYSTEM_TABLE                      *SystemTable
> +)
> +{
> +  EFI_STATUS                               Status;
> +  UBA_CONFIG_DATABASE_PROTOCOL             *UbaConfigProtocol =3D NULL;
> +
> +  DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeWilsonCitySMT\n"));
> +  Status =3D gBS->LocateProtocol (
> +                  &gUbaConfigDatabaseProtocolGuid,
> +                  NULL,
> +                  &UbaConfigProtocol
> +                  );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigProtocol->AddData (
> +                                     UbaConfigProtocol,
> +                                     &gPlatformSlotDataDxeGuid,
> +                                     &TypeWilsonCitySMTSlotTable,
> +                                     sizeof(TypeWilsonCitySMTSlotTable)
> +                                     );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigProtocol->AddData (
> +                                     UbaConfigProtocol,
> +                                     &gPlatformSlotDataDxeGuid,
> +                                     &TypeWilsonCitySMTSlotTable2,
> +                                     sizeof(TypeWilsonCitySMTSlotTable2)
> +                                     );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  return Status;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
> new file mode 100644
> index 0000000000..9be882b09e
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
> @@ -0,0 +1,57 @@
> +/** @file
> +
> +  @copyright
> +  Copyright 2016 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SLOT_DATA_UPDATE_DXE_H_
> +#define _SLOT_DATA_UPDATE_DXE_H_
> +
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +
> +#include <Protocol/UbaCfgDb.h>
> +
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PciLib.h>
> +
> +#include <Library/UbaSlotUpdateLib.h>
> +#include <IioPlatformData.h>
> +
> +typedef enum {
> +  Iio_Socket0 =3D 0,
> +  Iio_Socket1,
> +  Iio_Socket2,
> +  Iio_Socket3,
> +  Iio_Socket4,
> +  Iio_Socket5,
> +  Iio_Socket6,
> +  Iio_Socket7
> +} IIO_SOCKETS;
> +
> +typedef enum {
> +  Iio_Iou0 =3D0,
> +  Iio_Iou1,
> +  Iio_Iou2,
> +  Iio_Mcp0,
> +  Iio_Mcp1,
> +  Iio_IouMax
> +} IIO_IOUS;
> +
> +typedef enum {
> +  Bw5_Addr_0 =3D 0,
> +  Bw5_Addr_1,
> +  Bw5_Addr_2,
> +  Bw5_Addr_3,
> +  Bw5_Addr_Max
> +} BW5_ADDRESS;
> +
> +#endif   //_SLOT_DATA_UPDATE_DXE_H_
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
> new file mode 100644
> index 0000000000..31c9eea5e3
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
> @@ -0,0 +1,48 @@
> +## @file
> +#
> +# @copyright
> +# Copyright 2018 - 2021 Intel Corporation. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +[defines]
> +  INF_VERSION                    =3D 0x00010005
> +  BASE_NAME                      =3D SlotDataUpdateDxeWilsonCitySMT
> +  FILE_GUID                      =3D BBDB00BE-4C5C-7AD3-D34A-7A979492840=
D
> +  MODULE_TYPE                    =3D DXE_DRIVER
> +  VERSION_STRING                 =3D 1.0
> +  ENTRY_POINT                    =3D SlotDataUpdateEntry
> +
> +[Sources]
> +  SlotDataUpdateDxe.c
> +  SlotDataUpdateDxe.h
> +
> +[LibraryClasses]
> +  BaseLib
> +  BaseMemoryLib
> +  MemoryAllocationLib
> +  DebugLib
> +  UefiBootServicesTableLib
> +  UefiDriverEntryPoint
> +  UefiRuntimeServicesTableLib
> +  UefiLib
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  WhitleySiliconPkg/WhitleySiliconPkg.dec
> +  WhitleySiliconPkg/CpRcPkg.dec
> +  WhitleySiliconPkg/SiliconPkg.dec
> +  WhitleyOpenBoardPkg/PlatformPkg.dec
> +
> +[Guids]
> +
> +[FixedPcd]
> +  gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
> +
> +[Protocols]
> +  gUbaConfigDatabaseProtocolGuid
> +
> +[Depex]
> +  gEfiPlatformTypeWilsonCitySMTProtocolGuid
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
> new file mode 100644
> index 0000000000..769003d2be
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
> @@ -0,0 +1,127 @@
> +/** @file
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "UsbOcUpdateDxe.h"
> +
> +#include <Library/UbaUsbOcUpdateLib.h>
> +#include <PchLimits.h>
> +#include <ConfigBlock/UsbConfig.h>
> +#include <ConfigBlock/Usb2PhyConfig.h>
> +
> +USB_OVERCURRENT_PIN
> TypeWilsonCitySMTUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] =3D
> {
> +                          UsbOverCurrentPinSkip,   //Port00: BMC
> +                          UsbOverCurrentPinSkip,   //Port01: BMC
> +                          UsbOverCurrentPin0,      //Port02: Rear Panel
> +                          UsbOverCurrentPin1,      //Port03: Rear Panel
> +                          UsbOverCurrentPin1,      //Port04: Rear Panel
> +                          UsbOverCurrentPinSkip,   //Port05: NC
> +                          UsbOverCurrentPinSkip,   //Port06: NC
> +                          UsbOverCurrentPin4,      //Port07: Type A inte=
rnal
> +                          UsbOverCurrentPinSkip,   //Port08: NC
> +                          UsbOverCurrentPinSkip,   //Port09: NC
> +                          UsbOverCurrentPin6,      //Port10: Front Panel
> +                          UsbOverCurrentPinSkip,   //Port11: NC
> +                          UsbOverCurrentPin6,      //Port12: Front Panel
> +                          UsbOverCurrentPinSkip,   //Port13: NC
> +                          UsbOverCurrentPinSkip,
> +                          UsbOverCurrentPinSkip
> +                       };
> +
> +USB_OVERCURRENT_PIN
> TypeWilsonCitySMTUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] =3D
> {
> +                          UsbOverCurrentPin6,    //Port01: Front Panel
> +                          UsbOverCurrentPin6,    //Port02: Front Panel
> +                          UsbOverCurrentPin0,    //Port03: Rear Panel
> +                          UsbOverCurrentPin1,    //Port04: Rear Panel
> +                          UsbOverCurrentPin1,    //Port05: Rear Panel
> +                          UsbOverCurrentPinSkip, //Port06: NC
> +                          UsbOverCurrentPinSkip,
> +                          UsbOverCurrentPinSkip,
> +                          UsbOverCurrentPinSkip,
> +                          UsbOverCurrentPinSkip
> +                       };
> +
> +USB2_PHY_PARAMETERS
> TypeWilsonCitySMTUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_P
> ORTS] =3D {
> +                        {3, 0, 3, 1},   // PP0
> +                        {5, 0, 3, 1},   // PP1
> +                        {3, 0, 3, 1},   // PP2
> +                        {0, 5, 1, 1},   // PP3
> +                        {3, 0, 3, 1},   // PP4
> +                        {3, 0, 3, 1},   // PP5
> +                        {3, 0, 3, 1},   // PP6
> +                        {3, 0, 3, 1},   // PP7
> +                        {2, 2, 1, 0},   // PP8
> +                        {6, 0, 2, 1},   // PP9
> +                        {2, 2, 1, 0},   // PP10
> +                        {6, 0, 2, 1},   // PP11
> +                        {0, 5, 1, 1},   // PP12
> +                        {7, 0, 2, 1},   // PP13
> +                      };
> +
> +EFI_STATUS
> +TypeWilsonCitySMTPlatformUsbOcUpdateCallback (
> +  IN OUT   USB_OVERCURRENT_PIN   **Usb20OverCurrentMappings,
> +  IN OUT   USB_OVERCURRENT_PIN   **Usb30OverCurrentMappings,
> +  IN OUT   USB2_PHY_PARAMETERS        **Usb20AfeParams
> +)
> +{
> +  *Usb20OverCurrentMappings   =3D
> &TypeWilsonCitySMTUsb20OverCurrentMappings[0];
> +  *Usb30OverCurrentMappings   =3D
> &TypeWilsonCitySMTUsb30OverCurrentMappings[0];
> +
> +  *Usb20AfeParams   =3D TypeWilsonCitySMTUsb20AfeParams;
> +  return EFI_SUCCESS;
> +}
> +
> +PLATFORM_USBOC_UPDATE_TABLE  TypeWilsonCitySMTUsbOcUpdate =3D
> +{
> +   PLATFORM_USBOC_UPDATE_SIGNATURE,
> +   PLATFORM_USBOC_UPDATE_VERSION,
> +   TypeWilsonCitySMTPlatformUsbOcUpdateCallback
> +};
> +
> +/**
> +  The Driver Entry Point.
> +
> +  The function is the driver Entry point.
> +
> +  @param ImageHandle   A handle for the image that is initializing this =
driver
> +  @param SystemTable   A pointer to the EFI system table
> +
> +  @retval EFI_SUCCESS:              Driver initialized successfully
> +  @retval EFI_LOAD_ERROR:           Failed to Initialize or has been loa=
ded
> +  @retval EFI_OUT_OF_RESOURCES      Could not allocate needed resources
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +UsbOcUpdateEntry (
> +  IN EFI_HANDLE                            ImageHandle,
> +  IN EFI_SYSTEM_TABLE                      *SystemTable
> +)
> +{
> +  EFI_STATUS                          Status;
> +  UBA_CONFIG_DATABASE_PROTOCOL        *UbaConfigProtocol =3D NULL;
> +
> +  DEBUG((DEBUG_INFO, "UBA:UsbOcUpdate-TypeWilsonCitySMT\n"));
> +  Status =3D gBS->LocateProtocol (
> +                  &gUbaConfigDatabaseProtocolGuid,
> +                  NULL,
> +                  &UbaConfigProtocol
> +                  );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigProtocol->AddData (
> +                                     UbaConfigProtocol,
> +                                     &gDxePlatformUbaOcConfigDataGuid,
> +                                     &TypeWilsonCitySMTUsbOcUpdate,
> +                                     sizeof(TypeWilsonCitySMTUsbOcUpdate=
)
> +                                     );
> +
> +  return Status;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
> new file mode 100644
> index 0000000000..3813eadae9
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
> @@ -0,0 +1,27 @@
> +/** @file
> +
> +  @copyright
> +  Copyright 2015 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _USBOC_UPDATE_DXE_H_
> +#define _USBOC_UPDATE_DXE_H_
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +
> +#include <Protocol/UbaCfgDb.h>
> +
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +
> +
> +
> +#endif  //_USBOC_UPDATE_DXE_H_
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
> new file mode 100644
> index 0000000000..ef80d3ec56
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
> @@ -0,0 +1,44 @@
> +## @file
> +#
> +# @copyright
> +# Copyright 2018 - 2021 Intel Corporation. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +[defines]
> +  INF_VERSION                    =3D 0x00010005
> +  BASE_NAME                      =3D UsbOcUpdateDxeWilsonCitySMT
> +  FILE_GUID                      =3D 5861D662-4CE8-F72D-B0E4-258B859BF9F=
5
> +  MODULE_TYPE                    =3D DXE_DRIVER
> +  VERSION_STRING                 =3D 1.0
> +  ENTRY_POINT                    =3D UsbOcUpdateEntry
> +
> +[sources]
> +  UsbOcUpdateDxe.c
> +  UsbOcUpdateDxe.h
> +
> +[LibraryClasses]
> +  BaseLib
> +  BaseMemoryLib
> +  MemoryAllocationLib
> +  DebugLib
> +  UefiBootServicesTableLib
> +  UefiDriverEntryPoint
> +  UefiRuntimeServicesTableLib
> +  UefiLib
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  WhitleySiliconPkg/WhitleySiliconPkg.dec
> +  WhitleySiliconPkg/SiliconPkg.dec
> +  WhitleyOpenBoardPkg/PlatformPkg.dec
> +
> +[Guids]
> +
> +[Protocols]
> +  gUbaConfigDatabaseProtocolGuid
> +
> +[Depex]
> +  gEfiPlatformTypeWilsonCitySMTProtocolGuid
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/AcpiTablePcds.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/AcpiTablePcds.c
> new file mode 100644
> index 0000000000..437cb211b6
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/AcpiTablePcds.c
> @@ -0,0 +1,51 @@
> +/** @file
> +  ACPI table pcds update.
> +
> +  @copyright
> +  Copyright 2015 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiBoardInit.h"
> +#include <Library/PcdLib.h>
> +#include <Library/HobLib.h>
> +#include <Guid/PlatformInfo.h>
> +#include <UncoreCommonIncludes.h>
> +#include <Cpu/CpuIds.h>
> +
> +EFI_STATUS
> +TypeWilsonCitySMTPlatformUpdateAcpiTablePcds (
> +  VOID
> +  )
> +{
> +  CHAR8     AcpiName10nm[]    =3D "EPRP10NM";     // USED for identify A=
CPI
> table for 10nm in systmeboard dxe driver
> +  CHAR8     OemTableIdXhci[]  =3D "xh_nccrb";
> +
> +  UINTN     Size;
> +  EFI_STATUS Status;
> +
> +  EFI_HOB_GUID_TYPE                     *GuidHob;
> +  EFI_PLATFORM_INFO                     *PlatformInfo;
> +
> +  GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid);
> +  ASSERT (GuidHob !=3D NULL);
> +  if (GuidHob =3D=3D NULL) {
> +    return EFI_NOT_FOUND;
> +  }
> +  PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob);
> +  //#
> +  //#ACPI items
> +  //#
> +  Size =3D AsciiStrSize (AcpiName10nm);
> +  Status =3D PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiName10nm);
> +  DEBUG ((DEBUG_INFO, "%a TypeWilsonCitySMT ICX\n",
> __FUNCTION__));
> +  ASSERT_EFI_ERROR (Status);
> +
> +  Size =3D AsciiStrSize (OemTableIdXhci);
> +  Status =3D PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci);
> +  ASSERT_EFI_ERROR (Status);
> +
> +  return Status;
> +}
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/GpioTable.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/GpioTable.c
> new file mode 100644
> index 0000000000..f8e6051df2
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/GpioTable.c
> @@ -0,0 +1,327 @@
> +/** @file
> +
> +  @copyright
> +  Copyright 2020 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiBoardInit.h"
> +#include <Library/UbaGpioUpdateLib.h>
> +
> +#include <Library/GpioLib.h>
> +#include <Library/UbaGpioInitLib.h>
> +#include <GpioPinsSklH.h>
> +#include <Library/PcdLib.h>
> +#include <Ppi/DynamicSiLibraryPpi.h>
> +
> +//
> +// Board     : Wilson City SMT
> +//
> +static GPIO_INIT_CONFIG mGpioTableWilsonCitySMT [] =3D
> +  {
> +    {GPIO_SKL_H_GPP_A0,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
> +    {GPIO_SKL_H_GPP_A1,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0
> +    {GPIO_SKL_H_GPP_A2,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1
> +    {GPIO_SKL_H_GPP_A3,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2
> +    {GPIO_SKL_H_GPP_A4,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3
> +    {GPIO_SKL_H_GPP_A5,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
> +    {GPIO_SKL_H_GPP_A6,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
> +    {GPIO_SKL_H_GPP_A7,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
> +    {GPIO_SKL_H_GPP_A8,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N
> +    {GPIO_SKL_H_GPP_A9,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI
> +    {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10
> +    {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N
> +    {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N
> +    {GPIO_SKL_H_GPP_A13, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N
> +    {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N
> +    {GPIO_SKL_H_GPP_A15, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_15_FM_SUSACK_N
> +    {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16
> +    {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16
> +    {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS
> +    {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20
> +    {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21
> +    {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22
> +    {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23
> +    {GPIO_SKL_H_GPP_B0,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0
> +    {GPIO_SKL_H_GPP_B1,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1
> +    {GPIO_SKL_H_GPP_B2,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N
> +    {GPIO_SKL_H_GPP_B3,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_3_FM_QAT_ENABLE_N
> +    {GPIO_SKL_H_GPP_B4,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_4_FM_QAT_SEL
> +    {GPIO_SKL_H_GPP_B5,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1
> +    {GPIO_SKL_H_GPP_B6,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2
> +    {GPIO_SKL_H_GPP_B7,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7
> +    {GPIO_SKL_H_GPP_B8,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8
> +    {GPIO_SKL_H_GPP_B9,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2
> +    {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N
> +    {GPIO_SKL_H_GPP_B11, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_B_11_FM_PMBUS_ALERT_B_EN
> +    {GPIO_SKL_H_GPP_B12, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N
> +    {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_13_RST_PLTRST_N
> +    {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
> +    {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N
> +    {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N
> +    {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N
> +    {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT
> +    {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5
> +    {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioPlatformReset,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N
> +    {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21
> +    {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE
> +    {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_
> N
> +    {GPIO_SKL_H_GPP_C2,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP
> +    {GPIO_SKL_H_GPP_C5,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N
> +    {GPIO_SKL_H_GPP_C8,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N
> +    {GPIO_SKL_H_GPP_C9,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_9_FM_MFG_MODE
> +    {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone}},//GPP_C_10_FM_PCH_SATA_RAID_KEY
> +    {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N
> +    {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0
> +    {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1
> +    {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N
> +    {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0
> +    {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1
> +    {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0
> +    {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1
> +    {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_C_19_RST_SMB_HOST_PCH_MUX_N
> +    {GPIO_SKL_H_GPP_C20, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_20_FM_THROTTLE_N
> +    {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N
> +    {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N
> +    {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N
> +    {GPIO_SKL_H_GPP_D0,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
> +    {GPIO_SKL_H_GPP_D1,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N
> +    {GPIO_SKL_H_GPP_D2,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR
> +    {GPIO_SKL_H_GPP_D3,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT
> +    {GPIO_SKL_H_GPP_D4,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA
> +    {GPIO_SKL_H_GPP_D5,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5
> +    {GPIO_SKL_H_GPP_D6,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6
> +    {GPIO_SKL_H_GPP_D7,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7
> +    {GPIO_SKL_H_GPP_D8,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL
> +    {GPIO_SKL_H_GPP_D9,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9
> +    {GPIO_SKL_H_GPP_D10, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP
> +    {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11
> +    {GPIO_SKL_H_GPP_D12, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1
> +    {GPIO_SKL_H_GPP_D13, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL
> +    {GPIO_SKL_H_GPP_D14, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA
> +    {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0
> +    {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1
> +    {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2
> +    {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N
> +    {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R
> +    {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20
> +    {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21
> +    {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22
> +    {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23
> +    {GPIO_SKL_H_GPP_E0,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N
> +    {GPIO_SKL_H_GPP_E1,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N
> +    {GPIO_SKL_H_GPP_E2,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N
> +    {GPIO_SKL_H_GPP_E3,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis,    GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N
> +    {GPIO_SKL_H_GPP_E4,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4
> +    {GPIO_SKL_H_GPP_E5,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5
> +    {GPIO_SKL_H_GPP_E6,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E_6
> +    {GPIO_SKL_H_GPP_E7,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N
> +    {GPIO_SKL_H_GPP_E8,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N
> +    {GPIO_SKL_H_GPP_E9,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N
> +    {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N
> +    {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N
> +    {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N
> +    {GPIO_SKL_H_GPP_F0,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N
> +    {GPIO_SKL_H_GPP_F1,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N
> +    {GPIO_SKL_H_GPP_F2,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N
> +    {GPIO_SKL_H_GPP_F3,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N
> +    {GPIO_SKL_H_GPP_F4,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N
> +    {GPIO_SKL_H_GPP_F5,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N
> +    {GPIO_SKL_H_GPP_F6,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK
> +    {GPIO_SKL_H_GPP_F7,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI
> +    {GPIO_SKL_H_GPP_F8,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS
> +    {GPIO_SKL_H_GPP_F9,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO
> +    {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK
> +    {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD
> +    {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1
> +    {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0
> +    {GPIO_SKL_H_GPP_F14, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N
> +    {GPIO_SKL_H_GPP_F15, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N
> +    {GPIO_SKL_H_GPP_F16, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N
> +    {GPIO_SKL_H_GPP_F17, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N
> +    {GPIO_SKL_H_GPP_F18, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N
> +    {GPIO_SKL_H_GPP_F19, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL
> +    {GPIO_SKL_H_GPP_F20, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA
> +    {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21
> +    {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK
> +    {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD
> +    {GPIO_SKL_H_GPP_G0,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0
> +    {GPIO_SKL_H_GPP_G1,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1
> +    {GPIO_SKL_H_GPP_G2,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2
> +    {GPIO_SKL_H_GPP_G3,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3
> +    {GPIO_SKL_H_GPP_G4,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4
> +    {GPIO_SKL_H_GPP_G5,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5
> +    {GPIO_SKL_H_GPP_G6,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6
> +    {GPIO_SKL_H_GPP_G7,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7
> +    {GPIO_SKL_H_GPP_G8,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0
> +    {GPIO_SKL_H_GPP_G9,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1
> +    {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2
> +    {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3
> +    {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_12_FM_BOARD_SKU_ID0
> +    {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1
> +    {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2
> +    {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3
> +    {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4
> +    {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE
> +    {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N
> +    {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N
> +    {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_G_20_IRQ_SML1_PMBUS_ALERT_N
> +    {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N
> +    {GPIO_SKL_H_GPP_G22, { GpioPadModeNative3, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP
> +    {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23
> +    {GPIO_SKL_H_GPP_H0,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2
> +    {GPIO_SKL_H_GPP_H1,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N
> +    {GPIO_SKL_H_GPP_H2,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0
> +    {GPIO_SKL_H_GPP_H3,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1
> +    {GPIO_SKL_H_GPP_H4,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4
> +    {GPIO_SKL_H_GPP_H6,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N
> +    {GPIO_SKL_H_GPP_H7,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3
> +    {GPIO_SKL_H_GPP_H8,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N
> +    {GPIO_SKL_H_GPP_H9,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5
> +    {GPIO_SKL_H_GPP_H10, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_H_10_SMB_SMLINK2_STBY_LVC3_R_SCL
> +    {GPIO_SKL_H_GPP_H11, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_H_11_SMB_SMLINK2_STBY_LVC3_R_SDA
> +    {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE
> +    {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N
> +    {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N
> +    {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N
> +    {GPIO_SKL_H_GPP_H20, { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL
> +    {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N
> +    {GPIO_SKL_H_GPP_H22, { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL
> +    {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23
> +    {GPIO_SKL_H_GPP_I0,  { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0
> +    {GPIO_SKL_H_GPP_I1,  { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1
> +    {GPIO_SKL_H_GPP_I2,  { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2
> +    {GPIO_SKL_H_GPP_I3,  { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3
> +    {GPIO_SKL_H_GPP_I4,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I_4
> +    {GPIO_SKL_H_GPP_I5,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I_5
> +    {GPIO_SKL_H_GPP_I6,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I_6
> +    {GPIO_SKL_H_GPP_I7,  { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7
> +    {GPIO_SKL_H_GPP_I8,  { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N
> +    {GPIO_SKL_H_GPP_I9,  { GpioPadModeNative2, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N
> +    {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10
> +//    {GPIO_SKL_H_GPP_I11, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_I_11_PD_3P3_RCOMP
> +    {GPIO_SKL_H_GPD0,    { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_0_FM_FIVRBREAK_N
> +    {GPIO_SKL_H_GPD1,    { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_1_PU_ACPRESENT
> +    {GPIO_SKL_H_GPD2,    { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N
> +    {GPIO_SKL_H_GPD3,    { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N
> +    {GPIO_SKL_H_GPD4,    { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_4_FM_SLPS3_N
> +    {GPIO_SKL_H_GPD5,    { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_5_FM_SLPS4_N
> +    {GPIO_SKL_H_GPD6,    { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_6_FM_SLPA_N
> +    {GPIO_SKL_H_GPD7,    { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_7_TP_GPD_7
> +    {GPIO_SKL_H_GPD8,    { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK
> +    {GPIO_SKL_H_GPD9,    { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_9_TP_GPD_9_SLP
> +    {GPIO_SKL_H_GPD10,   { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_10_FM_SLPS5_N
> +    {GPIO_SKL_H_GPD11,   { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N
> +    {GPIO_SKL_H_GPP_J0,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0
> +    {GPIO_SKL_H_GPP_J1,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1
> +    {GPIO_SKL_H_GPP_J2,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2
> +    {GPIO_SKL_H_GPP_J3,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3
> +    {GPIO_SKL_H_GPP_J4,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4
> +    {GPIO_SKL_H_GPP_J5,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5
> +    {GPIO_SKL_H_GPP_J6,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6
> +    {GPIO_SKL_H_GPP_J7,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7
> +    {GPIO_SKL_H_GPP_J8,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8
> +    {GPIO_SKL_H_GPP_J9,  { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9
> +    {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10
> +    {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11
> +    {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12
> +    {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13
> +    {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14
> +    {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15
> +    {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16
> +    {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17
> +    {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18
> +    {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19
> +    {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20
> +    {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21
> +    {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22
> +    {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio,    GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23
> +    {GPIO_SKL_H_GPP_K0,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH
> +    {GPIO_SKL_H_GPP_K1,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0
> +    {GPIO_SKL_H_GPP_K2,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1
> +    {GPIO_SKL_H_GPP_K3,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN
> +    {GPIO_SKL_H_GPP_K4,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV
> +    {GPIO_SKL_H_GPP_K5,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0
> +    {GPIO_SKL_H_GPP_K6,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1
> +    {GPIO_SKL_H_GPP_K7,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirInOut,    GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER
> +    {GPIO_SKL_H_GPP_K8,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN
> +    {GPIO_SKL_H_GPP_K9,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT
> +    {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn,       GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone,
> GpioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N
> +//    {GPIO_SKL_H_GPP_K11, { GpioPadModeNative1,
> GpioHostOwnDefault,    GpioDirIn,       GpioOutLow,     GpioIntDis,
> GpioResetPwrGood, GpioTermNone,
> GpioPadConfigLock}},//GPP_K_11_PD_1P8_3P3_RCOMP
> +    {GPIO_SKL_H_GPP_L2,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0
> +    {GPIO_SKL_H_GPP_L3,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1
> +    {GPIO_SKL_H_GPP_L4,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2
> +    {GPIO_SKL_H_GPP_L5,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3
> +    {GPIO_SKL_H_GPP_L6,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4
> +    {GPIO_SKL_H_GPP_L7,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5
> +    {GPIO_SKL_H_GPP_L8,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6
> +    {GPIO_SKL_H_GPP_L9,  { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7
> +    {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK
> +    {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0
> +    {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1
> +    {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2
> +    {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3
> +    {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4
> +    {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5
> +    {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6
> +    {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7
> +    {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirOut,      GpioOutLow,     GpioIntDis, GpioResetPwrGood,
> GpioTermNone, GpioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK
> +};
> +
> +static GPIO_INIT_CONFIG mGpioTableWilsonCitySMTMiniPch [] =3D
> +{
> +    {GPIO_SKL_H_GPP_C5,  { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone,
> GpioPadConfigLock}},//GPP_C_5
> +    {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirInOut, GpioOutHigh,
> GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_C_10_FM_PCH_SATA
> _RAID_KEY
> +    {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetDeep,  GpioTermNone,
> GpioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0
> +    {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetDeep,  GpioTermNone,
> GpioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1
> +    {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio,    GpioHostOwnAcpi,
> GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntNmi,GpioResetNormal,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
> +    {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone,
> GpioPadConfigLock}},//GPP_G_12_FM_BOARD_SKU_ID0
> +    {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone,
> GpioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1
> +    {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone,
> GpioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2
> +    {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone,
> GpioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3
> +    {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone,
> GpioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4
> +    {GPIO_SKL_H_GPP_D0,  { GpioPadModeGpio,    GpioHostOwnAcpi,
> GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntNmi,GpioResetNormal,
> GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
> +    {GPIO_SKL_H_GPP_D4,  { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone,
> GpioPadConfigLock}},//GPP_D_4
> +    {GPIO_SKL_H_GPP_D5,  { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirOut,   GpioOutHigh,    GpioIntDis,GpioResetNormal,GpioTermNone,
> GpioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N
> +    {GPIO_SKL_H_GPP_D6,  { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntLevel | GpioIntApic,GpioResetNormal,
> GpioTermNone, GpioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N
> +    {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio,    GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci,GpioResetNormal,
> GpioTermNone}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N
> +    {GPIO_SKL_H_GPP_E7,  { GpioPadModeGpio,    GpioHostOwnGpio,
> GpioDirIn,    GpioOutDefault, GpioIntDis,GpioResetDeep,  GpioTermNone,
> GpioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_N
> +};
> +
> +
> +
> +EFI_STATUS
> +TypeWilsonCitySMTInstallGpioData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +)
> +{
> +  EFI_STATUS                            Status =3D EFI_SUCCESS;
> +  DYNAMIC_SI_LIBARY_PPI                 *DynamicSiLibraryPpi =3D NULL;
> +
> +  Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
> &DynamicSiLibraryPpi);
> +  if (EFI_ERROR (Status)) {
> +    ASSERT_EFI_ERROR (Status);
> +    return Status;
> +  }
> +
> +  if (DynamicSiLibraryPpi->GetPchSeries () =3D=3D PchMini) {
> +    Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformGpioInitDataGuid,
> +                                 &mGpioTableWilsonCitySMTMiniPch,
> +                                 sizeof(mGpioTableWilsonCitySMTMiniPch)
> +                                 );
> +    Status =3D PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof
> (mGpioTableWilsonCitySMTMiniPch));
> +  } else {
> +    Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformGpioInitDataGuid,
> +                                 &mGpioTableWilsonCitySMT,
> +                                 sizeof(mGpioTableWilsonCitySMT)
> +                                 );
> +    Status =3D PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof
> (mGpioTableWilsonCitySMT));
> +  }
> +  ASSERT_EFI_ERROR (Status);
> +  return Status;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/IioBifurInit.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/IioBifurInit.c
> new file mode 100644
> index 0000000000..32de972eb6
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/IioBifurInit.c
> @@ -0,0 +1,249 @@
> +/** @file
> +  IIO Config Update.
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiBoardInit.h"
> +#include <Library/UbaIioConfigLib.h>
> +#include <IioPlatformData.h>
> +
> +typedef enum {
> +  Iio_Socket0 =3D 0,
> +  Iio_Socket1,
> +  Iio_Socket2,
> +  Iio_Socket3,
> +  Iio_Socket4,
> +  Iio_Socket5,
> +  Iio_Socket6,
> +  Iio_Socket7
> +} IIO_SOCKETS;
> +
> +typedef enum {
> +  Iio_Iou0 =3D 0,
> +  Iio_Iou1,
> +  Iio_Iou2,
> +  Iio_Iou3,
> +  Iio_Iou4,
> +  Iio_IouMax
> +} IIO_IOUS;
> +
> +typedef enum {
> +  VPP_PORT_0 =3D 0,
> +  VPP_PORT_1,
> +  VPP_PORT_2,
> +  VPP_PORT_3
> +} VPP_PORT;
> +
> +#define ENABLE            1
> +#define DISABLE           0
> +
> +//
> +// WilsonCitySMT should has the same settings like WilsomCity-LCC
> +//
> +
> +//
> +//  config file  : Wilson_City_PCIe_Slot_Config_1p70.xlsx
> +//  config sheet : WilsonCity_ICX
> +//
> +static IIO_BIFURCATION_DATA_ENTRY_EX   IioBifurcationTable[] =3D
> +{
> +
> +  { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
> +  { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
> +  { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
> +  { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, 0           , 0x76   =
     , 0xE2
> , 4             },
> +  { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_x4x4x4x4, VPP_PORT_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
> +
> +  { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0           , 0x70   =
     , 0xE2
> , 4             },
> +  { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0           , 0x7C   =
     , 0xE2
> , 4             },
> +  { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
> +  { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX,
> SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX  },
> +  { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_x4x4x4x4, 0           , 0x74   =
     , 0xE2
> , 4             }
> +};
> +
> +static IIO_SLOT_CONFIG_DATA_ENTRY_EX   IioSlotTable[] =3D {
> +  // Port Index  | Slot       |Interlock |power       |Power        |Hot=
plug  |Vpp
> Port      |Vpp Addr      |PCIeSSD  |PCIeSSD       |PCIeSSD       |Hidden
> |Common   |  SRIS   |Uplink   |Retimer  |Retimer       |Retimer       |Re=
timer
> |Mux           |Mux           |ExtnCard |ExtnCard      |ExtnCard      |Ex=
tnCard
> |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard Hotplug|ExtnCard
> Hotplug|Max Retimer|
> +  //             |            |          |Limit Scale |Limit Value  |Cap=
      |              |
> |Cap      |Port          |Address       |          |Clock    |         |P=
ort     |         |Address
> |Channel       |Width      |Address       |Channel       |Support  |SMBus=
 Port
> |SMBus Addr    |Retimer  |SMBus Address   |Width           |Hotplug  |Vpp=
 Port
> |Vpp Address     |           |
> +  {SOCKET_0_INDEX +
> +    PORT_1A_INDEX, 6          , DISABLE , 0           , 75          , DI=
SABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX ,
> VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE ,
> SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX ,
> SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE ,
> SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   ,
> SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_2A_INDEX, 7          , DISABLE , 0           , 75          , DI=
SABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX ,
> VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE ,
> SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX ,
> SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE ,
> SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   ,
> SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_0_INDEX +
> +    PORT_4A_INDEX, 2          , DISABLE , 0           , 200         , DI=
SABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX ,
> VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE ,
> SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2         , 4            ,
> ENABLE  , VPP_PORT_0   , 0x76         , ENABLE  , SMB_ADDR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_0     , 0x40           , 0x1      },
> +  {SOCKET_0_INDEX +
> +    PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2
> , 4            , ENABLE  , VPP_PORT_0   , 0x76         , ENABLE  , SMB_AD=
DR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_1     , 0x40           , 0x1      },
> +  {SOCKET_0_INDEX +
> +    PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2
> , 4            , ENABLE  , VPP_PORT_0   , 0x76         , ENABLE  , SMB_AD=
DR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_0     , 0x42           , 0x1      },
> +  {SOCKET_0_INDEX +
> +    PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2
> , 4            , ENABLE  , VPP_PORT_0   , 0x76         , ENABLE  , SMB_AD=
DR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_1     , 0x42           , 0x1      },
> +  {SOCKET_0_INDEX +
> +    PORT_5A_INDEX, 10         , DISABLE , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_0   , 0x4C         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , ENABLE  , 0x26         , 2      =
      , 16        ,
> 0xe2         , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX
> , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   ,
> SMB_ADDR_MAX   , 0x1      },
> +  {SOCKET_0_INDEX +
> +    PORT_5B_INDEX, 11         , DISABLE , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_1   , 0x4C         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , ENABLE  , 0x26         , 2      =
      , 16        ,
> 0xe2         , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX
> , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   ,
> SMB_ADDR_MAX   , 0x1      },
> +  {SOCKET_0_INDEX +
> +    PORT_5C_INDEX, 12         , DISABLE , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_0   , 0x4E         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , ENABLE  , 0x26         , 2      =
      , 16        ,
> 0xe2         , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX
> , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   ,
> SMB_ADDR_MAX   , 0x1      },
> +  {SOCKET_0_INDEX +
> +    PORT_5D_INDEX, 13         , DISABLE , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_1   , 0x4E         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , ENABLE  , 0x26         , 2      =
      , 16        ,
> 0xe2         , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX
> , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   ,
> SMB_ADDR_MAX   , 0x1      },
> +
> +  {SOCKET_1_INDEX +
> +    PORT_1A_INDEX, 4          , ENABLE  , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_0   , 0x4A         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX ,
> SMB_DATA_MAX , NOT_EXIST , 0xe2         , 4            , ENABLE  , VPP_PO=
RT_0   ,
> 0x70         , ENABLE  , SMB_ADDR_MAX   , NOT_EXIST      , ENABLE  ,
> VPP_PORT_0     , 0x40           , 0x1      },
> +  {SOCKET_1_INDEX +
> +    PORT_1B_INDEX, NO_SLT_IMP , ENABLE  , PWR_SCL_MAX ,
> PWR_VAL_MAX , ENABLE  , VPP_PORT_0   , 0x4A         , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2
> , 4            , ENABLE  , VPP_PORT_0   , 0x70         , ENABLE  , SMB_AD=
DR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_1     , 0x40           , 0x1      },
> +  {SOCKET_1_INDEX +
> +    PORT_1C_INDEX, NO_SLT_IMP , ENABLE  , PWR_SCL_MAX ,
> PWR_VAL_MAX , ENABLE  , VPP_PORT_0   , 0x4A         , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2
> , 4            , ENABLE  , VPP_PORT_0   , 0x70         , ENABLE  , SMB_AD=
DR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_0     , 0x42           , 0x1      },
> +  {SOCKET_1_INDEX +
> +    PORT_1D_INDEX, NO_SLT_IMP , ENABLE  , PWR_SCL_MAX ,
> PWR_VAL_MAX , ENABLE  , VPP_PORT_0   , 0x4A         , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2
> , 4            , ENABLE  , VPP_PORT_0   , 0x70         , ENABLE  , SMB_AD=
DR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_1     , 0x42           , 0x1      },
> +  {SOCKET_1_INDEX +
> +    PORT_2A_INDEX, 9          , DISABLE , 0           , 25          , DI=
SABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX ,
> VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE ,
> SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2         , 4            ,
> ENABLE  , VPP_PORT_0   , 0x7C         , ENABLE  , SMB_ADDR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_0     , 0x44           , 0x1      },
> +  {SOCKET_1_INDEX +
> +    PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2
> , 4            , ENABLE  , VPP_PORT_0   , 0x7C         , ENABLE  , SMB_AD=
DR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_1     , 0x44           , 0x1      },
> +  {SOCKET_1_INDEX +
> +    PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2
> , 4            , ENABLE  , VPP_PORT_0   , 0x7C         , ENABLE  , SMB_AD=
DR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_0     , 0x46           , 0x1      },
> +  {SOCKET_1_INDEX +
> +    PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2
> , 4            , ENABLE  , VPP_PORT_0   , 0x7C         , ENABLE  , SMB_AD=
DR_MAX   ,
> NOT_EXIST      , ENABLE  , VPP_PORT_1     , 0x46           , 0x1      },
> +  {SOCKET_1_INDEX +
> +    PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_1_INDEX +
> +    PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_1_INDEX +
> +    PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_1_INDEX +
> +    PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_1_INDEX +
> +    PORT_4A_INDEX, 8          , DISABLE , 0           , 25          , DI=
SABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX ,
> VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE , DISABLE , DISABLE ,
> SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX ,
> SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE ,
> SMB_ADDR_MAX   , NOT_EXIST      , DISABLE , VPP_PORT_MAX   ,
> SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_1_INDEX +
> +    PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_1_INDEX +
> +    PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_1_INDEX +
> +    PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX ,
> PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE ,
> VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE  , DISABLE ,
> DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST ,
> SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX ,
> SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX   , NOT_EXIST      , DISABLE ,
> VPP_PORT_MAX   , SMB_ADDR_MAX   , 0x0      },
> +  {SOCKET_1_INDEX +
> +    PORT_5A_INDEX, 14         , DISABLE , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_0   , 0x4C         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , ENABLE  , 0x20         , 2      =
      , 16        ,
> 0xe2         , 4            , ENABLE  , VPP_PORT_0   , 0x74         , ENA=
BLE  ,
> SMB_ADDR_MAX   , NOT_EXIST      , ENABLE  , VPP_PORT_0     , 0x40        =
   , 0x1
> },
> +  {SOCKET_1_INDEX +
> +    PORT_5B_INDEX, 15         , DISABLE , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_1   , 0x4C         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , ENABLE  , 0x20         , 2      =
      , 16        ,
> 0xe2         , 4            , ENABLE  , VPP_PORT_0   , 0x74         , ENA=
BLE  ,
> SMB_ADDR_MAX   , NOT_EXIST      , ENABLE  , VPP_PORT_1     , 0x40        =
   , 0x1
> },
> +  {SOCKET_1_INDEX +
> +    PORT_5C_INDEX, 16         , DISABLE , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_0   , 0x4E         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , ENABLE  , 0x20         , 2      =
      , 16        ,
> 0xe2         , 4            , ENABLE  , VPP_PORT_0   , 0x74         , ENA=
BLE  ,
> SMB_ADDR_MAX   , NOT_EXIST      , ENABLE  , VPP_PORT_0     , 0x42        =
   , 0x1
> },
> +  {SOCKET_1_INDEX +
> +    PORT_5D_INDEX, 17         , DISABLE , 0           , 25          , EN=
ABLE  ,
> VPP_PORT_1   , 0x4E         , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,
> NOT_HIDE , ENABLE  , DISABLE , DISABLE , ENABLE  , 0x20         , 2      =
      , 16        ,
> 0xe2         , 4            , ENABLE  , VPP_PORT_0   , 0x74         , ENA=
BLE  ,
> SMB_ADDR_MAX   , NOT_EXIST      , ENABLE  , VPP_PORT_1     , 0x42        =
   , 0x1
> }
> +};
> +
> +EFI_STATUS
> +UpdateWilsonCitySMTIioConfig (
> +  IN  IIO_GLOBALS             *IioGlobalData
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX
> TypeWilsonCitySMTIioConfigTable =3D
> +{
> +  PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
> +  PLATFORM_IIO_CONFIG_UPDATE_VERSION_2,
> +
> +  IioBifurcationTable,
> +  sizeof(IioBifurcationTable),
> +  UpdateWilsonCitySMTIioConfig,
> +  IioSlotTable,
> +  sizeof(IioSlotTable)
> +};
> +
> +/**
> +  Entry point function for the PEIM
> +
> +  @param FileHandle      Handle of the file being invoked.
> +  @param PeiServices     Describes the list of possible PEI Services.
> +
> +  @return EFI_SUCCESS    If we installed our PPI
> +
> +**/
> +EFI_STATUS
> +TypeWilsonCitySMTIioPortBifurcationInit (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +)
> +{
> +  EFI_STATUS                         Status;
> +  EFI_HOB_GUID_TYPE                  *GuidHob;
> +  EFI_PLATFORM_INFO                  *PlatformInfo;
> +  PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX   *PlatformIioInfoPtr;
> +  UINTN                              PlatformIioInfoSize;
> +
> +
> +  GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid);
> +  ASSERT (GuidHob !=3D NULL);
> +  if (GuidHob =3D=3D NULL) {
> +    return EFI_NOT_FOUND;
> +  }
> +  PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob);
> +
> +  //
> +  // This is config for ICX
> +  //
> +  PlatformIioInfoPtr =3D &TypeWilsonCitySMTIioConfigTable;
> +  PlatformIioInfoSize =3D sizeof(TypeWilsonCitySMTIioConfigTable);
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformIioConfigDataGuid,
> +                                 PlatformIioInfoPtr,
> +                                 PlatformIioInfoSize
> +                                 );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformIioConfigDataGuid_1,
> +                                 PlatformIioInfoPtr,
> +                                 PlatformIioInfoSize
> +                                 );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformIioConfigDataGuid_2,
> +                                 PlatformIioInfoPtr,
> +                                 PlatformIioInfoSize
> +                                 );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformIioConfigDataGuid_3,
> +                                 PlatformIioInfoPtr,
> +                                 PlatformIioInfoSize
> +                                 );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  return Status;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/KtiEparam.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/KtiEparam.c
> new file mode 100644
> index 0000000000..9c0c75f47f
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/KtiEparam.c
> @@ -0,0 +1,79 @@
> +/** @file
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiBoardInit.h"
> +#include <KtiSetupDefinitions.h>
> +#include <UbaKti.h>
> +
> +extern EFI_GUID gPlatformKtiEparamUpdateDataGuid;
> +
> +ALL_LANES_EPARAM_LINK_INFO
> KtiWilsonCitySMTIcxAllLanesEparamTable[] =3D {
> +  //
> +  // SocketID, Freq, Link, TXEQL, CTLEPEAK
> +  //
> +  //
> +  // Socket 0
> +  //
> +  {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE},
> +  {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE},
> +  {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE},
> +  //
> +  // Socket 1
> +  //
> +  {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK0), 0x2A31383F, ADAPTIVE_CTLE},
> +  {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A30393F, ADAPTIVE_CTLE},
> +  {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK2), 0x2C34373F, ADAPTIVE_CTLE},
> +  //
> +  // Socket 2
> +  //
> +  {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE},
> +  {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK1), 0x2F3A343F, ADAPTIVE_CTLE},
> +  {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK2), 0x2F3A343F, ADAPTIVE_CTLE},
> +  //
> +  // Socket 3
> +  //
> +  {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE},
> +  {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK1), 0x2F3A343F, ADAPTIVE_CTLE},
> +  {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 <<
> SPEED_REC_112GT), (1 << KTI_LINK2), 0x2F3A343F, ADAPTIVE_CTLE}
> +};
> +
> +PLATFORM_KTI_EPARAM_UPDATE_TABLE
> TypeWilsonCitySMTIcxKtiEparamUpdate =3D {
> +  PLATFORM_KTIEP_UPDATE_SIGNATURE,
> +  PLATFORM_KTIEP_UPDATE_VERSION,
> +  KtiWilsonCitySMTIcxAllLanesEparamTable,
> +  sizeof (KtiWilsonCitySMTIcxAllLanesEparamTable),
> +  NULL,
> +  0
> +};
> +
> +
> +EFI_STATUS
> +TypeWilsonCitySMTInstallKtiEparamData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +)
> +{
> +  EFI_STATUS                            Status;
> +  EFI_HOB_GUID_TYPE                     *GuidHob;
> +  EFI_PLATFORM_INFO                     *PlatformInfo;
> +
> +  GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid);
> +  ASSERT (GuidHob !=3D NULL);
> +  if (GuidHob =3D=3D NULL) {
> +    return EFI_NOT_FOUND;
> +  }
> +  PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob);
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformKtiEparamUpdateDataGuid,
> +                                 &TypeWilsonCitySMTIcxKtiEparamUpdate,
> +                                 sizeof(TypeWilsonCitySMTIcxKtiEparamUpd=
ate)
> +                                 );
> +
> +  return Status;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PcdData.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PcdData.c
> new file mode 100644
> index 0000000000..5ad03c93c7
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PcdData.c
> @@ -0,0 +1,273 @@
> +/** @file
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiBoardInit.h"
> +#include <ImonVrSvid.h>
> +#include <Library/MemVrSvidMapLib.h>
> +#include <Guid/PlatformInfo.h>
> +#include <Library/UbaPcdUpdateLib.h>
> +#include <Library/PcdLib.h>
> +#include <UncoreCommonIncludes.h>
> +#include <Ppi/DynamicSiLibraryPpi.h>
> +#include <CpuAndRevisionDefines.h>
> +
> +#define GPIO_SKL_H_GPP_B20      0x01010014
> +
> +VOID TypeWilsonCitySMTPlatformUpdateVrIdAddress (VOID);
> +
> +/**
> +  Update WilsonCity IMON SVID Information
> +
> +  retval N/A
> +**/
> +VOID
> +TypeWilsonCitySMTPlatformUpdateImonAddress (
> +  VOID
> +  )
> +{
> +  VCC_IMON *VccImon =3D NULL;
> +  UINTN Size =3D 0;
> +
> +  Size =3D sizeof (VCC_IMON);
> +  VccImon =3D (VCC_IMON *) PcdGetPtr (PcdImonAddr);
> +  if (VccImon =3D=3D NULL) {
> +    DEBUG ((DEBUG_ERROR, "UpdateImonAddress() - PcdImonAddr =3D=3D
> NULL\n"));
> +    return;
> +  }
> +
> +  VccImon->VrSvid[0] =3D PcdGet8 (PcdWilsonCitySvidVrP1V8);
> +  VccImon->VrSvid[1] =3D PcdGet8 (PcdWilsonCitySvidVrVccAna);
> +  VccImon->VrSvid[2] =3D IMON_ADDR_LIST_END; // End array with 0xFF
> +
> +  PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon);
> +}
> +
> +/**
> +  Update WilsonCity VR ID SVID Information
> +
> +  retval N/A
> +**/
> +VOID
> +TypeWilsonCitySMTPlatformUpdateVrIdAddress (
> +  VOID
> +  )
> +{
> +  MEM_SVID_MAP *MemSvidMap =3D NULL;
> +  UINTN Size =3D 0;
> +
> +  Size =3D sizeof (MEM_SVID_MAP);
> +  MemSvidMap =3D (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap);
> +  if (MemSvidMap =3D=3D NULL) {
> +    DEBUG ((DEBUG_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap =3D=3D
> NULL\n"));
> +    return;
> +  }
> +  /*
> +    Map VR ID Address to Memory controller
> +    The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x1=
4,
> and 0x16.
> +    Whitley PHAS indicates that Whitley (like Purley) only connects 2 VR=
s (VR
> ID's 0x10 and 0x12).
> +    Those are typically shared such that MC0/MC2 share the same DDR VR (=
as
> they are on the same side of the CPU)
> +    and MC1/MC3 share the other. Depending on motherboard layout and
> other design constraints, this could change
> +    BIT   4 =3D> 0 or 1, SVID BUS\Interface 0 or 1 respectively
> +    BIT 0:3 =3D> SVID ADDRESS
> +  */
> +  MemSvidMap->Socket[0].Mc[0] =3D 0x10;  //SVID BUS 1, ADDR 0
> +  MemSvidMap->Socket[0].Mc[1] =3D 0x12;  //SVID BUS 1, ADDR 2
> +  MemSvidMap->Socket[1].Mc[0] =3D 0x10;  //SVID BUS 1, ADDR 0
> +  MemSvidMap->Socket[1].Mc[1] =3D 0x12;  //SVID BUS 1, ADDR 2
> +  MemSvidMap->Socket[2].Mc[0] =3D 0x10;  //SVID BUS 1, ADDR 0
> +  MemSvidMap->Socket[2].Mc[1] =3D 0x12;  //SVID BUS 1, ADDR 2
> +  MemSvidMap->Socket[3].Mc[0] =3D 0x10;  //SVID BUS 1, ADDR 0
> +  MemSvidMap->Socket[3].Mc[1] =3D 0x12;  //SVID BUS 1, ADDR 2
> +  MemSvidMap->Socket[4].Mc[0] =3D 0x10;  //SVID BUS 1, ADDR 0
> +  MemSvidMap->Socket[4].Mc[1] =3D 0x12;  //SVID BUS 1, ADDR 2
> +  MemSvidMap->Socket[5].Mc[0] =3D 0x10;  //SVID BUS 1, ADDR 0
> +  MemSvidMap->Socket[5].Mc[1] =3D 0x12;  //SVID BUS 1, ADDR 2
> +  MemSvidMap->Socket[6].Mc[0] =3D 0x10;  //SVID BUS 1, ADDR 0
> +  MemSvidMap->Socket[6].Mc[1] =3D 0x12;  //SVID BUS 1, ADDR 2
> +  MemSvidMap->Socket[7].Mc[0] =3D 0x10;  //SVID BUS 1, ADDR 0
> +  MemSvidMap->Socket[7].Mc[1] =3D 0x12;  //SVID BUS 1, ADDR 2
> +
> +  PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap);
> +}
> +
> +EFI_STATUS
> +TypeWilsonCitySMTPlatformPcdUpdateCallback (
> +  VOID
> +)
> +{
> +  CHAR8     FamilyName[]  =3D "Whitley";
> +
> +  CHAR8     BoardName[]   =3D "EPRP";
> +  UINT32    Data32;
> +  UINTN     Size;
> +  UINTN     PlatformFeatureFlag =3D 0;
> +
> +  CHAR16    PlatformName[]   =3D L"TypeWilsonCitySMT";
> +  UINTN     PlatformNameSize =3D 0;
> +  EFI_STATUS Status;
> +
> +  //#Integer for BoardID, must match the SKU number and be unique.
> +  Status =3D PcdSet16S (PcdOemSkuBoardID                      , TypeWils=
onCitySMT);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +  Status =3D PcdSet16S (PcdOemSkuBoardFamily                  , 0x30);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  // Number of Sockets on Board.
> +  Status =3D PcdSet32S (PcdOemSkuBoardSocketCount, 2);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  // Max channel and max DIMM
> +  Status =3D PcdSet32S (PcdOemSkuMaxChannel , 8);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +  Status =3D PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +  Status =3D PcdSetBoolS (PcdOemSkuDimmLayout, TRUE);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  //Update Onboard Video Controller PCI Ven_id, Dev_id
> +  Status =3D PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  //#
> +  //# Misc.
> +  //#
> +  //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF
> +  Status =3D PcdSet16S (PcdOemSkuMrlAttnLed                   , 0xc0);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  //SDP Active Flag
> +  Status =3D PcdSet8S (PcdOemSkuSdpActiveFlag                , 0x0);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  //# Zero terminated string to ID family
> +  Size =3D AsciiStrSize (FamilyName);
> +  Status =3D PcdSetPtrS (PcdOemSkuFamilyName             , &Size, Family=
Name);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  //# Zero terminated string to Board Name
> +  Size =3D AsciiStrSize (BoardName);
> +  Status =3D PcdSetPtrS (PcdOemSkuBoardName              , &Size, BoardN=
ame);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  PlatformNameSize =3D sizeof (PlatformName);
> +  Status =3D PcdSet32S (PcdOemSkuPlatformNameSize           ,
> (UINT32)PlatformNameSize);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +  Status =3D PcdSetPtrS (PcdOemSkuPlatformName              ,
> &PlatformNameSize, PlatformName);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  //# FeaturesBasedOnPlatform
> +  Status =3D PcdSet32S (PcdOemSkuPlatformFeatureFlag           ,
> (UINT32)PlatformFeatureFlag);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  //# Assert GPIO
> +  Data32 =3D 0;
> +  Status =3D PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +  Status =3D PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20);
> +  ASSERT_EFI_ERROR(Status);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  //# UplinkPortIndex
> +  Status =3D PcdSet8S (PcdOemSkuUplinkPortIndex, 5);
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  DEBUG ((DEBUG_INFO, "Uba Callback: PlatformPcdUpdateCallback is
> called!\n"));
> +  Status =3D TypeWilsonCitySMTPlatformUpdateAcpiTablePcds ();
> +  //# BMC Pcie Port Number
> +  PcdSet8S (PcdOemSkuBmcPciePortNumber, 5);
> +  ASSERT_EFI_ERROR(Status);
> +
> +  //# Board Type Bit Mask
> +  PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK |
> (CPU_TYPE_F_MASK << 4));
> +  ASSERT_EFI_ERROR(Status);
> +
> +  //Update IMON Address
> +  TypeWilsonCitySMTPlatformUpdateImonAddress ();
> +
> +  return Status;
> +}
> +
> +PLATFORM_PCD_UPDATE_TABLE    TypeWilsonCitySMTPcdUpdateTable =3D
> +{
> +  PLATFORM_PCD_UPDATE_SIGNATURE,
> +  PLATFORM_PCD_UPDATE_VERSION,
> +  TypeWilsonCitySMTPlatformPcdUpdateCallback
> +};
> +
> +EFI_STATUS
> +TypeWilsonCitySMTInstallPcdData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +)
> +{
> +  EFI_STATUS                            Status;
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformPcdConfigDataGuid,
> +                                 &TypeWilsonCitySMTPcdUpdateTable,
> +                                 sizeof(TypeWilsonCitySMTPcdUpdateTable)
> +                                 );
> +
> +  return Status;
> +}
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PchEarlyUpdate.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PchEarlyUpdate.c
> new file mode 100644
> index 0000000000..6e2d6df7d7
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PchEarlyUpdate.c
> @@ -0,0 +1,103 @@
> +/** @file
> +  Pch Early update.
> +
> +  @copyright
> +  Copyright 2019 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiBoardInit.h"
> +
> +#include <Library/UbaPchEarlyUpdateLib.h>
> +
> +#include <PchAccess.h>
> +#include <GpioPinsSklH.h>
> +#include <Library/GpioLib.h>
> +#include <Ppi/DynamicSiLibraryPpi.h>
> +
> +EFI_STATUS
> +TypeWilsonCitySMTPchLanConfig (
> +  IN SYSTEM_CONFIGURATION         *SystemConfig
> +)
> +{
> +  DYNAMIC_SI_LIBARY_PPI  *DynamicSiLibraryPpi =3D NULL;
> +  EFI_STATUS              Status;
> +
> +  Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
> &DynamicSiLibraryPpi);
> +  if (EFI_ERROR (Status)) {
> +    ASSERT_EFI_ERROR (Status);
> +    return Status;
> +  }
> +
> +  DynamicSiLibraryPpi->GpioSetOutputValue (GPIO_SKL_H_GPP_I9,
> (UINT32)SystemConfig->LomDisableByGpio);
> +  DynamicSiLibraryPpi->PchDisableGbe ();
> +
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +TypeWilsonCitySMTOemInitLateHook (
> +  IN SYSTEM_CONFIGURATION         *SystemConfig
> +)
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +
> +PLATFORM_PCH_EARLY_UPDATE_TABLE
> TypeWilsonCitySMTPchEarlyUpdateTable =3D
> +{
> +  PLATFORM_PCH_EARLY_UPDATE_SIGNATURE,
> +  PLATFORM_PCH_EARLY_UPDATE_VERSION,
> +  TypeWilsonCitySMTPchLanConfig,
> +  TypeWilsonCitySMTOemInitLateHook
> +};
> +
> +
> +/**
> +  Entry point function for the PEIM
> +
> +  @param FileHandle      Handle of the file being invoked.
> +  @param PeiServices     Describes the list of possible PEI Services.
> +
> +  @return EFI_SUCCESS    If we installed our PPI
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +TypeWilsonCitySMTPchEarlyUpdate(
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +  )
> +{
> +  EFI_STATUS                            Status =3D EFI_SUCCESS;
> +  DYNAMIC_SI_LIBARY_PPI                 *DynamicSiLibraryPpi =3D NULL;
> +
> +  Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL,
> &DynamicSiLibraryPpi);
> +  if (EFI_ERROR (Status)) {
> +    ASSERT_EFI_ERROR (Status);
> +    return Status;
> +  }
> +
> +  if (DynamicSiLibraryPpi->GetPchSeries () =3D=3D PchMini) {
> +    return EFI_SUCCESS;
> +  }
> +
> +  Status =3D PeiServicesLocatePpi (
> +            &gUbaConfigDatabasePpiGuid,
> +            0,
> +            NULL,
> +            &UbaConfigPpi
> +            );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                               UbaConfigPpi,
> +                               &gPlatformPchEarlyConfigDataGuid,
> +                               &TypeWilsonCitySMTPchEarlyUpdateTable,
> +                               sizeof(TypeWilsonCitySMTPchEarlyUpdateTab=
le)
> +                               );
> +
> +  return Status;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PeiBoardInit.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PeiBoardInit.h
> new file mode 100644
> index 0000000000..1471d62c3d
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PeiBoardInit.h
> @@ -0,0 +1,79 @@
> +/** @file
> +  PeiBoardInit.
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_BOARD_INIT_PEIM_H_
> +#define _PEI_BOARD_INIT_PEIM_H_
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Ppi/UbaCfgDb.h>
> +#include <Guid/PlatformInfo.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/HobLib.h>
> +#include <Cpu/CpuIds.h>
> +
> +// TypeWilsonCitySMT
> +EFI_STATUS
> +TypeWilsonCitySMTPlatformUpdateUsbOcMappings (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +
> +EFI_STATUS
> +TypeWilsonCitySMTPlatformUpdateAcpiTablePcds (
> +  VOID
> +);
> +
> +EFI_STATUS
> +TypeWilsonCitySMTInstallClockgenData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +
> +EFI_STATUS
> +TypeWilsonCitySMTInstallPcdData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +
> +EFI_STATUS
> +TypeWilsonCitySMTPchEarlyUpdate (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +
> +EFI_STATUS
> +TypeWilsonCitySMTIioPortBifurcationInit (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +
> +EFI_STATUS
> +TypeWilsonCitySMTInstallSlotTableData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +
> +EFI_STATUS
> +TypeWilsonCitySMTInstallKtiEparamData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +
> +// TypeWilsonCitySMT
> +EFI_STATUS
> +TypeWilsonCitySMTInstallGpioData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +
> +EFI_STATUS
> +TypeWilsonCitySMTInstallSoftStrapData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +
> +EFI_STATUS
> +TypeWilsonCitySMTQATIioPortBifurcationInit (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +);
> +#endif // _PEI_BOARD_INIT_PEIM_H_
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PeiBoardInitLib.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PeiBoardInitLib.c
> new file mode 100644
> index 0000000000..c368f5d143
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PeiBoardInitLib.c
> @@ -0,0 +1,123 @@
> +/** @file
> +
> + @copyright
> +  Copyright 2018 - 2021 Intel Corporation.
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +
> +/**
> +  The constructor function for Board Init Libray.
> +
> +  @param  FileHandle  Handle of the file being invoked.
> +  @param  PeiServices Describes the list of possible PEI Services.
> +
> +  @retval  EFI_SUCCESS            Table initialization successfully.
> +  @retval  EFI_OUT_OF_RESOURCES   No enough memory to initialize table.
> +**/
> +
> +#include "PeiBoardInit.h"
> +#include <UncoreCommonIncludes.h>
> +#include <Library/PchMultiPchBase.h>
> +#include <Ppi/DynamicSiLibraryPpi.h>
> +
> +EFI_STATUS
> +EFIAPI
> +TypeWilsonCitySMTPeiBoardInitLibConstructor (
> +  IN EFI_PEI_FILE_HANDLE     FileHandle,
> +  IN CONST EFI_PEI_SERVICES  **PeiServices
> +  )
> +{
> +  EFI_STATUS                      Status =3D EFI_SUCCESS;
> +  UBA_CONFIG_DATABASE_PPI         *UbaConfigPpi;
> +  EFI_HOB_GUID_TYPE               *GuidHob;
> +  EFI_PLATFORM_INFO               *PlatformInfo;
> +  UINT8                           SocketIndex;
> +
> +  GuidHob       =3D GetFirstGuidHob (&gEfiPlatformInfoGuid);
> +  ASSERT (GuidHob !=3D NULL);
> +  if (GuidHob =3D=3D NULL) {
> +    return EFI_NOT_FOUND;
> +  }
> +  PlatformInfo  =3D GET_GUID_HOB_DATA(GuidHob);
> +
> +  if (PlatformInfo->BoardId =3D=3D TypeWilsonCitySMT) {
> +
> +    DEBUG ((DEBUG_INFO, "PEI UBA init BoardId 0x%X: WilsonCitySMT\n",
> PlatformInfo->BoardId));
> +
> +    Status =3D PeiServicesLocatePpi (
> +              &gUbaConfigDatabasePpiGuid,
> +              0,
> +              NULL,
> +              &UbaConfigPpi
> +              );
> +    if (EFI_ERROR(Status)) {
> +      return Status;
> +    }
> +
> +    Status =3D UbaConfigPpi->InitSku (
> +                       UbaConfigPpi,
> +                       PlatformInfo->BoardId,
> +                       NULL,
> +                       NULL
> +                       );
> +    ASSERT_EFI_ERROR (Status);
> +
> +    Status =3D TypeWilsonCitySMTInstallGpioData (UbaConfigPpi);
> +    if (EFI_ERROR(Status)) {
> +      return Status;
> +    }
> +
> +    Status =3D TypeWilsonCitySMTInstallPcdData (UbaConfigPpi);
> +    if (EFI_ERROR(Status)) {
> +      return Status;
> +    }
> +
> +    Status =3D TypeWilsonCitySMTInstallSoftStrapData (UbaConfigPpi);
> +    if (EFI_ERROR(Status)) {
> +      return Status;
> +    }
> +
> +    Status =3D TypeWilsonCitySMTPchEarlyUpdate (UbaConfigPpi);
> +    if (EFI_ERROR(Status)) {
> +      return Status;
> +    }
> +
> +    Status =3D TypeWilsonCitySMTPlatformUpdateUsbOcMappings
> (UbaConfigPpi);
> +    if (EFI_ERROR(Status)) {
> +      return Status;
> +    }
> +
> +    Status =3D TypeWilsonCitySMTInstallSlotTableData (UbaConfigPpi);
> +    if (EFI_ERROR(Status)) {
> +      return Status;
> +    }
> +
> +    Status =3D TypeWilsonCitySMTInstallKtiEparamData (UbaConfigPpi);
> +    if (EFI_ERROR(Status)) {
> +      return Status;
> +    }
> +
> +    //
> +    // Set default memory type connector to DimmConnectorSmt
> +    //
> +    (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType,
> sizeof (PlatformInfo->MemoryConnectorType), DimmConnectorSmt);
> +
> +    //
> +    // Initialize InterposerType to InterposerUnknown
> +    //
> +    for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; ++SocketIndex) {
> +      PlatformInfo->InterposerType[SocketIndex] =3D InterposerUnknown;
> +    }
> +
> +    //
> +    //  TypeWilsonCitySMTIioPortBifurcationInit will use PlatformInfo-
> >InterposerType for PPO.
> +    //
> +    Status =3D TypeWilsonCitySMTIioPortBifurcationInit (UbaConfigPpi);
> +    if (EFI_ERROR(Status)) {
> +      return Status;
> +    }
> +  }
> +  return Status;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PeiBoardInitLib.inf
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PeiBoardInitLib.inf
> new file mode 100644
> index 0000000000..240f7f82a8
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/PeiBoardInitLib.inf
> @@ -0,0 +1,166 @@
> +## @file
> +# Component information file for BoardInitLib in PEI post memory phase.
> +#
> +# @copyright
> +#  Copyright 2018 - 2021 Intel Corporation.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +# @par Specification Reference:
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    =3D 0x00010005
> +  BASE_NAME                      =3D TypeWilsonCitySMTPeiBoardInitLib
> +  FILE_GUID                      =3D 4A17DF4D-47B2-F538-CEE5-88A2FB46C5D=
3
> +  MODULE_TYPE                    =3D PEIM
> +  VERSION_STRING                 =3D 1.0
> +  LIBRARY_CLASS                  =3D NULL|PEIM
> +  CONSTRUCTOR                    =3D TypeWilsonCitySMTPeiBoardInitLibCon=
structor
> +
> +[LibraryClasses]
> +  BaseLib
> +  DebugLib
> +  BaseMemoryLib
> +  MemoryAllocationLib
> +  PeiServicesLib
> +  HobLib
> +  PeiServicesTablePointerLib
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  WhitleySiliconPkg/WhitleySiliconPkg.dec
> +  WhitleyOpenBoardPkg/PlatformPkg.dec
> +  WhitleySiliconPkg/SiliconPkg.dec
> +  WhitleySiliconPkg/CpRcPkg.dec
> +
> +[Sources]
> +  PeiBoardInitLib.c
> +  GpioTable.c
> +  PcdData.c
> +  UsbOC.c
> +  AcpiTablePcds.c
> +  IioBifurInit.c
> +  SlotTable.c
> +  KtiEparam.c
> +  PchEarlyUpdate.c
> +  SoftStrapFixup.c
> +  PeiBoardInit.h
> +
> +[FixedPcd]
> +
> +[Pcd]
> +  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuBoardID
> +  gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID
> +  gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName
> +  gOemSkuTokenSpaceGuid.PcdOemSkuBoardName
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel
> +  gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel
> +  gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed
> +  gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL
> +  gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10
> +  gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11
> +
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize
> +  gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag
> +  gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO
> +  gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue
> +  gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber
> +  gOemSkuTokenSpaceGuid.PcdOemTableIdXhci
> +  gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex
> +  gPlatformTokenSpaceGuid.PcdBoardTypeBitmask
> +  gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8
> +  gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna
> +  gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr
> +  gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap
> +
> +  gPlatformTokenSpaceGuid.PcdMemInterposerMap
> +  gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId
> +  gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId
> +
> +[Ppis]
> +  gUbaConfigDatabasePpiGuid
> +  gDynamicSiLibraryPpiGuid                  ## CONSUMES
> +
> +[Guids]
> +  gPlatformGpioInitDataGuid
> +
> +[Depex]
> +  gDynamicSiLibraryPpiGuid
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/SlotTable.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/SlotTable.c
> new file mode 100644
> index 0000000000..e9d7c62576
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/SlotTable.c
> @@ -0,0 +1,171 @@
> +/** @file
> +  Slot Table Update.
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiBoardInit.h"
> +#include <Library/UbaSlotUpdateLib.h>
> +#include <IioPlatformData.h>
> +
> +#define PCI_DEVICE_ON_BOARD_TRUE 0
> +#define PCI_DEVICE_ON_BOARD_FALSE 1
> +
> +typedef enum {
> +  Iio_Socket0 =3D 0,
> +  Iio_Socket1,
> +  Iio_Socket2,
> +  Iio_Socket3,
> +  Iio_Socket4,
> +  Iio_Socket5,
> +  Iio_Socket6,
> +  Iio_Socket7
> +} IIO_SOCKETS;
> +
> +typedef enum {
> +  Iio_Iou0 =3D0,
> +  Iio_Iou1,
> +  Iio_Iou2,
> +  Iio_Iou3,
> +  Iio_Iou4,
> +  Iio_IouMax
> +} IIO_IOUS;
> +
> +typedef enum {
> +  Bw5_Addr_0 =3D 0,
> +  Bw5_Addr_1,
> +  Bw5_Addr_2,
> +  Bw5_Addr_3,
> +  Bw5_Addr_Max
> +} BW5_ADDRESS;
> +
> +static UINT8 TypeWilsonCitySMTPchPciSlotImpementedTableData[] =3D {
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 0
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 1
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 2
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 3
> +    PCI_DEVICE_ON_BOARD_TRUE,   // Root Port 4
> +    PCI_DEVICE_ON_BOARD_TRUE,   // Root Port 5
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 6
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 7
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 8
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 9
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 10
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 11
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 12
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 13
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 14
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 15
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 16
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 17
> +    PCI_DEVICE_ON_BOARD_FALSE,  // Root Port 18
> +    PCI_DEVICE_ON_BOARD_FALSE   // Root Port 19
> +};
> +
> +UINT8
> +GetTypeWilsonCitySMTIOU0Setting (
> +  UINT8  IOU0Data
> +)
> +{
> +  //
> +  // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
> +  //
> +  IOU0Data =3D IIO_BIFURCATE_xxx8xxx8;
> +  return IOU0Data;
> +}
> +
> +UINT8
> +GetTypeWilsonCitySMTIOU2Setting (
> +  UINT8  SkuPersonalityType,
> +  UINT8  IOU2Data
> +)
> +{
> +  return IOU2Data;
> +}
> +
> +static IIO_BROADWAY_ADDRESS_DATA_ENTRY
> SlotTypeWilsonCitySMTBroadwayTable[] =3D {
> +    {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
> +    {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
> +    {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
> +};
> +
> +
> +PLATFORM_SLOT_UPDATE_TABLE  TypeWilsonCitySMTSlotTable =3D
> +{
> +  PLATFORM_SLOT_UPDATE_SIGNATURE,
> +  PLATFORM_SLOT_UPDATE_VERSION,
> +
> +  SlotTypeWilsonCitySMTBroadwayTable,
> +  GetTypeWilsonCitySMTIOU0Setting,
> +  0
> +};
> +
> +PLATFORM_SLOT_UPDATE_TABLE2  TypeWilsonCitySMTSlotTable2 =3D
> +{
> +  PLATFORM_SLOT_UPDATE_SIGNATURE,
> +  PLATFORM_SLOT_UPDATE_VERSION,
> +
> +  SlotTypeWilsonCitySMTBroadwayTable,
> +  GetTypeWilsonCitySMTIOU0Setting,
> +  0,
> +  GetTypeWilsonCitySMTIOU2Setting
> +};
> +
> +PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE
> TypeWilsonCitySMTPchPciSlotImplementedTable =3D {
> +  PLATFORM_SLOT_UPDATE_SIGNATURE,
> +  PLATFORM_SLOT_UPDATE_VERSION,
> +
> +  TypeWilsonCitySMTPchPciSlotImpementedTableData
> +};
> +
> +/**
> +  Entry point function for the PEIM
> +
> +  @param FileHandle      Handle of the file being invoked.
> +  @param PeiServices     Describes the list of possible PEI Services.
> +
> +  @return EFI_SUCCESS    If we installed our PPI
> +
> +**/
> +EFI_STATUS
> +TypeWilsonCitySMTInstallSlotTableData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +)
> +{
> +  EFI_STATUS                         Status;
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformSlotDataGuid,
> +                                 &TypeWilsonCitySMTSlotTable,
> +                                 sizeof(TypeWilsonCitySMTSlotTable)
> +                                 );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformSlotDataGuid2,
> +                                 &TypeWilsonCitySMTSlotTable2,
> +                                 sizeof(TypeWilsonCitySMTSlotTable2)
> +                                 );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformPciSlotImplementedGuid,
> +                                 &TypeWilsonCitySMTPchPciSlotImplemented=
Table,
> +                                 sizeof(TypeWilsonCitySMTPchPciSlotImple=
mentedTable)
> +                                 );
> +  if (EFI_ERROR(Status)) {
> +    return Status;
> +  }
> +
> +  return Status;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/SoftStrapFixup.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/SoftStrapFixup.c
> new file mode 100644
> index 0000000000..e59e788ff0
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/SoftStrapFixup.c
> @@ -0,0 +1,120 @@
> +/** @file
> +  Soft Strap update.
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiBoardInit.h"
> +#include <Library/UbaSoftStrapUpdateLib.h>
> +
> +PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY
> TypeWilsonCitySMTSoftStrapTable[] =3D
> +{
> +// SoftStrapNumber, LowBit, BitLength, Value
> +  {3,    1, 1, 0x1 },    // Intel QuickAssist Endpoint 2 (EP[2]) Primary=
 Mux Select
> +  {4,   24, 1, 0x0 },    // 10 GbE MAC Power Gate Control
> +  {15,   4, 2, 0x3 },    // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP=
2)
> +  {15,   6, 2, 0x1 },    // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP=
3)
> +  {15,  18, 1, 0x1 },    // Polarity of GPP_H20 (GPIO polarity of Select=
 between
> sSATA Port 2 and PCIe Port 8)
> +  {16,   4, 2, 0x3 },    // sSATA / PCIe GP Select for Port 2 (SATA_PCIE=
_GP2)
> +  {16,   6, 2, 0x1 },    // sSATA / PCIe GP Select for Port 3 (SATA_PCIE=
_GP3)
> +  {17,   6, 1, 0x0 },    // Intel (R) GbE Legacy PHY over PCIe Enabled
> +  {17,  12, 2, 0x3 },    // sSATA / PCIe Combo Port 2
> +  {18,   0, 2, 0x1 },    // sSATA / PCIe Combo Port 3
> +  {18,   6, 2, 0x3 },    // SATA / PCIe Combo Port 0
> +  {18,   8, 2, 0x3 },    // SATA / PCIe Combo Port 1
> +  {18,  10, 2, 0x3 },    // SATA / PCIe Combo Port 2
> +  {18,  12, 2, 0x3 },    // SATA / PCIe Combo Port 3
> +  {18,  14, 2, 0x3 },    // SATA / PCIe Combo Port 4
> +  {19,   2, 1, 0x1 },    // Polarity Select sSATA / PCIe Combo Port 2
> +  {19,  16, 2, 0x3 },    // SATA / PCIe Combo Port 5
> +  {19,  18, 2, 0x3 },    // SATA / PCIe Combo Port 6
> +  {19,  20, 2, 0x3 },    // SATA / PCIe Combo Port 7
> +  {19,  26, 1, 0x1 },    // Statically assign PCH PCIe NP8 Uplink to act=
 as
> Downlink or Uplink(PCIEUDS)
> +  {33,  24, 7, 0x17},    // IE SMLink1 I2C Target Address
> +  {64,  24, 7, 0x17},    // ME SMLink1 I2C Target Address
> +  {84,  24, 1, 0x0 },    // SMS1 Gbe Legacy MAC SMBus Address Enable
> +  {85,   8, 3, 0x0 },    // SMS1 PMC SMBus Connect
> +  {88,   8, 2, 0x3 },    // Root Port Configuration 0
> +  {93,   0, 2, 0x3 },    // Flex IO Port 18 AUXILLARY Mux Select between=
 SATA
> Port 0 and PCIe Port 12
> +  {93,   2, 2, 0x3 },    // Flex IO Port 19 AUXILLARY Mux Select between=
 SATA
> Port 1 and PCIe Port 13
> +  {93,   4, 2, 0x3 },    // Flex IO Port 20 AUXILLARY Mux Select between=
 SATA
> Port 2 and PCIe Port 14
> +  {94,   0, 2, 0x3 },    // Flex IO Port 21 AUXILLARY Mux Select between=
 SATA
> Port 3 and PCIe Port 15
> +  {94,   2, 2, 0x3 },    // Flex IO Port 22 AUXILLARY Mux Select between=
 SATA
> Port 4 and PCIe Port 16
> +  {94,   4, 2, 0x3 },    // Flex IO Port 23 AUXILLARY Mux Select between=
 SATA
> Port 5 and PCIe Port 17
> +  {94,   6, 2, 0x3 },    // Flex IO Port 24 AUXILLARY Mux Select between=
 SATA
> Port 6 and PCIe Port 18
> +  {94,   8, 2, 0x3 },    // Flex IO Port 25 AUXILLARY Mux Select between=
 SATA
> Port 7 and PCIe Port 19
> +  {102,  0, 2, 0x3 },    // Flex IO Port 18 Mux Select between SATA Port=
 0 and
> PCIe Port 12
> +  {102,  2, 2, 0x3 },    // Flex IO Port 18 Mux Select between SATA Port=
 1 and
> PCIe Port 13
> +  {102,  4, 2, 0x3 },    // Flex IO Port 18 Mux Select between SATA Port=
 2 and
> PCIe Port 14
> +  {102,  6, 2, 0x3 },    // Flex IO Port 18 Mux Select between SATA Port=
 3 and
> PCIe Port 15
> +  {102,  8, 2, 0x3 },    // Flex IO Port 18 Mux Select between SATA Port=
 4 and
> PCIe Port 16
> +  {102, 10, 2, 0x3 },    // Flex IO Port 18 Mux Select between SATA Port=
 5 and
> PCIe Port 17
> +  {102, 12, 2, 0x3 },    // Flex IO Port 18 Mux Select between SATA Port=
 6 and
> PCIe Port 18
> +  {102, 14, 2, 0x3 },    // Flex IO Port 18 Mux Select between SATA Port=
 7 and
> PCIe Port 19
> +  {103, 16, 3, 0x0 },    // GbE Legacy PHY Smbus Connection
> +  {103, 26, 1, 0x0 },    // GbE Legacy LCD SMBus PHY Address Enabled
> +  {103, 27, 1, 0x0 },    // GbE Legacy LC SMBus Address Enabled
> +//  {133,  1, 1, 0x1 },    // Dual I/O  Read Enabled
> +//  {133,  2, 1, 0x1 },    // Quad Output Read Enabled
> +//  {133,  3, 1, 0x1 },    // Quad I/O Read Enabled
> +//  {136, 10, 2, 0x3 },    // eSPI / EC Maximum I/O Mode
> +//  {136, 12, 1, 0x1 },    // Slave 1 (2nd eSPI device) Enable
> +//  {136, 16, 3, 0x4 },    // eSPI / EC Slave 1 Device Bus Frequency
> +//  {136, 19, 2, 0x3 },    // eSPI / EC Slave Device Maximum I/O Mode
> +
> +//
> +// END OF LIST
> +//
> +  {0, 0, 0, 0}
> +};
> +
> +UINT32
> +TypeWilsonCitySMTSystemBoardRevIdValue (VOID)
> +{
> +  EFI_HOB_GUID_TYPE       *GuidHob;
> +  EFI_PLATFORM_INFO       *PlatformInfo;
> +
> +  GuidHob       =3D GetFirstGuidHob (&gEfiPlatformInfoGuid);
> +  ASSERT(GuidHob !=3D NULL);
> +  if (GuidHob =3D=3D NULL) {
> +    return 0xFF;
> +  }
> +  PlatformInfo  =3D GET_GUID_HOB_DATA(GuidHob);
> +  return PlatformInfo->TypeRevisionId;
> +}
> +
> +VOID
> +TypeWilsonCitySMTPlatformSpecificUpdate (
> +  IN OUT  UINT8                 *FlashDescriptorCopy
> +  )
> +{
> +}
> +
> +PLATFORM_PCH_SOFTSTRAP_UPDATE
> TypeWilsonCitySMTSoftStrapUpdate =3D
> +{
> +  PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE,
> +  PLATFORM_SOFT_STRAP_UPDATE_VERSION,
> +  TypeWilsonCitySMTSoftStrapTable,
> +  TypeWilsonCitySMTPlatformSpecificUpdate
> +};
> +
> +EFI_STATUS
> +TypeWilsonCitySMTInstallSoftStrapData (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +  )
> +{
> +  EFI_STATUS                            Status;
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPlatformPchSoftStrapConfigDataGuid,
> +                                 &TypeWilsonCitySMTSoftStrapUpdate,
> +                                 sizeof(TypeWilsonCitySMTSoftStrapUpdate=
)
> +                                 );
> +
> +  return Status;
> +}
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/UsbOC.c
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/UsbOC.c
> new file mode 100644
> index 0000000000..d95fd5490e
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT
> /Pei/UsbOC.c
> @@ -0,0 +1,126 @@
> +/** @file
> +
> +  @copyright
> +  Copyright 2018 - 2021 Intel Corporation. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiBoardInit.h"
> +
> +
> +#include <Library/PcdLib.h>
> +#include <Library/UbaUsbOcUpdateLib.h>
> +#include <PchLimits.h>
> +#include <ConfigBlock/UsbConfig.h>
> +#include <ConfigBlock/Usb2PhyConfig.h>
> +
> +USB_OVERCURRENT_PIN
> TypeWilsonCitySMTUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] =3D
> {
> +                          UsbOverCurrentPin0,
> +                          UsbOverCurrentPin1,
> +                          UsbOverCurrentPin1,
> +                          UsbOverCurrentPin2,
> +                          UsbOverCurrentPin3,
> +                          UsbOverCurrentPin3,
> +                          UsbOverCurrentPin7,
> +                          UsbOverCurrentPin7,
> +                          UsbOverCurrentPin6,
> +                          UsbOverCurrentPin4,
> +                          UsbOverCurrentPin6,
> +                          UsbOverCurrentPin4,
> +                          UsbOverCurrentPin5,
> +                          UsbOverCurrentPin4,
> +                          UsbOverCurrentPinSkip,
> +                          UsbOverCurrentPinSkip
> +                       };
> +
> +USB_OVERCURRENT_PIN
> TypeWilsonCitySMTUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] =3D
> {
> +                          UsbOverCurrentPin0,
> +                          UsbOverCurrentPin1,
> +                          UsbOverCurrentPin1,
> +                          UsbOverCurrentPin2,
> +                          UsbOverCurrentPin3,
> +                          UsbOverCurrentPin3,
> +                          UsbOverCurrentPinSkip,
> +                          UsbOverCurrentPinSkip,
> +                          UsbOverCurrentPinSkip,
> +                          UsbOverCurrentPinSkip
> +                       };
> +
> +USB2_PHY_PARAMETERS
> TypeWilsonCitySMTUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_P
> ORTS] =3D {
> +                        {3, 0, 3, 1},   // PP0
> +                        {5, 0, 3, 1},   // PP1
> +                        {3, 0, 3, 1},   // PP2
> +                        {0, 5, 1, 1},   // PP3
> +                        {3, 0, 3, 1},   // PP4
> +                        {3, 0, 3, 1},   // PP5
> +                        {3, 0, 3, 1},   // PP6
> +                        {3, 0, 3, 1},   // PP7
> +                        {2, 2, 1, 0},   // PP8
> +                        {6, 0, 2, 1},   // PP9
> +                        {2, 2, 1, 0},   // PP10
> +                        {6, 0, 2, 1},   // PP11
> +                        {0, 5, 1, 1},   // PP12
> +                        {7, 0, 2, 1},   // PP13
> +                      };
> +
> +EFI_STATUS
> +TypeWilsonCitySMTPlatformUsbOcUpdateCallback (
> +  IN OUT   USB_OVERCURRENT_PIN   **Usb20OverCurrentMappings,
> +  IN OUT   USB_OVERCURRENT_PIN   **Usb30OverCurrentMappings,
> +  IN OUT   USB2_PHY_PARAMETERS        **Usb20AfeParams
> +)
> +{
> +  *Usb20OverCurrentMappings   =3D
> &TypeWilsonCitySMTUsb20OverCurrentMappings[0];
> +  *Usb30OverCurrentMappings   =3D
> &TypeWilsonCitySMTUsb30OverCurrentMappings[0];
> +
> +  *Usb20AfeParams   =3D TypeWilsonCitySMTUsb20AfeParams;
> +  return EFI_SUCCESS;
> +}
> +
> +PLATFORM_USBOC_UPDATE_TABLE  TypeWilsonCitySMTUsbOcUpdate =3D
> +{
> +   PLATFORM_USBOC_UPDATE_SIGNATURE,
> +   PLATFORM_USBOC_UPDATE_VERSION,
> +   TypeWilsonCitySMTPlatformUsbOcUpdateCallback
> +};
> +
> +EFI_STATUS
> +TypeWilsonCitySMTPlatformUpdateUsbOcMappings (
> +  IN UBA_CONFIG_DATABASE_PPI    *UbaConfigPpi
> +)
> +{
> +  //#
> +  //# USB, see PG 104 in GZP SCH
> +  //#
> +
> +//  USB2      USB3      Port                            OC
> +//
> +//Port00:     PORT5     Back Panel                      ,OC0#
> +//Port01:     PORT2     Back Panel                      ,OC0#
> +//Port02:     PORT3     Back Panel                      ,OC1#
> +//Port03:     PORT0     NOT USED                        ,NA
> +//Port04:               BMC1.0                          ,NA
> +//Port05:               INTERNAL_2X5_A                  ,OC2#
> +//Port06:               INTERNAL_2X5_A                  ,OC2#
> +//Port07:               NOT USED                        ,NA
> +//Port08:               EUSB (AKA SSD)                  ,NA
> +//Port09:               INTERNAL_TYPEA                  ,OC6#
> +//Port10:     PORT1     Front Panel                     ,OC5#
> +//Port11:               NOT USED                        ,NA
> +//Port12:               BMC2.0                          ,NA
> +//Port13:     PORT4     Front Panel                     ,OC5#
> +
> +  EFI_STATUS                   Status;
> +
> +  Status =3D UbaConfigPpi->AddData (
> +                                 UbaConfigPpi,
> +                                 &gPeiPlatformUbaOcConfigDataGuid,
> +                                 &TypeWilsonCitySMTUsbOcUpdate,
> +                                 sizeof(TypeWilsonCitySMTUsbOcUpdate)
> +                                 );
> +
> +  return Status;
> +}
> +
> +
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
> b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
> index 6f367b58e7..f37093bccd 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
> @@ -15,6 +15,7 @@ $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf {
>          <LibraryClasses>
>=20
> NULL|$(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Pei/PeiBoardInitLib.inf
>=20
> NULL|$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Pei/PeiBoardInitLib.inf
> +
> NULL|$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.inf
>             #
>             #### NO PLATFORM SPECIFIC LIBRARY CLASSES AFTER THIS LINE!!!!
>             #
> @@ -42,3 +43,10 @@
> $(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/SlotDataUpdateDxe/Slot
> DataUpdateDxe.i
>=20
> $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/UsbOcUpdateDxe/UsbO
> cUpdateDxe.inf
>=20
> $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/IioCfgUpdateDxe/IioCfg
> UpdateDxe.inf
>=20
> $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/Slot
> DataUpdateDxe.inf
> +
> +#
> +# Platform TypeWilsonCitySMT
> +#
> +$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/Us
> bOcUpdateDxe.inf
> +$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCf
> gUpdateDxe.inf
> +$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/Sl
> otDataUpdateDxe.inf
> --
> 2.27.0.windows.1