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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Thanks for your update. This patch updates PciExpressLib library class to depend on PcdPciExpressBa= seAddress and PcdPciExpressBaseSize both. So, all PciExpressLib library ins= tances (BasePciExpressLib, DxeRuntimePciExpressLib and SmmPciExpressLib) sh= ould be updated. Otherwise, the developer may be confused when he finds Pcd= PciExpressBaseSize doesn't work. Can you let me know why you only update Ba= sePciExpressLib library instance? Thanks Liming -----Original Message----- From: Marcello Sylvester Bauer =20 Sent: 2020=1B$BG/=1B(B7=1B$B7n=1B(B27=1B$BF|=1B(B 16:19 To: devel@edk2.groups.io Cc: Patrick Rudolph ; Christian Walter ; Kinney, Michael D = ; Gao, Liming Subject: [PATCH v4 2/3] MdePkg/BasePciExpressLib: Support variable size MMC= ONF Add support for arbitrary sized MMCONF by introducing a new PCD. Signed-off-by: Patrick Rudolph Signed-off-by: Marcello Sylvester Bauer Cc: Patrick Rudolph Cc: Christian Walter Cc: Michael D Kinney Cc: Liming Gao --- MdePkg/MdePkg.dec | 4 + MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf | 6 +- MdePkg/Include/Library/PciExpressLib.h | 5 +- MdePkg/Library/BasePciExpressLib/PciExpressLib.c | 216 +++++++++++++= ++++--- 4 files changed, 193 insertions(+), 38 deletions(-) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 73f6c2407357..812b= e75fb3b2 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2274,6 +2274,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynami= c, PcdsDynamicEx] # @Prompt PCI Express Base Address. gEfiMdePkgTokenSpaceGuid.PcdPciExp= ressBaseAddress|0xE0000000|UINT64|0x0000000a + ## This value is used to se= t the size of PCI express hierarchy. The default is 256 MB.+ # @Prompt PCI= Express Base Size.+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x1000= 0000|UINT64|0x0000000f+ ## Default current ISO 639-2 language: English & = French. # @Prompt Default Value of LangCodes Variable. gEfiMdePkgTokenS= paceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|VOID*|0x0000001cdif= f --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf b/MdePkg/L= ibrary/BasePciExpressLib/BasePciExpressLib.inf index a7edb74cde71..12734b022ac7 100644 --- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf +++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf @@ -1,7 +1,7 @@ ## @file-# Instance of PCI Express Library using the 256 MB PCI Express M= MIO window.+# Instance of PCI Express Library using the variable size PCI = Express MMIO window. #-# PCI Express Library that uses the 256 MB PCI Expr= ess MMIO window to perform+# PCI Express Library that uses the variable si= ze PCI Express MMIO window to perform # PCI Configuration cycles. Layers o= n top of an I/O Library instance. # # Copyright (c) 2007 - 2018, Intel Cor= poration. All rights reserved.
@@ -38,4 +38,4 @@ [LibraryClasses] [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES-+ = gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMESdiff --git a/Md= ePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Library/PciExpressLib= .h index 826fdcf7db6c..d78193a0a352 100644 --- a/MdePkg/Include/Library/PciExpressLib.h +++ b/MdePkg/Include/Library/PciExpressLib.h @@ -2,8 +2,9 @@ Provides services to access PCI Configuration Space using the MMIO PCI E= xpress window. This library is identical to the PCI Library, except the = access method for performing PCI- configuration cycles must be through the= 256 MB PCI Express MMIO window whose base address- is defined by PcdPciEx= pressBaseAddress.+ configuration cycles must be through the PCI Express MM= IO window whose base address+ is defined by PcdPciExpressBaseAddress and s= ize defined by PcdPciExpressBaseSize.+ Copyright (c) 2006 - 2018, Intel Co= rporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-P= atentdiff --git a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c b/MdePkg= /Library/BasePciExpressLib/PciExpressLib.c index 99a166c3609b..0311ecb3025f 100644 --- a/MdePkg/Library/BasePciExpressLib/PciExpressLib.c +++ b/MdePkg/Library/BasePciExpressLib/PciExpressLib.c @@ -22,7 +22,8 @@ /** Assert the validity of a PCI address. A valid PCI address should co= ntain 1's- only in the low 28 bits.+ only in the low 28 bits. PcdPciExpre= ssBaseSize limits the size to the real+ number of PCI busses in this segme= nt. @param A The address to validate. @@ -79,6 +80,24 @@ GetPciExpressB= aseAddress ( return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress); } +/**+ Gets= the size of PCI Express.++ This internal functions retrieves PCI Express = Base Size via a PCD entry+ PcdPciExpressBaseSize.++ @return The base size= of PCI Express.++**/+STATIC+UINTN+PcdPciExpressBaseSize (+ VOID+ )+{+ r= eturn (UINTN) PcdGet64 (PcdPciExpressBaseSize);+}+ /** Reads an 8-bit PCI= configuration register. @@ -91,7 +110,8 @@ GetPciExpressBaseAddress ( @param Address The address that encodes the PCI Bus, Device, Function a= nd Register. - @return The read value from the PCI confi= guration register.+ @retval 0xFF Invalid PCI address.+ @retval other The= read value from the PCI configuration register. **/ UINT8@@ -101,6 +121,9= @@ PciExpressRead8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioRead8 ((UINTN) Ge= tPciExpressBaseAddress () + Address); } @@ -117,7 +140,8 @@ PciExpressRead8= ( Register. @param Value The value to write. - @retu= rn The value written to the PCI configuration register.+ @retval 0xFF Inv= alid PCI address.+ @retval other The value written to the PCI configuratio= n register. **/ UINT8@@ -128,6 +152,9 @@ PciExpressWrite8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioWrite8 ((UINTN) G= etPciExpressBaseAddress () + Address, Value); } @@ -148,7 +175,8 @@ PciExpr= essWrite8 ( Register. @param OrData The value to OR with the PCI= configuration register. - @return The value written back to the PCI confi= guration register.+ @retval 0xFF Invalid PCI address.+ @retval other The= value written to the PCI configuration register. **/ UINT8@@ -159,6 +187,= 9 @@ PciExpressOr8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioOr8 ((UINTN) GetP= ciExpressBaseAddress () + Address, OrData); } @@ -179,7 +210,8 @@ PciExpres= sOr8 ( Register. @param AndData The value to AND with the PC= I configuration register. - @return The value written back to the PCI conf= iguration register.+ @retval 0xFF Invalid PCI address.+ @retval other Th= e value written back to the PCI configuration register. **/ UINT8@@ -190,6= +222,9 @@ PciExpressAnd8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioAnd8 ((UINTN) Get= PciExpressBaseAddress () + Address, AndData); } @@ -212,7 +247,8 @@ PciExpr= essAnd8 ( @param AndData The value to AND with the PCI configuration register. = @param OrData The value to OR with the result of the AND operation. - @r= eturn The value written back to the PCI configuration register.+ @retval 0= xFF Invalid PCI address.+ @retval other The value written back to the PCI= configuration register. **/ UINT8@@ -224,6 +260,9 @@ PciExpressAndThenOr8= ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioAndThenOr8 ( = (UINTN) GetPciExpressBaseAddress () + Address, AndData,@@= -249,7 +288,9 @@ PciExpressAndThenOr8 ( @param EndBit The ordinal of the most significant bit in the bit fie= ld. Range 0..7. - @return The value of the bit field r= ead from the PCI configuration register.+ @retval 0xFF Invalid PCI addres= s.+ @retval other The value of the bit field read from the PCI configurati= on+ register. **/ UINT8@@ -261,6 +302,9 @@ PciExpressBitFie= ldRead8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldRead8 ( = (UINTN) GetPciExpressBaseAddress () + Address, StartBi= t,@@ -289,7 +333,8 @@ PciExpressBitFieldRead8 ( Range 0..7. @param Value The new value of the b= it field. - @return The value written back to the PCI configuration regist= er.+ @retval 0xFF Invalid PCI address.+ @retval other The value written = back to the PCI configuration register. **/ UINT8@@ -302,6 +347,9 @@ PciEx= pressBitFieldWrite8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldWrite8 ( = (UINTN) GetPciExpressBaseAddress () + Address, StartB= it,@@ -334,7 +382,8 @@ PciExpressBitFieldWrite8 ( Range 0..7. @param OrData The value to OR with t= he PCI configuration register. - @return The value written back to the PCI= configuration register.+ @retval 0xFF Invalid PCI address.+ @retval oth= er The value written back to the PCI configuration register. **/ UINT8@@ -= 347,6 +396,9 @@ PciExpressBitFieldOr8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldOr8 ( = (UINTN) GetPciExpressBaseAddress () + Address, StartBit,= @@ -379,7 +431,8 @@ PciExpressBitFieldOr8 ( Range 0..7. @param AndData The value to AND with = the PCI configuration register. - @return The value written back to the PC= I configuration register.+ @retval 0xFF Invalid PCI address.+ @retval ot= her The value written back to the PCI configuration register. **/ UINT8@@ = -392,6 +445,9 @@ PciExpressBitFieldAnd8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldAnd8 ( = (UINTN) GetPciExpressBaseAddress () + Address, StartBit= ,@@ -428,7 +484,8 @@ PciExpressBitFieldAnd8 ( @param AndData The value to AND with the PCI configuration register. = @param OrData The value to OR with the result of the AND operation. -= @return The value written back to the PCI configuration register.+ @retv= al 0xFF Invalid PCI address.+ @retval other The value written back to the= PCI configuration register. **/ UINT8@@ -442,6 +499,9 @@ PciExpressBitFie= ldAndThenOr8 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT8) ~0;+ } return MmioBitFieldAndThenOr= 8 ( (UINTN) GetPciExpressBaseAddress () + Address, St= artBit,@@ -464,7 +524,8 @@ PciExpressBitFieldAndThenOr8 ( @param Address The address that encodes the PCI Bus, Device, Function a= nd Register. - @return The read value from the PCI confi= guration register.+ @retval 0xFF Invalid PCI address.+ @retval other The= read value from the PCI configuration register. **/ UINT16@@ -474,6 +535,= 9 @@ PciExpressRead16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioRead16 ((UINTN) = GetPciExpressBaseAddress () + Address); } @@ -491,7 +555,8 @@ PciExpressRea= d16 ( Register. @param Value The value to write. - @retu= rn The value written to the PCI configuration register.+ @retval 0xFFFF I= nvalid PCI address.+ @retval other The value written to the PCI configur= ation register. **/ UINT16@@ -502,6 +567,9 @@ PciExpressWrite16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioWrite16 ((UINTN)= GetPciExpressBaseAddress () + Address, Value); } @@ -523,7 +591,8 @@ PciEx= pressWrite16 ( Register. @param OrData The value to OR with the PCI= configuration register. - @return The value written back to the PCI confi= guration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other = The value written back to the PCI configuration register. **/ UINT16@@ -5= 34,6 +603,9 @@ PciExpressOr16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioOr16 ((UINTN) Ge= tPciExpressBaseAddress () + Address, OrData); } @@ -555,7 +627,8 @@ PciExpr= essOr16 ( Register. @param AndData The value to AND with the PC= I configuration register. - @return The value written back to the PCI conf= iguration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other = The value written back to the PCI configuration register. **/ UINT16@@ -= 566,6 +639,9 @@ PciExpressAnd16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioAnd16 ((UINTN) G= etPciExpressBaseAddress () + Address, AndData); } @@ -589,7 +665,8 @@ PciEx= pressAnd16 ( @param AndData The value to AND with the PCI configuration register. = @param OrData The value to OR with the result of the AND operation. - @r= eturn The value written back to the PCI configuration register.+ @retval 0= xFFFF Invalid PCI address.+ @retval other The value written back to the= PCI configuration register. **/ UINT16@@ -601,6 +678,9 @@ PciExpressAndTh= enOr16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioAndThenOr16 ( = (UINTN) GetPciExpressBaseAddress () + Address, AndData,= @@ -627,7 +707,9 @@ PciExpressAndThenOr16 ( @param EndBit The ordinal of the most significant bit in the bit fie= ld. Range 0..15. - @return The value of the bit field = read from the PCI configuration register.+ @retval 0xFFFF Invalid PCI add= ress.+ @retval other The value of the bit field read from the PCI config= uration+ register. **/ UINT16@@ -639,6 +721,9 @@ PciExpre= ssBitFieldRead16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldRead16 (= (UINTN) GetPciExpressBaseAddress () + Address, Start= Bit,@@ -668,7 +753,8 @@ PciExpressBitFieldRead16 ( Range 0..15. @param Value The new value of the = bit field. - @return The value written back to the PCI configuration regis= ter.+ @retval 0xFFFF Invalid PCI address.+ @retval other The value wri= tten back to the PCI configuration register. **/ UINT16@@ -681,6 +767,9 @@= PciExpressBitFieldWrite16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldWrite16 = ( (UINTN) GetPciExpressBaseAddress () + Address, Star= tBit,@@ -714,7 +803,8 @@ PciExpressBitFieldWrite16 ( Range 0..15. @param OrData The value to OR with = the PCI configuration register. - @return The value written back to the PC= I configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval = other The value written back to the PCI configuration register. **/ UINT= 16@@ -727,6 +817,9 @@ PciExpressBitFieldOr16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldOr16 ( = (UINTN) GetPciExpressBaseAddress () + Address, StartBi= t,@@ -760,7 +853,8 @@ PciExpressBitFieldOr16 ( Range 0..15. @param AndData The value to AND with= the PCI configuration register. - @return The value written back to the P= CI configuration register.+ @retval 0xFFFF Invalid PCI address.+ @retval= other The value written back to the PCI configuration register. **/ UIN= T16@@ -773,6 +867,9 @@ PciExpressBitFieldAnd16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldAnd16 ( = (UINTN) GetPciExpressBaseAddress () + Address, StartB= it,@@ -810,7 +907,8 @@ PciExpressBitFieldAnd16 ( @param AndData The value to AND with the PCI configuration register. = @param OrData The value to OR with the result of the AND operation. -= @return The value written back to the PCI configuration register.+ @retv= al 0xFFFF Invalid PCI address.+ @retval other The value written back to= the PCI configuration register. **/ UINT16@@ -824,6 +922,9 @@ PciExpressB= itFieldAndThenOr16 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT16) ~0;+ } return MmioBitFieldAndThenO= r16 ( (UINTN) GetPciExpressBaseAddress () + Address, = StartBit,@@ -846,7 +947,8 @@ PciExpressBitFieldAndThenOr16 ( @param Address The address that encodes the PCI Bus, Device, Function a= nd Register. - @return The read value from the PCI confi= guration register.+ @retval 0xFFFF Invalid PCI address.+ @retval other = The read value from the PCI configuration register. **/ UINT32@@ -856,6 += 958,9 @@ PciExpressRead32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioRead32 ((UINTN) = GetPciExpressBaseAddress () + Address); } @@ -873,7 +978,8 @@ PciExpressRea= d32 ( Register. @param Value The value to write. - @retu= rn The value written to the PCI configuration register.+ @retval 0xFFFFFFF= F Invalid PCI address.+ @retval other The value written to the PCI = configuration register. **/ UINT32@@ -884,6 +990,9 @@ PciExpressWrite32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioWrite32 ((UINTN)= GetPciExpressBaseAddress () + Address, Value); } @@ -905,7 +1014,8 @@ PciE= xpressWrite32 ( Register. @param OrData The value to OR with the PCI= configuration register. - @return The value written back to the PCI confi= guration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval oth= er The value written back to the PCI configuration register. **/ UIN= T32@@ -916,6 +1026,9 @@ PciExpressOr32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioOr32 ((UINTN) Ge= tPciExpressBaseAddress () + Address, OrData); } @@ -937,7 +1050,8 @@ PciExp= ressOr32 ( Register. @param AndData The value to AND with the PC= I configuration register. - @return The value written back to the PCI conf= iguration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval ot= her The value written back to the PCI configuration register. **/ UI= NT32@@ -948,6 +1062,9 @@ PciExpressAnd32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioAnd32 ((UINTN) G= etPciExpressBaseAddress () + Address, AndData); } @@ -971,7 +1088,8 @@ PciE= xpressAnd32 ( @param AndData The value to AND with the PCI configuration register. = @param OrData The value to OR with the result of the AND operation. - @r= eturn The value written back to the PCI configuration register.+ @retval 0= xFFFFFFFF Invalid PCI address.+ @retval other The value written bac= k to the PCI configuration register. **/ UINT32@@ -983,6 +1101,9 @@ PciExp= ressAndThenOr32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioAndThenOr32 ( = (UINTN) GetPciExpressBaseAddress () + Address, AndData,= @@ -1009,7 +1130,9 @@ PciExpressAndThenOr32 ( @param EndBit The ordinal of the most significant bit in the bit fie= ld. Range 0..31. - @return The value of the bit field = read from the PCI configuration register.+ @retval 0xFFFFFFFF Invalid PCI= address.+ @retval other The value of the bit field read from the PC= I+ configuration register. **/ UINT32@@ -1021,6 +1144= ,9 @@ PciExpressBitFieldRead32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldRead32 (= (UINTN) GetPciExpressBaseAddress () + Address, Start= Bit,@@ -1050,7 +1176,8 @@ PciExpressBitFieldRead32 ( Range 0..31. @param Value The new value of the = bit field. - @return The value written back to the PCI configuration regis= ter.+ @retval 0xFFFFFFFF Invalid PCI address.+ @retval other The v= alue written back to the PCI configuration register. **/ UINT32@@ -1063,6 = +1190,9 @@ PciExpressBitFieldWrite32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldWrite32 = ( (UINTN) GetPciExpressBaseAddress () + Address, Star= tBit,@@ -1096,7 +1226,8 @@ PciExpressBitFieldWrite32 ( Range 0..31. @param OrData The value to OR with = the PCI configuration register. - @return The value written back to the PC= I configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @ret= val other The value written back to the PCI configuration register. = **/ UINT32@@ -1109,6 +1240,9 @@ PciExpressBitFieldOr32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldOr32 ( = (UINTN) GetPciExpressBaseAddress () + Address, StartBi= t,@@ -1142,7 +1276,8 @@ PciExpressBitFieldOr32 ( Range 0..31. @param AndData The value to AND with= the PCI configuration register. - @return The value written back to the P= CI configuration register.+ @retval 0xFFFFFFFF Invalid PCI address.+ @re= tval other The value written back to the PCI configuration register. = **/ UINT32@@ -1155,6 +1290,9 @@ PciExpressBitFieldAnd32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldAnd32 ( = (UINTN) GetPciExpressBaseAddress () + Address, StartB= it,@@ -1192,7 +1330,8 @@ PciExpressBitFieldAnd32 ( @param AndData The value to AND with the PCI configuration register. = @param OrData The value to OR with the result of the AND operation. -= @return The value written back to the PCI configuration register.+ @retv= al 0xFFFFFFFF Invalid PCI address.+ @retval other The value written= back to the PCI configuration register. **/ UINT32@@ -1206,6 +1345,9 @@ P= ciExpressBitFieldAndThenOr32 ( ) { ASSERT_INVALID_PCI_ADDRESS (Address);+ if (Address >=3D PcdPciExp= ressBaseSize()) {+ return (UINT32) ~0;+ } return MmioBitFieldAndThenO= r32 ( (UINTN) GetPciExpressBaseAddress () + Address, = StartBit,@@ -1235,7 +1377,8 @@ PciExpressBitFieldAndThenOr32 ( @param Size The size in bytes of the transfer. @param Buffe= r The pointer to a buffer receiving the data read. - @return Size r= ead data from StartAddress.+ @retval (UINTN)~0 Invalid PCI address.+ @re= tval other Size read data from StartAddress. **/ UINTN@@ -1249,6 +139= 2,9 @@ PciExpressReadBuffer ( UINTN ReturnValue; ASSERT_INVALID_PCI_ADDRESS (StartAddress);+ if = (StartAddress >=3D PcdPciExpressBaseSize()) {+ return (UINTN) ~0;+ } = ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); if (Size =3D=3D 0)= {@@ -1335,7 +1481,8 @@ PciExpressReadBuffer ( @param Size The size in bytes of the transfer. @param Buffe= r The pointer to a buffer containing the data to write. - @return S= ize written to StartAddress.+ @retval (UINTN)~0 Invalid PCI address.+ @r= etval other Size written to StartAddress. **/ UINTN@@ -1349,6 +1496,9= @@ PciExpressWriteBuffer ( UINTN ReturnValue; ASSERT_INVALID_PCI_ADD= RESS (StartAddress);+ if (StartAddress >=3D PcdPciExpressBaseSize()) {+ = return (UINTN) ~0;+ } ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x10= 00); if (Size =3D=3D 0) {--=20 2.27.0