Re: [PATCH V4 0/2] CXL Specification Registers

["Liming Gao" <liming.gao@intel.com>]

This version is good to me. Reviewed-by: Liming Gao <liming.gao@intel.com>

-----Original Message-----
From: Javeed, Ashraf <ashraf.javeed@intel.com> 
Sent: 2020年7月25日 2:26
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [PATCH V4 0/2] CXL Specification Registers

These 2 patches introduces the Compute Express Link (CXL) Specificition defined registers.
The Cxl11.h has the actual register definitions of the CXL Specification Revision 1.1; and the Cxl.h is the main header file to include all versions of the CXL register definitions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2611

Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
--

Ashraf Javeed (2):
  MdePkg/Include/IndustryStandard: CXL 1.1 Registers
  MdePkg/Include/IndustryStandard: Main CXL header

 MdePkg/Include/IndustryStandard/Cxl.h   |  22 ++++++++++++++++++++++
 MdePkg/Include/IndustryStandard/Cxl11.h | 569 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 MdePkg/Include/IndustryStandard/Pci.h   |   6 ++----
 3 files changed, 593 insertions(+), 4 deletions(-)  create mode 100644 MdePkg/Include/IndustryStandard/Cxl.h
 create mode 100644 MdePkg/Include/IndustryStandard/Cxl11.h

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