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Thread-Topic: [PATCH v2 1/1] BaseLib:Fix RISC-V Supervisor mode (S-Mode) trap handler reentry issue. Thread-Index: AQHWYAuDRVW3Fs+DjUGsHSUaKmVYeakUWlJQ Date: Thu, 23 Jul 2020 01:04:35 +0000 Message-ID: References: <20200722085351.6153-1-abner.chang@hpe.com> In-Reply-To: <20200722085351.6153-1-abner.chang@hpe.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.2.0.6 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: hpe.com; dkim=none (message not signed) header.d=none;hpe.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.198.147.194] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 55165dc9-81f0-41ee-8593-08d82ea45da4 x-ms-traffictypediagnostic: MW3PR11MB4683: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3631; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: HohC5e6v0SicCCZ8cjtcPZWv+nUgxHZncpqcKUMAjoACBaQl98oIDA76i/Opdjk6f+caCwIDaoMq2FCTG3Tt4mJH7/eoMM8DncX2sAboK2u0MT39yb3B6qnR08QqbzXvc5uIGfPK4peg3xSdVHC7khKkw5fHmzHAXIYoK7nZCsh1Smj8tA9kJe7PQQGFiNa6z5KKpOTKEjNLJR86VXiKLJ6MfnuZMVLg3T54BCc9J3KTnZ5VUrbz8Up1TMJFDZrOxpyqJHNGSEInVpjvxN38jtUrxE+gPRfMHVzwjYmnJV8XSRcl6RmotTuYrjJdctXeX6GXKsYMlLYqkcyU0/ePjw== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR11MB1630.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(4636009)(136003)(346002)(376002)(366004)(396003)(39860400002)(55016002)(9686003)(8676002)(478600001)(186003)(19627235002)(64756008)(66446008)(66556008)(7696005)(52536014)(6506007)(66476007)(83380400001)(53546011)(76116006)(66946007)(316002)(33656002)(26005)(54906003)(8936002)(5660300002)(71200400001)(4326008)(86362001)(2906002)(296002)(110136005);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: BN0mC4TRAaNQXulha1ajMdk8kJCmDiwYru6wLqwmXvJwyq9qbIt0BOLUNA1c2VgeOG/SLiZQC2tLN0sYI17Tz5/UnOyyaLrOLzRZ4QXVMwCTo3YtAW80/yuA0CkW2O/J3Vj324VDXKKk2ZEv66ixreVD6r3+IAJpvm4855+9oouFyjPjp1jc9I3uzTiov7Ks9HD5ccpKw+ZOdshcC8SUSMgqbLd9lW18Os5i+/adtspwI4oaeIBGynM+aYthwPjMHQgF7mrnL6T68yMUFZx/AhkFx/a72aQDYDR4GbXl+EKdocvwu50VF1f3DWP1LErXbSNlMcyS95V/4I4R3Wpy5h6rQ6wffNSt2Z2+3GWGvMqcsumPdZ54VP+KM+x9qlee3C/iPALe0QrZLpbkYn74fpX/vv1iud4cLUdWu6YVMMHLeUJSCZRAbv5b6VQANhnVSI8L0o9chXBS809Gx2yvudGVG7b6wE3qCQ1JvUMBpT9u0wXP5khCJski9GE4mmkM MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR11MB1630.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 55165dc9-81f0-41ee-8593-08d82ea45da4 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Jul 2020 01:04:35.3042 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XP0fEGNR5x4M33H5I6TZPDelGot7yTEQcZXOj8p7gILLlIYLiImjcQfBk75LrrAkifVB6/A5BKn/LA/iMF57cQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR11MB4683 Return-Path: liming.gao@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Acked-by: Liming Gao -----Original Message----- From: Abner Chang =20 Sent: 2020=1B$BG/=1B(B7=1B$B7n=1B(B22=1B$BF|=1B(B 16:54 To: devel@edk2.groups.io Cc: abner.chang@hpe.com; Daniel Schaefer ; Kinney,= Michael D ; Gao, Liming = ; Leif Lindholm Subject: [PATCH v2 1/1] BaseLib:Fix RISC-V Supervisor mode (S-Mode) trap ha= ndler reentry issue. While RISC-V hart is trapped into S-Mode, the S-Mode interrupt CSR (SIE) is= disabled by RISC-V hart. However the (SIE) is enabled again by RestoreTPL,= this causes the second S-Mode trap is triggered by the machine mode (M-Mod= e)timer interrupt redirection. The SRET instruction clear Supervisor Previo= us Privilege (SPP) to zero (User mode) in the second S-Mode interrupt accor= ding to the RISC-V spec. Above brings hart to the user mode (U-Mode) when e= xecute SRET in the nested S-Mode interrupt handler because SPP is set to Us= er Mode in the second interrupt. Afterward, system runs in U-Mode and any a= ccesses to S-Mode CSR causes the invalid instruction exception. Signed-off-by: Abner Chang Reviewed-by: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Daniel Schaefer Cc: Leif Lindholm --- .../Library/BaseLib/RiscV64/RiscVInterrupt.S | 45 ++++++++++++++++--- 1 file changed, 38 insertions(+), 7 deletions(-) diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Libra= ry/BaseLib/RiscV64/RiscVInterrupt.S index 766fcfb9cb..e821124781 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S @@ -12,21 +12,52 @@ ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts= ) ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt) ASM_GLOBAL ASM_PFX(= RiscVGetSupervisorModeInterrupts) -# define MSTATUS_SIE 0x00000002-# de= fine CSR_SSTATUS 0x100+#define SSTATUS_SIE 0x00000002+= #define CSR_SSTATUS 0x100+#define SSTATUS_SPP_BIT_POSITIO= N 8 +//+// This routine disables supervisor mode interrupt+// ASM_PFX(Ri= scVDisableSupervisorModeInterrupts):- li a1, MSTATUS_SIE- csrc CSR_SSTA= TUS, a1+ add sp, sp, -(__SIZEOF_POINTER__)+ sd a1, (sp)+ li a1, = SSTATUS_SIE+ csrc CSR_SSTATUS, a1+ ld a1, (sp)+ add sp, sp, (__SIZ= EOF_POINTER__) ret +//+// This routine enables supervisor mode interrupt+= // ASM_PFX(RiscVEnableSupervisorModeInterrupt):- li a1, MSTATUS_SIE- cs= rs CSR_SSTATUS, a1+ add sp, sp, -2*(__SIZEOF_POINTER__)+ sd a0, (0*_= _SIZEOF_POINTER__)(sp)+ sd a1, (1*__SIZEOF_POINTER__)(sp)++ csrr a0, = CSR_SSTATUS+ and a0, a0, (1 << SSTATUS_SPP_BIT_POSITION)+ bnez a0, InT= rap // We are in supervisor mode (SMode)+ // tr= ap handler.+ // Skip enabling SIE becasue SIE+ = // is set to disabled by RISC-V hart+ = // when the trap takes hart to SMode.++ li a1, SSTATUS_SIE+ csrs = CSR_SSTATUS, a1+InTrap:+ ld a0, (0*__SIZEOF_POINTER__)(sp)+ ld a1, = (1*__SIZEOF_POINTER__)(sp)+ add sp, sp, 2*(__SIZEOF_POINTER__) ret +//= +// This routine returns supervisor mode interrupt+// status.+// ASM_PFX(Ri= scVGetSupervisorModeInterrupts): csrr a0, CSR_SSTATUS- andi a0, a0, MSTA= TUS_SIE+ andi a0, a0, SSTATUS_SIE ret --=20 2.25.0