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Fri, 3 Jul 2020 01:54:18 +0000 From: "Liming Gao" To: "devel@edk2.groups.io" , "Lohr, Paul A" , "Yao, Jiewen" , "De Leon Vazquez, Lorena R" CC: "Kinney, Michael D" Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix Thread-Topic: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix Thread-Index: AdXw5cIqcI9g1CYLQByg/sbQxnIlIgABtlAQF+LrE7AAGPt4IA== Date: Fri, 3 Jul 2020 01:54:18 +0000 Message-ID: References: <74D8A39837DF1E4DA445A8C0B3885C503F96301F@shsmsx102.ccr.corp.intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.2.0.6 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.198.147.219] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: b93f4f12-65ce-414a-6217-08d81ef3ffc4 x-ms-traffictypediagnostic: MWHPR11MB1744: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; 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boundary="_000_MWHPR11MB1630D840F159DD04403E4F20806A0MWHPR11MB1630namp_" --_000_MWHPR11MB1630D840F159DD04403E4F20806A0MWHPR11MB1630namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Paul: This patch is missing to be merged. Lorena: I can't extract the patch from the mail. Can you send the patch to me? I= can help merge it. Thanks Liming From: devel@edk2.groups.io On Behalf Of Lohr, Paul = A Sent: Thursday, July 2, 2020 9:56 PM To: devel@edk2.groups.io; Yao, Jiewen ; De Leon Vazq= uez, Lorena R Cc: Kinney, Michael D Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU = generic bug fix Hello, It seems this did not get checked in. Is there something wrong with the p= atch itself? Or was this simply submitted incorrectly? I don't see a Bugz= illa associated with it is why I ask. Paul A. Lohr - Server Firmware Enabling 512.239.9073 (cell) 512.794.5044 (work) From: devel@edk2.groups.io > On Behalf Of Yao, Jiewen Sent: Monday, March 2, 2020 5:46 PM To: De Leon Vazquez, Lorena R >; devel@edk2.groups.io Cc: Kinney, Michael D > Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU = generic bug fix Reviewed-by: jiewen.yao@intel.com From: De Leon Vazquez, Lorena R > Sent: Tuesday, March 3, 2020 7:04 AM To: devel@edk2.groups.io Cc: Yao, Jiewen >; Kinne= y, Michael D = > Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bug fix Looks like Addresswidth is BIT wise values. Right now these values are not= used any Suggested-by: Star Zeng star.zeng@intel.com Signed-off-by: lorena.r.de.leon.vazquez@intel.com -- .../Feature/VTd/IntelVTdDxe/TranslationTable.c | 11 ++++------- .../Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 11 ++++------- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transla= tionTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transla= tionTable.c index cc970c0..61fbb4a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTab= le.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTab= le.c @@ -128,14 +128,11 @@ CreateContextEntry ( DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInfor= mation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId= .Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0= ) { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VT= D %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Ro= otEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transla= tionTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Trans= lationTableEx.c index 0da1611..6bd31b7 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTab= leEx.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTab= leEx.c @@ -78,14 +78,11 @@ CreateExtContextEntry ( DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInfo= rmation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceI= d.Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ExtContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ExtContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0= ) { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VT= D %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Ex= tRootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); -- 2.21.0.windows.1 --_000_MWHPR11MB1630D840F159DD04403E4F20806A0MWHPR11MB1630namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Paul:

  This patch is missing to be merged.

 

Lorena:

  I can’t extract the patch from th= e mail. Can you send the patch to me? I can help merge it.

 

Thanks

Liming

From: devel@edk2.groups.io <devel@edk2.gr= oups.io> On Behalf Of Lohr, Paul A
Sent: Thursday, July 2, 2020 9:56 PM
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@intel.com>;= De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg:= IOMMU generic bug fix

 

Hello,

 

It seems this did not get checked in.  Is ther= e something wrong with the patch itself?  Or was this simply submitted= incorrectly?  I don’t see a Bugzilla associated with it is why = I ask.

 

Paul A. Lohr – S= erver Firmware Enabling

512.239.9073 (cell)<= /o:p>

512.794.5044 (work)<= /o:p>

 

From: devel@edk2.groups.io <deve= l@edk2.groups.io> On Behalf Of Yao, Jiewen
Sent: Monday, March 2, 2020 5:46 PM
To: De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@intel.com>; devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@intel.com>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH] IntelSiliconPkg:= IOMMU generic bug fix

 

Reviewed-by: jiewen.yao@intel.com

 

From: De Leon Vazquez, Lorena R <lorena.r.de.leon.vazquez@in= tel.com>
Sent: Tuesday, March 3, 2020 7:04 AM
To: devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.= yao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: [edk2-platforms] [PATCH] IntelSiliconPkg: IOMMU generic bu= g fix

 

Looks like Addresswidth is BIT wise values. Right n= ow these values are not used any

 

Suggested-by: Sta= r Zeng star.zeng@intel.com<= /span>

Signed-off-by: lorena.r.de.leon.vaz= quez@intel.com

 

--

.../Feature/VTd/IntelVTdDxe/TranslationTable.c = ;       | 11 ++++-------=

.../Feature/VTd/IntelVTdDxe/TranslationTableEx.c&nb= sp;     | 11 ++++-------

2 files changed, 8 insertions(+), 14 deletions(= -)

 

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/= VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/= VTd/IntelVTdDxe/TranslationTable.c

index cc970c0..61fbb4a 100644

--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Int= elVTdDxe/TranslationTable.c

+++ b/Silicon/Intel/IntelSiliconPkg/Fea= ture/VTd/IntelVTdDxe/TranslationTable.c

@@ -128,14 +128,11 @@ CreateContextEntry (=

 

     DEBUG ((DEBUG_INFO,&q= uot;Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].= Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));=

 

-    switch (mVtdUnitInformation[Vtd= Index].CapReg.Bits.SAGAW) {

-    case BIT1:

-      ContextEntry->Bi= ts.AddressWidth =3D 0x1;

-      break;

-    case BIT2:

-      ContextEntry->Bi= ts.AddressWidth =3D 0x2;

-      break;

+    if ((mVtdUnitInformation[Vt= dIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) {

+      DEBUG((DEBUG_ER= ROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n",= VtdIndex));

+      return error;

     }

+    ContextEntry->Bits.Addre= ssWidth =3D 0x2;

   }

 

   FlushPageTableMemory (VtdIndex, (= UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(Entry= TablePages));

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/= VTd/IntelVTdDxe/TranslationTableEx.c b/Silicon/Intel/IntelSiliconPkg/Featur= e/VTd/IntelVTdDxe/TranslationTableEx.c

index 0da1611..6bd31b7 100644

--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Int= elVTdDxe/TranslationTableEx.c

+++ b/Silicon/Intel/IntelSiliconPkg/Fea= ture/VTd/IntelVTdDxe/TranslationTableEx.c

@@ -78,14 +78,11 @@ CreateExtContextEntry (

 

     DEBUG ((DEBUG_INFO,&q= uot;DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex]= .Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function))= ;

 

-    switch (mVtdUnitInformation[Vtd= Index].CapReg.Bits.SAGAW) {

-    case BIT1:

-      ExtContextEntry->= ;Bits.AddressWidth =3D 0x1;

-      break;

-    case BIT2:

-      ExtContextEntry->= ;Bits.AddressWidth =3D 0x2;

-      break;

+    if ((mVtdUnitInformation[Vt= dIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) {

+      DEBUG((DEBUG_ER= ROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n",= VtdIndex));

+      return error;

     }

+    ContextEntry->Bits.Addre= ssWidth =3D 0x2;

   }

 

   FlushPageTableMemory (VtdIndex, (= UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(En= tryTablePages));

--

2.21.0.windows.1

 

--_000_MWHPR11MB1630D840F159DD04403E4F20806A0MWHPR11MB1630namp_--