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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Doran, Which platform are you using? I thought those platforms are quite old and n= o one is using them. > -----Original Message----- > From: Oram, Isaac W > Sent: Tuesday, August 30, 2022 6:27 AM > To: Benjamin Doron ; devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Sinha, Ankit = ; Ni, Ray > ; Chaganty, Rangasai V > Subject: RE: [edk2-devel][edk2-platforms][PATCH v1 1/5] IntelSiliconPkg/F= eature/PeiSmmAccessLibSmramc: Implement > chipset support >=20 > Reviewed-by: Isaac Oram >=20 > I would prefer to see contents of sections indented, but it is a nit. > It might be slightly better to have PcdsFixedAtBuild type PCD for the reg= ister information, but this is pretty stable HW, so it > is ok. >=20 > Regards, > Isaac >=20 > -----Original Message----- > From: Benjamin Doron > Sent: Monday, August 29, 2022 1:36 PM > To: devel@edk2.groups.io > Cc: Desimone, Nathaniel L ; Sinha, Ankit = ; Ni, Ray > ; Chaganty, Rangasai V ;= Oram, Isaac W > Subject: [edk2-devel][edk2-platforms][PATCH v1 1/5] IntelSiliconPkg/Featu= re/PeiSmmAccessLibSmramc: Implement > chipset support >=20 > SMRAM must be opened to retrieve the lockbox for S3, and SMM communicatio= n depends on this PPI. For security > purposes, SMRAM lock must be performed before EndOfPei (although FSP noti= fy performs lockdown too). >=20 > It seems to me that this library is generic and applicable to all Intel p= latforms in the tree using the MCH SMRAMC register. >=20 > Cc: Nate DeSimone > Cc: Ankit Sinha > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Isaac Oram > Signed-off-by: Benjamin Doron > --- > .../PeiSmmAccessLibSmramc/PeiSmmAccessLib.c | 430 ++++++++++++++++++ > .../PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf | 41 ++ > 2 files changed, 471 insertions(+) > create mode 100644 > Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.c > create mode 100644 > Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf >=20 > diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiS= mmAccessLibSmramc/PeiSmmAccessLib.c > b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib= Smramc/PeiSmmAccessLib.c > new file mode 100644 > index 000000000000..5b472bf86abf > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce > +++ ssLibSmramc/PeiSmmAccessLib.c > @@ -0,0 +1,430 @@ > +/** @file+ This is to publish the SMM Access Ppi instance.++ Copyright= (c) 2019 - 2020, Intel Corporation. All rights > reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#includ= e +#include > +#include +#include +#include > +#include +#include +#include > ++#include +#include ++#define > SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a')++///+= /// Private data+///+typedef struct {+ > UINTN Signature;+ EFI_HANDLE Handle;+ EFI_PE= I_MM_ACCESS_PPI SmmAccess;+ //+ // Local Data for > SMM Access interface goes here+ //+ UINTN NumberRegions= ;+ EFI_SMRAM_DESCRIPTOR *SmramDesc;+} > SMM_ACCESS_PRIVATE_DATA;++#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \+= CR (a, \+ > SMM_ACCESS_PRIVATE_DATA, \+ SmmAccess, \+ SMM_ACCESS_PR= IVATE_DATA_SIGNATURE \+ )++//+// > Common registers:+//+// DEVICE 0 (Memory Controller Hub)+//+#define SA_MC= _BUS 0x00+#define SA_MC_DEV > 0x00+#define SA_MC_FUN 0x00+///+/// Description:+/// The SMRAMC= register controls how accesses to Compatible > SMRAM spaces are treated. The Open, Close and Lock bits function only wh= en G_SMRAME bit is set to 1. Also, the Open > bit must be reset before the Lock bit is set.+///+#define R_SA_SMRAMC (0= x88)+#define B_SA_SMRAMC_D_LCK_MASK > (0x10)+#define B_SA_SMRAMC_D_CLS_MASK (0x20)+#define B_SA_SMRAMC_D_OP= EN_MASK (0x40)++/**+ This > routine accepts a request to "open" a region of SMRAM. The+ region coul= d be legacy ABSEG, HSEG, or TSEG near top of > physical memory.+ The use of "open" means that the memory is visible fro= m all PEIM+ and SMM agents.++ @param[in] > PeiServices - General purpose services available to every PEIM.+= @param[in] This - Pointer to the SMM Access > Interface.+ @param[in] DescriptorIndex - Region of SMRAM to Open.++= @retval EFI_SUCCESS - The region was > successfully opened.+ @retval EFI_DEVICE_ERROR - The region could= not be opened because locked by+ > chipset.+ @retval EFI_INVALID_PARAMETER - The descriptor index was out= of bounds.+**/+EFI_STATUS+EFIAPI+Open > (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_P= PI *This,+ IN UINTN > DescriptorIndex+ )+{+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ UINT8 = Index;+ UINT64 Address;+ > UINT8 SmramControl;++ SmmAccess =3D SMM_ACCESS_PRIVATE= _DATA_FROM_THIS (This);+ if > (DescriptorIndex >=3D SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN,= "SMRAM region out of range\n"));++ > return EFI_INVALID_PARAMETER;+ } else if (SmmAccess->SmramDesc[Descripto= rIndex].RegionState & > EFI_SMRAM_LOCKED) {+ //+ // Cannot open a "locked" region+ //+ = DEBUG ((DEBUG_WARN, "Cannot open a locked > SMRAM region\n"));++ return EFI_DEVICE_ERROR;+ }++ ///+ /// BEGIN C= HIPSET CODE+ ///+ ///+ /// SMRAM register > is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Address =3D PCI_SEGMENT_LIB_ADDRE= SS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, > R_SA_SMRAMC);+ SmramControl =3D PciSegmentRead8 (Address);+ ///+ /// = Is SMRAM locked?+ ///+ if ((SmramControl > & B_SA_SMRAMC_D_LCK_MASK) !=3D 0) {+ ///+ /// Cannot Open a locked = region+ ///+ for (Index =3D 0; Index < > SmmAccess->NumberRegions; Index++) {+ SmmAccess->SmramDesc[Index].Re= gionState |=3D > EFI_SMRAM_LOCKED;+ }+ DEBUG ((DEBUG_WARN, "Cannot open a locked SMR= AM region\n"));+ return > EFI_DEVICE_ERROR;+ }+ ///+ /// Open SMRAM region+ ///+ SmramControl = |=3D B_SA_SMRAMC_D_OPEN_MASK;+ > SmramControl &=3D ~(B_SA_SMRAMC_D_CLS_MASK);++ PciSegmentWrite8 (Address= , SmramControl);+ ///+ /// END > CHIPSET CODE+ ///++ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= =3D (UINT64) ~(EFI_SMRAM_CLOSED | > EFI_ALLOCATED);+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D = (UINT64) EFI_SMRAM_OPEN;+ > SmmAccess->SmmAccess.OpenState =3D TRUE;+ return EFI_SUCCESS;+}++/**+ T= his routine accepts a request to "close" a > region of SMRAM. This is valid for+ compatible SMRAM region.++ @param[= in] PeiServices - General purpose services > available to every PEIM.+ @param[in] This - Pointer to t= he SMM Access Interface.+ @param[in] DescriptorIndex > - Region of SMRAM to Close.++ @retval EFI_SUCCESS - The reg= ion was successfully closed.+ @retval > EFI_DEVICE_ERROR - The region could not be closed because locked b= y+ chipset.+ @retval > EFI_INVALID_PARAMETER - The descriptor index was out of bounds.+**/+EFI= _STATUS+EFIAPI+Close (+ IN > EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This= ,+ IN UINTN DescriptorIndex+ )+{+ > SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ BOOLEAN OpenState;+= UINT8 Index;+ UINT64 > Address;+ UINT8 SmramControl;++ SmmAccess =3D SMM_ACC= ESS_PRIVATE_DATA_FROM_THIS (This);+ if > (DescriptorIndex >=3D SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN,= "SMRAM region out of range\n"));++ > return EFI_INVALID_PARAMETER;+ } else if (SmmAccess->SmramDesc[Descripto= rIndex].RegionState & > EFI_SMRAM_LOCKED) {+ //+ // Cannot close a "locked" region+ //+ = DEBUG ((DEBUG_WARN, "Cannot close a locked > SMRAM region\n"));++ return EFI_DEVICE_ERROR;+ }++ if (SmmAccess->Sm= ramDesc[DescriptorIndex].RegionState & > EFI_SMRAM_CLOSED) {+ return EFI_DEVICE_ERROR;+ }++ ///+ /// BEGIN C= HIPSET CODE+ ///+ ///+ /// SMRAM > register is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Address =3D PCI_SEGMENT_= LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, > SA_MC_FUN, R_SA_SMRAMC);+ SmramControl =3D PciSegmentRead8 (Address);+ = ///+ /// Is SMRAM locked?+ ///+ if > ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) !=3D 0) {+ ///+ /// Cannot= Close a locked region+ ///+ for (Index =3D 0; > Index < SmmAccess->NumberRegions; Index++) {+ SmmAccess->SmramDesc[I= ndex].RegionState |=3D > EFI_SMRAM_LOCKED;+ }+ DEBUG ((DEBUG_WARN, "Cannot close a locked SM= RAM region\n"));+ return > EFI_DEVICE_ERROR;+ }+ ///+ /// Close SMRAM region+ ///+ SmramControl= &=3D ~(B_SA_SMRAMC_D_OPEN_MASK);++ > PciSegmentWrite8 (Address, SmramControl);+ ///+ /// END CHIPSET CODE+ = ///++ SmmAccess- > >SmramDesc[DescriptorIndex].RegionState &=3D (UINT64) ~EFI_SMRAM_OPEN;+ = SmmAccess- > >SmramDesc[DescriptorIndex].RegionState |=3D (UINT64) (EFI_SMRAM_CLOSED |= EFI_ALLOCATED);++ //+ // Find out if any > regions are still open+ //+ OpenState =3D FALSE;+ for (Index =3D 0; In= dex < SmmAccess->NumberRegions; Index++) {+ if > ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) =3D=3D EFI_SM= RAM_OPEN) {+ OpenState =3D > TRUE;+ }+ }++ SmmAccess->SmmAccess.OpenState =3D OpenState;+ return= EFI_SUCCESS;+}++/**+ This routine accepts a > request to "lock" SMRAM. The+ region could be legacy AB or TSEG near to= p of physical memory.+ The use of "lock" means > that the memory can no longer be opened+ to PEIM.++ @param[in] PeiServi= ces - General purpose services available > to every PEIM.+ @param[in] This - Pointer to the SMM Acc= ess Interface.+ @param[in] DescriptorIndex - Region > of SMRAM to Lock.++ @retval EFI_SUCCESS - The region was suc= cessfully locked.+ @retval EFI_DEVICE_ERROR - > The region could not be locked because at least+ = one range is still open.+ @retval > EFI_INVALID_PARAMETER - The descriptor index was out of bounds.+**/+EFI= _STATUS+EFIAPI+Lock (+ IN > EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *= This,+ IN UINTN DescriptorIndex+ )+{+ > SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ UINT64 Address;+ = UINT8 SmramControl;++ SmmAccess =3D > SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ if (DescriptorIndex >=3D SmmA= ccess->NumberRegions) {+ DEBUG > ((DEBUG_WARN, "SMRAM region out of range\n"));++ return EFI_INVALID_PA= RAMETER;+ } else if (SmmAccess- > >SmmAccess.OpenState) {+ DEBUG ((DEBUG_WARN, "Cannot lock SMRAM when S= MRAM regions are still open\n"));++ > return EFI_DEVICE_ERROR;+ }++ SmmAccess->SmramDesc[DescriptorIndex].Reg= ionState |=3D (UINT64) > EFI_SMRAM_LOCKED;+ SmmAccess->SmmAccess.LockState =3D TRUE;++ ///+ ///= BEGIN CHIPSET CODE+ ///+ ///+ /// > SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Address =3D PCI_SE= GMENT_LIB_ADDRESS (0, SA_MC_BUS, > SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);+ SmramControl =3D PciSegmentRead8 (A= ddress);++ ///+ /// Lock the > SMRAM+ ///+ SmramControl |=3D B_SA_SMRAMC_D_LCK_MASK;++ PciSegmentWrit= e8 (Address, SmramControl);+ ///+ > /// END CHIPSET CODE+ ///++ return EFI_SUCCESS;+}++/**+ This routine s= ervices a user request to discover the > SMRAM+ capabilities of this platform. This will report the possible+ r= anges that are possible for SMRAM access, based > upon the+ memory controller capabilities.++ @param[in] PeiServices = - General purpose services available to every > PEIM.+ @param[in] This - Pointer to the SMRAM Access Inte= rface.+ @param[in, out] SmramMapSize - Pointer to > the variable containing size of the+ bu= ffer to contain the description information.+ @param[in, out] > SmramMap - Buffer containing the data describing the Smram+ = region descriptors.++ @retval > EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer.+ = @retval EFI_SUCCESS - The user provided a > sufficiently-sized buffer.+**/+EFI_STATUS+EFIAPI+GetCapabilities (+ IN E= FI_PEI_SERVICES **PeiServices,+ IN > EFI_PEI_MM_ACCESS_PPI *This,+ IN OUT UINTN = *SmramMapSize,+ IN OUT EFI_SMRAM_DESCRIPTOR > *SmramMap+ )+{+ EFI_STATUS Status;+ SMM_ACCESS_PRIVATE_DA= TA *SmmAccess;+ UINTN > NecessaryBufferSize;++ SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_F= ROM_THIS (This);+ NecessaryBufferSize =3D > SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DESCRIPTOR);+ if (*SmramMap= Size < NecessaryBufferSize) {+ > DEBUG ((DEBUG_WARN, "SMRAM Map Buffer too small\n"));++ Status =3D EFI= _BUFFER_TOO_SMALL;+ } else {+ > CopyMem (SmramMap, SmmAccess->SmramDesc, NecessaryBufferSize);+ Status= =3D EFI_SUCCESS;+ }++ *SmramMapSize > =3D NecessaryBufferSize;+ return Status;+}++/**+ This function is to in= stall an SMM Access PPI+ - Introduction \n+ > An API to install an instance of EFI_PEI_MM_ACCESS_PPI. This PPI is commo= nly used to control SMM mode memory access > for S3 resume.++ @retval EFI_SUCCESS - Ppi successfully star= ted and installed.+ @retval EFI_NOT_FOUND - Ppi > can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have eno= ugh resources to initialize the > driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmAccessPpi (+ VOID+ )+{+ EFI= _STATUS Status;+ UINTN > Index;+ EFI_PEI_PPI_DESCRIPTOR *PpiList;+ EFI_SMRAM_HOB_DESCRI= PTOR_BLOCK *DescriptorBlock;+ > SMM_ACCESS_PRIVATE_DATA *SmmAccessPrivate;+ VOID = *HobList;++ //+ // Initialize private data+ > //+ SmmAccessPrivate =3D AllocateZeroPool (sizeof (*SmmAccessPrivate));= + ASSERT (SmmAccessPrivate !=3D NULL);+ if > (SmmAccessPrivate =3D=3D NULL) {+ return EFI_OUT_OF_RESOURCES;+ }+ P= piList =3D AllocateZeroPool (sizeof > (*PpiList));+ ASSERT (PpiList !=3D NULL);+ if (PpiList =3D=3D NULL) {+ = return EFI_OUT_OF_RESOURCES;+ }++ > SmmAccessPrivate->Signature =3D SMM_ACCESS_PRIVATE_DATA_SIGNATURE;+ SmmA= ccessPrivate->Handle =3D NULL;++ > //+ // Get Hob list+ //+ HobList =3D GetFirstGuidHob (&gEfiSmmSmramMem= oryGuid);+ if (HobList =3D=3D NULL) {+ DEBUG > ((DEBUG_WARN, "SmramMemoryReserve HOB not found\n"));+ return EFI_NOT_= FOUND;+ }++ DescriptorBlock =3D > (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) ((UINT8 *) HobList + sizeof (EFI_HOB_G= UID_TYPE));++ //+ // Alloc space for > SmmAccessPrivate->SmramDesc+ //+ SmmAccessPrivate->SmramDesc =3D Alloca= teZeroPool ((DescriptorBlock- > >NumberOfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR));+ if (SmmA= ccessPrivate->SmramDesc =3D=3D NULL) > {+ DEBUG ((DEBUG_WARN, "Alloc SmmAccessPrivate->SmramDesc fail.\n"));+= return EFI_OUT_OF_RESOURCES;+ }++ > DEBUG ((DEBUG_INFO, "Alloc SmmAccessPrivate->SmramDesc success.\n"));++ = //+ // use the hob to publish SMRAM > capabilities+ //+ for (Index =3D 0; Index < DescriptorBlock->NumberOfSm= mReservedRegions; Index++) {+ > SmmAccessPrivate->SmramDesc[Index].PhysicalStart =3D DescriptorBlock->De= scriptor[Index].PhysicalStart;+ > SmmAccessPrivate->SmramDesc[Index].CpuStart =3D DescriptorBlock->De= scriptor[Index].CpuStart;+ > SmmAccessPrivate->SmramDesc[Index].PhysicalSize =3D DescriptorBlock->De= scriptor[Index].PhysicalSize;+ > SmmAccessPrivate->SmramDesc[Index].RegionState =3D DescriptorBlock->De= scriptor[Index].RegionState;+ }++ > SmmAccessPrivate->NumberRegions =3D Index;+ SmmAccessPrivate= ->SmmAccess.Open =3D Open;+ > SmmAccessPrivate->SmmAccess.Close =3D Close;+ SmmAccessPrivate= ->SmmAccess.Lock =3D Lock;+ > SmmAccessPrivate->SmmAccess.GetCapabilities =3D GetCapabilities;+ SmmAcc= essPrivate->SmmAccess.LockState =3D > FALSE;+ SmmAccessPrivate->SmmAccess.OpenState =3D FALSE;++ //+ /= / Install PPI+ //+ PpiList->Flags =3D > (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);+ P= piList->Guid =3D > &gEfiPeiMmAccessPpiGuid;+ PpiList->Ppi =3D &SmmAccessPrivate->SmmAcce= ss;++ Status =3D PeiServicesInstallPpi > (PpiList);+ ASSERT_EFI_ERROR (Status);++ return EFI_SUCCESS;+}diff --gi= t > a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib= Smramc/PeiSmmAccessLib.inf > b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib= Smramc/PeiSmmAccessLib.inf > new file mode 100644 > index 000000000000..916346aacff3 > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce > +++ ssLibSmramc/PeiSmmAccessLib.inf > @@ -0,0 +1,41 @@ > +## @file+# Library description file for the SmmAccess PPI+#+# Copyright > +(c) 2019, Intel Corporation. All rights reserved.
+# > +SPDX-License-Identifier: > +BSD-2-Clause-Patent+#+##++[Defines]+INF_VERSION =3D 0x00010017+BASE_NAME > +=3D PeiSmmAccessLibSmramc+FILE_GUID =3D > +3D28FD4B-F46F-4E24-88AA-9DA09C51BE87+VERSION_STRING =3D 1.0+MODULE_TYPE = =3D PEIM+LIBRARY_CLASS =3D > SmmAccessLib+++[LibraryClasses]+BaseMemoryLib+MemoryAllocationLib+DebugLi= b+HobLib+PciSegmentLib+PeiServicesL > ib+++[Packages]+MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec+++[= Sources]+PeiSmmAccessLib.c+++[Ppis]+gE > fiPeiMmAccessPpiGuid ## PRODUCES+++[Guids]+gEfiSmmSmramMemoryGuid-- > 2.37.2