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Thread-Topic: [PATCH v2 4/6] UefiCpuPkg: Replace Opcode with the corresponding instructions. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni -----Original Message----- From: Lou, Yun =20 Sent: Monday, January 10, 2022 11:13 PM To: devel@edk2.groups.io Cc: Lou, Yun ; Ni, Ray ; Dong, Eric ; Laszlo Ersek ; Kumar, Rahul1 Subject: [PATCH v2 4/6] UefiCpuPkg: Replace Opcode with the corresponding i= nstructions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be= used to compare the results of two different EDK II builds to determine if= they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou Cc: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm = | 4 +-- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm = | 11 +++++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm = | 9 +++---- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm = | 14 +++++------ UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.na= sm | 26 ++++++++++---------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm = | 6 ++--- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm = | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm = | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm = | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm = | 4 +-- 10 files changed, 43 insertions(+), 43 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm b/UefiCpuPkg/CpuDxe/X64/CpuA= sm.nasm index 66f8857fc0..a894ff53ad 100644 --- a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm +++ b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= ----- ;*-;* Copyright (c) 2016, Intel Corporation. All rights reserved.+;* Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<= BR> ;* SPDX-License-Identifier: BSD-2-Clause-Patent ;* ;* CpuAsm.nasm@= @ -23,7 +23,7 @@ ASM_PFX(SetCodeSelector): push rcx lea rax, [setCodeSelectorLongJump] push rax= - o64 retf+ retfq setCodeSelectorLongJump: ret diff --git a/UefiC= puPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCp= uPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm index 58d5312899..3fe9aed1e8 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.na= sm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm +++ .nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2016, Intel Corporation. All rights reserved.
+;= Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
; S= PDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -32,12 +32,1= 3 @@ ALIGN 8 ; exception handler stub table ; AsmIdtVectorBegin:+%assign Vector 0 %rep = 32- db 0x6a ; push #VectorNum- db ($ - AsmIdtVecto= rBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum+ push= byte %[Vector]; push eax mov eax, ASM_PFX(CommonInterrup= tEntry) jmp eax+%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@= -287,7 +288,7 @@ ErrorCodeAndVectorOnStack: test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. = ; edx still contains result from CPUID above jz .3- d= b 0xf, 0xae, 0x7 ;fxsave [edi]+ fxsave [edi] .3: ;; UEFI calling = convention for IA32 requires that Direction flag in EFLAGs is clear@@ -320,= 7 +321,7 @@ ErrorCodeAndVectorOnStack: ; are supported test edx, BIT24 ; Test for= FXSAVE/FXRESTOR support jz .4- db 0xf, 0xae, 0xe ; fxrsto= r [esi]+ fxrstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/= Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/= Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm index dd3f74d2aa..b63cfeac6d 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.n= asm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAs +++ m.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2017, Intel Corporation. All rights reserved.
+;= Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
; S= PDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -79,8 +79,7 = @@ AsmExceptionEntryBegin: DoIret%[Vector]: iretd ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):- = db 0x6a ; push #VectorNum- db %[Vector]+ push b= yte %[Vector] mov eax, ASM_PFX(CommonTaskSwtichEntryPoint) call= eax mov esp, eax ; Restore stack top@@ -244,7 +243,7 @@ ASM_= PFX(CommonTaskSwtichEntryPoint): clts sub esp, 512 mov edi, esp- db 0xf, 0xae, = 0x7 ;fxsave [edi]+ fxsave [edi] .3: ;; UINT32 ExceptionData;@@ -277,7= +276,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz = .4 mov esi, esp- db 0xf, 0xae, 0xe ; fxrstor [esi]+ fx= rstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/Library/CpuExc= eptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExcep= tionHandlerLib/X64/ExceptionHandlerAsm.nasm index 2a5545ecfd..9a806d1f86 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nas= m +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm. +++ nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved= .
+; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<= BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -32,1= 2 +32,13 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin:+%assign Vector 0 %rep 32- db 0x6a = ; push #VectorNum- db ($ - AsmIdtVectorBegin) / ((AsmIdtVect= orEnd - AsmIdtVectorBegin) / 32) ; VectorNum+ push byte %[Vector] = push rax mov rax, ASM_PFX(CommonInterruptEntry) jmp rax= +%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -257,7 +258,7 @@ DrFin= ish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp- db= 0xf, 0xae, 0x7 ;fxsave [rdi]+ fxsave [rdi] ;; UEFI calling convention = for x64 requires that Direction flag in EFLAGs is clear cld@@ -284,7 +2= 85,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp- db 0xf, 0xae, 0xE = ; fxrstor [rsi]+ fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr= 2, Dr3, Dr6, Dr7;@@ -371,8 +372,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov= rax, [rax] ; restore rax popfq ; restor= e EFLAGS- DB 0x48 ; prefix to composite "retq" with n= ext "retf"- retf ; far return+ retfq DoIret: = iretq diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5Exc= eptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode= 5ExceptionHandlerAsm.nasm index 84a12ddb88..9c72fa5815 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandl +++ erAsm.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved= .
+; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<= BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -54,1= 2 +54,13 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin:+%assign Vector 0 %rep 32- db 0x6a = ; push #VectorNum- db ($ - AsmIdtVectorBegin) / ((AsmIdtVect= orEnd - AsmIdtVectorBegin) / 32) ; VectorNum+ push byte %[Vector] = push rax mov rax, strict qword 0 ; mov rax, ASM_PFX(Comm= onInterruptEntry) jmp rax+%assign Vector Vector+1 %endrep AsmIdtVec= torEnd: @@ -280,7 +281,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp- db= 0xf, 0xae, 0x7 ;fxsave [rdi]+ fxsave [rdi] ;; UEFI calling convention = for x64 requires that Direction flag in EFLAGs is clear cld@@ -335,15 += 336,15 @@ DrFinish: jz CetDone ; SSP should be 0xFC0 = at this point mov rax, 0x04 ; advance past cs:lip:prevssp= ;supervisor shadow stack token- INCSSP_RAX ; After this= SSP should be 0xFE0- SAVEPREVSSP ; now the shadow stack= restore token will be created at 0xFB8- READSSP_RAX ; R= ead new SSP, SSP should be 0xFE8+ incsspq rax ; After th= is SSP should be 0xFE0+ saveprevssp ; now the shadow sta= ck restore token will be created at 0xFB8+ rdsspq rax ;= Read new SSP, SSP should be 0xFE8 sub rax, 0x10- CLRSSBSY_RAX = ; Clear token at 0xFD8, SSP should be 0 after this+ clrssb= sy [rax] ; Clear token at 0xFD8, SSP should be 0 after this = sub rax, 0x20- RSTORSSP_RAX ; Restore to token at 0= xFB8, new SSP will be 0xFB8+ rstorssp [rax] ; Restore to to= ken at 0xFB8, new SSP will be 0xFB8 mov rax, 0x01 ; Pop o= ff the new save token created- INCSSP_RAX ; SSP should = be 0xFC0 now+ incsspq rax ; SSP should be 0xFC0 now CetD= one: cli@@ -353,7 +354,7 @@ CetDone: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp- db 0xf, 0xae, 0xE = ; fxrstor [rsi]+ fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr= 2, Dr3, Dr6, Dr7;@@ -440,8 +441,7 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov= rax, [rax] ; restore rax popfq ; restor= e EFLAGS- DB 0x48 ; prefix to composite "retq" with = next "retf"- retf ; far return+ retfq DoIret: = iretq diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/Uefi= CpuPkg/Library/MpInitLib/X64/MpFuncs.nasm index f7f2937faf..f1422fd30a 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved= .
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<= BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name:@@ -345,= 7 +345,7 @@ BITS 64 ; ; Far return into 32-bit mode ;-o64 retf+ retfq BITS 32 = CompatMode:@@ -507,7 +507,7 @@ NoSevEs: ; ; Far return into 32-bit mode ;-o64 retf+ retfq BITS 32 = PmEntry:diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm b/UefiCpuPkg/P= iSmmCpuDxeSmm/Ia32/Cet.nasm index 0919d6d05f..9d66b9c5da 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2019, Intel Corporation. All rights reserved.
+;= Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
; S= PDX-License-Identifier: BSD-2-Clause-Patent ; ;----------------------------= ---------------------------------------------------@@ -13,7 +13,7 @@ ASM_PF= X(DisableCet): ; Skip the pushed data for call mov eax, 1- INCSSP_EAX+ = incsspd eax mov eax, cr4 btr eax, 23 = ; clear CETdiff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/Uef= iCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index 167f5e14db..19de5f614e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved= .
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<= BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX= -License-Identifier: BSD-2-Clause-Patent ;@@ -252,7 +252,7 @@ CetInterruptD= one: mov eax, 0x668 | CR4_CET mov cr4, eax - SETSSBSY+ se= tssbsy CetDone: diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm b/Uefi= CpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm index 3240f9d974..8bbdbb31cc 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2019, Intel Corporation. All rights reserved.
+;= Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
; S= PDX-License-Identifier: BSD-2-Clause-Patent ; ;----------------------------= ---------------------------------------------------@@ -14,7 +14,7 @@ ASM_PF= X(DisableCet): ; Skip the pushed data for call mov rax, 1- INCSSP_RAX+ = incsspq rax mov rax, cr4 btr eax, 23 = ; clear CETdiff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/Uefi= CpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 0e154e5db9..d302ca8d01 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved= .
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<= BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.
; SPDX= -License-Identifier: BSD-2-Clause-Patent ;@@ -279,7 +279,7 @@ CetInterruptD= one: mov eax, 0x668 | CR4_CET mov cr4, rax - SETSSBSY+ se= tssbsy CetDone: --=20 2.28.0.windows.1