From: "Ni, Ray" <ray.ni@intel.com>
To: "Tan, Dun" <dun.tan@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Dong, Eric" <eric.dong@intel.com>,
"Kumar, Rahul R" <rahul.r.kumar@intel.com>
Subject: Re: [PATCH 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: Introduce page table pool mechanism
Date: Mon, 19 Dec 2022 06:37:31 +0000 [thread overview]
Message-ID: <MWHPR11MB1631988A149A55881E07CAA18CE59@MWHPR11MB1631.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20221216030059.1373-2-dun.tan@intel.com>
> + //
> + // If page table memory has been marked as RO, mark the new pool pages as read-only.
> + //
> + if (mIsReadOnlyPageTable) {
> + AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
> + SmmSetMemoryAttributes ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, EFI_PAGES_TO_SIZE (PoolPages),
> EFI_MEMORY_RO);
> + AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
> + }
> +
If you check other logic that clears WP bit in CR0, CET is disabled before clearing WP.
You need to follow the same pattern here.
Other looks good to me.
next prev parent reply other threads:[~2022-12-19 6:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-16 3:00 [PATCH 0/3] Introduce page table pool mechanism in SMM page table duntan
2022-12-16 3:00 ` [PATCH 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: Introduce page table pool mechanism duntan
2022-12-19 6:37 ` Ni, Ray [this message]
2022-12-16 3:00 ` [PATCH 2/3] UefiCpuPkg: Remove unused API in SmmCpuFeaturesLib.h duntan
2022-12-19 6:37 ` Ni, Ray
2022-12-16 3:00 ` [PATCH 3/3] UefiCpuPkg: Simplify the code to set smm page table as RO duntan
2022-12-19 7:53 ` Ni, Ray
2022-12-21 3:37 ` duntan
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