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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of duntan > Sent: Wednesday, August 10, 2022 1:37 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Kumar, > Rahul R > Subject: [edk2-devel] [Patch V2 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: > Remove mInternalCr3 in PiSmmCpuDxeSmm >=20 > This patch is code refactoring and doesn't change any functionality. > Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous > code, mInternalCr3 is used to pass address of page table which is > different from Cr3 register in different level of SetMemoryAttributes > function. Now remove it and pass the page table base address from the > root function parameter to simplify the code logic. >=20 > Signed-off-by: Dun Tan > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > --- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 30 +++++----------= ---- > ----------- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 26 > +++++++++----------------- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 110 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- > --------------------------------------------------- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 73 > +++++++++++++++++++++++-------------------------------------------------- > 4 files changed, 94 insertions(+), 145 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > index 8ec8790c05..97058a2810 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > @@ -28,26 +28,6 @@ EnableCet ( > VOID > ); >=20 > -/** > - Get page table base address and the depth of the page table. > - > - @param[out] Base Page table base address. > - @param[out] FiveLevels TRUE means 5 level paging. FALSE means 4 level > paging. > -**/ > -VOID > -GetPageTable ( > - OUT UINTN *Base, > - OUT BOOLEAN *FiveLevels OPTIONAL > - ) > -{ > - *Base =3D ((mInternalCr3 =3D=3D 0) ? > - (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) : > - mInternalCr3); > - if (FiveLevels !=3D NULL) { > - *FiveLevels =3D FALSE; > - } > -} > - > /** > Create PageTable for SMM use. >=20 > @@ -297,10 +277,10 @@ SetPageTableAttributes ( > DEBUG ((DEBUG_INFO, "Start...\n")); > PageTableSplitted =3D FALSE; >=20 > - GetPageTable (&PageTableBase, NULL); > - L3PageTable =3D (UINT64 *)PageTableBase; > + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; > + L3PageTable =3D (UINT64 *)PageTableBase; >=20 > - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, > SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); > + SmmSetMemoryAttributesEx (PageTableBase, FALSE, > (EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > PageTableSplitted =3D (PageTableSplitted || IsSplitted); >=20 > for (Index3 =3D 0; Index3 < 4; Index3++) { > @@ -309,7 +289,7 @@ SetPageTableAttributes ( > continue; > } >=20 > - SmmSetMemoryAttributesEx > ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > + SmmSetMemoryAttributesEx (PageTableBase, FALSE, > (EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > PageTableSplitted =3D (PageTableSplitted || IsSplitted); >=20 > for (Index2 =3D 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) { > @@ -323,7 +303,7 @@ SetPageTableAttributes ( > continue; > } >=20 > - SmmSetMemoryAttributesEx > ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > + SmmSetMemoryAttributesEx (PageTableBase, FALSE, > (EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > PageTableSplitted =3D (PageTableSplitted || IsSplitted); > } > } > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > index dfeceec2aa..ef8bf5947d 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h > @@ -264,7 +264,7 @@ extern UINTN mMaxNumberOfCpus; > extern UINTN mNumberOfCpus; > extern EFI_SMM_CPU_PROTOCOL mSmmCpu; > extern EFI_MM_MP_PROTOCOL mSmmMp; > -extern UINTN mInternalCr3; > +extern BOOLEAN m5LevelPagingNeeded; >=20 > /// > /// The mode of the CPU at the time an SMI occurs > @@ -682,7 +682,6 @@ SmmBlockingStartupThisAp ( >=20 > **/ > EFI_STATUS > -EFIAPI > SmmSetMemoryAttributes ( > IN EFI_PHYSICAL_ADDRESS BaseAddress, > IN UINT64 Length, > @@ -712,7 +711,6 @@ SmmSetMemoryAttributes ( >=20 > **/ > EFI_STATUS > -EFIAPI > SmmClearMemoryAttributes ( > IN EFI_PHYSICAL_ADDRESS BaseAddress, > IN UINT64 Length, > @@ -957,22 +955,12 @@ SetPageTableAttributes ( > VOID > ); >=20 > -/** > - Get page table base address and the depth of the page table. > - > - @param[out] Base Page table base address. > - @param[out] FiveLevels TRUE means 5 level paging. FALSE means 4 level > paging. > -**/ > -VOID > -GetPageTable ( > - OUT UINTN *Base, > - OUT BOOLEAN *FiveLevels OPTIONAL > - ); > - > /** > This function sets the attributes for the memory region specified by > BaseAddress and > Length from their current attributes to the attributes specified by > Attributes. >=20 > + @param[in] PageTableBase The page table base. > + @param[in] EnablePML5Paging If PML5 paging is enabled. > @param[in] BaseAddress The physical address that is the start a= ddress > of a memory region. > @param[in] Length The size in bytes of the memory region. > @param[in] Attributes The bit mask of attributes to set for th= e memory > region. > @@ -993,8 +981,9 @@ GetPageTable ( >=20 > **/ > EFI_STATUS > -EFIAPI > SmmSetMemoryAttributesEx ( > + IN UINTN PageTableBase, > + IN BOOLEAN EnablePML5Paging, > IN EFI_PHYSICAL_ADDRESS BaseAddress, > IN UINT64 Length, > IN UINT64 Attributes, > @@ -1005,6 +994,8 @@ SmmSetMemoryAttributesEx ( > This function clears the attributes for the memory region specified by > BaseAddress and > Length from their current attributes to the attributes specified by > Attributes. >=20 > + @param[in] PageTableBase The page table base. > + @param[in] EnablePML5Paging If PML5 paging is enabled. > @param[in] BaseAddress The physical address that is the start a= ddress > of a memory region. > @param[in] Length The size in bytes of the memory region. > @param[in] Attributes The bit mask of attributes to clear for = the > memory region. > @@ -1025,8 +1016,9 @@ SmmSetMemoryAttributesEx ( >=20 > **/ > EFI_STATUS > -EFIAPI > SmmClearMemoryAttributesEx ( > + IN UINTN PageTableBase, > + IN BOOLEAN EnablePML5Paging, > IN EFI_PHYSICAL_ADDRESS BaseAddress, > IN UINT64 Length, > IN UINT64 Attributes, > diff --git > a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > index 237742d7e6..3602d99fc4 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > @@ -32,24 +32,8 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { > { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 }, > }; >=20 > -UINTN mInternalCr3; > UINTN mIsShadowStack =3D FALSE; >=20 > -/** > - Set the internal page table base address. > - If it is non zero, further MemoryAttribute modification will be on thi= s page > table. > - If it is zero, further MemoryAttribute modification will be on real pa= ge table. > - > - @param Cr3 page table base. > -**/ > -VOID > -SetPageTableBase ( > - IN UINTN Cr3 > - ) > -{ > - mInternalCr3 =3D Cr3; > -} > - > /** > Return length according to page attributes. >=20 > @@ -99,31 +83,31 @@ PageAttributeToMask ( > /** > Return page table entry to match the address. >=20 > - @param[in] Address The address to be checked. > - @param[out] PageAttributes The page attribute of the page entry. > + @param[in] PageTableBase The page table base. > + @param[in] Enable5LevelPaging If PML5 paging is enabled. > + @param[in] Address The address to be checked. > + @param[out] PageAttributes The page attribute of the page entry. >=20 > @return The page entry. > **/ > VOID * > GetPageTableEntry ( > + IN UINTN PageTableBase, > + IN BOOLEAN Enable5LevelPaging, > IN PHYSICAL_ADDRESS Address, > OUT PAGE_ATTRIBUTE *PageAttribute > ) > { > - UINTN Index1; > - UINTN Index2; > - UINTN Index3; > - UINTN Index4; > - UINTN Index5; > - UINT64 *L1PageTable; > - UINT64 *L2PageTable; > - UINT64 *L3PageTable; > - UINT64 *L4PageTable; > - UINT64 *L5PageTable; > - UINTN PageTableBase; > - BOOLEAN Enable5LevelPaging; > - > - GetPageTable (&PageTableBase, &Enable5LevelPaging); > + UINTN Index1; > + UINTN Index2; > + UINTN Index3; > + UINTN Index4; > + UINTN Index5; > + UINT64 *L1PageTable; > + UINT64 *L2PageTable; > + UINT64 *L3PageTable; > + UINT64 *L4PageTable; > + UINT64 *L5PageTable; >=20 > Index5 =3D ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK; > Index4 =3D ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK; > @@ -399,6 +383,8 @@ SplitPage ( >=20 > Caller should make sure BaseAddress and Length is at page boundary. >=20 > + @param[in] PageTableBase The page table base. > + @param[in] EnablePML5Paging If PML5 paging is enabled. > @param[in] BaseAddress The physical address that is the start a= ddress > of a memory region. > @param[in] Length The size in bytes of the memory region. > @param[in] Attributes The bit mask of attributes to modify for= the > memory region. > @@ -420,8 +406,9 @@ SplitPage ( > range specified by BaseAddress and Le= ngth. > **/ > RETURN_STATUS > -EFIAPI > ConvertMemoryPageAttributes ( > + IN UINTN PageTableBase, > + IN BOOLEAN EnablePML5Paging, > IN PHYSICAL_ADDRESS BaseAddress, > IN UINT64 Length, > IN UINT64 Attributes, > @@ -475,7 +462,7 @@ ConvertMemoryPageAttributes ( > // Below logic is to check 2M/4K page to make sure we do not waste > memory. > // > while (Length !=3D 0) { > - PageEntry =3D GetPageTableEntry (BaseAddress, &PageAttribute); > + PageEntry =3D GetPageTableEntry (PageTableBase, EnablePML5Paging, > BaseAddress, &PageAttribute); > if (PageEntry =3D=3D NULL) { > return RETURN_UNSUPPORTED; > } > @@ -558,6 +545,8 @@ FlushTlbForAll ( > This function sets the attributes for the memory region specified by > BaseAddress and > Length from their current attributes to the attributes specified by > Attributes. >=20 > + @param[in] PageTableBase The page table base. > + @param[in] EnablePML5Paging If PML5 paging is enabled. > @param[in] BaseAddress The physical address that is the start a= ddress > of a memory region. > @param[in] Length The size in bytes of the memory region. > @param[in] Attributes The bit mask of attributes to set for th= e memory > region. > @@ -578,8 +567,9 @@ FlushTlbForAll ( >=20 > **/ > EFI_STATUS > -EFIAPI > SmmSetMemoryAttributesEx ( > + IN UINTN PageTableBase, > + IN BOOLEAN EnablePML5Paging, > IN EFI_PHYSICAL_ADDRESS BaseAddress, > IN UINT64 Length, > IN UINT64 Attributes, > @@ -589,7 +579,7 @@ SmmSetMemoryAttributesEx ( > EFI_STATUS Status; > BOOLEAN IsModified; >=20 > - Status =3D ConvertMemoryPageAttributes (BaseAddress, Length, Attribute= s, > TRUE, IsSplitted, &IsModified); > + Status =3D ConvertMemoryPageAttributes (PageTableBase, > EnablePML5Paging, BaseAddress, Length, Attributes, TRUE, IsSplitted, > &IsModified); > if (!EFI_ERROR (Status)) { > if (IsModified) { > // > @@ -606,6 +596,8 @@ SmmSetMemoryAttributesEx ( > This function clears the attributes for the memory region specified by > BaseAddress and > Length from their current attributes to the attributes specified by > Attributes. >=20 > + @param[in] PageTableBase The page table base. > + @param[in] EnablePML5Paging If PML5 paging is enabled. > @param[in] BaseAddress The physical address that is the start a= ddress > of a memory region. > @param[in] Length The size in bytes of the memory region. > @param[in] Attributes The bit mask of attributes to clear for = the > memory region. > @@ -626,8 +618,9 @@ SmmSetMemoryAttributesEx ( >=20 > **/ > EFI_STATUS > -EFIAPI > SmmClearMemoryAttributesEx ( > + IN UINTN PageTableBase, > + IN BOOLEAN EnablePML5Paging, > IN EFI_PHYSICAL_ADDRESS BaseAddress, > IN UINT64 Length, > IN UINT64 Attributes, > @@ -637,7 +630,7 @@ SmmClearMemoryAttributesEx ( > EFI_STATUS Status; > BOOLEAN IsModified; >=20 > - Status =3D ConvertMemoryPageAttributes (BaseAddress, Length, Attribute= s, > FALSE, IsSplitted, &IsModified); > + Status =3D ConvertMemoryPageAttributes (PageTableBase, > EnablePML5Paging, BaseAddress, Length, Attributes, FALSE, IsSplitted, > &IsModified); > if (!EFI_ERROR (Status)) { > if (IsModified) { > // > @@ -673,14 +666,20 @@ SmmClearMemoryAttributesEx ( >=20 > **/ > EFI_STATUS > -EFIAPI > SmmSetMemoryAttributes ( > IN EFI_PHYSICAL_ADDRESS BaseAddress, > IN UINT64 Length, > IN UINT64 Attributes > ) > { > - return SmmSetMemoryAttributesEx (BaseAddress, Length, Attributes, > NULL); > + IA32_CR4 Cr4; > + UINTN PageTableBase; > + BOOLEAN Enable5LevelPaging; > + > + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; > + Cr4.UintN =3D AsmReadCr4 (); > + Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); > + return SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, > BaseAddress, Length, Attributes, NULL); > } >=20 > /** > @@ -706,14 +705,20 @@ SmmSetMemoryAttributes ( >=20 > **/ > EFI_STATUS > -EFIAPI > SmmClearMemoryAttributes ( > IN EFI_PHYSICAL_ADDRESS BaseAddress, > IN UINT64 Length, > IN UINT64 Attributes > ) > { > - return SmmClearMemoryAttributesEx (BaseAddress, Length, Attributes, > NULL); > + IA32_CR4 Cr4; > + UINTN PageTableBase; > + BOOLEAN Enable5LevelPaging; > + > + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; > + Cr4.UintN =3D AsmReadCr4 (); > + Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); > + return SmmClearMemoryAttributesEx (PageTableBase, > Enable5LevelPaging, BaseAddress, Length, Attributes, NULL); > } >=20 > /** > @@ -734,11 +739,8 @@ SetShadowStack ( > { > EFI_STATUS Status; >=20 > - SetPageTableBase (Cr3); > mIsShadowStack =3D TRUE; > - Status =3D SmmSetMemoryAttributes (BaseAddress, Length, > EFI_MEMORY_RO); > - > - SetPageTableBase (0); > + Status =3D SmmSetMemoryAttributesEx (Cr3, m5LevelPagingNeeded, > BaseAddress, Length, EFI_MEMORY_RO, NULL); > mIsShadowStack =3D FALSE; >=20 > return Status; > @@ -762,12 +764,7 @@ SetNotPresentPage ( > { > EFI_STATUS Status; >=20 > - SetPageTableBase (Cr3); > - > - Status =3D SmmSetMemoryAttributes (BaseAddress, Length, > EFI_MEMORY_RP); > - > - SetPageTableBase (0); > - > + Status =3D SmmSetMemoryAttributesEx (Cr3, m5LevelPagingNeeded, > BaseAddress, Length, EFI_MEMORY_RP, NULL); > return Status; > } >=20 > @@ -1560,6 +1557,9 @@ EdkiiSmmGetMemoryAttributes ( > UINT64 MemAttr; > PAGE_ATTRIBUTE PageAttr; > INT64 Size; > + UINTN PageTableBase; > + BOOLEAN EnablePML5Paging; > + IA32_CR4 Cr4; >=20 > if ((Length < SIZE_4KB) || (Attributes =3D=3D NULL)) { > return EFI_INVALID_PARAMETER; > @@ -1568,8 +1568,12 @@ EdkiiSmmGetMemoryAttributes ( > Size =3D (INT64)Length; > MemAttr =3D (UINT64)-1; >=20 > + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; > + Cr4.UintN =3D AsmReadCr4 (); > + EnablePML5Paging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); > + > do { > - PageEntry =3D GetPageTableEntry (BaseAddress, &PageAttr); > + PageEntry =3D GetPageTableEntry (PageTableBase, EnablePML5Paging, > BaseAddress, &PageAttr); > if ((PageEntry =3D=3D NULL) || (PageAttr =3D=3D PageNone)) { > return EFI_UNSUPPORTED; > } > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > index 538394f239..6e920b32af 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > @@ -113,36 +113,6 @@ Is5LevelPagingNeeded ( > } > } >=20 > -/** > - Get page table base address and the depth of the page table. > - > - @param[out] Base Page table base address. > - @param[out] FiveLevels TRUE means 5 level paging. FALSE means 4 level > paging. > -**/ > -VOID > -GetPageTable ( > - OUT UINTN *Base, > - OUT BOOLEAN *FiveLevels OPTIONAL > - ) > -{ > - IA32_CR4 Cr4; > - > - if (mInternalCr3 =3D=3D 0) { > - *Base =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; > - if (FiveLevels !=3D NULL) { > - Cr4.UintN =3D AsmReadCr4 (); > - *FiveLevels =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); > - } > - > - return; > - } > - > - *Base =3D mInternalCr3; > - if (FiveLevels !=3D NULL) { > - *FiveLevels =3D m5LevelPagingNeeded; > - } > -} > - > /** > Set sub-entries number in entry. >=20 > @@ -1195,20 +1165,21 @@ SetPageTableAttributes ( > VOID > ) > { > - UINTN Index2; > - UINTN Index3; > - UINTN Index4; > - UINTN Index5; > - UINT64 *L1PageTable; > - UINT64 *L2PageTable; > - UINT64 *L3PageTable; > - UINT64 *L4PageTable; > - UINT64 *L5PageTable; > - UINTN PageTableBase; > - BOOLEAN IsSplitted; > - BOOLEAN PageTableSplitted; > - BOOLEAN CetEnabled; > - BOOLEAN Enable5LevelPaging; > + UINTN Index2; > + UINTN Index3; > + UINTN Index4; > + UINTN Index5; > + UINT64 *L1PageTable; > + UINT64 *L2PageTable; > + UINT64 *L3PageTable; > + UINT64 *L4PageTable; > + UINT64 *L5PageTable; > + UINTN PageTableBase; > + BOOLEAN IsSplitted; > + BOOLEAN PageTableSplitted; > + BOOLEAN CetEnabled; > + BOOLEAN Enable5LevelPaging; > + IA32_CR4 Cr4; >=20 > // > // Don't mark page table memory as read-only if > @@ -1258,11 +1229,13 @@ SetPageTableAttributes ( > PageTableSplitted =3D FALSE; > L5PageTable =3D NULL; >=20 > - GetPageTable (&PageTableBase, &Enable5LevelPaging); > + PageTableBase =3D AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64; > + Cr4.UintN =3D AsmReadCr4 (); > + Enable5LevelPaging =3D (BOOLEAN)(Cr4.Bits.LA57 =3D=3D 1); >=20 > if (Enable5LevelPaging) { > L5PageTable =3D (UINT64 *)PageTableBase; > - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, > SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); > + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, > (EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > PageTableSplitted =3D (PageTableSplitted || IsSplitted); > } >=20 > @@ -1276,7 +1249,7 @@ SetPageTableAttributes ( > L4PageTable =3D (UINT64 *)PageTableBase; > } >=20 > - SmmSetMemoryAttributesEx > ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, > (EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > PageTableSplitted =3D (PageTableSplitted || IsSplitted); >=20 > for (Index4 =3D 0; Index4 < SIZE_4KB/sizeof (UINT64); Index4++) { > @@ -1285,7 +1258,7 @@ SetPageTableAttributes ( > continue; > } >=20 > - SmmSetMemoryAttributesEx > ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, > (EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > PageTableSplitted =3D (PageTableSplitted || IsSplitted); >=20 > for (Index3 =3D 0; Index3 < SIZE_4KB/sizeof (UINT64); Index3++) = { > @@ -1299,7 +1272,7 @@ SetPageTableAttributes ( > continue; > } >=20 > - SmmSetMemoryAttributesEx > ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, > (EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > PageTableSplitted =3D (PageTableSplitted || IsSplitted); >=20 > for (Index2 =3D 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++= ) { > @@ -1313,7 +1286,7 @@ SetPageTableAttributes ( > continue; > } >=20 > - SmmSetMemoryAttributesEx > ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > + SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, > (EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, > &IsSplitted); > PageTableSplitted =3D (PageTableSplitted || IsSplitted); > } > } > -- > 2.31.1.windows.1 >=20 >=20 >=20 >=20 >=20