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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Taylor Beebe > Sent: Thursday, June 16, 2022 5:23 AM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Kumar, = Rahul1 > Subject: [PATCH v1 1/1] UefiCpuPkg: CpuDxe: Set RW and P Attributes on Sp= lit Pages >=20 > From: Taylor Beebe >=20 > A memory range can be submitted for attribute changes which is large > enough to not require a page split during the attribute update. Consider > the following scenario: >=20 > 1. An attribute update removed the RW attribute on a range large enough > to not require a page split. > 2. Later, an attributes update is called to re-add the RW attribute for > a subsection of that larger page which requires a split > 3. The attribute update logic performs a page split, so now the parent > and child pages have matching attributes > 4. Then, the attribute update logic changes the child page to have the > RW attribute. > 5. The child page would then correctly have the RW attribute added but > the parent page would still have the RW attribute removed which will > cause an improper access violation. >=20 > The page being split should have loose attributes to accommodate the > above case. The split page should always have the attributes set so > the lowest level page frame determines the access rights as detailed > in 4.10.2.2 of the Intel 64 and IA-32 Architectures Software > Developer Manual. Setting the User/Supervisor attribute shouldn't > be necessary. >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Signed-off-by: Taylor Beebe > --- > UefiCpuPkg/CpuDxe/CpuPageTable.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) >=20 > diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPage= Table.c > index f7a4d92e921a..288d9996f6c3 100644 > --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c > +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c > @@ -38,6 +38,8 @@ > #define IA32_PG_NX BIT63 >=20 > #define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_P= G_RW | IA32_PG_P) > +#define PAGE_ATTRIBUTE_BITS_POST_SPLIT (IA32_PG_RW | IA32_PG_P) > + > // > // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE > // X64 PAE PDPTE does not have such restriction > @@ -583,7 +585,7 @@ SplitPage ( > NewPageEntry[Index] =3D (BaseAddress + SIZE_4KB * Index) | Addre= ssEncMask | ((*PageEntry) & > PAGE_PROGATE_BITS); > } >=20 > - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((= *PageEntry) & PAGE_ATTRIBUTE_BITS); > + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | AddressEncMask | PA= GE_ATTRIBUTE_BITS_POST_SPLIT; > return RETURN_SUCCESS; > } else { > return RETURN_UNSUPPORTED; > @@ -606,7 +608,7 @@ SplitPage ( > NewPageEntry[Index] =3D (BaseAddress + SIZE_2MB * Index) | Addre= ssEncMask | IA32_PG_PS | ((*PageEntry) & > PAGE_PROGATE_BITS); > } >=20 > - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((= *PageEntry) & PAGE_ATTRIBUTE_BITS); > + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | AddressEncMask | PA= GE_ATTRIBUTE_BITS_POST_SPLIT; > return RETURN_SUCCESS; > } else { > return RETURN_UNSUPPORTED; > -- > 2.32.0.windows.2