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Wed, 17 Mar 2021 02:55:17 +0000 From: "Gao, Zhichao" To: "devel@edk2.groups.io" , "Kuo, IanX" , "Ni, Ray" CC: "Ke, VincentX" Subject: Re: [edk2-devel] [PATCH] ShellPkg/Library: Fix bug in Pci.c Thread-Topic: [edk2-devel] [PATCH] ShellPkg/Library: Fix bug in Pci.c Thread-Index: AQHXGkjoPR+griBxVUenJlnGQdAEmKqHZFMg Date: Wed, 17 Mar 2021 02:55:16 +0000 Message-ID: References: <19d74844dec841c0c8dda5d6426c67d609ec9d44.1615887240.git.vincentx.ke@intel.com> In-Reply-To: <19d74844dec841c0c8dda5d6426c67d609ec9d44.1615887240.git.vincentx.ke@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.198.147.213] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e1a9a809-127e-4fce-208f-08d8e8f0185e x-ms-traffictypediagnostic: MW3PR11MB4617: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5236; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Ian/Vincent, Sorry, I just notice the NextCapabilityOffset starts from base address of t= he PCI config space. So the comment I give in previous patch is incorrect. And refer the PCIe spec, its valid value should be 0x100 to (0x1000 - sizeo= f (PCI_EXP_EXT_HDR)) or 0x0 (to terminate the list of capabilities). The title of the patch is too common. The title should give a tiny descript= ion of the change. Here is an example: ShellPkg/Pci: Add valid check for PCI extended config space parser If you have a better title, just update your own style. Thanks, Zhichao > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of IanX > Kuo > Sent: Saturday, April 10, 2021 1:35 AM > To: devel@edk2.groups.io > Cc: Ke, VincentX > Subject: [edk2-devel] [PATCH] ShellPkg/Library: Fix bug in Pci.c >=20 > From: VincentX Ke >=20 > Bugzilla: 3262 (https://bugzilla.tianocore.org/show_bug.cgi?id=3D3262) >=20 > No need to print PCIe details while CapabilityId is 0xFFFF. > Limit the NextCapabilityOffset value to AllocatePool() memory. >=20 > Signed-off-by: VincentX Ke > --- > ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) >=20 > diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c > b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c > index a2f04d8db5..9ebf1c26ef 100644 > --- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c > +++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c > @@ -2038,12 +2038,14 @@ LocatePciCapability ( > @param[in] PciExpressCap PCI Express capability buffer. @para= m[in] > ExtendedConfigSpace PCI Express extended configuration space.+ > @param[in] ExtendedConfigSize PCI Express extended configuration size. > @param[in] ExtendedCapability PCI Express extended capability ID to > explain. **/ VOID PciExplainPciExpress ( IN PCI_CAPABILITY_PCIEXP > *PciExpressCap, IN UINT8 *ExtendedCon= figSpace,+ IN > UINTN ExtendedConfigSize, IN CONST UIN= T16 > ExtendedCapability ); @@ -2921,6 +2923,7 @@ ShellCommandRunPci ( > PciExplainPciExpress ( (PCI_CAPABILITY_PCIEXP *) ((UIN= T8 *) > &ConfigSpace + PcieCapabilityPtr), ExtendedConfigSpace,+ > ExtendedConfigSize, ExtendedCapability ); }@@ -= 5698,12 > +5701,14 @@ PrintPciExtendedCapabilityDetails( > @param[in] PciExpressCap PCI Express capability buffer. @para= m[in] > ExtendedConfigSpace PCI Express extended configuration space.+ > @param[in] ExtendedConfigSize PCI Express extended configuration size. > @param[in] ExtendedCapability PCI Express extended capability ID to > explain. **/ VOID PciExplainPciExpress ( IN PCI_CAPABILITY_PCIEXP > *PciExpressCap, IN UINT8 *ExtendedCon= figSpace,+ IN > UINTN ExtendedConfigSize, IN CONST UIN= T16 > ExtendedCapability ) {@@ -5786,7 +5791,7 @@ PciExplainPciExpress ( > } ExtHdr =3D (PCI_EXP_EXT_HDR*)ExtendedConfigSpace;- while (ExtHdr= - > >CapabilityId !=3D 0 && ExtHdr->CapabilityVersion !=3D 0) {+ while (ExtH= dr- > >CapabilityId !=3D 0 && ExtHdr->CapabilityVersion !=3D 0 && ExtHdr- > >CapabilityId !=3D 0xFFFF) { // // Process this item //@@ -58= 00,7 +5805,7 > @@ PciExplainPciExpress ( > // // Advance to the next item if it exists //- if (ExtHd= r- > >NextCapabilityOffset !=3D 0) {+ if (ExtHdr->NextCapabilityOffset !=3D= 0 && > (ExtHdr->NextCapabilityOffset <=3D (UINT32)(ExtendedConfigSize - sizeof > (PCI_EXP_EXT_HDR)))) { ExtHdr =3D > (PCI_EXP_EXT_HDR*)(ExtendedConfigSpace + ExtHdr->NextCapabilityOffset > - EFI_PCIE_CAPABILITY_BASE_OFFSET); } else { break;-- > 2.18.0.windows.1 >=20 >=20 >=20 > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#72862): https://edk2.groups.io/g/devel/message/72862 > Mute This Topic: https://groups.io/mt/81372175/1768756 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [zhichao.gao@intel.com] > -=3D-=3D-=3D-=3D-=3D-=3D >=20