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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Please ignore patch V2 and review patch V3, I have changed the commit messa= ge. > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Heng Luo > Sent: Monday, January 4, 2021 2:46 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Wu, Hao A > Subject: [edk2-devel] [Patch V2 2/2] MdeModulePkg/Bus/Pci/PciBusDxe: > Support PCIe Resizable BAR Capability >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D313 >=20 > Add PcdPcieResizableBarCapabilitySupport to enable/disable PCIe Resizable > BAR Capability fearture. > Program the Resizable BAR Register if the device suports PCIe Resizable B= AR > Capability and PcdPcieResizableBarCapabilitySupport is TRUE. >=20 > Cc: Ray Ni > Cc: Hao A Wu > Signed-off-by: Heng Luo > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 4 +++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 3 ++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 27 > ++++++++++++++++++++++++++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h | 12 > +++++++++++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 185 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++-------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h | 22 > +++++++++++++++++++++- > MdeModulePkg/MdeModulePkg.dec | 8 +++++++- > 7 files changed, 241 insertions(+), 20 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > index d4113993c8..a619a68526 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -1,7 +1,7 @@ > /** @file Header files and data structures needed by PCI Bus module. - > Copyright (c) 2006 - 2019, Intel Corporation. All rights > reserved.
+Copyright (c) 2006 - 2021, Intel Corporation. All rights > reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -280,6 > +280,8 @@ struct _PCI_IO_DEVICE { > // This field is used to support this case. // UINT16 > BridgeIoAlignment;+ UINT32 ResizableB= arOffset;+ > UINT32 ResizableBarNumber; }; #define > PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \diff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > index 9284998f36..e317169d9c 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > @@ -2,7 +2,7 @@ > # The PCI bus driver will probe all PCI devices and allocate MMIO and I= O > space for these devices. # Please use PCD feature flag > PcdPciBusHotplugDeviceSupport to enable hot plug supporting. #-# > Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# > Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
# = # > SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -106,6 +106,7 @@ > gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport ## > CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport > ## CONSUMES > gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## > SOMETIMES_CONSUMES+ > gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport ## > CONSUMES [UserExtensions.TianoCore."ExtraFiles"] PciBusDxeExtra.unidif= f > --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > index 6c68a97d4e..1b64924b7b 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > @@ -1,7 +1,7 @@ > /** @file PCI emumeration support functions implementation for PCI Bus > module. -Copyright (c) 2006 - 2019, Intel Corporation. All rights > reserved.
+Copyright (c) 2006 - 2021, Intel Corporation. All rights > reserved.
(C) Copyright 2015 Hewlett Packard Enterprise Development > LP
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -2426,6 +2426,31 > @@ CreatePciIoDevice ( > } } + PciIoDevice->ResizableBarOffset =3D 0;+ if (PcdGetBool > (PcdPcieResizableBarSupport)) {+ Status =3D > LocatePciExpressCapabilityRegBlock (+ PciIoDevice,+ > PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID,+ > &PciIoDevice->ResizableBarOffset,+ NULL+ );+ = if > (!EFI_ERROR (Status)) {+ > PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL > ResizableBarControl;+ UINT32 = Offset;+ > Offset =3D PciIoDevice->ResizableBarOffset + sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)+ + sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY),+ > PciIo->Pci.Read (+ PciIo,+ EfiPciIoWidthUint8,+ > Offset,+ sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL),+ > &ResizableBarControl+ );+ PciIoDevice->ResizableBarNumb= er =3D > ResizableBarControl.Bits.ResizableBarNumber;+ PciProgramResizableBar > (PciIoDevice, PciResizableBarMax);+ }+ }+ // // Initialize the re= served > resource list //diff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > index d76606c7df..4581b270c9 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > @@ -1,7 +1,7 @@ > /** @file PCI enumeration support functions declaration for PCI Bus > module. -Copyright (c) 2006 - 2019, Intel Corporation. All rights > reserved.
+Copyright (c) 2006 - 2021, Intel Corporation. All rights > reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -467,4 > +467,14 @@ DumpPpbPaddingResource ( > IN PCI_BAR_TYPE ResourceType ); +/**+ Dump the = PCI BAR > information.++ @param PciIoDevice PCI IO > instance.+**/+VOID+DumpPciBars (+ IN PCI_IO_DEVICE > *PciIoDevice+ );+ #endifdiff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > index 72690ab647..6bba283671 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > @@ -1,7 +1,7 @@ > /** @file Internal library implementation for PCI Bus module. -Copyrig= ht (c) > 2006 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 20= 06 - > 2021, Intel Corporation. All rights reserved.
(C) Copyright 2015 Hewl= ett > Packard Enterprise Development LP
SPDX-License-Identifier: BSD-2- > Clause-Patent @@ -377,6 +377,60 @@ DumpResourceMap ( > } } +/**+ Adjust the Devices' BAR size to minimum value if it support > Resizeable BAR capability.++ @param RootBridgeDev Pointer to instance o= f > PCI_IO_DEVICE..++ @return TRUE if BAR size is > adjusted.++**/+BOOLEAN+AdjustPciDeviceBarSize (+ IN PCI_IO_DEVICE > *RootBridgeDev+ )+{+ PCI_IO_DEVICE *PciIoDevice;+ LIST_ENTRY > *CurrentLink;+ BOOLEAN Adjusted;+ UINTN Offset;+ = UINTN > BarIndex;++ Adjusted =3D FALSE;+ CurrentLink =3D RootBridgeDev- > >ChildList.ForwardLink;++ while (CurrentLink !=3D NULL && CurrentLink != =3D > &RootBridgeDev->ChildList) {+ PciIoDevice =3D PCI_IO_DEVICE_FROM_LINK > (CurrentLink);++ if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {+ if > (AdjustPciDeviceBarSize (PciIoDevice)) {+ Adjusted =3D TRUE;+ = }+ } else > {+ if (PciIoDevice->ResizableBarOffset !=3D 0) {+ DEBUG ((+ > DEBUG_ERROR,+ "PciBus: [%02x|%02x|%02x] Adjust Pci Device Bar > Size\n",+ PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, > PciIoDevice->FunctionNumber+ ));+ PciProgramResizableBar > (PciIoDevice, PciResizableBarMin);+ //+ // Start to parse t= he bars+ > //+ for (Offset =3D 0x10, BarIndex =3D 0; Offset <=3D 0x24 && BarI= ndex < > PCI_MAX_BAR; BarIndex++) {+ Offset =3D PciParseBar (PciIoDevice,= Offset, > BarIndex);+ }+ Adjusted =3D TRUE;+ DEBUG_CODE (DumpP= ciBars > (PciIoDevice););+ }+ }++ CurrentLink =3D CurrentLink->ForwardL= ink;+ }++ > return Adjusted;+}+ /** Submits the I/O and memory resource > requirements for the specified PCI Host Bridge. @@ -422,6 +476,10 @@ > PciHostBridgeResourceAllocator ( > PCI_RESOURCE_NODE PMem64Pool; > EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData; > EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD > AllocFailExtendedData;+ BOOLEAN > ResizableBarNeedAdjust;+ BOOLEAN > ResizableBarAdjusted;++ ResizableBarNeedAdjust =3D PcdGetBool > (PcdPcieResizableBarSupport); // // It may try several times if the = resource > allocation fails@@ -703,19 +761,30 @@ PciHostBridgeResourceAllocator ( > sizeof (AllocFailExtendedData) ); - Status = =3D > PciHostBridgeAdjustAllocation (- &IoPool,- = &Mem32Pool,- > &PMem32Pool,- &Mem64Pool,- &PMem64Pool,- > IoResStatus,- Mem32ResStatus,- PMem32ResS= tatus,- > Mem64ResStatus,- PMem64ResStatus- );-+ = //+ // > When resource conflict happens, adjust the BAR size first.+ // Only w= hen > adjusting BAR size doesn't help or BAR size cannot be adjusted,+ // r= eject > the device who requests largest resource that causes conflict.+ //+ > ResizableBarAdjusted =3D FALSE;+ if (ResizableBarNeedAdjust) {+ > ResizableBarAdjusted =3D AdjustPciDeviceBarSize (RootBridgeDev);+ > ResizableBarNeedAdjust =3D FALSE;+ }+ if (!ResizableBarAdjusted= ) {+ > Status =3D PciHostBridgeAdjustAllocation (+ &IoPool,+ > &Mem32Pool,+ &PMem32Pool,+ &Mem64Pool,+ > &PMem64Pool,+ IoResStatus,+ Mem32ResSta= tus,+ > PMem32ResStatus,+ Mem64ResStatus,+ > PMem64ResStatus+ );+ } // // Destroy al= l the resource > tree //@@ -1651,3 +1720,91 @@ PciHostBridgeEnumerator ( > return EFI_SUCCESS; }++/**+ This function is used to program the > Resizable BAR Register.++ @param PciIoDevice A pointer to the > PCI_IO_DEVICE.+ @param ResizableBarOp PciResizableBarMax: Set BA= R > to max size+ PciResizableBarMin: set BAR t= o min size.++ > @retval EFI_SUCCESS Successfully enumerated the host bridge.+ > @retval other Some error occurred when enumerating the ho= st > bridge.++**/+EFI_STATUS+PciProgramResizableBar (+ IN PCI_IO_DEVICE > *PciIoDevice,+ IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp+ )+{+ > EFI_PCI_IO_PROTOCOL *PciIo;+ UINT64 Capabilities;+ UINT= 32 > Index;+ UINT32 Offset;+ INTN Bit;+ UIN= TN > ResizableBarNumber;+ EFI_STATUS Status;+ > PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY > Entries[PCI_MAX_BAR];++ ASSERT (PciIoDevice->ResizableBarOffset !=3D 0);= ++ > DEBUG ((DEBUG_INFO, " Programs Resizable BAR register, offset: 0x%08x, > number: %d\n",+ PciIoDevice->ResizableBarOffset, PciIoDevice- > >ResizableBarNumber));++ ResizableBarNumber =3D MIN (PciIoDevice- > >ResizableBarNumber, PCI_MAX_BAR);+ PciIo =3D &PciIoDevice->PciIo;+ Sta= tus > =3D PciIo->Pci.Read (+ PciIo,+ EfiPciIoWidthUint8,+ = PciIoDevice- > >ResizableBarOffset + sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER),+ sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) * > ResizableBarNumber,+ (VOID *)(&Entries)+ );+ ASSERT_EF= I_ERROR > (Status);++ for (Index =3D 0; Index < ResizableBarNumber; Index++) {++ = //+ > // When the bit of Capabilities Set, indicates that the Function supports= + > // operating with the BAR sized to (2^Bit) MB.+ // Example:+ // Bit= 0 is > set: supports operating with the BAR sized to 1 MB+ // Bit 1 is set: > supports operating with the BAR sized to 2 MB+ // Bit n is set: suppor= ts > operating with the BAR sized to (2^n) MB+ //+ Capabilities =3D > LShiftU64(Entries[Index].ResizableBarControl.Bits.BarSizeCapability, 28)+ > | Entries[Index].ResizableBarCapability.Bits.BarSizeCapability;++ if > (ResizableBarOp =3D=3D PciResizableBarMax) {+ Bit =3D > HighBitSet64(Capabilities);+ } else if (ResizableBarOp =3D=3D PciResiz= ableBarMin) > {+ Bit =3D LowBitSet64(Capabilities);+ } else {+ ASSERT ((Re= sizableBarOp > =3D=3D PciResizableBarMax) || (ResizableBarOp =3D=3D PciResizableBarMin))= ;+ }++ > ASSERT (Bit >=3D 0);++ Offset =3D PciIoDevice->ResizableBarOffset + si= zeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)+ + Index * sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY)+ + > OFFSET_OF (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY, > ResizableBarControl);++ Entries[Index].ResizableBarControl.Bits.BarSiz= e =3D > (UINT32) Bit;+ DEBUG ((+ DEBUG_INFO,+ " Resizable Bar: Off= set =3D > 0x%x, Bar Size Capability =3D 0x%016lx, New Bar Size =3D 0x%lx\n",+ > OFFSET_OF (PCI_TYPE00, > Device.Bar[Entries[Index].ResizableBarControl.Bits.BarIndex]),+ > Capabilities, LShiftU64 (SIZE_1MB, Bit)+ ));+ PciIo->Pci.Write (+ > PciIo,+ EfiPciIoWidthUint32,+ Offset,+ 1= ,+ > &Entries[Index].ResizableBarControl.Uint32+ );+ }++ return > EFI_SUCCESS;+}diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > index 10b435d146..aeec6d6b6d 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > @@ -1,7 +1,7 @@ > /** @file Internal library declaration for PCI Bus module. -Copyright = (c) > 2006 - 2011, Intel Corporation. All rights reserved.
+Copyright (c) 20= 06 - > 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier= : BSD- > 2-Clause-Patent **/@@ -24,6 +24,10 @@ typedef struct { > UINT8 *AllocRes; } > EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD; +typedef enum {+ > PciResizableBarMin =3D 0x00,+ PciResizableBarMax =3D 0xFF+} > PCI_RESIZABLE_BAR_OPERATION; /** Retrieve the PCI Card device BAR > information via PciIo interface.@@ -156,4 +160,20 @@ > PciHostBridgeEnumerator ( > IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL > *PciResAlloc ); +/**+ This function is used to program the Resizable B= AR > Register.++ @param PciIoDevice A pointer to the PCI_IO_DEVICE= .+ > @param ResizableBarOp PciResizableBarMax: Set BAR to max size+ > PciResizableBarMin: set BAR to min size.++ @retval EFI_SUCCESS > Successfully enumerated the host bridge.+ @retval other = Some > error occurred when enumerating the host > bridge.++**/+EFI_STATUS+PciProgramResizableBar (+ IN PCI_IO_DEVICE > *PciIoDevice,+ IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp+ ); > #endifdiff --git a/MdeModulePkg/MdeModulePkg.dec > b/MdeModulePkg/MdeModulePkg.dec > index 9b52b34494..9173fdef83 100644 > --- a/MdeModulePkg/MdeModulePkg.dec > +++ b/MdeModulePkg/MdeModulePkg.dec > @@ -4,7 +4,7 @@ > # and libraries instances, which are used for those modules. # # Copyrig= ht (c) > 2019, NVIDIA CORPORATION. All rights reserved.-# Copyright (c) 2007 - 202= 0, > Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2021, = Intel > Corporation. All rights reserved.
# Copyright (c) 2016, Linaro Ltd. A= ll > rights reserved.
# (C) Copyright 2016 - 2019 Hewlett Packard Enterpri= se > Development LP
# Copyright (c) 2017, AMD Incorporated. All rights > reserved.
@@ -2043,6 +2043,12 @@ > # @Prompt Enable StatusCode via memory. > gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE|BOOL > EAN|0x00010023 + ## Indicates if the PCIe Resizable BAR Capability > Supported.

+ # TRUE - PCIe Resizable BAR Capability is > supported.
+ # FALSE - PCIe Resizable BAR Capability is not > supported.
+ # @Prompt Enable PCIe Resizable BAR Capability > support.+ > gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|TRUE|BOO > LEAN|0x10000024+ [PcdsPatchableInModule] ## Specify memory size with > page number for PEI code when # Loading Module at Fixed Address featur= e > is enabled.-- > 2.24.0.windows.2 >=20 >=20 >=20 > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#69540): https://edk2.groups.io/g/devel/message/69540 > Mute This Topic: https://groups.io/mt/79419465/3906523 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [heng.luo@intel.com] -= =3D- > =3D-=3D-=3D-=3D-=3D >=20