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Mon, 4 Jan 2021 06:39:59 +0000 From: "Heng Luo" To: "Ni, Ray" , "devel@edk2.groups.io" CC: "Wu, Hao A" Subject: Re: [edk2-devel] [PATCH 2/2] MdeModulePkg/Bus/Pci/PciBusDxe: Support PCIe Resizable BAR Capability Thread-Topic: [edk2-devel] [PATCH 2/2] MdeModulePkg/Bus/Pci/PciBusDxe: Support PCIe Resizable BAR Capability Thread-Index: AQHW4ls3zAtW86vVy0esKr+cIfyNk6oXA8wA Date: Mon, 4 Jan 2021 06:39:59 +0000 Message-ID: References: <20201228082610.2565-1-heng.luo@intel.com> <20201228082610.2565-2-heng.luo@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.55.46.46] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 24669649-1f21-4da1-7021-08d8b07b8ef1 x-ms-traffictypediagnostic: MWHPR1101MB2157: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thank Ray, I will send out patch V2 following you comments, and also change= Copyright year to 2021. Thanks, heng > -----Original Message----- > From: Ni, Ray > Sent: Monday, January 4, 2021 1:34 PM > To: devel@edk2.groups.io; Luo, Heng > Cc: Wu, Hao A > Subject: RE: [edk2-devel] [PATCH 2/2] MdeModulePkg/Bus/Pci/PciBusDxe: > Support PCIe Resizable BAR Capability >=20 > 1. PcdPcieResizableBarCapabilitySupport: can you rename to > PcdPcieResizableBarSupport? > I understand your name is more precise but it's a bit long.:) >=20 > 2. > // > // Try to adjust the Devices' BAR size to minimum value in first lo= op > // if enabling PCIe Resizable BAR Capability support. > // call PciHostBridgeAdjustAllocation() only if BAR size is not adj= ust. > // > --> > // > // When resource conflict happens, adjust the BAR size first. > // Only when adjusting BAR size doesn't help or BAR size cannot be > adjusted, > // reject the device who requests largest resource that causes confl= ict. > // > 3. PCI_RESIZEABLE_BAR_CAP: Can you please rename the type to > PCI_RESIZABLE_BAR_OPERATION? > Similar comments to ResizableBarCap. Can you please rename to > ResizableBarOp? >=20 > 4. Capabilities =3D Entries[BarIndex].ResizableBarControl.Bits.BarSizeCap= ability > << 28 > | Entries[BarIndex].ResizableBarCapability.Bits.BarSize= Capability; >=20 > You need to use LShiftU64() >=20 > 5. Entries[BarIndex].ResizableBarControl.Bits.BarIndex > I suggest you rename BarIndex to Index. Because it can avoid confusion. S= o > the above code will be: > Entries[Index].ResizableBarControl.Bits.BarIndex >=20 > Thanks, > Ray >=20 > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of Heng > > Luo > > Sent: Monday, December 28, 2020 4:26 PM > > To: devel@edk2.groups.io > > Cc: Ni, Ray ; Wu, Hao A > > Subject: [edk2-devel] [PATCH 2/2] MdeModulePkg/Bus/Pci/PciBusDxe: > > Support PCIe Resizable BAR Capability > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D313 > > > > Add PcdPcieResizableBarCapabilitySupport to enable/disable PCIe > > Resizable BAR Capability fearture. > > Program the Resizable BAR Register if the device suports PCIe > > Resizable BAR Capability and PcdPcieResizableBarCapabilitySupport is > TRUE. > > > > Cc: Ray Ni > > Cc: Hao A Wu > > Signed-off-by: Heng Luo > > --- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 4 +++- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 3 ++- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 27 > > ++++++++++++++++++++++++++- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h | 12 > > +++++++++++- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 185 > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > +++++++++++++++++++++++++++++++++++++++++++-------------- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h | 22 > > +++++++++++++++++++++- > > MdeModulePkg/MdeModulePkg.dec | 6 ++++++ > > 7 files changed, 240 insertions(+), 19 deletions(-) > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > > index d4113993c8..add1756d5c 100644 > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > > @@ -1,7 +1,7 @@ > > /** @file > > > > Header files and data structures needed by PCI Bus module. > > > > > > > > -Copyright (c) 2006 - 2019, Intel Corporation. All rights > > reserved.
> > > > +Copyright (c) 2006 - 2020, Intel Corporation. All rights > > +reserved.
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > **/ > > > > @@ -280,6 +280,8 @@ struct _PCI_IO_DEVICE { > > // This field is used to support this case. > > > > // > > > > UINT16 BridgeIoAlignment; > > > > + UINT32 ResizableBarOffset; > > > > + UINT32 ResizableBarNumber; > > > > }; > > > > > > > > #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > index 9284998f36..b3e5213b92 100644 > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > @@ -2,7 +2,7 @@ > > # The PCI bus driver will probe all PCI devices and allocate MMIO > > and IO space for these devices. > > > > # Please use PCD feature flag PcdPciBusHotplugDeviceSupport to > > enable hot plug supporting. > > > > # > > > > -# Copyright (c) 2006 - 2019, Intel Corporation. All rights > > reserved.
> > > > +# Copyright (c) 2006 - 2020, Intel Corporation. All rights > > +reserved.
> > > > # > > > > # SPDX-License-Identifier: BSD-2-Clause-Patent > > > > # > > > > @@ -106,6 +106,7 @@ > > gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport ## > CONSUMES > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## > > CONSUMES > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## > > SOMETIMES_CONSUMES > > > > + > gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarCapabilitySupport > > ## CONSUMES > > > > > > > > [UserExtensions.TianoCore."ExtraFiles"] > > > > PciBusDxeExtra.uni > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > > index 6c68a97d4e..d1d38241da 100644 > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > > @@ -1,7 +1,7 @@ > > /** @file > > > > PCI emumeration support functions implementation for PCI Bus module. > > > > > > > > -Copyright (c) 2006 - 2019, Intel Corporation. All rights > > reserved.
> > > > +Copyright (c) 2006 - 2020, Intel Corporation. All rights > > +reserved.
> > > > (C) Copyright 2015 Hewlett Packard Enterprise Development LP
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > @@ -2426,6 +2426,31 @@ CreatePciIoDevice ( > > } > > > > } > > > > > > > > + PciIoDevice->ResizableBarOffset =3D 0; > > > > + if (PcdGetBool (PcdPcieResizableBarCapabilitySupport)) { > > > > + Status =3D LocatePciExpressCapabilityRegBlock ( > > > > + PciIoDevice, > > > > + PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID, > > > > + &PciIoDevice->ResizableBarOffset, > > > > + NULL > > > > + ); > > > > + if (!EFI_ERROR (Status)) { > > > > + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL > > ResizableBarControl; > > > > + UINT32 Offset; > > > > + Offset =3D PciIoDevice->ResizableBarOffset + sizeof > > (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER) > > > > + + sizeof > > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY), > > > > + PciIo->Pci.Read ( > > > > + PciIo, > > > > + EfiPciIoWidthUint8, > > > > + Offset, > > > > + sizeof > > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL), > > > > + &ResizableBarControl > > > > + ); > > > > + PciIoDevice->ResizableBarNumber =3D > > ResizableBarControl.Bits.ResizableBarNumber; > > > > + PciProgramResizableBar (PciIoDevice, PciResizableBarMax); > > > > + } > > > > + } > > > > + > > > > // > > > > // Initialize the reserved resource list > > > > // > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > > index d76606c7df..919d678e2f 100644 > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > > @@ -1,7 +1,7 @@ > > /** @file > > > > PCI enumeration support functions declaration for PCI Bus module. > > > > > > > > -Copyright (c) 2006 - 2019, Intel Corporation. All rights > > reserved.
> > > > +Copyright (c) 2006 - 2020, Intel Corporation. All rights > > +reserved.
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > **/ > > > > @@ -467,4 +467,14 @@ DumpPpbPaddingResource ( > > IN PCI_BAR_TYPE ResourceType > > > > ); > > > > > > > > +/** > > > > + Dump the PCI BAR information. > > > > + > > > > + @param PciIoDevice PCI IO instance. > > > > +**/ > > > > +VOID > > > > +DumpPciBars ( > > > > + IN PCI_IO_DEVICE *PciIoDevice > > > > + ); > > > > + > > > > #endif > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > > index 72690ab647..1a7ddb4455 100644 > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > > @@ -1,7 +1,7 @@ > > /** @file > > > > Internal library implementation for PCI Bus module. > > > > > > > > -Copyright (c) 2006 - 2019, Intel Corporation. All rights > > reserved.
> > > > +Copyright (c) 2006 - 2020, Intel Corporation. All rights > > +reserved.
> > > > (C) Copyright 2015 Hewlett Packard Enterprise Development LP
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > @@ -377,6 +377,60 @@ DumpResourceMap ( > > } > > > > } > > > > > > > > +/** > > > > + Adjust the Devices' BAR size to minimum value if it support > > + Resizeable BAR > > capability. > > > > + > > > > + @param RootBridgeDev Pointer to instance of PCI_IO_DEVICE.. > > > > + > > > > + @return TRUE if BAR size is adjusted. > > > > + > > > > +**/ > > > > +BOOLEAN > > > > +AdjustPciDeviceBarSize ( > > > > + IN PCI_IO_DEVICE *RootBridgeDev > > > > + ) > > > > +{ > > > > + PCI_IO_DEVICE *PciIoDevice; > > > > + LIST_ENTRY *CurrentLink; > > > > + BOOLEAN Adjusted; > > > > + UINTN Offset; > > > > + UINTN BarIndex; > > > > + > > > > + Adjusted =3D FALSE; > > > > + CurrentLink =3D RootBridgeDev->ChildList.ForwardLink; > > > > + > > > > + while (CurrentLink !=3D NULL && CurrentLink !=3D > > + &RootBridgeDev->ChildList) { > > > > + PciIoDevice =3D PCI_IO_DEVICE_FROM_LINK (CurrentLink); > > > > + > > > > + if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { > > > > + if (AdjustPciDeviceBarSize (PciIoDevice)) { > > > > + Adjusted =3D TRUE; > > > > + } > > > > + } else { > > > > + if (PciIoDevice->ResizableBarOffset !=3D 0) { > > > > + DEBUG (( > > > > + DEBUG_ERROR, > > > > + "PciBus: [%02x|%02x|%02x] Adjust Pci Device Bar Size\n", > > > > + PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, > > + PciIoDevice- > > >FunctionNumber > > > > + )); > > > > + PciProgramResizableBar (PciIoDevice, PciResizableBarMin); > > > > + // > > > > + // Start to parse the bars > > > > + // > > > > + for (Offset =3D 0x10, BarIndex =3D 0; Offset <=3D 0x24 && BarI= ndex > > + < > > PCI_MAX_BAR; BarIndex++) { > > > > + Offset =3D PciParseBar (PciIoDevice, Offset, BarIndex); > > > > + } > > > > + Adjusted =3D TRUE; > > > > + DEBUG_CODE (DumpPciBars (PciIoDevice);); > > > > + } > > > > + } > > > > + > > > > + CurrentLink =3D CurrentLink->ForwardLink; > > > > + } > > > > + > > > > + return Adjusted; > > > > +} > > > > + > > > > /** > > > > Submits the I/O and memory resource requirements for the specified > > PCI Host Bridge. > > > > > > > > @@ -422,6 +476,10 @@ PciHostBridgeResourceAllocator ( > > PCI_RESOURCE_NODE PMem64Pool; > > > > EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD > HandleExtendedData; > > > > EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD > > AllocFailExtendedData; > > > > + BOOLEAN ResizableBarNeedAdjus= t; > > > > + BOOLEAN ResizableBarAdjusted; > > > > + > > > > + ResizableBarNeedAdjust =3D PcdGetBool > > (PcdPcieResizableBarCapabilitySupport); > > > > > > > > // > > > > // It may try several times if the resource allocation fails > > > > @@ -703,19 +761,30 @@ PciHostBridgeResourceAllocator ( > > sizeof (AllocFailExtendedData) > > > > ); > > > > > > > > - Status =3D PciHostBridgeAdjustAllocation ( > > > > - &IoPool, > > > > - &Mem32Pool, > > > > - &PMem32Pool, > > > > - &Mem64Pool, > > > > - &PMem64Pool, > > > > - IoResStatus, > > > > - Mem32ResStatus, > > > > - PMem32ResStatus, > > > > - Mem64ResStatus, > > > > - PMem64ResStatus > > > > - ); > > > > - > > > > + // > > > > + // Try to adjust the Devices' BAR size to minimum value in > > + first loop > > > > + // if enabling PCIe Resizable BAR Capability support. > > > > + // call PciHostBridgeAdjustAllocation() only if BAR size is not = adjust. > > > > + // > > > > + ResizableBarAdjusted =3D FALSE; > > > > + if (ResizableBarNeedAdjust) { > > > > + ResizableBarAdjusted =3D AdjustPciDeviceBarSize > > + (RootBridgeDev); > > > > + ResizableBarNeedAdjust =3D FALSE; > > > > + } > > > > + if (!ResizableBarAdjusted) { > > > > + Status =3D PciHostBridgeAdjustAllocation ( > > > > + &IoPool, > > > > + &Mem32Pool, > > > > + &PMem32Pool, > > > > + &Mem64Pool, > > > > + &PMem64Pool, > > > > + IoResStatus, > > > > + Mem32ResStatus, > > > > + PMem32ResStatus, > > > > + Mem64ResStatus, > > > > + PMem64ResStatus > > > > + ); > > > > + } > > > > // > > > > // Destroy all the resource tree > > > > // > > > > @@ -1651,3 +1720,91 @@ PciHostBridgeEnumerator ( > > > > > > return EFI_SUCCESS; > > > > } > > > > + > > > > +/** > > > > + This function is used to program the Resizable BAR Register. > > > > + > > > > + @param PciIoDevice A pointer to the PCI_IO_DEVICE. > > > > + @param ResizableBarCap PciResizableBarMax: Set BAR to max siz= e > > > > + PciResizableBarMin: set BAR to min siz= e. > > > > + > > > > + @retval EFI_SUCCESS Successfully enumerated the host bridg= e. > > > > + @retval other Some error occurred when enumerating t= he host > > bridge. > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +PciProgramResizableBar ( > > > > + IN PCI_IO_DEVICE *PciIoDevice, > > > > + IN PCI_RESIZEABLE_BAR_CAP ResizableBarCap > > > > + ) > > > > +{ > > > > + EFI_PCI_IO_PROTOCOL *PciIo; > > > > + UINT64 Capabilities; > > > > + UINT32 BarIndex; > > > > + UINT32 Offset; > > > > + INTN Bit; > > > > + UINTN ResizableBarNumber; > > > > + EFI_STATUS Status; > > > > + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY > > Entries[PCI_MAX_BAR]; > > > > + > > > > + ASSERT (PciIoDevice->ResizableBarOffset !=3D 0); > > > > + > > > > + DEBUG ((DEBUG_INFO, " Programs Resizable BAR register, offset: > 0x%08x, > > number: %d\n", > > > > + PciIoDevice->ResizableBarOffset, > > + PciIoDevice->ResizableBarNumber)); > > > > + > > > > + ResizableBarNumber =3D MIN (PciIoDevice->ResizableBarNumber, > > PCI_MAX_BAR); > > > > + PciIo =3D &PciIoDevice->PciIo; > > > > + Status =3D PciIo->Pci.Read ( > > > > + PciIo, > > > > + EfiPciIoWidthUint8, > > > > + PciIoDevice->ResizableBarOffset + sizeof > > (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER), > > > > + sizeof > > + (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) > > * ResizableBarNumber, > > > > + (VOID *)(&Entries) > > > > + ); > > > > + ASSERT_EFI_ERROR (Status); > > > > + > > > > + for (BarIndex =3D 0; BarIndex < ResizableBarNumber; BarIndex++) { > > > > + > > > > + // > > > > + // When the bit of Capabilities Set, indicates that the Function > > + supports > > > > + // operating with the BAR sized to (2^Bit) MB. > > > > + // Example: > > > > + // Bit 0 is set: supports operating with the BAR sized to 1 MB > > > > + // Bit 1 is set: supports operating with the BAR sized to 2 MB > > > > + // Bit n is set: supports operating with the BAR sized to (2^n) > > + MB > > > > + // > > > > + Capabilities =3D > > + Entries[BarIndex].ResizableBarControl.Bits.BarSizeCapability > > << 28 > > > > + | > > + Entries[BarIndex].ResizableBarCapability.Bits.BarSizeCapability; > > > > + > > > > + if (ResizableBarCap =3D=3D PciResizableBarMax) { > > > > + Bit =3D HighBitSet64(Capabilities); > > > > + } else if (ResizableBarCap =3D=3D PciResizableBarMin) { > > > > + Bit =3D LowBitSet64(Capabilities); > > > > + } else { > > > > + ASSERT ((ResizableBarCap =3D=3D PciResizableBarMax) || > > + (ResizableBarCap > > =3D=3D PciResizableBarMin)); > > > > + } > > > > + > > > > + ASSERT (Bit >=3D 0); > > > > + > > > > + Offset =3D PciIoDevice->ResizableBarOffset + sizeof > > (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER) > > > > + + BarIndex * sizeof > > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) > > > > + + OFFSET_OF > > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY, > > ResizableBarControl); > > > > + > > > > + Entries[BarIndex].ResizableBarControl.Bits.BarSize =3D (UINT32) > > + Bit; > > > > + DEBUG (( > > > > + DEBUG_INFO, > > > > + " Resizable Bar: Offset =3D 0x%x, Bar Size Capability =3D 0x%0= 16lx, New > Bar > > Size =3D 0x%lx\n", > > > > + OFFSET_OF (PCI_TYPE00, > > Device.Bar[Entries[BarIndex].ResizableBarControl.Bits.BarIndex]), > > > > + Capabilities, LShiftU64 (SIZE_1MB, Bit) > > > > + )); > > > > + PciIo->Pci.Write ( > > > > + PciIo, > > > > + EfiPciIoWidthUint32, > > > > + Offset, > > > > + 1, > > > > + &Entries[BarIndex].ResizableBarControl.Uint32 > > > > + ); > > > > + } > > > > + > > > > + return EFI_SUCCESS; > > > > +} > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > > index 10b435d146..94b20f18e8 100644 > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > > @@ -1,7 +1,7 @@ > > /** @file > > > > Internal library declaration for PCI Bus module. > > > > > > > > -Copyright (c) 2006 - 2011, Intel Corporation. All rights > > reserved.
> > > > +Copyright (c) 2006 - 2020, Intel Corporation. All rights > > +reserved.
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > **/ > > > > @@ -24,6 +24,10 @@ typedef struct { > > UINT8 *AllocRes; > > > > } EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD; > > > > > > > > +typedef enum { > > > > + PciResizableBarMin =3D 0x00, > > > > + PciResizableBarMax =3D 0xFF > > > > +} PCI_RESIZEABLE_BAR_CAP; > > > > > > > > /** > > > > Retrieve the PCI Card device BAR information via PciIo interface. > > > > @@ -156,4 +160,20 @@ PciHostBridgeEnumerator ( > > IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL > > *PciResAlloc > > > > ); > > > > > > > > +/** > > > > + This function is used to program the Resizable BAR Register. > > > > + > > > > + @param PciIoDevice A pointer to the PCI_IO_DEVICE. > > > > + @param ResizableBarCap PciResizableBarMax: Set BAR to max siz= e > > > > + PciResizableBarMin: set BAR to min siz= e. > > > > + > > > > + @retval EFI_SUCCESS Successfully enumerated the host bridg= e. > > > > + @retval other Some error occurred when enumerating t= he host > > bridge. > > > > + > > > > +**/ > > > > +EFI_STATUS > > > > +PciProgramResizableBar ( > > > > + IN PCI_IO_DEVICE *PciIoDevice, > > > > + IN PCI_RESIZEABLE_BAR_CAP ResizableBarCap > > > > + ); > > > > #endif > > > > diff --git a/MdeModulePkg/MdeModulePkg.dec > > b/MdeModulePkg/MdeModulePkg.dec index 9b52b34494..10c819ee39 > 100644 > > --- a/MdeModulePkg/MdeModulePkg.dec > > +++ b/MdeModulePkg/MdeModulePkg.dec > > @@ -2043,6 +2043,12 @@ > > # @Prompt Enable StatusCode via memory. > > > > > > > gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE|BOOL > E > > AN|0x00010023 > > > > > > > > + ## Indicates if the PCIe Resizable BAR Capability > > + Supported.

> > > > + # TRUE - PCIe Resizable BAR Capability is supported.
> > > > + # FALSE - PCIe Resizable BAR Capability is not supported.
> > > > + # @Prompt Enable PCIe Resizable BAR Capability support. > > > > + > > > gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarCapabilitySupport|T > R > > UE|BOOLEAN|0x10000024 > > > > + > > > > [PcdsPatchableInModule] > > > > ## Specify memory size with page number for PEI code when > > > > # Loading Module at Fixed Address feature is enabled. > > > > -- > > 2.24.0.windows.2 > > > > > > > > -=3D-=3D-=3D-=3D-=3D-=3D > > Groups.io Links: You receive all messages sent to this group. > > View/Reply Online (#69478): > > https://edk2.groups.io/g/devel/message/69478 > > Mute This Topic: https://groups.io/mt/79265865/1712937 > > Group Owner: devel+owner@edk2.groups.io > > Unsubscribe: https://edk2.groups.io/g/devel/unsub [ray.ni@intel.com] > > -=3D-=3D-=3D-=3D-=3D-=3D > >