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MWHPR11MB1805 Return-Path: heng.luo@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I will send Patch V3 to remove commented code in SiliconEnableAcpi() and as= sociated comments. > -----Original Message----- > From: Chaganty, Rangasai V > Sent: Wednesday, February 10, 2021 8:39 AM > To: Luo, Heng ; devel@edk2.groups.io > Cc: Desimone, Nathaniel L > Subject: RE: [Patch V2 4/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add libr= ary > instances >=20 > Please remove commented code in SiliconEnableAcpi() and associated > comments. >=20 > Thanks, > Sai >=20 > -----Original Message----- > From: Luo, Heng > Sent: Tuesday, February 09, 2021 12:46 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [Patch V2 4/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add library > instances >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3175 >=20 > Adds the following library instances: > * TigerlakeURvp/Library/BoardAcpiLib > * TigerlakeURvp/Library/BoardInitLib > * TigerlakeURvp/Library/PeiPlatformHookLib >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/S > mmMultiBoardAcpiSupportLib.c | 88 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/S > mmMultiBoardAcpiSupportLib.inf | 43 > +++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/S > mmSiliconAcpiEnableLib.c | 160 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/S > mmTigerlakeURvpAcpiEnableLib.c | 51 > +++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/B= o > ardPchInitPreMemLib.c | 160 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/B= o > ardSaInitPreMemLib.c | 96 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/G= pi > oTableTigerlakeUDdr4Rvp.h | 93 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/G= pi > oTableTigerlakeUDdr4RvpPreMem.h | 33 > +++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/P= ei > MultiBoardInitPostMemLib.c | 41 > +++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/P= ei > MultiBoardInitPostMemLib.inf | 49 > +++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/P= ei > MultiBoardInitPreMemLib.c | 88 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/P= ei > MultiBoardInitPreMemLib.inf | 115 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/P= ei > TigerlakeURvpDetect.c | 39 > +++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/P= ei > TigerlakeURvpInitPostMemLib.c | 153 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/P= ei > TigerlakeURvpInitPreMemLib.c | 445 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/T= ig > erlakeURvpInit.h | 23 +++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHoo > kLib/PeiPlatformHooklib.c | 212 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHoo > kLib/PeiPlatformHooklib.inf | 58 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 18 files changed, 1947 insertions(+) >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmMultiBoardAcpiSupportLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmMultiBoardAcpiSupportLib.c > new file mode 100644 > index 0000000000..1436d9b79a > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmMultiBoardAcpiSupportLib.c > @@ -0,0 +1,88 @@ > +/** @file >=20 > + Tiger Lake U RVP SMM Multi-Board ACPI Support library >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TglBoardEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TglBoardDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +MultiBoardEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ) >=20 > +{ >=20 > + SiliconEnableAcpi (EnableSci); >=20 > + return TglBoardEnableAcpi (EnableSci); >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +MultiBoardDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ) >=20 > +{ >=20 > + SiliconDisableAcpi (DisableSci); >=20 > + return TglBoardDisableAcpi (DisableSci); >=20 > +} >=20 > + >=20 > +BOARD_ACPI_ENABLE_FUNC mBoardAcpiEnableFunc =3D { >=20 > + MultiBoardEnableAcpi, >=20 > + MultiBoardDisableAcpi, >=20 > +}; >=20 > + >=20 > +/** >=20 > + The constructor function to register mBoardAcpiEnableFunc function. >=20 > + >=20 > + @param[in] ImageHandle The firmware allocated handle for the EFI ima= ge. >=20 > + @param[in] SystemTable A pointer to the EFI System Table. >=20 > + >=20 > + @retval EFI_SUCCESS This constructor always return EFI_SUCCESS. >=20 > + It will ASSERT on errors. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SmmMultiBoardAcpiSupportLibConstructor ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); >=20 > + return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc); >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmMultiBoardAcpiSupportLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmMultiBoardAcpiSupportLib.inf > new file mode 100644 > index 0000000000..6f6a9272f9 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmMultiBoardAcpiSupportLib.inf > @@ -0,0 +1,43 @@ > +## @file >=20 > +# Tiger Lake U RVP SMM Multi-Board ACPI Support library >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D SmmMultiBoardAcpiSupportLib >=20 > + FILE_GUID =3D 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF= 5 >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D DXE_SMM_DRIVER >=20 > + LIBRARY_CLASS =3D NULL >=20 > + CONSTRUCTOR =3D SmmMultiBoardAcpiSupportLibConstruc= tor >=20 > + >=20 > +# >=20 > +# The following information is for reference only and not required by th= e build > tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + PciLib >=20 > + MmPciLib >=20 > + PchCycleDecodingLib >=20 > + PchPciBdfLib >=20 > + PmcLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + TigerlakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > + SmmTigerlakeURvpAcpiEnableLib.c >=20 > + SmmSiliconAcpiEnableLib.c >=20 > + SmmMultiBoardAcpiSupportLib.c >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmSiliconAcpiEnableLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmSiliconAcpiEnableLib.c > new file mode 100644 > index 0000000000..32afeb405e > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmSiliconAcpiEnableLib.c > @@ -0,0 +1,160 @@ > +/** @file >=20 > + Tiger Lake U RVP SMM Silicon ACPI Enable library >=20 > + >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Clear Port 80h >=20 > + >=20 > + SMI handler to enable ACPI mode >=20 > + >=20 > + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI >=20 > + >=20 > + Disables the SW SMI Timer. >=20 > + ACPI events are disabled and ACPI event status is cleared. >=20 > + SCI mode is then enabled. >=20 > + >=20 > + Clear SLP SMI status >=20 > + Enable SLP SMI >=20 > + >=20 > + Disable SW SMI Timer >=20 > + >=20 > + Clear all ACPI event status and disable all ACPI events >=20 > + >=20 > + Disable PM sources except power button >=20 > + Clear status bits >=20 > + >=20 > + Disable GPE0 sources >=20 > + Clear status bits >=20 > + >=20 > + Disable GPE1 sources >=20 > + Clear status bits >=20 > + >=20 > + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) >=20 > + >=20 > + Enable SCI >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ) >=20 > +{ >=20 > + >=20 > + UINT32 SmiEn; >=20 > + UINT32 SmiSts; >=20 > + UINT32 ULKMC; >=20 > + UINTN LpcBaseAddress; >=20 > + UINT16 AcpiBaseAddr; >=20 > + UINT32 Pm1Cnt; >=20 > + >=20 > + LpcBaseAddress =3D LpcPciCfgBase (); >=20 > + >=20 > + // >=20 > + // Get the ACPI Base Address >=20 > + // >=20 > + AcpiBaseAddr =3D PmcGetAcpiBase(); >=20 > + // >=20 > + // BIOS must also ensure that CF9GR is cleared and locked before handi= ng > control to the >=20 > + // OS in order to prevent the host from issuing global resets and rese= tting ME >=20 > + // >=20 > + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global R= eset >=20 > + // MmioWrite32 ( >=20 > + // PmcBaseAddress + R_PCH_PMC_ETR3), >=20 > + // PmInit); >=20 > + >=20 > + // >=20 > + // Clear Port 80h >=20 > + // >=20 > + IoWrite8 (0x80, 0); >=20 > + >=20 > + // >=20 > + // Disable SW SMI Timer and clean the status >=20 > + // >=20 > + SmiEn =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN); >=20 > + SmiEn &=3D ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | > B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB); >=20 > + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn); >=20 > + >=20 > + SmiSts =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS); >=20 > + SmiSts |=3D B_ACPI_IO_SMI_EN_LEGACY_USB2 | > B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB; >=20 > + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts); >=20 > + >=20 > + // >=20 > + // Disable port 60/64 SMI trap if they are enabled >=20 > + // >=20 > + ULKMC =3D MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & > ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN | > B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN | > B_LPC_CFG_ULKMC_A20PASSEN); >=20 > + MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC); >=20 > + >=20 > + // >=20 > + // Disable PM sources except power button >=20 > + // >=20 > + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, > B_ACPI_IO_PM1_EN_PWRBTN); >=20 > + >=20 > + // >=20 > + // Clear PM status except Power Button status for RapidStart Resume >=20 > + // >=20 > + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF); >=20 > + >=20 > + // >=20 > + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) >=20 > + // >=20 > + IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD); >=20 > + IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0); >=20 > + >=20 > + // >=20 > + // Enable SCI >=20 > + // >=20 > + if (EnableSci) { >=20 > + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT); >=20 > + Pm1Cnt |=3D B_ACPI_IO_PM1_CNT_SCI_EN; >=20 > + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ) >=20 > +{ >=20 > + >=20 > + UINT16 AcpiBaseAddr; >=20 > + UINT32 Pm1Cnt; >=20 > + >=20 > + // >=20 > + // Get the ACPI Base Address >=20 > + // >=20 > + AcpiBaseAddr =3D PmcGetAcpiBase(); >=20 > + // >=20 > + // Disable SCI >=20 > + // >=20 > + if (DisableSci) { >=20 > + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT); >=20 > + Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SCI_EN; >=20 > + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmTigerlakeURvpAcpiEnableLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmTigerlakeURvpAcpiEnableLib.c > new file mode 100644 > index 0000000000..3eb302c30d > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib= / > SmmTigerlakeURvpAcpiEnableLib.c > @@ -0,0 +1,51 @@ > +/** @file >=20 > + Tiger Lake U RVP SMM Board ACPI Enable library >=20 > + >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Enable Board Acpi >=20 > + >=20 > + @param[in] EnableSci Enable SCI if EnableSci parameters is True. >=20 > + >=20 > + @retval EFI_SUCCESS The function always return successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TglBoardEnableAcpi ( >=20 > + IN BOOLEAN EnableSci >=20 > + ) >=20 > +{ >=20 > + // enable additional board register >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Disable Board Acpi >=20 > + >=20 > + @param[in] DisableSci Disable SCI if DisableSci parameters is True= . >=20 > + >=20 > + @retval EFI_SUCCESS The function always return successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TglBoardDisableAcpi ( >=20 > + IN BOOLEAN DisableSci >=20 > + ) >=20 > +{ >=20 > + // enable additional board register >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /B > oardPchInitPreMemLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /B > oardPchInitPreMemLib.c > new file mode 100644 > index 0000000000..1c7e574f7d > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /B > oardPchInitPreMemLib.c > @@ -0,0 +1,160 @@ > +/** @file >=20 > + Source code for the board PCH configuration Pcd init functions for Pre= - > Memory Init phase. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include "TigerlakeURvpInit.h" >=20 > +#include "GpioTableTigerlakeUDdr4RvpPreMem.h" >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +/** >=20 > + Board Root Port Clock Info configuration init function for PEI pre-mem= ory > phase. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +RootPortClkInfoInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS]; >=20 > + UINT32 Index; >=20 > + >=20 > + // >=20 > + // The default clock assignment will be FREE_RUNNING, which correspond= s to > PchClockUsageUnspecified >=20 > + // This is safe but power-consuming setting. If Platform code doesn't = contain > port-clock map for a given board, >=20 > + // the clocks will keep on running anyway, allowing PCIe devices to op= erate. > Downside is that clocks will >=20 > + // continue to draw power. To prevent this, remember to provide port-c= lock > map for every board. >=20 > + // >=20 > + for (Index =3D 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) { >=20 > + Clock[Index].PcieClock.ClkReqSupported =3D TRUE; >=20 > + Clock[Index].PcieClock.ClockUsage =3D FREE_RUNNING; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Assign ClkReq signal to root port. (Base 0) >=20 > + /// For LP, Set 0 - 6 >=20 > + /// For H, Set 0 - 15 >=20 > + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be av= ailable > for Root Port. >=20 > + /// >=20 > + >=20 > + switch (BoardId) { >=20 > + // CLKREQ >=20 > + case BoardIdTglUDdr4: >=20 > + Clock[0].PcieClock.ClockUsage =3D PCIE_PEG; >=20 > + Clock[1].PcieClock.ClockUsage =3D PCIE_PCH + 2; >=20 > + Clock[2].PcieClock.ClockUsage =3D PCIE_PCH + 3; >=20 > + Clock[3].PcieClock.ClockUsage =3D PCIE_PCH + 8; >=20 > + Clock[4].PcieClock.ClockUsage =3D LAN_CLOCK; >=20 > + Clock[5].PcieClock.ClockUsage =3D PCIE_PCH + 7; >=20 > + Clock[6].PcieClock.ClockUsage =3D PCIE_PCH + 4; >=20 > + break; >=20 > + default: >=20 > + >=20 > + break; >=20 > + } >=20 > + >=20 > + PcdSet64S (PcdPcieClock0, Clock[ 0].Blob); >=20 > + PcdSet64S (PcdPcieClock1, Clock[ 1].Blob); >=20 > + PcdSet64S (PcdPcieClock2, Clock[ 2].Blob); >=20 > + PcdSet64S (PcdPcieClock3, Clock[ 3].Blob); >=20 > + PcdSet64S (PcdPcieClock4, Clock[ 4].Blob); >=20 > + PcdSet64S (PcdPcieClock5, Clock[ 5].Blob); >=20 > + PcdSet64S (PcdPcieClock6, Clock[ 6].Blob); >=20 > + PcdSet64S (PcdPcieClock7, Clock[ 7].Blob); >=20 > + PcdSet64S (PcdPcieClock8, Clock[ 8].Blob); >=20 > + PcdSet64S (PcdPcieClock9, Clock[ 9].Blob); >=20 > + PcdSet64S (PcdPcieClock10, Clock[10].Blob); >=20 > + PcdSet64S (PcdPcieClock11, Clock[11].Blob); >=20 > + PcdSet64S (PcdPcieClock12, Clock[12].Blob); >=20 > + PcdSet64S (PcdPcieClock13, Clock[13].Blob); >=20 > + PcdSet64S (PcdPcieClock14, Clock[14].Blob); >=20 > + PcdSet64S (PcdPcieClock15, Clock[15].Blob); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Board USB related configuration init function for PEI pre-memory phase= . >=20 > + >=20 > + @param[in] BoardId An unsigned integrer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +UsbConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Board GPIO Group Tier configuration init function for PEI pre-memory p= hase. >=20 > + >=20 > + @param[in] BoardId An unsigned integrer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioGroupTierInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + GPIO init function for PEI pre-memory phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integrer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +GpioTablePreMemInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + >=20 > + // >=20 > + // GPIO Table Init. >=20 > + // >=20 > + switch (BoardId) { >=20 > + case BoardIdTglUDdr4: >=20 > + PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) > mGpioTablePreMemTglUDdr4); >=20 > + PcdSet16S (PcdBoardGpioTablePreMemSize, > mGpioTablePreMemTglUDdr4Size); >=20 > + break; >=20 > + >=20 > + default: >=20 > + break; >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + PmConfig init function for PEI pre-memory phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integrer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PchPmConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /B > oardSaInitPreMemLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /B > oardSaInitPreMemLib.c > new file mode 100644 > index 0000000000..b468e21ec9 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /B > oardSaInitPreMemLib.c > @@ -0,0 +1,96 @@ > +/** @file >=20 > + Source code for the board SA configuration Pcd init functions in Pre-Me= mory > init phase. >=20 > + >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include "TigerlakeURvpInit.h" >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + MRC configuration init function for PEI pre-memory phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integer represent the board = id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +SaMiscConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // UserBd >=20 > + // >=20 > + switch (BoardId) { >=20 > + case BoardIdTglUDdr4: >=20 > + // >=20 > + // Assign UserBd to 5 which is assigned to MrcInputs->BoardType bt= User4 > for ULT platforms. >=20 > + // This is required to skip Memory voltage programming based on GP= IO's in > MRC >=20 > + // >=20 > + PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT pla= tform >=20 > + break; >=20 > + >=20 > + default: >=20 > + // MiscPeiPreMemConfig.UserBd =3D 0 by default. >=20 > + break; >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Board Memory Init related configuration init function for PEI pre-memo= ry > phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integrer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +MrcConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + >=20 > + PcdSet8S (PcdMrcSpdAddressTable0, 0xA0); >=20 > + PcdSet8S (PcdMrcSpdAddressTable1, 0xA2); >=20 > + PcdSet8S (PcdMrcSpdAddressTable2, 0xA4); >=20 > + PcdSet8S (PcdMrcSpdAddressTable3, 0xA6); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Board SA related GPIO configuration init function for PEI pre-memory p= hase. >=20 > + >=20 > + @param[in] BoardId An unsigned integer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +SaGpioConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + SA Display DDI configuration init function for PEI pre-memory phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +SaDisplayConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /G > pioTableTigerlakeUDdr4Rvp.h > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /G > pioTableTigerlakeUDdr4Rvp.h > new file mode 100644 > index 0000000000..0b605698c0 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /G > pioTableTigerlakeUDdr4Rvp.h > @@ -0,0 +1,93 @@ > +/** @file >=20 > + GPIO definition table for Tiger Lake U RVP >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_H_ >=20 > +#define _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +GPIO_INIT_CONFIG mGpioTableTglUDdr4[] =3D >=20 > +{ >=20 > + // M.2 Key-E - WLAN/BT >=20 > + {GPIO_VER2_LP_GPP_A13, {GpioPadModeGpio, GpioHostOwnDefault, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermNone, GpioPadConfigUnlock }}, // BT_RF_KILL_N >=20 > + {GPIO_VER2_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnDefault, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermNone, GpioPadConfigUnlock }}, // WIFI_RF_KILL_N >=20 > + {GPIO_VER2_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnDefault, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, > GpioTermNone, GpioPadConfigUnlock }}, // WLAN_RST_N >=20 > + {GPIO_VER2_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, > GpioTermNone, GpioPadConfigUnlock }}, // WIFI_WAKE_N >=20 > + {GPIO_VER2_LP_GPP_H19, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, > GpioTermNone, GpioPadConfigUnlock }}, // UART_BT_WAKE_N : Not default > POR >=20 > + {GPIO_VER2_LP_GPP_A10, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirIn, GpioOutDefault, GpioIntDis, GpioPlatformReset, > GpioTermNone}}, // M.2 BT >=20 > + >=20 > + // X4 Pcie Slot for Gen3 and Gen 4 >=20 > + {GPIO_VER2_LP_GPP_A14, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, > //ONBOARD_X4_PCIE_SLOT1_PWREN_N >=20 > + {GPIO_VER2_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //ONBOARD_X4_PCIE_SLOT1_RESET_N >=20 > + {GPIO_VER2_LP_GPP_F5, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, > GpioTermNone, GpioPadConfigUnlock }}, > //ONBOARD_X4_PCIE_SLOT1_WAKE_N >=20 > + {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //ONBOARD_X4_PCIE_SLOT1_DGPU_SEL >=20 > + {GPIO_VER2_LP_GPP_F21, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, > GpioOutDefault,GpioIntDis,GpioPlatformReset, GpioTermNone}}, > //ONBOARD_X4_PCIE_SLOT1_DGPU_PWROK >=20 > + >=20 > + // TBT Re-Timers >=20 > + {GPIO_VER2_LP_GPD7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, > GpioOutHigh, GpioIntDis,GpioDswReset, GpioTermNone}}, > //TCP_RETIMER_PERST_N >=20 > + >=20 > + // Battery Charger Vmin to PCH PROCHOT, derived from ICL >=20 > + {GPIO_VER2_LP_GPP_B2, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault,GpioIntEdge|GpioIntSci,GpioPlatformReset, > GpioTermNone, GpioPadConfigUnlock }}, //BC_PROCHOT_N >=20 > + >=20 > + // SATA Direct Connect >=20 > + {GPIO_VER2_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //SATA_DIRECT_PWREN >=20 > + >=20 > + // FPS >=20 > + {GPIO_VER2_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //FPS_RST_N >=20 > + {GPIO_VER2_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, > GpioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset, GpioTermNone, > GpioPadConfigUnlock }}, //FPS_INT >=20 > + >=20 > + // PCH M.2 SSD >=20 > + {GPIO_VER2_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //M2_PCH_SSD_PWREN >=20 > + {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //M2_SSD_RST_N >=20 > + >=20 > + >=20 > + // Camera >=20 > + {GPIO_VER2_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //CRD_CAM_PWREN - CAM1 >=20 > + {GPIO_VER2_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //WF_CAM_RST_N - CAM1 >=20 > + >=20 > + {GPIO_VER2_LP_GPP_H12, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //CAM2_RST_N >=20 > + >=20 > + {GPIO_VER2_LP_GPP_H15, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //CAM3_PWREN >=20 > + {GPIO_VER2_LP_GPP_H13, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //CAM3_RST_N >=20 > + >=20 > + // Camera Common GPIO's for all Camera, Rework Options >=20 > + {GPIO_VER2_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, > //CRD_CAM_STROBE_1 >=20 > + {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //WF_CAM_CLK_EN >=20 > + >=20 > + // Audio >=20 > + {GPIO_VER2_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //SPKR_PD_N >=20 > + {GPIO_VER2_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset, > GpioTermNone, GpioPadConfigUnlock }}, // CODEC_INT_N >=20 > + >=20 > + // Touch Pad >=20 > + // Touch Pad and Touch Panel 2 share the same Power Enable, default is > Touch pad >=20 > + {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //TCH_PAD_LS_EN - PWR_En >=20 > + {GPIO_VER2_LP_GPP_C8, {GpioPadModeGpio, GpioHostOwnGpio, > GpioDirInInv, GpioOutDefault,GpioIntEdge|GpioIntApic,GpioPlatformReset, > GpioTermNone, GpioPadConfigUnlock }}, //TCH_PAD_INT_N >=20 > + >=20 > + // EC >=20 > + {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, > GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N >=20 > + {GPIO_VER2_LP_GPP_E8, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, > GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, > //EC_SLP_S0_CS_N >=20 > + >=20 > + // SPI TPM, derived from ICL >=20 > + {GPIO_VER2_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, > GpioOutDefault,GpioIntLevel | GpioIntApic, GpioHostDeepReset, > GpioTermWpu20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N >=20 > + >=20 > + // TypeC BIAS : Not used by default in RVP, derived from ICL >=20 > + {GPIO_VER2_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, > //DISP_AUX_P_BIAS_GPIO >=20 > + {GPIO_VER2_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //DISP_AUX_N_BIAS_GPIO >=20 > + >=20 > + // LAN : Not used by Default in RVP >=20 > + >=20 > + // X1 Pcie Slot >=20 > + {GPIO_VER2_LP_GPP_F4, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, > GpioTermNone, GpioPadConfigUnlock }}, //X1 Slot WAKE >=20 > + {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}= , > //X1 Slot RESET >=20 > +}; >=20 > + >=20 > + >=20 > +UINT16 mGpioTableTglUDdr4Size =3D sizeof (mGpioTableTglUDdr4) / sizeof > (GPIO_INIT_CONFIG); >=20 > + >=20 > +#endif // _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_H_ >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /G > pioTableTigerlakeUDdr4RvpPreMem.h > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /G > pioTableTigerlakeUDdr4RvpPreMem.h > new file mode 100644 > index 0000000000..7b08676037 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /G > pioTableTigerlakeUDdr4RvpPreMem.h > @@ -0,0 +1,33 @@ > +/** @file >=20 > + GPIO definition table for Tiger Lake U DDR4 RVP Pre-Memory >=20 > + >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_PREMEM_H_ >=20 > +#define _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_PREMEM_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +GPIO_INIT_CONFIG mGpioTablePreMemTglUDdr4[] =3D >=20 > +{ >=20 > + { GPIO_VER2_LP_GPP_A14, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone } }, > //ONBOARD_X4_PCIE_SLOT1_PWREN_N >=20 > + { GPIO_VER2_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, > //ONBOARD_X4_PCIE_SLOT1_RESET_N >=20 > + // CPU M.2 SSD >=20 > + { GPIO_VER2_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, > //CPU SSD PWREN >=20 > + { GPIO_VER2_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, > //CPU SSD RESET >=20 > + // X1 Pcie Slot >=20 > + { GPIO_VER2_LP_GPP_F9, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, > //X1 Slot PWREN >=20 > + { GPIO_VER2_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone } }, > //TC_RETIMER_FORCE_PWR >=20 > + // Camera >=20 > + { GPIO_VER2_LP_GPP_R6, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, > //CAM2_PWREN/BIOS_REC >=20 > + { GPIO_VER2_LP_GPP_R5, { GpioPadModeGpio, GpioHostOwnAcpi, > GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone } }, > //CRD_CAM_PRIVACY_LED_1 >=20 > +}; >=20 > + >=20 > +UINT16 mGpioTablePreMemTglUDdr4Size =3D sizeof > (mGpioTablePreMemTglUDdr4) / sizeof (GPIO_INIT_CONFIG); >=20 > + >=20 > +#endif //_GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_PREMEM_H_ >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPostMemLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPostMemLib.c > new file mode 100644 > index 0000000000..f652dcf8e6 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPostMemLib.c > @@ -0,0 +1,41 @@ > +/** @file >=20 > + Tiger Lake U RVP Multi-Board Initialization Post-Memory library >=20 > + >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardInitBeforeSiliconInit( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +BOARD_POST_MEM_INIT_FUNC mTigerlakeURvpBoardInitFunc =3D { >=20 > + TigerlakeURvpBoardInitBeforeSiliconInit, >=20 > + NULL, // BoardInitAfterSiliconInit >=20 > +}; >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiTigerlakeURvpMultiBoardInitLibConstructor ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + if (LibPcdGetSku () =3D=3D SkuIdTglU) { >=20 > + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); >=20 > + return RegisterBoardPostMemInit (&mTigerlakeURvpBoardInitFunc); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPostMemLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPostMemLib.inf > new file mode 100644 > index 0000000000..d00f350dfe > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPostMemLib.inf > @@ -0,0 +1,49 @@ > +## @file >=20 > +# Component information file for TigerlakeURvpInitLib in PEI post memor= y > phase. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiTigerlakeURvpMultiBoardInitLib >=20 > + FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF901749928= 0 >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D NULL >=20 > + CONSTRUCTOR =3D PeiTigerlakeURvpMultiBoardInitLibCo= nstructor >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + DebugLib >=20 > + BaseMemoryLib >=20 > + MemoryAllocationLib >=20 > + PcdLib >=20 > + MultiBoardInitSupportLib >=20 > + PeiPlatformHookLib >=20 > + PciSegmentLib >=20 > + >=20 > +[Packages] >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + TigerlakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > + PeiTigerlakeURvpInitPostMemLib.c >=20 > + PeiMultiBoardInitPostMemLib.c >=20 > + >=20 > + GpioTableTigerlakeUDdr4Rvp.h >=20 > + >=20 > +[FixedPcd] >=20 > + >=20 > +[Pcd] >=20 > + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable >=20 > + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize >=20 > + >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase >=20 > + gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPreMemLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPreMemLib.c > new file mode 100644 > index 0000000000..6200f3b86e > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPreMemLib.c > @@ -0,0 +1,88 @@ > +/** @file >=20 > + Tiger Lake U RVP Multi-Board Initialization Pre-Memory library >=20 > + >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardDetect ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpMultiBoardDetect ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_BOOT_MODE >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardBootModeDetect ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardDebugInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardInitBeforeMemoryInit ( >=20 > + VOID >=20 > + ); >=20 > + >=20 > + >=20 > +BOARD_DETECT_FUNC mTigerlakeURvpBoardDetectFunc =3D { >=20 > + TigerlakeURvpMultiBoardDetect >=20 > +}; >=20 > + >=20 > +BOARD_PRE_MEM_INIT_FUNC mTigerlakeURvpBoardPreMemInitFunc =3D { >=20 > + TigerlakeURvpBoardDebugInit, >=20 > + TigerlakeURvpBoardBootModeDetect, >=20 > + TigerlakeURvpBoardInitBeforeMemoryInit, >=20 > + NULL, // BoardInitAfterMemoryInit >=20 > + NULL, // BoardInitBeforeTempRamExit >=20 > + NULL, // BoardInitAfterTempRamExit >=20 > +}; >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpMultiBoardDetect ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, " In TglUMultiBoardDetect \n")); >=20 > + >=20 > + TigerlakeURvpBoardDetect (); >=20 > + >=20 > + if (LibPcdGetSku () =3D=3D SkuIdTglU) { >=20 > + RegisterBoardPreMemInit (&mTigerlakeURvpBoardPreMemInitFunc); >=20 > + } else { >=20 > + DEBUG ((DEBUG_WARN,"Not a Valid TigerLake U Board\n")); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiTigerlakeURvpMultiBoardInitPreMemLibConstructor ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return RegisterBoardDetect (&mTigerlakeURvpBoardDetectFunc); >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPreMemLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPreMemLib.inf > new file mode 100644 > index 0000000000..b8f1cf8aee > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiMultiBoardInitPreMemLib.inf > @@ -0,0 +1,115 @@ > +## @file >=20 > +# Component information file for PEI TigerlakeURvp Board Init Pre-Mem > Library >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiTigerlakeURvpMultiBoardInitPreMe= mLib >=20 > + FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574= F >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D NULL >=20 > + CONSTRUCTOR =3D > PeiTigerlakeURvpMultiBoardInitPreMemLibConstructor >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + DebugLib >=20 > + BaseMemoryLib >=20 > + MemoryAllocationLib >=20 > + PcdLib >=20 > + PeiPlatformHookLib >=20 > + MultiBoardInitSupportLib >=20 > + PeiLib >=20 > + >=20 > +[Packages] >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + TigerlakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + IntelFsp2Pkg/IntelFsp2Pkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > + PeiTigerlakeURvpInitPreMemLib.c >=20 > + PeiMultiBoardInitPreMemLib.c >=20 > + PeiTigerlakeURvpDetect.c >=20 > + BoardSaInitPreMemLib.c >=20 > + BoardPchInitPreMemLib.c >=20 > + GpioTableTigerlakeUDdr4RvpPreMem.h >=20 > + >=20 > +[Ppis] >=20 > + gEfiPeiReadOnlyVariable2PpiGuid >=20 > + gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES >=20 > + gEfiPeiResetPpiGuid ## PRODUCES >=20 > +[Pcd] >=20 > + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort >=20 > + >=20 > + # SA Misc Config >=20 > + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdData >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize >=20 > + >=20 > + # SPD Address Table >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 >=20 > + >=20 > + #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > + # Board Init Table List >=20 > + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem >=20 > + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize >=20 > + >=20 > + # Board Information >=20 > + gBoardModuleTokenSpaceGuid.PcdCpuRatio >=20 > + gBoardModuleTokenSpaceGuid.PcdBiosGuard >=20 > + >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUM= ES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUM= ES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUM= ES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUM= ES >=20 > + >=20 > + # SA USB Config >=20 > + gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable >=20 > + >=20 > + # PCIe Clock Info >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock0 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock1 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock2 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock3 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock4 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock5 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock6 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock7 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock8 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock9 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock10 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock11 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock12 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock13 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock14 >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock15 >=20 > + >=20 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress >=20 > + >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress >=20 > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize >=20 > + >=20 > + gSiPkgTokenSpaceGuid.PcdMchBaseAddress >=20 > + gSiPkgTokenSpaceGuid.PcdMchMmioSize >=20 > + >=20 > + gBoardModuleTokenSpaceGuid.PcdDmiBaseAddress >=20 > + gBoardModuleTokenSpaceGuid.PcdDmiMmioSize >=20 > + gBoardModuleTokenSpaceGuid.PcdEpBaseAddress >=20 > + gBoardModuleTokenSpaceGuid.PcdEpMmioSize >=20 > + >=20 > +[Guids] >=20 > + gFspNonVolatileStorageHobGuid >=20 > + gEfiMemoryOverwriteControlDataGuid >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiTigerlakeURvpDetect.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiTigerlakeURvpDetect.c > new file mode 100644 > index 0000000000..a11724072f > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiTigerlakeURvpDetect.c > @@ -0,0 +1,39 @@ > +/** @file >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > + >=20 > +BOOLEAN >=20 > +TigerlakeURvp( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return TRUE; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardDetect ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + if (LibPcdGetSku () !=3D 0) { >=20 > + return EFI_SUCCESS; >=20 > + } >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "TigerLakeU Board Detection Callback\n")); >=20 > + >=20 > + if (TigerlakeURvp ()) { >=20 > + LibPcdSetSku (SkuIdTglU); >=20 > + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); >=20 > + ASSERT (LibPcdGetSku() =3D=3D SkuIdTglU); >=20 > + } >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiTigerlakeURvpInitPostMemLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiTigerlakeURvpInitPostMemLib.c > new file mode 100644 > index 0000000000..e775f83cce > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiTigerlakeURvpInitPostMemLib.c > @@ -0,0 +1,153 @@ > +/** @file >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include "TigerlakeURvpInit.h" >=20 > +#include "GpioTableTigerlakeUDdr4Rvp.h" >=20 > +#include >=20 > + >=20 > +/** >=20 > + GPIO init function for PEI post memory phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integrer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +BoardGpioInit( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // GPIO Table Init. >=20 > + // >=20 > + switch (BoardId) { >=20 > + >=20 > + case BoardIdTglUDdr4: >=20 > + PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableTglUDdr4); >=20 > + PcdSet16S (PcdBoardGpioTableSize, mGpioTableTglUDdr4Size); >=20 > + break; >=20 > + >=20 > + default: >=20 > + break; >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Touch panel GPIO init function for PEI post memory phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integrer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +TouchPanelGpioInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Misc. init function for PEI post memory phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integrer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +BoardMiscInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Security GPIO init function for PEI post memory phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integrer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +BoardSecurityInit ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Board configuration initialization in the post-memory boot phase. >=20 > +**/ >=20 > +VOID >=20 > +BoardConfigInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT16 BoardId; >=20 > + >=20 > + BoardId =3D BoardIdTglUDdr4; >=20 > + >=20 > + Status =3D BoardGpioInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D TouchPanelGpioInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D BoardMiscInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D BoardSecurityInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Configure GPIO and SIO >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardInitBeforeSiliconInit( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "Board Init before Silicon Init\n")); >=20 > + >=20 > + BoardConfigInit (); >=20 > + // >=20 > + // Configure GPIO and SIO >=20 > + // >=20 > + Status =3D BoardInit (); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // >=20 > + // Initializing Platform Specific Programming >=20 > + // >=20 > + Status =3D PlatformSpecificInit (); >=20 > + ASSERT_EFI_ERROR(Status); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiTigerlakeURvpInitPreMemLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiTigerlakeURvpInitPreMemLib.c > new file mode 100644 > index 0000000000..2ad229c1cd > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /P > eiTigerlakeURvpInitPreMemLib.c > @@ -0,0 +1,445 @@ > +/** @file >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/// >=20 > +/// Reset Generator I/O Port >=20 > +/// >=20 > +#define RESET_GENERATOR_PORT 0xCF9 >=20 > + >=20 > +typedef struct { >=20 > + EFI_PHYSICAL_ADDRESS BaseAddress; >=20 > + UINT64 Length; >=20 > +} MEMORY_MAP; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] =3D { >=20 > + { FixedPcdGet64 (PcdLocalApicAddress), FixedPcdGet32 > (PcdLocalApicMmioSize) }, >=20 > + { FixedPcdGet64 (PcdMchBaseAddress), FixedPcdGet32 (PcdMchMmioSize)= }, >=20 > + { FixedPcdGet64 (PcdDmiBaseAddress), FixedPcdGet32 (PcdDmiMmioSize)= }, >=20 > + { FixedPcdGet64 (PcdEpBaseAddress), FixedPcdGet32 (PcdEpMmioSize) = } >=20 > +}; >=20 > + >=20 > +EFI_STATUS >=20 > +MrcConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +SaGpioConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +SaMiscConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +RootPortClkInfoInit ( >=20 > + IN UINT16 BoardId >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +UsbConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +GpioGroupTierInit ( >=20 > + IN UINT16 BoardId >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +GpioTablePreMemInit ( >=20 > + IN UINT16 BoardId >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +PchPmConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +SaDisplayConfigInit ( >=20 > + IN UINT16 BoardId >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PlatformInitPreMemCallBack ( >=20 > + IN CONST EFI_PEI_SERVICES **PeiServices, >=20 > + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, >=20 > + IN VOID *Ppi >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +MemoryDiscoveredPpiNotify ( >=20 > + IN CONST EFI_PEI_SERVICES **PeiServices, >=20 > + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, >=20 > + IN VOID *Ppi >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PchReset ( >=20 > + IN CONST EFI_PEI_SERVICES **PeiServices >=20 > + ); >=20 > + >=20 > +static EFI_PEI_RESET_PPI mResetPpi =3D { >=20 > + PchReset >=20 > +}; >=20 > + >=20 > +static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] =3D { >=20 > + { >=20 > + (EFI_PEI_PPI_DESCRIPTOR_PPI | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), >=20 > + &gEfiPeiResetPpiGuid, >=20 > + &mResetPpi >=20 > + } >=20 > +}; >=20 > + >=20 > +static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList =3D { >=20 > + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), >=20 > + &gEfiPeiReadOnlyVariable2PpiGuid, >=20 > + (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack >=20 > +}; >=20 > + >=20 > +static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =3D { >=20 > + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), >=20 > + &gEfiPeiMemoryDiscoveredPpiGuid, >=20 > + (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify >=20 > +}; >=20 > + >=20 > +/** >=20 > + Board misc init function for PEI pre-memory phase. >=20 > + >=20 > + @param[in] BoardId An unsigned integer represent the board id. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +BoardMiscInitPreMem ( >=20 > + IN UINT16 BoardId >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Board configuration initialization in the pre-memory boot phase. >=20 > +**/ >=20 > +VOID >=20 > +BoardConfigInitPreMem ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT16 BoardId; >=20 > + >=20 > + BoardId =3D BoardIdTglUDdr4; >=20 > + >=20 > + Status =3D MrcConfigInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D SaGpioConfigInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D SaMiscConfigInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D RootPortClkInfoInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D UsbConfigInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D GpioGroupTierInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D GpioTablePreMemInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D PchPmConfigInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D BoardMiscInitPreMem (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + Status =3D SaDisplayConfigInit (BoardId); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > +} >=20 > + >=20 > +/** >=20 > + This function handles PlatformInit task after PeiReadOnlyVariable2 PPI > produced >=20 > + >=20 > + @param[in] PeiServices Pointer to PEI Services Table. >=20 > + @param[in] NotifyDesc Pointer to the descriptor for the Notificati= on event > that >=20 > + caused this function to execute. >=20 > + @param[in] Ppi Pointer to the PPI data associated with this= function. >=20 > + >=20 > + @retval EFI_SUCCESS The function completes successfully >=20 > + @retval others Failure >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PlatformInitPreMemCallBack ( >=20 > + IN CONST EFI_PEI_SERVICES **PeiServices, >=20 > + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, >=20 > + IN VOID *Ppi >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "PlatformInitPreMemCallBack Start...\n")); >=20 > + // >=20 > + // Init Board Config Pcd. >=20 > + // >=20 > + BoardConfigInitPreMem (); >=20 > + >=20 > + /// >=20 > + /// Configure GPIO and SIO >=20 > + /// >=20 > + Status =3D BoardInitPreMem (); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + /// >=20 > + /// Install Pre Memory PPIs >=20 > + /// >=20 > + Status =3D PeiServicesInstallPpi (&mPreMemPpiList[0]); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "PlatformInitPreMemCallBack End...\n")); >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Provide hard reset PPI service. >=20 > + To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT > (0xCF9). >=20 > + >=20 > + @param[in] PeiServices General purpose services available to ev= ery PEIM. >=20 > + >=20 > + @retval Not return System reset occured. >=20 > + @retval EFI_DEVICE_ERROR Device error, could not reset the system= . >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PchReset ( >=20 > + IN CONST EFI_PEI_SERVICES **PeiServices >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "Perform Cold Reset\n")); >=20 > + IoWrite8 (RESET_GENERATOR_PORT, 0x0E); >=20 > + >=20 > + CpuDeadLoop (); >=20 > + >=20 > + /// >=20 > + /// System reset occured, should never reach at this line. >=20 > + /// >=20 > + ASSERT_EFI_ERROR (EFI_DEVICE_ERROR); >=20 > + return EFI_DEVICE_ERROR; >=20 > +} >=20 > + >=20 > +/** >=20 > + Install Firmware Volume Hob's once there is main memory >=20 > + >=20 > + @param[in] PeiServices General purpose services available to ev= ery PEIM. >=20 > + @param[in] NotifyDescriptor Notify that this module published. >=20 > + @param[in] Ppi PPI that was installed. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +MemoryDiscoveredPpiNotify ( >=20 > + IN CONST EFI_PEI_SERVICES **PeiServices, >=20 > + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, >=20 > + IN VOID *Ppi >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_BOOT_MODE BootMode; >=20 > + UINTN Index; >=20 > + UINT8 PhysicalAddressBits; >=20 > + UINT32 RegEax; >=20 > + MEMORY_MAP PcieMmioMap; >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "MemoryDiscoveredPpiNotify Start!\n")); >=20 > + >=20 > + Index =3D 0; >=20 > + >=20 > + Status =3D PeiServicesGetBootMode (&BootMode); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); >=20 > + if (RegEax >=3D 0x80000008) { >=20 > + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); >=20 > + PhysicalAddressBits =3D (UINT8)RegEax; >=20 > + } >=20 > + else { >=20 > + PhysicalAddressBits =3D 36; >=20 > + } >=20 > + >=20 > + /// >=20 > + /// Create a CPU hand-off information >=20 > + /// >=20 > + BuildCpuHob (PhysicalAddressBits, 16); >=20 > + >=20 > + /// >=20 > + /// Build Memory Mapped IO Resource which is used to build E820 Table = in > LegacyBios. >=20 > + /// >=20 > + PcieMmioMap.BaseAddress =3D FixedPcdGet64 (PcdPciExpressBaseAddress); >=20 > + PcieMmioMap.Length =3D PcdGet32 (PcdPciExpressRegionLength); >=20 > + >=20 > + BuildResourceDescriptorHob ( >=20 > + EFI_RESOURCE_MEMORY_MAPPED_IO, >=20 > + (EFI_RESOURCE_ATTRIBUTE_PRESENT | >=20 > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | >=20 > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), >=20 > + PcieMmioMap.BaseAddress, >=20 > + PcieMmioMap.Length >=20 > + ); >=20 > + BuildMemoryAllocationHob ( >=20 > + PcieMmioMap.BaseAddress, >=20 > + PcieMmioMap.Length, >=20 > + EfiMemoryMappedIO >=20 > + ); >=20 > + for (Index =3D 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP)); Inde= x++) { >=20 > + BuildResourceDescriptorHob ( >=20 > + EFI_RESOURCE_MEMORY_MAPPED_IO, >=20 > + (EFI_RESOURCE_ATTRIBUTE_PRESENT | >=20 > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | >=20 > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), >=20 > + MmioMap[Index].BaseAddress, >=20 > + MmioMap[Index].Length >=20 > + ); >=20 > + BuildMemoryAllocationHob ( >=20 > + MmioMap[Index].BaseAddress, >=20 > + MmioMap[Index].Length, >=20 > + EfiMemoryMappedIO >=20 > + ); >=20 > + } >=20 > + >=20 > + // >=20 > + // Report resource HOB for flash FV >=20 > + // >=20 > + BuildResourceDescriptorHob ( >=20 > + EFI_RESOURCE_MEMORY_MAPPED_IO, >=20 > + (EFI_RESOURCE_ATTRIBUTE_PRESENT | >=20 > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | >=20 > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), >=20 > + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress), >=20 > + (UINTN) FixedPcdGet32 (PcdFlashAreaSize) >=20 > + ); >=20 > + >=20 > + BuildMemoryAllocationHob ( >=20 > + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress), >=20 > + (UINTN) FixedPcdGet32 (PcdFlashAreaSize), >=20 > + EfiMemoryMappedIO >=20 > + ); >=20 > + >=20 > + BuildFvHob ( >=20 > + (UINTN)FixedPcdGet32 (PcdFlashAreaBaseAddress), >=20 > + (UINTN)FixedPcdGet32 (PcdFlashAreaSize) >=20 > + ); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "MemoryDiscoveredPpiNotify End!\n")); >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Board configuration init function for PEI pre-memory phase. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > + @retval EFI_INVALID_PARAMETER The parameter is NULL. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpInitPreMem ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + DEBUG ((DEBUG_INFO, "TigerlakeURvpInitPreMem Start!\n")); >=20 > + /// >=20 > + /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 P= PI > produced >=20 > + /// >=20 > + Status =3D PeiServicesNotifyPpi (&mPreMemNotifyList); >=20 > + >=20 > + /// >=20 > + /// After code reorangized, memorycallback will run because the PPI is= already >=20 > + /// installed when code run to here, it is supposed that the InstallEf= iMemory is >=20 > + /// done before. >=20 > + /// >=20 > + Status =3D PeiServicesNotifyPpi (&mMemDiscoveredNotifyList); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "TigerlakeURvpInitPreMem End!\n")); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure GPIO and SIO before memory ready >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardInitBeforeMemoryInit( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + >=20 > + TigerlakeURvpInitPreMem(); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardDebugInit( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + /// >=20 > + /// Do Early PCH init >=20 > + /// >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +EFI_BOOT_MODE >=20 > +EFIAPI >=20 > +TigerlakeURvpBoardBootModeDetect( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return BOOT_WITH_FULL_CONFIGURATION; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /T > igerlakeURvpInit.h > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /T > igerlakeURvpInit.h > new file mode 100644 > index 0000000000..ccffcc6761 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib= /T > igerlakeURvpInit.h > @@ -0,0 +1,23 @@ > +/** @file >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _TIGER_LAKE_U_RVP_INIT_H_ >=20 > +#define _TIGER_LAKE_U_RVP_INIT_H_ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern GPIO_INIT_CONFIG mGpioTableTglUDdr4[]; >=20 > +extern UINT16 mGpioTableTglUDdr4Size; >=20 > + >=20 > + >=20 > +#endif // _TIGER_LAKE_U_RVP_INIT_H_ >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformH= o > okLib/PeiPlatformHooklib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformH= o > okLib/PeiPlatformHooklib.c > new file mode 100644 > index 0000000000..6c2587391d > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformH= o > okLib/PeiPlatformHooklib.c > @@ -0,0 +1,212 @@ > +/** @file >=20 > + PEI Library Functions. Initialize GPIOs >=20 > + >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680 >=20 > + >=20 > +#define RECOVERY_MODE_GPIO_PIN 0 /= / Platform > specific @todo use PCD >=20 > + >=20 > +#define MANUFACTURE_MODE_GPIO_PIN 0 /= / Platform > specific @todo use PCD >=20 > + >=20 > +/** >=20 > + Configures GPIO >=20 > + >=20 > + @param[in] GpioTable Point to Platform Gpio table >=20 > + @param[in] GpioTableCount Number of Gpio table entries >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +ConfigureGpio ( >=20 > + IN GPIO_INIT_CONFIG *GpioDefinition, >=20 > + IN UINT16 GpioTableCount >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); >=20 > + >=20 > + >=20 > + CreateGpioCheckConflictHob (GpioDefinition, GpioTableCount); >=20 > + >=20 > + >=20 > + GpioConfigurePads (GpioTableCount, GpioDefinition); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure GPIO group GPE tier. >=20 > + >=20 > + @retval none. >=20 > +**/ >=20 > +VOID >=20 > +GpioGroupTierInitHook( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook Start\n")); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook End\n")); >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure single GPIO pad for touchpanel interrupt >=20 > +**/ >=20 > +VOID >=20 > +TouchpanelGpioInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure GPIO Before Memory is not ready. >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +GpioInitPreMem ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + if (PcdGet32 (PcdBoardGpioTablePreMem) !=3D 0 && PcdGet16 > (PcdBoardGpioTablePreMemSize) !=3D 0) { >=20 > + DEBUG ((DEBUG_INFO, "Pre-mem Gpio Config\n")); >=20 > + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTablePreMem), > (UINTN) PcdGet16 (PcdBoardGpioTablePreMemSize)); >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + Basic GPIO configuration before memory is ready >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +GpioInitEarlyPreMem ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure GPIO >=20 > + >=20 > +**/ >=20 > + >=20 > +VOID >=20 > +GpioInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "Post-mem Gpio Config\n")); >=20 > + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN) > PcdGet16 (PcdBoardGpioTableSize)); >=20 > + >=20 > + TouchpanelGpioInit(); >=20 > + >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure Super IO >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +SioInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Program and Enable Default Super IO Configuration Port Addresses an= d > range >=20 > + // >=20 > + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), > 0x10); >=20 > + >=20 > + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10); >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure GPIO and SIO before memory ready >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +BoardInitPreMem ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + // >=20 > + // Obtain Platform Info from HOB. >=20 > + // >=20 > + GpioInitPreMem (); >=20 > + GpioGroupTierInitHook (); >=20 > + SioInit (); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "BoardInitPreMem Done\n")); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Configure GPIO and SIO >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +BoardInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + >=20 > + GpioInit (); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Do platform specific programming post-memory. >=20 > + >=20 > + @retval EFI_SUCCESS The function completed successfully. >=20 > +**/ >=20 > + >=20 > +EFI_STATUS >=20 > +PlatformSpecificInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Early Board Configuration before memory is ready >=20 > + >=20 > + @retval EFI_SUCCESS Operation success. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +BoardInitEarlyPreMem ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + GpioInitEarlyPreMem (); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformH= o > okLib/PeiPlatformHooklib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformH= o > okLib/PeiPlatformHooklib.inf > new file mode 100644 > index 0000000000..8e4ce47d5a > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformH= o > okLib/PeiPlatformHooklib.inf > @@ -0,0 +1,58 @@ > +## @file >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D PeiPlatformHookLib >=20 > + FILE_GUID =3D AD901798-B0DA-4B20-B90C-283F886E76D= 0 >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D PEIM >=20 > + LIBRARY_CLASS =3D PeiPlatformHookLib|PEIM PEI_CORE SE= C >=20 > + >=20 > +[LibraryClasses] >=20 > + DebugLib >=20 > + BaseMemoryLib >=20 > + IoLib >=20 > + HobLib >=20 > + PcdLib >=20 > + TimerLib >=20 > + PchCycleDecodingLib >=20 > + GpioLib >=20 > + PeiServicesLib >=20 > + ConfigBlockLib >=20 > + PmcLib >=20 > + PchPcrLib >=20 > + PciSegmentLib >=20 > + GpioCheckConflictLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Pcd] >=20 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress = ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize ## > CONSUMES >=20 > + >=20 > +[Sources] >=20 > + PeiPlatformHooklib.c >=20 > + >=20 > +[Ppis] >=20 > + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES >=20 > + gSiPolicyPpiGuid ## CONSUMES >=20 > + >=20 > +[Guids] >=20 > + gSaDataHobGuid ## CONSUMES >=20 > + gEfiGlobalVariableGuid ## CONSUMES >=20 > + gGpioCheckConflictHobGuid ## CONSUMES >=20 > + >=20 > -- > 2.24.0.windows.2