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Tue, 9 Feb 2021 08:47:10 +0000 From: "Heng Luo" To: "Chaganty, Rangasai V" , "devel@edk2.groups.io" CC: "Desimone, Nathaniel L" Subject: Re: [PATCH 3/8] TigerlakeOpenBoardPkg: Add library instances Thread-Topic: [PATCH 3/8] TigerlakeOpenBoardPkg: Add library instances Thread-Index: AQHW/ROC/DXZYvRT4UKYFbuKphMRGKpO/kWAgAAAvdCAAEvtAA== Date: Tue, 9 Feb 2021 08:47:10 +0000 Message-ID: References: <20210207053834.4048-1-heng.luo@intel.com> <20210207053834.4048-3-heng.luo@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.198.147.210] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 42438cbc-83cb-451e-1ad6-08d8ccd74a02 x-ms-traffictypediagnostic: MWHPR11MB0016: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:316; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thank Sai, I have sent Patch V2:=20 1. remove file PeiFspSiPolicyInitLib.c. 2. remove "PeiFspSiPolicyInitLib.c" from FspWrapper\Library\PeiFspPolicyIni= tLib\PeiFspPolicyInitLib.inf 3. remove the code below It8628SioSerialPortInit Thanks, Heng > -----Original Message----- > From: Chaganty, Rangasai V > Sent: Tuesday, February 9, 2021 8:45 AM > To: Luo, Heng ; devel@edk2.groups.io > Cc: Desimone, Nathaniel L > Subject: RE: [PATCH 3/8] TigerlakeOpenBoardPkg: Add library instances >=20 > Also, PeiFspSiPolicyInitLib.c is only including three header files. Pleas= e double > check and remove this file if these header files are already included by = the callers. >=20 > -----Original Message----- > From: Chaganty, Rangasai V > Sent: Monday, February 08, 2021 4:43 PM > To: Luo, Heng ; devel@edk2.groups.io > Cc: Desimone, Nathaniel L > Subject: RE: [PATCH 3/8] TigerlakeOpenBoardPkg: Add library instances >=20 > In BasePlatformHookLib.c, the code below It8628SioSerialPortInit () can b= e > removed. >=20 > Thanks, > Sai >=20 > -----Original Message----- > From: Luo, Heng > Sent: Saturday, February 06, 2021 9:38 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Desimone, > Nathaniel L > Subject: [PATCH 3/8] TigerlakeOpenBoardPkg: Add library instances >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3175 >=20 > Adds the following library instances: > * FspWrapper/Library/PeiFspPolicyInitLib > * FspWrapper/Library/PeiSiDefaultPolicyInitLib > * FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib > * Library/BasePlatformHookLib > * Library/SmmSpiFlashCommonLib > * Policy/Library/DxeSiliconPolicyUpdateLib >=20 > Cc: Sai Chaganty > Cc: Nate DeSimone > Signed-off-by: Heng Luo > --- >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspCpuPolicyInitLib.c | 79 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspMePolicyInitLib.c | 51 > +++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspMiscUpdInitLib.c | 27 +++++++++++++++++++= ++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspPchPolicyInitLib.c | 372 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspPolicyInitLib.c | 308 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspPolicyInitLib.h | 187 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspPolicyInitLib.inf | 184 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspSaPolicyInitLib.c | 240 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspSecurityPolicyInitLib.c | 49 > +++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitL= ib/ > PeiFspSiPolicyInitLib.c | 10 ++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolic= yI > nitLib/PeiSiDefaultPolicyInitLib.c | 39 > +++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolic= yI > nitLib/PeiSiDefaultPolicyInitLib.inf | 38 > ++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefau > ltPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c | 40 > ++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefau > ltPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf | 38 > ++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlat= f > ormHookLib.c | 460 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlat= f > ormHookLib.inf | 51 > +++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmS > piFlashCommonLib.inf | 49 > +++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFla > shCommon.c | 210 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFla > shCommonSmmLib.c | 58 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat= eLi > b/DxeGopPolicyInit.c | 168 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat= eLi > b/DxePchPolicyInit.c | 61 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat= eLi > b/DxeSaPolicyInit.c | 61 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat= eLi > b/DxeSiliconPolicyUpdateLate.c | 97 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++ >=20 > Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat= eLi > b/DxeSiliconPolicyUpdateLib.inf | 49 > +++++++++++++++++++++++++++++++++++++++++++++++++ > 24 files changed, 2926 insertions(+) >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspCpuPolicyInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspCpuPolicyInitLib.c > new file mode 100644 > index 0000000000..1358d6a19b > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspCpuPolicyInitLib.c > @@ -0,0 +1,79 @@ > +/** @file >=20 > + Implementation of Fsp CPU Policy Initialization. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Performs FSP CPU PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspCpuPolicyInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; >=20 > + CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig; >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + EFI_STATUS Status; >=20 > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; >=20 > + SiPreMemPolicyPpi =3D NULL; >=20 > +#endif >=20 > + >=20 > + CpuConfigLibPreMemConfig =3D NULL; >=20 > + CpuSecurityPreMemConfig =3D NULL; >=20 > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem > Start\n")); >=20 > + >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + // >=20 > + // Locate SiPreMemPolicyPpi >=20 > + // >=20 > + Status =3D PeiServicesLocatePpi ( >=20 > + &gSiPreMemPolicyPpiGuid, >=20 > + 0, >=20 > + NULL, >=20 > + (VOID **) &SiPreMemPolicyPpi >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); >=20 > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem > End\n")); >=20 > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig); >=20 > + ASSERT_EFI_ERROR(Status); >=20 > +#endif >=20 > + // >=20 > + // Cpu Config Lib policies >=20 > + // >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.CpuRatio, > CpuConfigLibPreMemConfig->CpuRatio, 0); >=20 > + DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n")); >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.BiosGuard, > CpuSecurityPreMemConfig->BiosGuard, 0); >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.PrmrrSize, > CpuSecurityPreMemConfig->PrmrrSize, SIZE_1MB); >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.EnableC6Dram, > CpuSecurityPreMemConfig->EnableC6Dram, 1); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspMePolicyInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspMePolicyInitLib.c > new file mode 100644 > index 0000000000..53b5ef43cd > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspMePolicyInitLib.c > @@ -0,0 +1,51 @@ > +/** @file >=20 > + Implementation of Fsp Me Policy Initialization. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Performs FSP ME PEI Policy pre mem initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspMePolicyInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n")); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs FSP ME PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspMePolicyInit ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n")); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspMiscUpdInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspMiscUpdInitLib.c > new file mode 100644 > index 0000000000..5a12e569d9 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspMiscUpdInitLib.c > @@ -0,0 +1,27 @@ > +/** @file >=20 > + Implementation of Fsp Misc UPD Initialization. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +/** >=20 > + Performs FSP Misc UPD initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspMiscUpdInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPchPolicyInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPchPolicyInitLib.c > new file mode 100644 > index 0000000000..67b75d6faf > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPchPolicyInitLib.c > @@ -0,0 +1,372 @@ > +/** @file >=20 > + Implementation of Fsp PCH Policy Initialization. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +// >=20 > +// USB limits >=20 > +// >=20 > +#define PCH_MAX_USB2_PORTS 16 >=20 > +#define PCH_MAX_USB3_PORTS 10 >=20 > + >=20 > +// >=20 > +// TypeC port map GPIO pin >=20 > +// >=20 > +IOM_AUX_ORI_PAD_CONFIG > mIomAuxNullTable[MAX_IOM_AUX_BIAS_COUNT] =3D { >=20 > + // Pull UP GPIO Pin, Pull Down GPIO pin >=20 > + {0, 0}, // Port 0 >=20 > + {0, 0}, // Port 1 >=20 > + {0, 0}, // Port 2 >=20 > + {0, 0}, // Port 3 >=20 > +}; >=20 > + >=20 > + >=20 > +VOID >=20 > +UpdatePcieClockInfo ( >=20 > + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig, >=20 > + IN FSPM_UPD *FspmUpd, >=20 > + UINTN Index, >=20 > + UINT64 Data >=20 > + ) >=20 > +{ >=20 > + PCD64_BLOB Pcd64; >=20 > + >=20 > + Pcd64.Blob =3D Data; >=20 > + DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, > Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, > Pcd64.PcieClock.ClkReqSupported)); >=20 > + >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.PcieClkSrcUsage[Index], > PcieRpPreMemConfig->PcieClock[Index].Usage, > (UINT8)Pcd64.PcieClock.ClockUsage); >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.PcieClkSrcClkReq[Index], > PcieRpPreMemConfig->PcieClock[Index].ClkReq, > Pcd64.PcieClock.ClkReqSupported ? (UINT8)Index : 0xFF); >=20 > +} >=20 > +/** >=20 > + Performs FSP PCH PEI Policy pre mem initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspPchPolicyInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + UINTN Index; >=20 > + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; >=20 > + HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig; >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; >=20 > + EFI_STATUS Status; >=20 > + >=20 > + // >=20 > + // Locate PchPreMemPolicyPpi >=20 > + // >=20 > + SiPreMemPolicy =3D NULL; >=20 > + PcieRpPreMemConfig =3D NULL; >=20 > + HdaPreMemConfig =3D NULL; >=20 > + Status =3D PeiServicesLocatePpi ( >=20 > + &gSiPreMemPolicyPpiGuid, >=20 > + 0, >=20 > + NULL, >=20 > + (VOID **) &SiPreMemPolicy >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gHdAudioPreMemConfigGuid, (VOID *) &HdaPreMemConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > +#else >=20 > + PcieRpPreMemConfig =3D NULL; >=20 > + HdaPreMemConfig =3D NULL; >=20 > +#endif >=20 > + >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64 > (PcdPcieClock0)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64 > (PcdPcieClock1)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64 > (PcdPcieClock2)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64 > (PcdPcieClock3)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64 > (PcdPcieClock4)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64 > (PcdPcieClock5)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64 > (PcdPcieClock6)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64 > (PcdPcieClock7)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64 > (PcdPcieClock8)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64 > (PcdPcieClock9)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64 > (PcdPcieClock10)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64 > (PcdPcieClock11)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64 > (PcdPcieClock12)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64 > (PcdPcieClock13)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64 > (PcdPcieClock14)); >=20 > + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64 > (PcdPcieClock15)); >=20 > + >=20 > + // >=20 > + // Update HDA policies >=20 > + // >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaIDispLinkTmode, > HdaPreMemConfig->IDispLinkTmode, 0); >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaSdiEnable[0], > HdaPreMemConfig->AudioLinkHda.SdiEnable[0], FALSE); >=20 > + >=20 > + for (Index =3D 0; Index < GetPchHdaMaxDmicLinkNum (); Index++) { >=20 > + UPDATE_POLICY (FspmUpd- > >FspmConfig.PchHdaAudioLinkDmicClockSelect[Index], HdaPreMemConfig- > >AudioLinkDmic[Index].DmicClockSelect, 0); >=20 > + } >=20 > + DEBUG((DEBUG_INFO | DEBUG_INIT, "UpdatePeiPchPolicyPreMem\n")); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + This function updates USB Policy per port OC Pin number >=20 > + >=20 > + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer >=20 > + @param[in] PortIndex USB Port index >=20 > + @param[in] Pin OverCurrent pin number >=20 > +**/ >=20 > +VOID >=20 > +UpdateUsb20OverCurrentPolicy ( >=20 > + IN OUT FSPS_UPD *FspsUpd, >=20 > + IN USB_CONFIG *UsbConfig, >=20 > + IN UINT8 PortIndex, >=20 > + UINT8 Pin >=20 > +) >=20 > +{ >=20 > + if (PortIndex < MAX_USB2_PORTS && ((Pin < USB_OC_MAX_PINS) || (Pin =3D= =3D > USB_OC_SKIP))) { >=20 > + UPDATE_POLICY ( >=20 > + FspsUpd->FspsConfig.Usb2OverCurrentPin[PortIndex], >=20 > + UsbConfig->PortUsb20[PortIndex].OverCurrentPin, >=20 > + Pin >=20 > + ); >=20 > + } else { >=20 > + if (PortIndex >=3D MAX_USB2_PORTS) { >=20 > + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port > number %d is not a valid USB2 port number\n", PortIndex)); >=20 > + } else { >=20 > + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid > OverCurrent pin specified USB2 port %d\n", PortIndex)); >=20 > + } >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + This function updates USB Policy per port OC Pin number >=20 > + >=20 > + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer >=20 > + @param[in] PortIndex USB Port index >=20 > + @param[in] Pin OverCurrent pin number >=20 > +**/ >=20 > +VOID >=20 > +UpdateUsb30OverCurrentPolicy ( >=20 > + IN OUT FSPS_UPD *FspsUpd, >=20 > + IN USB_CONFIG *UsbConfig, >=20 > + IN UINT8 PortIndex, >=20 > + UINT8 Pin >=20 > +) >=20 > +{ >=20 > + if (PortIndex < MAX_USB3_PORTS && ((Pin < USB_OC_MAX_PINS) || (Pin =3D= =3D > USB_OC_SKIP))) { >=20 > + UPDATE_POLICY ( >=20 > + FspsUpd->FspsConfig.Usb3OverCurrentPin[PortIndex], >=20 > + UsbConfig->PortUsb30[PortIndex].OverCurrentPin, >=20 > + Pin >=20 > + ); >=20 > + } else { >=20 > + if (PortIndex >=3D MAX_USB2_PORTS) { >=20 > + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port > number %d is not a valid USB3 port number\n", PortIndex)); >=20 > + } else { >=20 > + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid > OverCurrent pin specified USB3 port %d\n", PortIndex)); >=20 > + } >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > + This function performs PCH USB Platform Policy initialization >=20 > + >=20 > + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer >=20 > + @param[in] PchSetup Pointer to PCH_SETUP data buffer >=20 > +**/ >=20 > +VOID >=20 > +UpdatePchUsbConfig ( >=20 > + IN OUT FSPS_UPD *FspsUpd, >=20 > + IN OUT USB_CONFIG *UsbConfig >=20 > + ) >=20 > +{ >=20 > + UINTN PortIndex; >=20 > + >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.PchUsbOverCurrentEnable, > UsbConfig->OverCurrentEnable, TRUE); >=20 > + >=20 > + for (PortIndex =3D 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); > PortIndex++) { >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.PortUsb20Enable[PortIndex], > UsbConfig->PortUsb20[PortIndex].Enable, TRUE); >=20 > + } >=20 > + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortInd= ex++) { >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.PortUsb30Enable[PortIndex], > UsbConfig->PortUsb30[PortIndex].Enable, TRUE); >=20 > + } >=20 > + >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.XdciEnable, UsbConfig- > >XdciConfig.Enable, FALSE); >=20 > + >=20 > + // >=20 > + // Platform Board programming per the layout of each port. >=20 > + // >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 0, PcdGet8 > (PcdUsb20OverCurrentPinPort0)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 1, PcdGet8 > (PcdUsb20OverCurrentPinPort1)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 2, PcdGet8 > (PcdUsb20OverCurrentPinPort2)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 3, PcdGet8 > (PcdUsb20OverCurrentPinPort3)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 4, PcdGet8 > (PcdUsb20OverCurrentPinPort4)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 5, PcdGet8 > (PcdUsb20OverCurrentPinPort5)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 6, PcdGet8 > (PcdUsb20OverCurrentPinPort6)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 7, PcdGet8 > (PcdUsb20OverCurrentPinPort7)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 8, PcdGet8 > (PcdUsb20OverCurrentPinPort8)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 9, PcdGet8 > (PcdUsb20OverCurrentPinPort9)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,10, PcdGet8 > (PcdUsb20OverCurrentPinPort10)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,11, PcdGet8 > (PcdUsb20OverCurrentPinPort11)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,12, PcdGet8 > (PcdUsb20OverCurrentPinPort12)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,13, PcdGet8 > (PcdUsb20OverCurrentPinPort13)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,14, PcdGet8 > (PcdUsb20OverCurrentPinPort14)); >=20 > + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,15, PcdGet8 > (PcdUsb20OverCurrentPinPort15)); >=20 > + >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 0, PcdGet8 > (PcdUsb30OverCurrentPinPort0)); >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 1, PcdGet8 > (PcdUsb30OverCurrentPinPort1)); >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 2, PcdGet8 > (PcdUsb30OverCurrentPinPort2)); >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 3, PcdGet8 > (PcdUsb30OverCurrentPinPort3)); >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 4, PcdGet8 > (PcdUsb30OverCurrentPinPort4)); >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 5, PcdGet8 > (PcdUsb30OverCurrentPinPort5)); >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 6, PcdGet8 > (PcdUsb30OverCurrentPinPort6)); >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 7, PcdGet8 > (PcdUsb30OverCurrentPinPort7)); >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 8, PcdGet8 > (PcdUsb30OverCurrentPinPort8)); >=20 > + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 9, PcdGet8 > (PcdUsb30OverCurrentPinPort9)); >=20 > + >=20 > +} >=20 > + >=20 > +/** >=20 > + Update CNVi config >=20 > + >=20 > + @param[in] SiPolicy Pointer to SI_POLICY_PPI >=20 > + @param[in] FspsUpd Pointer to FspsUpd structure >=20 > + @param[in] PchSetup Pointer to PCH_SETUP buffer >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +UpdateCnviConfig ( >=20 > + IN OUT FSPS_UPD *FspsUpd, >=20 > + IN OUT CNVI_CONFIG *CnviConfig >=20 > + ) >=20 > +{ >=20 > + >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.CnviMode, CnviConfig->Mod= e, > CnviModeDisabled); >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.CnviBtCore, CnviConfig->BtC= ore, > FALSE); >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.CnviBtAudioOffload, CnviConfig- > >BtAudioOffload, 0); >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs FSP PCH PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspPchPolicyInit ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ) >=20 > +{ >=20 > + UINTN Index; >=20 > + SATA_CONFIG *SataConfig; >=20 > + USB_CONFIG *UsbConfig; >=20 > + TCSS_PEI_CONFIG *TcssConfig; >=20 > + SERIAL_IO_CONFIG *SerialIoConfig; >=20 > + CNVI_CONFIG *CnviConfig; >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + SI_POLICY_PPI *SiPolicy; >=20 > + EFI_STATUS Status; >=20 > +#endif >=20 > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n")); >=20 > + >=20 > + SataConfig =3D NULL; >=20 > + UsbConfig =3D NULL; >=20 > + TcssConfig =3D NULL; >=20 > + SerialIoConfig =3D NULL; >=20 > + CnviConfig =3D NULL; >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + // >=20 > + // Locate SiPolicyPpi >=20 > + // >=20 > + SiPolicy =3D NULL; >=20 > + Status =3D PeiServicesLocatePpi ( >=20 > + &gSiPolicyPpiGuid, >=20 > + 0, >=20 > + NULL, >=20 > + (VOID **) &SiPolicy >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return EFI_NOT_FOUND; >=20 > + } >=20 > + >=20 > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID = *) > &SataConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *= ) > &UsbConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gTcssPeiConfigGuid, (VO= ID *) > &TcssConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (V= OID *) > &SerialIoConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID = *) > &CnviConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + if (EFI_ERROR (Status)) { >=20 > + return Status; >=20 > + } >=20 > +#endif >=20 > + >=20 > + // >=20 > + // Update Sata Policies >=20 > + // >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.SataEnable, SataConfig->Enable, > TRUE); >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.SataMode, SataConfig->SataMode, > SataModeAhci); >=20 > + >=20 > + for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index++) { >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.SataPortsEnable[Index], SataConfi= g- > >PortSettings[Index].Enable, TRUE); >=20 > + } >=20 > + >=20 > + // >=20 > + // Update Pch Usb Config >=20 > + // >=20 > + UpdatePchUsbConfig (FspsUpd, UsbConfig); >=20 > + >=20 > + // >=20 > + // I2C >=20 > + // >=20 > + for (Index =3D 0; Index < 8; Index++) { >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.SerialIoI2cMode[Index], > SerialIoConfig->I2cDeviceConfig[Index].Mode, 0); >=20 > + UPDATE_POLICY (FspsUpd- > >FspsConfig.PchSerialIoI2cPadsTermination[Index], SerialIoConfig- > >I2cDeviceConfig[Index].PadTermination, 0); >=20 > + } >=20 > + >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cSdaPinMux[4], > SerialIoConfig->I2cDeviceConfig[4].PinMux.Sda, > GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_H8); >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cSclPinMux[4], > SerialIoConfig->I2cDeviceConfig[4].PinMux.Scl, > GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_H9); >=20 > + >=20 > + // >=20 > + // Type C >=20 > + // >=20 > + for (Index =3D 0; Index < MAX_IOM_AUX_BIAS_COUNT; Index++) { >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.IomTypeCPortPadCfg[(Index * 2)], > TcssConfig->IomConfig.IomAuxPortPad[Index].GpioPullN, > mIomAuxNullTable[Index].GpioPullN); >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.IomTypeCPortPadCfg[(Index * 2) + = 1], > TcssConfig->IomConfig.IomAuxPortPad[Index].GpioPullP, > mIomAuxNullTable[Index].GpioPullP); >=20 > + } >=20 > + >=20 > + // >=20 > + // Cnvi >=20 > + // >=20 > + UpdateCnviConfig (FspsUpd, CnviConfig); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPolicyInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPolicyInitLib.c > new file mode 100644 > index 0000000000..fc523e93d1 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPolicyInitLib.c > @@ -0,0 +1,308 @@ > +/** @file >=20 > + Instance of Fsp Policy Initialization Library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +VOID >=20 > +EFIAPI >=20 > +FspPolicyInitPreMem( >=20 > + IN FSPM_UPD *FspmUpdDataPtr >=20 > +); >=20 > + >=20 > +VOID * >=20 > +EFIAPI >=20 > +SiliconPolicyInitPreMem( >=20 > + IN OUT VOID *FspmUpd >=20 > +) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "FspmUpd - 0x%x\n", FspmUpd)); >=20 > + FspPolicyInitPreMem ((FSPM_UPD *) FspmUpd); >=20 > + return FspmUpd; >=20 > +} >=20 > + >=20 > +/** >=20 > + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. >=20 > + While installed, RC assumes the Policy is ready and finalized. So plea= se update > and override >=20 > + any setting before calling this function. >=20 > + >=20 > + @retval EFI_SUCCESS The policy is installed. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiPreMemInstallPolicyReadyPpi ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPreMemPpiDesc; >=20 > + >=20 > + SiPolicyReadyPreMemPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) > AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); >=20 > + if (SiPolicyReadyPreMemPpiDesc =3D=3D NULL) { >=20 > + ASSERT (FALSE); >=20 > + return EFI_OUT_OF_RESOURCES; >=20 > + } >=20 > + >=20 > + SiPolicyReadyPreMemPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; >=20 > + SiPolicyReadyPreMemPpiDesc->Guid =3D &gSiPreMemPolicyReadyPpiGuid; >=20 > + SiPolicyReadyPreMemPpiDesc->Ppi =3D NULL; >=20 > + >=20 > + // >=20 > + // Install PreMem Silicon Policy Ready PPI >=20 > + // >=20 > + Status =3D PeiServicesInstallPpi (SiPolicyReadyPreMemPpiDesc); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > +} >=20 > + >=20 > +RETURN_STATUS >=20 > +EFIAPI >=20 > +SiliconPolicyDonePreMem( >=20 > + IN VOID *FspmUpd >=20 > +) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi; >=20 > + EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc; >=20 > + >=20 > + FspmArchConfigPpi =3D (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeo= f > (FSPM_ARCH_CONFIG_PPI)); >=20 > + if (FspmArchConfigPpi =3D=3D NULL) { >=20 > + ASSERT (FALSE); >=20 > + return EFI_OUT_OF_RESOURCES; >=20 > + } >=20 > + FspmArchConfigPpi->Revision =3D 1; >=20 > + FspmArchConfigPpi->NvsBufferPtr =3D NULL; >=20 > + FspmArchConfigPpi->BootLoaderTolumSize =3D 0; >=20 > + >=20 > + FspmArchConfigPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool > (sizeof (EFI_PEI_PPI_DESCRIPTOR)); >=20 > + if (FspmArchConfigPpiDesc =3D=3D NULL) { >=20 > + ASSERT (FALSE); >=20 > + return EFI_OUT_OF_RESOURCES; >=20 > + } >=20 > + FspmArchConfigPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; >=20 > + FspmArchConfigPpiDesc->Guid =3D &gFspmArchConfigPpiGuid; >=20 > + FspmArchConfigPpiDesc->Ppi =3D FspmArchConfigPpi; >=20 > + // >=20 > + // Install FSP-M Arch Config PPI >=20 > + // >=20 > + Status =3D PeiServicesInstallPpi (FspmArchConfigPpiDesc); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > +#endif >=20 > + >=20 > + // >=20 > + // Install Policy Ready PPI >=20 > + // While installed, RC assumes the Policy is ready and finalized. So p= lease >=20 > + // update and override any setting before calling this function. >=20 > + // >=20 > + Status =3D SiPreMemInstallPolicyReadyPpi (); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre- > Memory\n")); >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs FSP PEI Policy Pre-memory initialization. >=20 > + >=20 > + @param[in] FspmUpdDataPtr Pointer to FSPM UPD data. >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +FspPolicyInitPreMem ( >=20 > + IN FSPM_UPD *FspmUpdDataPtr >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + // >=20 > + // PCH Pei Fsp Policy Initialization >=20 > + // >=20 > + Status =3D PeiFspPchPolicyInitPreMem (FspmUpdDataPtr); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy in Pre-Memory > Initialization fail, Status =3D %r\n", Status)); >=20 > + } >=20 > + >=20 > + // >=20 > + // Cpu Pei Fsp Policy Initialization >=20 > + // >=20 > + Status =3D PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy in Pre-Memory > Initialization fail, Status =3D %r\n", Status)); >=20 > + } >=20 > + >=20 > + // >=20 > + // Security Pei Fsp Policy Initialization >=20 > + // >=20 > + Status =3D PeiFspSecurityPolicyInitPreMem (FspmUpdDataPtr); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy in Pre-Memory > Initialization fail, Status =3D %r\n", Status)); >=20 > + } >=20 > + >=20 > + // >=20 > + // ME Pei Fsp Policy Initialization >=20 > + // >=20 > + Status =3D PeiFspMePolicyInitPreMem (FspmUpdDataPtr); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy in Pre-Memory > Initialization fail, Status =3D %r\n", Status)); >=20 > + } >=20 > + >=20 > + // >=20 > + // SystemAgent Pei Fsp Policy Initialization >=20 > + // >=20 > + Status =3D PeiFspSaPolicyInitPreMem (FspmUpdDataPtr); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy in Pre- > Memory Initialization fail, Status =3D %r\n", Status)); >=20 > + } >=20 > + >=20 > + // >=20 > + // Other Upd Initialization >=20 > + // >=20 > + Status =3D PeiFspMiscUpdInitPreMem (FspmUpdDataPtr); >=20 > + >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs FSP PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer UPD data region >=20 > + >=20 > +**/ >=20 > +VOID >=20 > +EFIAPI >=20 > +FspPolicyInit ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + // >=20 > + // PCH Pei Fsp Policy Initialization >=20 > + // >=20 > + Status =3D PeiFspPchPolicyInit (FspsUpd); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy iInitialization fai= l, > Status =3D %r\n", Status)); >=20 > + } >=20 > + >=20 > + // >=20 > + // ME Pei Fsp Policy Initialization >=20 > + // >=20 > + Status =3D PeiFspMePolicyInit (FspsUpd); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy Initialization fail,= Status > =3D %r\n", Status)); >=20 > + } >=20 > + >=20 > + // >=20 > + // SystemAgent Pei Fsp Policy Initialization >=20 > + // >=20 > + Status =3D PeiFspSaPolicyInit (FspsUpd); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy Initializat= ion > fail, Status =3D %r\n", Status)); >=20 > + } >=20 > + >=20 > + // >=20 > + // Security Pei Fsp Policy Initialization >=20 > + // >=20 > + Status =3D PeiFspSecurityPolicyInit(FspsUpd); >=20 > + if (EFI_ERROR(Status)) { >=20 > + DEBUG((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy Initialization = fail, > Status =3D %r\n", Status)); >=20 > + } >=20 > + >=20 > +} >=20 > + >=20 > +/** >=20 > +Performs silicon post-mem policy initialization. >=20 > + >=20 > +The meaning of Policy is defined by silicon code. >=20 > +It could be the raw data, a handle, a PPI, etc. >=20 > + >=20 > +The returned data must be used as input data for SiliconPolicyDonePostMe= m(), >=20 > +and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem(). >=20 > + >=20 > +1) In FSP path, the input Policy should be FspsUpd. >=20 > +Value of FspsUpd has been initialized by FSP binary default value. >=20 > +Only a subset of FspsUpd needs to be updated for different silicon sku. >=20 > +The return data is same FspsUpd. >=20 > + >=20 > +2) In non-FSP path, the input policy could be NULL. >=20 > +The return data is the initialized policy. >=20 > + >=20 > +@param[in, out] Policy Pointer to policy. >=20 > + >=20 > +@return the initialized policy. >=20 > +**/ >=20 > +VOID * >=20 > +EFIAPI >=20 > +SiliconPolicyInitPostMem( >=20 > + IN OUT VOID *FspsUpd >=20 > +) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO, "FspsUpd - 0x%x\n", FspsUpd)); >=20 > + FspPolicyInit ((FSPS_UPD *) FspsUpd); >=20 > + return FspsUpd; >=20 > +} >=20 > + >=20 > +/** >=20 > + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. >=20 > + While installed, RC assumes the Policy is ready and finalized. So plea= se update > and override >=20 > + any setting before calling this function. >=20 > + >=20 > + @retval EFI_SUCCESS The policy is installed. >=20 > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiInstallPolicyReadyPpi ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc; >=20 > + >=20 > + SiPolicyReadyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (= sizeof > (EFI_PEI_PPI_DESCRIPTOR)); >=20 > + if (SiPolicyReadyPpiDesc =3D=3D NULL) { >=20 > + ASSERT (FALSE); >=20 > + return EFI_OUT_OF_RESOURCES; >=20 > + } >=20 > + >=20 > + SiPolicyReadyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; >=20 > + SiPolicyReadyPpiDesc->Guid =3D &gSiPolicyReadyPpiGuid; >=20 > + SiPolicyReadyPpiDesc->Ppi =3D NULL; >=20 > + >=20 > + // >=20 > + // Install Silicon Policy Ready PPI >=20 > + // >=20 > + Status =3D PeiServicesInstallPpi (SiPolicyReadyPpiDesc); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/* >=20 > +The silicon post-mem policy is finalized. >=20 > +Silicon code can do initialization based upon the policy data. >=20 > + >=20 > +The input Policy must be returned by SiliconPolicyInitPostMem(). >=20 > + >=20 > +@param[in] Policy Pointer to policy. >=20 > + >=20 > +@retval EFI_SUCCESS The policy is handled consumed by silicon code. >=20 > +*/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SiliconPolicyDonePostMem( >=20 > + IN OUT VOID *FspsUpd >=20 > +) >=20 > +{ >=20 > + SiInstallPolicyReadyPpi(); >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPolicyInitLib.h > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPolicyInitLib.h > new file mode 100644 > index 0000000000..cce0de0089 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPolicyInitLib.h > @@ -0,0 +1,187 @@ > +/** @file >=20 > + Internal header file for Fsp Policy Initialization Library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#ifndef _PEI_FSP_POLICY_INIT_LIB_H_ >=20 > +#define _PEI_FSP_POLICY_INIT_LIB_H_ >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Performs FSP PCH PEI Policy pre mem initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspPchPolicyInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP PCH PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspPchPolicyInit ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP CPU PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspCpuPolicyInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > +Performs FSP Security PEI Policy initialization. >=20 > + >=20 > +@param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > +@retval EFI_SUCCESS FSP UPD Data is updated. >=20 > +@retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > +@retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSecurityPolicyInitPreMem( >=20 > +IN OUT FSPM_UPD *FspmUpd >=20 > +); >=20 > + >=20 > +/** >=20 > + Performs FSP ME PEI Policy pre mem initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspMePolicyInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP ME PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspMePolicyInit ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP SA PEI Policy initialization in pre-memory. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSaPolicyInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP SA PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSaPolicyInit ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ); >=20 > + >=20 > + >=20 > +/** >=20 > +Performs FSP Security PEI Policy post memory initialization. >=20 > + >=20 > +@param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > +@retval EFI_SUCCESS FSP UPD Data is updated. >=20 > +@retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > +@retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSecurityPolicyInit( >=20 > +IN OUT FSPS_UPD *FspsUpd >=20 > +); >=20 > + >=20 > +/** >=20 > + PeiGetSectionFromFv finds the file in FV and gets file Address and Siz= e >=20 > + >=20 > + @param[in] NameGuid - File GUID >=20 > + @param[out] Address - Pointer to the File Address >=20 > + @param[out] Size - Pointer to File Size >=20 > + >=20 > + @retval EFI_SUCCESS Successfull in reading the section = from FV >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiGetSectionFromFv ( >=20 > + IN CONST EFI_GUID NameGuid, >=20 > + OUT VOID **Address, >=20 > + OUT UINT32 *Size >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs FSP Misc UPD initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspMiscUpdInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ); >=20 > + >=20 > +#endif // _PEI_FSP_POLICY_INIT_LIB_H_ >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPolicyInitLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPolicyInitLib.inf > new file mode 100644 > index 0000000000..936d331073 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspPolicyInitLib.inf > @@ -0,0 +1,184 @@ > +## @file >=20 > +# Library functions for Fsp Policy Initialization Library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +################################################################ > ################ >=20 > +# >=20 > +# Defines Section - statements that will be processed to create a Makefi= le. >=20 > +# >=20 > +################################################################ > ################ >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiFspPolicyInitLib >=20 > + FILE_GUID =3D 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E= 0 >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D SiliconPolicyInitLib >=20 > + >=20 > +# >=20 > +# The following information is for reference only and not required by th= e build > tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 >=20 > +# >=20 > + >=20 > +################################################################ > ################ >=20 > +# >=20 > +# Sources Section - list of files that are required for the build to suc= ceed. >=20 > +# >=20 > +################################################################ > ################ >=20 > + >=20 > +[Sources] >=20 > + PeiFspPolicyInitLib.c >=20 > + PeiFspSiPolicyInitLib.c >=20 > + PeiFspPchPolicyInitLib.c >=20 > + PeiFspCpuPolicyInitLib.c >=20 > + PeiFspMePolicyInitLib.c >=20 > + PeiFspSaPolicyInitLib.c >=20 > + PeiFspSecurityPolicyInitLib.c >=20 > + PeiFspMiscUpdInitLib.c >=20 > + >=20 > +################################################################ > ################ >=20 > +# >=20 > +# Package Dependency Section - list of Package files that are required f= or >=20 > +# this module. >=20 > +# >=20 > +################################################################ > ################ >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + IntelFsp2Pkg/IntelFsp2Pkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec >=20 > + TigerlakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + UefiCpuPkg/UefiCpuPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseMemoryLib >=20 > + DebugLib >=20 > + IoLib >=20 > + PeiServicesLib >=20 > + ConfigBlockLib >=20 > + PcdLib >=20 > + MemoryAllocationLib >=20 > + PchInfoLib >=20 > + FspWrapperApiLib >=20 > + PeiLib >=20 > + BmpSupportLib >=20 > + >=20 > +[Pcd] >=20 > + gSiPkgTokenSpaceGuid.PcdTsegSize ## C= ONSUMES >=20 > + >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## > CONSUMES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## > CONSUMES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## > CONSUMES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## > CONSUMES >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## > CONSUMES >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## > CONSUMES >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## > CONSUMES >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## > CONSUMES >=20 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## > CONSUMES >=20 > + # SA Misc Config >=20 > + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## C= ONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## C= ONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## > CONSUMES >=20 > + >=20 > + # SPD Address Table >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## > CONSUMES >=20 > + >=20 > + # PCIe Clock Info >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUM= ES >=20 > + >=20 > + # USB 2.0 Port Over Current Pin >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 ## > CONSUMES >=20 > + >=20 > + # USB 3.0 Port Over Current Pin >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 ## > CONSUMES >=20 > + >=20 > + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUM= ES >=20 > + >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr #= # > CONSUMES >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr > ## CONSUMES >=20 > + >=20 > +[Ppis] >=20 > + gSiPolicyPpiGuid ## CONSUMES >=20 > + gSiPreMemPolicyPpiGuid ## CONSUMES >=20 > + gSiPreMemPolicyReadyPpiGuid ## CONSUMES >=20 > + gSiPolicyReadyPpiGuid ## CONSUMES >=20 > + gFspmArchConfigPpiGuid ## SOMETIMES_PRODUCES >=20 > + >=20 > +[Guids] >=20 > + gPcieRpPreMemConfigGuid ## CONSUMES >=20 > + gPchGeneralPreMemConfigGuid ## CONSUMES >=20 > + gPcieRpPreMemConfigGuid ## CONSUMES >=20 > + gSataConfigGuid ## CONSUMES >=20 > + gHdAudioConfigGuid ## CONSUMES >=20 > + gSataConfigGuid ## CONSUMES >=20 > + gUsbConfigGuid ## CONSUMES >=20 > + gSaMiscPeiPreMemConfigGuid ## PRODUCES >=20 > + gHostBridgePeiPreMemConfigGuid ## CONSUMES >=20 > + gSaMiscPeiConfigGuid ## PRODUCES >=20 > + gMemoryConfigNoCrcGuid ## CONSUMES >=20 > + gSaMiscPeiConfigGuid ## CONSUMES >=20 > + gGraphicsPeiConfigGuid ## CONSUMES >=20 > + gMePeiPreMemConfigGuid ## CONSUMES >=20 > + gMePeiConfigGuid ## CONSUMES >=20 > + gPchGeneralConfigGuid ## CONSUMES >=20 > + gCpuConfigGuid ## CONSUMES >=20 > + gCpuConfigLibPreMemConfigGuid ## CONSUMES >=20 > + gTcssPeiConfigGuid ## CONSUMES >=20 > + gSerialIoConfigGuid ## CONSUMES >=20 > + gCpuSecurityPreMemConfigGuid ## CONSUMES >=20 > + gTianoLogoGuid ## CONSUMES >=20 > + gCnviConfigGuid ## CONSUMES >=20 > + gHdAudioPreMemConfigGuid ## CONSUMES >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspSaPolicyInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspSaPolicyInitLib.c > new file mode 100644 > index 0000000000..8f426ddb8d > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspSaPolicyInitLib.c > @@ -0,0 +1,240 @@ > +/** @file >=20 > + Implementation of Fsp SA Policy Initialization. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Performs FSP SA PEI Policy initialization in pre-memory. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSaPolicyInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; >=20 > + HOST_BRIDGE_PREMEM_CONFIG *HostBridgePreMemConfig; >=20 > + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + EFI_STATUS Status; >=20 > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; >=20 > +#endif >=20 > + >=20 > + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Pre Mem\n")); >=20 > + MiscPeiPreMemConfig =3D NULL; >=20 > + HostBridgePreMemConfig =3D NULL; >=20 > + MemConfigNoCrc =3D NULL; >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + // >=20 > + // Locate SiPreMemPolicyPpi >=20 > + // >=20 > + SiPreMemPolicyPpi =3D NULL; >=20 > + Status =3D PeiServicesLocatePpi( >=20 > + &gSiPreMemPolicyPpiGuid, >=20 > + 0, >=20 > + NULL, >=20 > + (VOID **) &SiPreMemPolicyPpi >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + if ((Status =3D=3D EFI_SUCCESS) && (SiPreMemPolicyPpi !=3D NULL)) { >=20 > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, > &gHostBridgePeiPreMemConfigGuid, (VOID *) &HostBridgePreMemConfig); >=20 > + ASSERT_EFI_ERROR(Status); >=20 > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + ZeroMem ((VOID *) MemConfigNoCrc->SpdData->SpdData, sizeof > (SPD_DATA_BUFFER)); >=20 > + } >=20 > +#endif >=20 > + >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[0], > MiscPeiPreMemConfig->SpdAddressTable[0], PcdGet8 > (PcdMrcSpdAddressTable0)); >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[1], > MiscPeiPreMemConfig->SpdAddressTable[1], PcdGet8 > (PcdMrcSpdAddressTable1)); >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[2], > MiscPeiPreMemConfig->SpdAddressTable[2], PcdGet8 > (PcdMrcSpdAddressTable2)); >=20 > + UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[3], > MiscPeiPreMemConfig->SpdAddressTable[3], PcdGet8 > (PcdMrcSpdAddressTable3)); >=20 > + >=20 > + if (PcdGet32 (PcdMrcSpdData)) { >=20 > + DEBUG((DEBUG_INFO, "PcdMrcSpdData !=3D NULL, MemConfigNoCrc- > >SpdData\n")); >=20 > + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)- > >FspmConfig.MemorySpdPtr000, (VOID *)MemConfigNoCrc->SpdData- > >SpdData[0][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), > PcdGet16(PcdMrcSpdDataSize)); >=20 > + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)- > >FspmConfig.MemorySpdPtr010, (VOID *)MemConfigNoCrc->SpdData- > >SpdData[0][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), > PcdGet16(PcdMrcSpdDataSize)); >=20 > + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)- > >FspmConfig.MemorySpdPtr020, (VOID *)MemConfigNoCrc->SpdData- > >SpdData[0][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), > PcdGet16(PcdMrcSpdDataSize)); >=20 > + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)- > >FspmConfig.MemorySpdPtr030, (VOID *)MemConfigNoCrc->SpdData- > >SpdData[0][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), > PcdGet16(PcdMrcSpdDataSize)); >=20 > + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)- > >FspmConfig.MemorySpdPtr100, (VOID *)MemConfigNoCrc->SpdData- > >SpdData[1][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), > PcdGet16(PcdMrcSpdDataSize)); >=20 > + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)- > >FspmConfig.MemorySpdPtr110, (VOID *)MemConfigNoCrc->SpdData- > >SpdData[1][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), > PcdGet16(PcdMrcSpdDataSize)); >=20 > + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)- > >FspmConfig.MemorySpdPtr120, (VOID *)MemConfigNoCrc->SpdData- > >SpdData[1][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), > PcdGet16(PcdMrcSpdDataSize)); >=20 > + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)- > >FspmConfig.MemorySpdPtr130, (VOID *)MemConfigNoCrc->SpdData- > >SpdData[1][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), > PcdGet16(PcdMrcSpdDataSize)); >=20 > + } >=20 > + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.TsegSize, > MiscPeiPreMemConfig->TsegSize, PcdGet32 (PcdTsegSize)); >=20 > + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, > MiscPeiPreMemConfig->UserBd, PcdGet8 (PcdSaMiscUserBd)); >=20 > + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)- > >FspmConfig.MmioSizeAdjustment, HostBridgePreMemConfig- > >MmioSizeAdjustment, PcdGet16 (PcdSaMiscMmioSizeAdjustment)); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > + >=20 > +/** >=20 > + Performs FSP SA PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +UpdateGraphics( >=20 > + IN OUT FSPS_UPD *FspsUpd, >=20 > + GRAPHICS_PEI_CONFIG *GtConfig >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + VOID *Buffer; >=20 > + UINT32 Size; >=20 > + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt; >=20 > + UINTN BltSize; >=20 > + UINTN Height; >=20 > + UINTN Width; >=20 > + >=20 > + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); >=20 > + UPDATE_POLICY (FspsUpd->FspsConfig.PeiGraphicsPeimInit, GtConfig- > >PeiGraphicsPeimInit, 1); >=20 > + >=20 > + Size =3D 0; >=20 > + Buffer =3D NULL; >=20 > + PeiGetSectionFromAnyFv(PcdGetPtr(PcdIntelGraphicsVbtFileGuid), > EFI_SECTION_RAW, 0, &Buffer, &Size); >=20 > + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromAnyFv is 0x%x\n"= , > Buffer)); >=20 > + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromAnyFv is 0x%x\n", > Size)); >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1 >=20 > + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32)(UINTN)Buffer; >=20 > +#else >=20 > + GtConfig->GraphicsConfigPtr =3D Buffer; >=20 > +#endif >=20 > + >=20 > + Size =3D 0; >=20 > + Buffer =3D NULL; >=20 > + PeiGetSectionFromAnyFv(&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, > &Size); >=20 > + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromAnyFv is 0x%x\n", > Buffer)); >=20 > + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromAnyFv is 0x%x\n", > Size)); >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1 >=20 > + FspsUpd->FspsConfig.LogoPtr =3D (UINT32)Buffer; >=20 > + FspsUpd->FspsConfig.LogoSize =3D Size; >=20 > +#else >=20 > + GtConfig->LogoPtr =3D Buffer; >=20 > + GtConfig->LogoSize =3D Size; >=20 > +#endif >=20 > + >=20 > + if (Buffer !=3D NULL) { >=20 > + Blt =3D NULL; >=20 > + Status =3D TranslateBmpToGopBlt ( >=20 > + Buffer, >=20 > + Size, >=20 > + &Blt, >=20 > + &BltSize, >=20 > + &Height, >=20 > + &Width >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt, Status =3D %r\n", St= atus)); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + return Status; >=20 > + } >=20 > + >=20 > + UPDATE_POLICY(FspsUpd->FspsConfig.BltBufferSize, GtConfig- > >BltBufferSize, BltSize); >=20 > + UPDATE_POLICY(FspsUpd->FspsConfig.LogoPixelWidth, GtConfig- > >LogoPixelWidth, Width); >=20 > + UPDATE_POLICY(FspsUpd->FspsConfig.LogoPixelHeight, GtConfig- > >LogoPixelHeight, Height); >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1 >=20 > + FspsUpd->FspsConfig.BltBufferAddress =3D (UINT32) Blt; >=20 > +#else >=20 > + GtConfig->BltBufferAddress =3D (VOID *) Blt; >=20 > +#endif >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs FSP SA PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSaPolicyInit ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ) >=20 > +{ >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + EFI_STATUS Status; >=20 > + SI_POLICY_PPI *SiPolicyPpi; >=20 > +#endif >=20 > + SA_MISC_PEI_CONFIG *MiscPeiConfig; >=20 > + GRAPHICS_PEI_CONFIG *GtConfig; >=20 > + >=20 > + MiscPeiConfig =3D NULL; >=20 > + GtConfig =3D NULL; >=20 > + >=20 > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0 >=20 > + // >=20 > + // Locate SiPolicyPpi >=20 > + // >=20 > + SiPolicyPpi =3D NULL; >=20 > + Status =3D PeiServicesLocatePpi( >=20 > + &gSiPolicyPpiGuid, >=20 > + 0, >=20 > + NULL, >=20 > + (VOID **)&SiPolicyPpi >=20 > + ); >=20 > + if ((Status =3D=3D EFI_SUCCESS) && (SiPolicyPpi !=3D NULL)) { >=20 > + MiscPeiConfig =3D NULL; >=20 > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGu= id, (VOID > *) &MiscPeiConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + GtConfig =3D NULL; >=20 > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfig= Guid, > (VOID *) &GtConfig); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + } >=20 > +#endif >=20 > + >=20 > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Wrapper UpdatePeiSaPolicy\n")); >=20 > + >=20 > + // >=20 > + // Update UPD: VBT & LogoPtr >=20 > + // >=20 > + UpdateGraphics(FspsUpd, GtConfig); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspSecurityPolicyInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspSecurityPolicyInitLib.c > new file mode 100644 > index 0000000000..91a60a6bd3 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspSecurityPolicyInitLib.c > @@ -0,0 +1,49 @@ > +/** @file >=20 > + Implementation of Fsp Security Policy Initialization. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Performs FSP Security PEI Policy initialization. >=20 > + >=20 > + @param[in][out] FspmUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSecurityPolicyInitPreMem ( >=20 > + IN OUT FSPM_UPD *FspmUpd >=20 > + ) >=20 > +{ >=20 > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem > End\n")); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs FSP Security PEI Policy post memory initialization. >=20 > + >=20 > + @param[in][out] FspsUpd Pointer to FSP UPD Data. >=20 > + >=20 > + @retval EFI_SUCCESS FSP UPD Data is updated. >=20 > + @retval EFI_NOT_FOUND Fail to locate required PPI. >=20 > + @retval Other FSP UPD Data update process fail. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiFspSecurityPolicyInit ( >=20 > + IN OUT FSPS_UPD *FspsUpd >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspSiPolicyInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspSiPolicyInitLib.c > new file mode 100644 > index 0000000000..23390d4cc4 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyIni= tLi > b/PeiFspSiPolicyInitLib.c > @@ -0,0 +1,10 @@ > +/** @file >=20 > + Implementation of Fsp SI Policy Initialization. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPol= ic > yInitLib/PeiSiDefaultPolicyInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPol= ic > yInitLib/PeiSiDefaultPolicyInitLib.c > new file mode 100644 > index 0000000000..b864753258 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPol= ic > yInitLib/PeiSiDefaultPolicyInitLib.c > @@ -0,0 +1,39 @@ > +/** @file >=20 > + Instance of Fsp Policy Initialization Library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiSiDefaultPolicyInitLibConstructor ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi; >=20 > + >=20 > + // >=20 > + // Locate Policy init PPI to install default silicon policy >=20 > + // >=20 > + Status =3D PeiServicesLocatePpi ( >=20 > + &gSiDefaultPolicyInitPpiGuid, >=20 > + 0, >=20 > + NULL, >=20 > + (VOID **) &PeiSiDefaultPolicyInitPpi >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + if (PeiSiDefaultPolicyInitPpi =3D=3D NULL) { >=20 > + return Status; >=20 > + } >=20 > + Status =3D PeiSiDefaultPolicyInitPpi->PeiPolicyInit (); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + return Status; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPol= ic > yInitLib/PeiSiDefaultPolicyInitLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPol= ic > yInitLib/PeiSiDefaultPolicyInitLib.inf > new file mode 100644 > index 0000000000..bcad97c267 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPol= ic > yInitLib/PeiSiDefaultPolicyInitLib.inf > @@ -0,0 +1,38 @@ > +## @file >=20 > +# Library functions for Fsp Policy Initialization Library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +################################################################ > ################ >=20 > +# >=20 > +# Defines Section - statements that will be processed to create a Makefi= le. >=20 > +# >=20 > +################################################################ > ################ >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiSiDefaultPolicyInitLib >=20 > + FILE_GUID =3D ADA1D87B-6891-453C-A0DB-92D4CFD4669= 3 >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D NULL >=20 > + CONSTRUCTOR =3D PeiSiDefaultPolicyInitLibConstructo= r >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > + PeiSiDefaultPolicyInitLib.c >=20 > + >=20 > +[LibraryClasses] >=20 > + PeiServicesLib >=20 > + DebugLib >=20 > + >=20 > +[Ppis] >=20 > + gSiDefaultPolicyInitPpiGuid ## CONSUMES >=20 > + >=20 > +[Depex] >=20 > + gSiDefaultPolicyInitPpiGuid >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDef > aultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDef > aultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c > new file mode 100644 > index 0000000000..f0eb3f3f14 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDef > aultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c > @@ -0,0 +1,40 @@ > +/** @file >=20 > + Instance of Fsp Policy Initialization Library. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PeiSiPreMemDefaultPolicyInitLibConstructor ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI > *PeiPreMemSiDefaultPolicyInitPpi; >=20 > + >=20 > + // >=20 > + // Locate Policy init PPI to install default silicon policy >=20 > + // >=20 > + Status =3D PeiServicesLocatePpi ( >=20 > + &gSiPreMemDefaultPolicyInitPpiGuid, >=20 > + 0, >=20 > + NULL, >=20 > + (VOID **) &PeiPreMemSiDefaultPolicyInitPpi >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + if (PeiPreMemSiDefaultPolicyInitPpi =3D=3D NULL) { >=20 > + return Status; >=20 > + } >=20 > + DEBUG ((DEBUG_INFO, "PeiPreMemSiDefaultPolicyInitPpi- > >PeiPreMemPolicyInit ()\n", Status)); >=20 > + Status =3D PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit (); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + return Status; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDef > aultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDef > aultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf > new file mode 100644 > index 0000000000..c118d7fe2c > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDef > aultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf > @@ -0,0 +1,38 @@ > +## @file >=20 > +# Library functions for Fsp Policy Initialization Library. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +################################################################ > ################ >=20 > +# >=20 > +# Defines Section - statements that will be processed to create a Makefi= le. >=20 > +# >=20 > +################################################################ > ################ >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D PeiSiPreMemDefaultPolicyInitLib >=20 > + FILE_GUID =3D F13311AD-9C5C-4212-AB02-9D0435B3FCF= 1 >=20 > + MODULE_TYPE =3D BASE >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D NULL >=20 > + CONSTRUCTOR =3D PeiSiPreMemDefaultPolicyInitLibCons= tructor >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Sources] >=20 > + PeiSiPreMemDefaultPolicyInitLib.c >=20 > + >=20 > +[LibraryClasses] >=20 > + PeiServicesLib >=20 > + DebugLib >=20 > + >=20 > +[Ppis] >=20 > + gSiPreMemDefaultPolicyInitPpiGuid ## CONSUMES >=20 > + >=20 > +[Depex] >=20 > + gSiPreMemDefaultPolicyInitPpiGuid >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.c > new file mode 100644 > index 0000000000..230ad36e09 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.c > @@ -0,0 +1,460 @@ > +/** @file >=20 > + Platform Hook Library instances >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +#define COM1_BASE 0x3f8 >=20 > +#define COM2_BASE 0x2f8 >=20 > + >=20 > +#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690 >=20 > + >=20 > +#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E >=20 > +#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F >=20 > +#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20 >=20 > + >=20 > +#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E >=20 > +#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F >=20 > +#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E >=20 > +#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F >=20 > + >=20 > +#define IT8628_ENTER_CONFIG_WRITE_SEQ_0 0x87 >=20 > +#define IT8628_ENTER_CONFIG_WRITE_SEQ_1 0x01 >=20 > +#define IT8628_ENTER_CONFIG_WRITE_SEQ_2 0x55 >=20 > +#define IT8628_ENTER_CONFIG_WRITE_SEQ_3 0x55 >=20 > +#define IT8628_EXIT_CONFIG 0x2 >=20 > +#define IT8628_CHIPID_BYTE1 0x86 >=20 > +#define IT8628_CHIPID_BYTE2 0x28 >=20 > + >=20 > +typedef struct { >=20 > + UINT8 Register; >=20 > + UINT8 Value; >=20 > +} EFI_SIO_TABLE; >=20 > + >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] > =3D { >=20 > + {0x29, 0x0A0}, // Enable super I/O clock and set to 4= 8MHz >=20 > + {0x22, 0x003}, // >=20 > + {0x07, 0x003}, // Select UART0 device >=20 > + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB >=20 > + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB >=20 > + {0x70, 0x004}, // Set to IRQ4 >=20 > + {0x30, 0x001}, // Enable it with Activation bit >=20 > + {0x07, 0x002}, // Select UART1 device >=20 > + {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB >=20 > + {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB >=20 > + {0x70, 0x003}, // Set to IRQ3 >=20 > + {0x30, 0x001}, // Enable it with Activation bit >=20 > + {0x07, 0x007}, // Select GPIO device >=20 > + {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Addre= ss > MSB >=20 > + {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base > Address LSB >=20 > + {0x30, 0x001}, // Enable it with Activation bit >=20 > + {0x21, 0x001}, // Global Device Enable >=20 > + {0x26, 0x000} // Fast Enable UART 0 & 1 as their ena= ble & activation > bit >=20 > +}; >=20 > + >=20 > +// >=20 > +// IT8628 >=20 > +// >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE > mSioIt8628TableSerialPort[] =3D { >=20 > + {0x023, 0x09}, // Clock Selection register >=20 > + {0x007, 0x01}, // Com1 Logical Device Number select >=20 > + {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register >=20 > + {0x060, 0x03}, // Serial Port 1 Base Address LSB Register >=20 > + {0x070, 0x04}, // Serial Port 1 Interrupt Level Select >=20 > + {0x030, 0x01}, // Serial Port 1 Activate >=20 > + {0x007, 0x02}, // Com1 Logical Device Number select >=20 > + {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register >=20 > + {0x060, 0x02}, // Serial Port 2 Base Address MSB Register >=20 > + {0x070, 0x03}, // Serial Port 2 Interrupt Level Select >=20 > + {0x030, 0x01} // Serial Port 2 Activate >=20 > + >=20 > +}; >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE > mSioTableWinbond_x374[] =3D { >=20 > + {0x07, 0x03}, // Select UART0 device >=20 > + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB >=20 > + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB >=20 > + {0x70, 0x04}, // Set to IRQ4 >=20 > + {0x30, 0x01} // Enable it with Activation bit >=20 > +}; >=20 > + >=20 > +/** >=20 > + Detect if a National 393 SIO is docked. If yes, enable the docked SIO >=20 > + and its serial port, and disable the onboard serial port. >=20 > + >=20 > + @retval EFI_SUCCESS Operations performed successfully. >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +CheckNationalSio ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT8 Data8; >=20 > + >=20 > + // >=20 > + // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). >=20 > + // We use (0x2e, 0x2f) which is determined by BADD default strapping >=20 > + // >=20 > + >=20 > + // >=20 > + // Read the Pc87393 signature >=20 > + // >=20 > + IoWrite8 (0x2e, 0x20); >=20 > + Data8 =3D IoRead8 (0x2f); >=20 > + >=20 > + if (Data8 =3D=3D 0xea) { >=20 > + // >=20 > + // Signature matches - National PC87393 SIO is docked >=20 > + // >=20 > + >=20 > + // >=20 > + // Enlarge the LPC decode scope to accommodate the Docking LPC Switc= h >=20 > + // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at >=20 > + // SIO_BASE_ADDRESS + 0x10) >=20 > + // >=20 > + PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & > (UINT16)~0x7F), 0x20); >=20 > + >=20 > + // >=20 > + // Enable port switch >=20 > + // >=20 > + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); >=20 > + >=20 > + // >=20 > + // Turn on docking power >=20 > + // >=20 > + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); >=20 > + >=20 > + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); >=20 > + >=20 > + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); >=20 > + >=20 > + // >=20 > + // Enable port switch >=20 > + // >=20 > + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); >=20 > + >=20 > + // >=20 > + // GPIO setting >=20 > + // >=20 > + IoWrite8 (0x2e, 0x24); >=20 > + IoWrite8 (0x2f, 0x29); >=20 > + >=20 > + // >=20 > + // Enable chip clock >=20 > + // >=20 > + IoWrite8 (0x2e, 0x29); >=20 > + IoWrite8 (0x2f, 0x1e); >=20 > + >=20 > + >=20 > + // >=20 > + // Enable serial port >=20 > + // >=20 > + >=20 > + // >=20 > + // Select com1 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x7); >=20 > + IoWrite8 (0x2f, 0x3); >=20 > + >=20 > + // >=20 > + // Base address: 0x3f8 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x60); >=20 > + IoWrite8 (0x2f, 0x03); >=20 > + IoWrite8 (0x2e, 0x61); >=20 > + IoWrite8 (0x2f, 0xf8); >=20 > + >=20 > + // >=20 > + // Interrupt: 4 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x70); >=20 > + IoWrite8 (0x2f, 0x04); >=20 > + >=20 > + // >=20 > + // Enable bank selection >=20 > + // >=20 > + IoWrite8 (0x2e, 0xf0); >=20 > + IoWrite8 (0x2f, 0x82); >=20 > + >=20 > + // >=20 > + // Activate >=20 > + // >=20 > + IoWrite8 (0x2e, 0x30); >=20 > + IoWrite8 (0x2f, 0x01); >=20 > + >=20 > + // >=20 > + // Disable onboard serial port >=20 > + // >=20 > + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); >=20 > + >=20 > + // >=20 > + // Power Down UARTs >=20 > + // >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); >=20 > + >=20 > + // >=20 > + // Dissable COM1 decode >=20 > + // >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); >=20 > + >=20 > + // >=20 > + // Disable COM2 decode >=20 > + // >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); >=20 > + >=20 > + // >=20 > + // Disable interrupt >=20 > + // >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); >=20 > + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); >=20 > + >=20 > + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); >=20 > + >=20 > + // >=20 > + // Enable floppy >=20 > + // >=20 > + >=20 > + // >=20 > + // Select floppy >=20 > + // >=20 > + IoWrite8 (0x2e, 0x7); >=20 > + IoWrite8 (0x2f, 0x0); >=20 > + >=20 > + // >=20 > + // Base address: 0x3f0 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x60); >=20 > + IoWrite8 (0x2f, 0x03); >=20 > + IoWrite8 (0x2e, 0x61); >=20 > + IoWrite8 (0x2f, 0xf0); >=20 > + >=20 > + // >=20 > + // Interrupt: 6 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x70); >=20 > + IoWrite8 (0x2f, 0x06); >=20 > + >=20 > + // >=20 > + // DMA 2 >=20 > + // >=20 > + IoWrite8 (0x2e, 0x74); >=20 > + IoWrite8 (0x2f, 0x02); >=20 > + >=20 > + // >=20 > + // Activate >=20 > + // >=20 > + IoWrite8 (0x2e, 0x30); >=20 > + IoWrite8 (0x2f, 0x01); >=20 > + >=20 > + } else { >=20 > + >=20 > + // >=20 > + // No National pc87393 SIO is docked, turn off dock power and >=20 > + // disable port switch >=20 > + // >=20 > + // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); >=20 > + // IoWrite8 (0x690, 0); >=20 > + >=20 > + // >=20 > + // If no National pc87393, just return >=20 > + // >=20 > + return ; >=20 > + } >=20 > +} >=20 > + >=20 > +/** >=20 > +Check whether the IT8628 SIO present on LPC. If yes, enable its serial p= orts >=20 > + >=20 > +@retval EFI_SUCCESS Operations performed successfully. >=20 > +**/ >=20 > +STATIC >=20 > +VOID >=20 > +It8628SioSerialPortInit ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT8 ChipId0 =3D 0; >=20 > + UINT8 ChipId1 =3D 0; >=20 > + UINT16 LpcIoDecondeRangeSet =3D 0; >=20 > + UINT16 LpcIoDecoodeSet =3D 0; >=20 > + UINT8 Index; >=20 > + UINTN LpcBaseAddr; >=20 > + >=20 > + >=20 > + >=20 > + // >=20 > + // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port > 2Eh/2Fh. >=20 > + // >=20 > + LpcBaseAddr =3D MmPciBase ( >=20 > + DEFAULT_PCI_BUS_NUMBER_PCH, >=20 > + LpcDevNumber (), >=20 > + LpcFuncNumber () >=20 > + ); >=20 > + >=20 > + LpcIoDecondeRangeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + > R_LPC_CFG_IOD); >=20 > + LpcIoDecoodeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + R_LPC_CFG_IOE); >=20 > + MmioWrite16 ((LpcBaseAddr + R_LPC_CFG_IOD), (LpcIoDecondeRangeSet | > ((V_LPC_CFG_IOD_COMB_2F8 << 4) | V_LPC_CFG_IOD_COMA_3F8))); >=20 > + MmioWrite16 ((LpcBaseAddr + R_LPC_CFG_IOE), (LpcIoDecoodeSet | > (B_LPC_CFG_IOE_SE | B_LPC_CFG_IOE_CBE | > B_LPC_CFG_IOE_CAE|B_LPC_CFG_IOE_KE))); >=20 > + >=20 > + >=20 > + // >=20 > + // Enter MB PnP Mode >=20 > + // >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, > IT8628_ENTER_CONFIG_WRITE_SEQ_0); >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, > IT8628_ENTER_CONFIG_WRITE_SEQ_1); >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, > IT8628_ENTER_CONFIG_WRITE_SEQ_2); >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, > IT8628_ENTER_CONFIG_WRITE_SEQ_3); >=20 > + >=20 > + // >=20 > + // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21) >=20 > + // >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20); >=20 > + ChipId0 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); >=20 > + >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21); >=20 > + ChipId1 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); >=20 > + >=20 > + // >=20 > + // Enable Serial Port 1, Port 2 >=20 > + // >=20 > + if ((ChipId0 =3D=3D IT8628_CHIPID_BYTE1) && (ChipId1 =3D=3D IT8628_CHI= PID_BYTE2)) > { >=20 > + for (Index =3D 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeo= f > (EFI_SIO_TABLE); Index++) { >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, > mSioIt8628TableSerialPort[Index].Register); >=20 > + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, > mSioIt8628TableSerialPort[Index].Value); >=20 > + } >=20 > + } >=20 > + >=20 > + // >=20 > + // Exit MB PnP Mode >=20 > + // >=20 > + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_EXIT_CONFIG); >=20 > + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, IT8628_EXIT_CONFIG); >=20 > + >=20 > + return; >=20 > +} >=20 > + >=20 > +/** >=20 > + Performs platform specific initialization required for the CPU to acce= ss >=20 > + the hardware associated with a SerialPortLib instance. This function = does >=20 > + not initialize the serial port hardware itself. Instead, it initializ= es >=20 > + hardware devices that are required for the CPU to access the serial po= rt >=20 > + hardware. This function may be called more than once. >=20 > + >=20 > + @retval RETURN_SUCCESS The platform specific initialization succ= eeded. >=20 > + @retval RETURN_DEVICE_ERROR The platform specific initialization coul= d > not be completed. >=20 > + >=20 > +**/ >=20 > +RETURN_STATUS >=20 > +EFIAPI >=20 > +PlatformHookSerialPortInitialize ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + UINT16 IndexPort; >=20 > + UINT16 DataPort; >=20 > + UINT8 Index; >=20 > + >=20 > + IndexPort =3D 0; >=20 > + DataPort =3D 0; >=20 > + Index =3D 0; >=20 > + >=20 > + // >=20 > + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port > 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. >=20 > + // >=20 > + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); >=20 > + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); >=20 > + >=20 > + // Configure Sio IT8628 >=20 > + It8628SioSerialPortInit (); >=20 > + >=20 > + if (IsMobileSku ()) { >=20 > + // >=20 > + // if no EC, it is SV Bidwell Bar board >=20 > + // >=20 > + if ((IoRead8 (0x66) !=3D 0xFF) && (IoRead8 (0x62) !=3D 0xFF)) { >=20 > + >=20 > + // >=20 > + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF; >=20 > + // >=20 > + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), > 0x10); >=20 > + >=20 > + // >=20 > + // Program and Enable Default Super IO Configuration Port Addresse= s and > range >=20 > + // >=20 > + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & > (~0xF), 0x10); >=20 > + >=20 > + // >=20 > + // Check if a National Pc87393 SIO is docked >=20 > + // >=20 > + CheckNationalSio (); >=20 > + >=20 > + // >=20 > + // Super I/O initialization for Winbond WPCN381U >=20 > + // >=20 > + IndexPort =3D LPC_SIO_INDEX_DEFAULT_PORT_2; >=20 > + DataPort =3D LPC_SIO_DATA_DEFAULT_PORT_2; >=20 > + >=20 > + // >=20 > + // Check for Winbond WPCN381U >=20 > + // >=20 > + IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID = register > is 0x20 >=20 > + if (IoRead8 (DataPort) =3D=3D 0xF4) { // Winbond WPCN381U Device= ID is 0xF4 >=20 > + // >=20 > + // Configure SIO >=20 > + // >=20 > + for (Index =3D 0; Index < sizeof (mSioTableWpcn381u) / sizeof > (EFI_SIO_TABLE); Index++) { >=20 > + IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register); >=20 > + IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value); >=20 > + } >=20 > + } >=20 > + } //EC is not exist, skip mobile board detection for SV board >=20 > + >=20 > + // >=20 > + //add for SV Bidwell Bar board >=20 > + // >=20 > + if (IoRead8 (COM1_BASE) =3D=3D 0xFF) { >=20 > + // >=20 > + // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (L= DC) >=20 > + // Looking for LDC2 card first >=20 > + // >=20 > + IoWrite8(LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55); >=20 > + if(IoRead8(LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) =3D=3D 0x55){ >=20 > + IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; >=20 > + DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT; >=20 > + } else { >=20 > + IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT; >=20 > + DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT; >=20 > + } >=20 > + >=20 > + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID regi= ster is 0x20 >=20 > + if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID = is 0xF1 >=20 > + for (Index =3D 0; Index < sizeof (mSioTableWinbond_x374) / sizeo= f > (EFI_SIO_TABLE); Index++) { >=20 > + IoWrite8 (IndexPort, mSioTableWinbond_x374[Index].Register); >=20 > + IoWrite8 (DataPort, mSioTableWinbond_x374[Index].Value); >=20 > + } >=20 > + } >=20 > + }// end of Bidwell Bar SIO initialization >=20 > + } >=20 > + >=20 > + return RETURN_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.inf > new file mode 100644 > index 0000000000..cf01780101 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.inf > @@ -0,0 +1,51 @@ > +## @file >=20 > +# Platform Hook Library instance for Tigerlake Mobile/Desktop CRB. >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D BasePlatformHookLib >=20 > + FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963= D >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D BASE >=20 > + LIBRARY_CLASS =3D PlatformHookLib >=20 > +# >=20 > +# The following information is for reference only and not required by th= e build > tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + IoLib >=20 > + PciSegmentLib >=20 > + MmPciLib >=20 > + PciLib >=20 > + PchCycleDecodingLib >=20 > + SaPlatformLib >=20 > + PchPciBdfLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + TigerlakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Pcd] >=20 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUM= ES >=20 > + >=20 > +[FixedPcd] >=20 > + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## > CONSUMES >=20 > + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUM= ES >=20 > + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## > CONSUMES >=20 > + >=20 > +[Sources] >=20 > + BasePlatformHookLib.c >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/Sm > mSpiFlashCommonLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/Sm > mSpiFlashCommonLib.inf > new file mode 100644 > index 0000000000..374f5ea52b > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/Sm > mSpiFlashCommonLib.inf > @@ -0,0 +1,49 @@ > +## @file >=20 > +# SMM Library instance of Spi Flash Common Library Class >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010017 >=20 > + BASE_NAME =3D SmmSpiFlashCommonLib >=20 > + FILE_GUID =3D 9632D96E-E849-4217-9217-DC500B8AAE4= 7 >=20 > + VERSION_STRING =3D 1.0 >=20 > + MODULE_TYPE =3D DXE_SMM_DRIVER >=20 > + LIBRARY_CLASS =3D SpiFlashCommonLib|DXE_SMM_DRIVER >=20 > + CONSTRUCTOR =3D SmmSpiFlashCommonLibConstructor >=20 > +# >=20 > +# The following information is for reference only and not required by th= e build > tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 >=20 > +# >=20 > + >=20 > +[LibraryClasses] >=20 > + IoLib >=20 > + MemoryAllocationLib >=20 > + BaseLib >=20 > + UefiLib >=20 > + SmmServicesTableLib >=20 > + BaseMemoryLib >=20 > + DebugLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + >=20 > +[Pcd] >=20 > + gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES >=20 > + gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES >=20 > + >=20 > +[Sources] >=20 > + SpiFlashCommonSmmLib.c >=20 > + SpiFlashCommon.c >=20 > + >=20 > +[Protocols] >=20 > + gPchSmmSpiProtocolGuid ## CONSUMES >=20 > + >=20 > +[Depex.X64.DXE_SMM_DRIVER] >=20 > + gPchSmmSpiProtocolGuid >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiF > lashCommon.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiF > lashCommon.c > new file mode 100644 > index 0000000000..f86896dd1f > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiF > lashCommon.c > @@ -0,0 +1,210 @@ > +/** @file >=20 > + Wrap EFI_SPI_PROTOCOL to provide some library level interfaces >=20 > + for module use. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +PCH_SPI_PROTOCOL *mSpiProtocol; >=20 > + >=20 > +// >=20 > +// Variables for boottime and runtime usage. >=20 > +// >=20 > +UINTN mBiosAreaBaseAddress =3D 0; >=20 > +UINTN mBiosSize =3D 0; >=20 > +UINTN mBiosOffset =3D 0; >=20 > + >=20 > +/** >=20 > + Enable block protection on the Serial Flash device. >=20 > + >=20 > + @retval EFI_SUCCESS Opertion is successful. >=20 > + @retval EFI_DEVICE_ERROR If there is any device errors. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SpiFlashLock ( >=20 > + VOID >=20 > + ) >=20 > +{ >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Read NumBytes bytes of data from the address specified by >=20 > + PAddress into Buffer. >=20 > + >=20 > + @param[in] Address The starting physical address of the rea= d. >=20 > + @param[in,out] NumBytes On input, the number of bytes to read. O= n > output, the number >=20 > + of bytes actually read. >=20 > + @param[out] Buffer The destination data buffer for the read= . >=20 > + >=20 > + @retval EFI_SUCCESS Operation is successful. >=20 > + @retval EFI_DEVICE_ERROR If there is any device errors. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SpiFlashRead ( >=20 > + IN UINTN Address, >=20 > + IN OUT UINT32 *NumBytes, >=20 > + OUT UINT8 *Buffer >=20 > + ) >=20 > +{ >=20 > + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); >=20 > + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + // >=20 > + // This function is implemented specifically for those platforms >=20 > + // at which the SPI device is memory mapped for read. So this >=20 > + // function just do a memory copy for Spi Flash Read. >=20 > + // >=20 > + CopyMem (Buffer, (VOID *) Address, *NumBytes); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > +/** >=20 > + Write NumBytes bytes of data from Buffer to the address specified by >=20 > + PAddresss. >=20 > + >=20 > + @param[in] Address The starting physical address of the w= rite. >=20 > + @param[in,out] NumBytes On input, the number of bytes to write= . On > output, >=20 > + the actual number of bytes written. >=20 > + @param[in] Buffer The source data buffer for the write. >=20 > + >=20 > + @retval EFI_SUCCESS Operation is successful. >=20 > + @retval EFI_DEVICE_ERROR If there is any device errors. >=20 > + @retval EFI_INVALID_PARAMETER Invalid parameter. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SpiFlashWrite ( >=20 > + IN UINTN Address, >=20 > + IN OUT UINT32 *NumBytes, >=20 > + IN UINT8 *Buffer >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINTN Offset; >=20 > + UINT32 Length; >=20 > + UINT32 RemainingBytes; >=20 > + >=20 > + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); >=20 > + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + ASSERT (Address >=3D mBiosAreaBaseAddress); >=20 > + if (Address < mBiosAreaBaseAddress) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + Offset =3D Address - mBiosAreaBaseAddress; >=20 > + >=20 > + ASSERT ((*NumBytes + Offset) <=3D mBiosSize); >=20 > + if ((*NumBytes + Offset) > mBiosSize) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + Status =3D EFI_SUCCESS; >=20 > + RemainingBytes =3D *NumBytes; >=20 > + >=20 > + >=20 > + while (RemainingBytes > 0) { >=20 > + if (RemainingBytes > SECTOR_SIZE_4KB) { >=20 > + Length =3D SECTOR_SIZE_4KB; >=20 > + } else { >=20 > + Length =3D RemainingBytes; >=20 > + } >=20 > + Status =3D mSpiProtocol->FlashWrite ( >=20 > + mSpiProtocol, >=20 > + FlashRegionBios, >=20 > + (UINT32) Offset, >=20 > + Length, >=20 > + Buffer >=20 > + ); >=20 > + if (EFI_ERROR (Status)) { >=20 > + break; >=20 > + } >=20 > + RemainingBytes -=3D Length; >=20 > + Offset +=3D Length; >=20 > + Buffer +=3D Length; >=20 > + } >=20 > + >=20 > + // >=20 > + // Actual number of bytes written >=20 > + // >=20 > + *NumBytes -=3D RemainingBytes; >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > + Erase the block starting at Address. >=20 > + >=20 > + @param[in] Address The starting physical address of the block= to be > erased. >=20 > + This library assume that caller garantee t= hat the PAddress >=20 > + is at the starting address of this block. >=20 > + @param[in] NumBytes On input, the number of bytes of the logic= al block > to be erased. >=20 > + On output, the actual number of bytes eras= ed. >=20 > + >=20 > + @retval EFI_SUCCESS. Operation is successful. >=20 > + @retval EFI_DEVICE_ERROR If there is any device errors. >=20 > + @retval EFI_INVALID_PARAMETER Invalid parameter. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SpiFlashBlockErase ( >=20 > + IN UINTN Address, >=20 > + IN UINTN *NumBytes >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINTN Offset; >=20 > + UINTN RemainingBytes; >=20 > + >=20 > + ASSERT (NumBytes !=3D NULL); >=20 > + if (NumBytes =3D=3D NULL) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + ASSERT (Address >=3D mBiosAreaBaseAddress); >=20 > + if (Address < mBiosAreaBaseAddress) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + Offset =3D Address - mBiosAreaBaseAddress; >=20 > + >=20 > + ASSERT ((*NumBytes % SECTOR_SIZE_4KB) =3D=3D 0); >=20 > + if ((*NumBytes % SECTOR_SIZE_4KB) !=3D 0) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + ASSERT ((*NumBytes + Offset) <=3D mBiosSize); >=20 > + if ((*NumBytes + Offset) > mBiosSize) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + Status =3D EFI_SUCCESS; >=20 > + RemainingBytes =3D *NumBytes; >=20 > + >=20 > + >=20 > + Status =3D mSpiProtocol->FlashErase ( >=20 > + mSpiProtocol, >=20 > + FlashRegionBios, >=20 > + (UINT32) Offset, >=20 > + (UINT32) RemainingBytes >=20 > + ); >=20 > + return Status; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiF > lashCommonSmmLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiF > lashCommonSmmLib.c > new file mode 100644 > index 0000000000..7941b8f872 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiF > lashCommonSmmLib.c > @@ -0,0 +1,58 @@ > +/** @file >=20 > + SMM Library instance of SPI Flash Common Library Class >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +extern PCH_SPI_PROTOCOL *mSpiProtocol; >=20 > + >=20 > +extern UINTN mBiosAreaBaseAddress; >=20 > +extern UINTN mBiosSize; >=20 > +extern UINTN mBiosOffset; >=20 > + >=20 > +/** >=20 > + The library constructuor. >=20 > + >=20 > + The function does the necessary initialization work for this library >=20 > + instance. >=20 > + >=20 > + @param[in] ImageHandle The firmware allocated handle for the UE= FI > image. >=20 > + @param[in] SystemTable A pointer to the EFI system table. >=20 > + >=20 > + @retval EFI_SUCCESS The function always return EFI_SUCCESS f= or now. >=20 > + It will ASSERT on error for debug versio= n. >=20 > + @retval EFI_ERROR Please reference LocateProtocol for erro= r code > details. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SmmSpiFlashCommonLibConstructor ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN EFI_SYSTEM_TABLE *SystemTable >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINT32 BaseAddr; >=20 > + UINT32 RegionSize; >=20 > + >=20 > + mBiosAreaBaseAddress =3D (UINTN)PcdGet32 (PcdBiosAreaBaseAddress); >=20 > + mBiosSize =3D (UINTN)PcdGet32 (PcdBiosSize); >=20 > + >=20 > + // >=20 > + // Locate the SMM SPI protocol. >=20 > + // >=20 > + Status =3D gSmst->SmmLocateProtocol ( >=20 > + &gPchSmmSpiProtocolGuid, >=20 > + NULL, >=20 > + (VOID **) &mSpiProtocol >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, > &BaseAddr, &RegionSize); >=20 > + mBiosOffset =3D BaseAddr; >=20 > + return Status; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeGopPolicyInit.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeGopPolicyInit.c > new file mode 100644 > index 0000000000..a2367047cd > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeGopPolicyInit.c > @@ -0,0 +1,168 @@ > +/** @file >=20 > + This file initialises and Installs GopPolicy Protocol. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL > mGOPPolicy; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize =3D 0; >=20 > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS > mVbtAddress =3D 0; >=20 > + >=20 > +/** >=20 > + @param[out] CurrentLidStatus >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_UNSUPPORTED >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetPlatformLidStatus ( >=20 > + OUT LID_STATUS *CurrentLidStatus >=20 > + ) >=20 > +{ >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > + >=20 > +/** >=20 > + @param[out] CurrentDockStatus >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_UNSUPPORTED >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetPlatformDockStatus ( >=20 > + OUT DOCK_STATUS CurrentDockStatus >=20 > + ) >=20 > +{ >=20 > + return EFI_UNSUPPORTED; >=20 > +} >=20 > + >=20 > +/** >=20 > + @param[out] VbtAddress >=20 > + @param[out] VbtSize >=20 > + >=20 > + @retval EFI_SUCCESS >=20 > + @retval EFI_NOT_FOUND >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GetVbtData ( >=20 > + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, >=20 > + OUT UINT32 *VbtSize >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + UINTN FvProtocolCount; >=20 > + EFI_HANDLE *FvHandles; >=20 > + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; >=20 > + UINTN Index; >=20 > + UINT32 AuthenticationStatus; >=20 > + UINT8 *Buffer; >=20 > + UINTN VbtBufferSize; >=20 > + >=20 > + >=20 > + Status =3D EFI_NOT_FOUND; >=20 > + if ( mVbtAddress =3D=3D 0) { >=20 > + Fv =3D NULL; >=20 > + >=20 > + Buffer =3D 0; >=20 > + FvHandles =3D NULL; >=20 > + Status =3D gBS->LocateHandleBuffer ( >=20 > + ByProtocol, >=20 > + &gEfiFirmwareVolume2ProtocolGuid, >=20 > + NULL, >=20 > + &FvProtocolCount, >=20 > + &FvHandles >=20 > + ); >=20 > + if (!EFI_ERROR (Status)) { >=20 > + for (Index =3D 0; Index < FvProtocolCount; Index++) { >=20 > + Status =3D gBS->HandleProtocol ( >=20 > + FvHandles[Index], >=20 > + &gEfiFirmwareVolume2ProtocolGuid, >=20 > + (VOID **) &Fv >=20 > + ); >=20 > + VbtBufferSize =3D 0; >=20 > + Status =3D Fv->ReadSection ( >=20 > + Fv, >=20 > + PcdGetPtr (PcdIntelGraphicsVbtFileGuid), >=20 > + EFI_SECTION_RAW, >=20 > + 0, >=20 > + (VOID **) &Buffer, >=20 > + &VbtBufferSize, >=20 > + &AuthenticationStatus >=20 > + ); >=20 > + if (!EFI_ERROR (Status)) { >=20 > + *VbtAddress =3D (EFI_PHYSICAL_ADDRESS)Buffer; >=20 > + *VbtSize =3D (UINT32)VbtBufferSize; >=20 > + mVbtAddress =3D *VbtAddress; >=20 > + mVbtSize =3D *VbtSize; >=20 > + Status =3D EFI_SUCCESS; >=20 > + break; >=20 > + } >=20 > + } >=20 > + } else { >=20 > + Status =3D EFI_NOT_FOUND; >=20 > + } >=20 > + >=20 > + if (FvHandles !=3D NULL) { >=20 > + FreePool (FvHandles); >=20 > + FvHandles =3D NULL; >=20 > + } >=20 > + } else { >=20 > + *VbtAddress =3D mVbtAddress; >=20 > + *VbtSize =3D mVbtSize; >=20 > + Status =3D EFI_SUCCESS; >=20 > + } >=20 > + >=20 > + return Status; >=20 > +} >=20 > + >=20 > +/** >=20 > +Initialize GOP DXE Policy >=20 > + >=20 > +@param[in] ImageHandle Image handle of this driver. >=20 > + >=20 > +@retval EFI_SUCCESS Initialization complete. >=20 > +@retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r. >=20 > +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze > the driver. >=20 > +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GopPolicyInitDxe ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + // >=20 > + // Initialize the EFI Driver Library >=20 > + // >=20 > + SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0); >=20 > + >=20 > + mGOPPolicy.Revision =3D GOP_POLICY_PROTOCOL_REVISION_03= ; >=20 > + mGOPPolicy.GetPlatformLidStatus =3D GetPlatformLidStatus; >=20 > + mGOPPolicy.GetVbtData =3D GetVbtData; >=20 > + mGOPPolicy.GetPlatformDockStatus =3D GetPlatformDockStatus; >=20 > + >=20 > + // >=20 > + // Install protocol to allow access to this Policy. >=20 > + // >=20 > + Status =3D gBS->InstallMultipleProtocolInterfaces ( >=20 > + &ImageHandle, >=20 > + &gGopPolicyProtocolGuid, >=20 > + &mGOPPolicy, >=20 > + NULL >=20 > + ); >=20 > + >=20 > + return Status; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxePchPolicyInit.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxePchPolicyInit.c > new file mode 100644 > index 0000000000..e75abcb42a > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxePchPolicyInit.c > @@ -0,0 +1,61 @@ > +/** @file >=20 > + This file initialises and Installs GopPolicy Protocol. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CreatePchDxeConfigBlocks ( >=20 > + IN OUT VOID **SaPolicy >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PchInstallPolicyProtocol ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN VOID *PchPolicy >=20 > + ); >=20 > + >=20 > +/** >=20 > + Initialize PCH DXE Policy >=20 > + >=20 > + @param[in] ImageHandle Image handle of this driver. >=20 > + >=20 > + @retval EFI_SUCCESS Initialization complete. >=20 > + @retval EFI_UNSUPPORTED The chipset is unsupported by this dri= ver. >=20 > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver. >=20 > + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PchPolicyInitDxe ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_HANDLE PchHandle; >=20 > + VOID *PchPolicy; >=20 > + >=20 > + // >=20 > + // Call CreatePchDxeConfigBlocks to create & initialize platform polic= y > structure >=20 > + // and get all Intel default policy settings. >=20 > + // >=20 > + Status =3D CreatePchDxeConfigBlocks (&PchPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // >=20 > + // Install PchInstallPolicyProtocol. >=20 > + // While installed, RC assumes the Policy is ready and finalized. So p= lease >=20 > + // update and override any setting before calling this function. >=20 > + // >=20 > + PchHandle =3D NULL; >=20 > + Status =3D PchInstallPolicyProtocol (PchHandle, PchPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeSaPolicyInit.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeSaPolicyInit.c > new file mode 100644 > index 0000000000..5a9def9d13 > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeSaPolicyInit.c > @@ -0,0 +1,61 @@ > +/** @file >=20 > + This file initialises and Installs GopPolicy Protocol. >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +CreateSaDxeConfigBlocks ( >=20 > + IN OUT VOID **SaPolicy >=20 > + ); >=20 > + >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaInstallPolicyProtocol ( >=20 > + IN EFI_HANDLE ImageHandle, >=20 > + IN VOID *SaPolicy >=20 > + ); >=20 > + >=20 > +/** >=20 > + Initialize SA DXE Policy >=20 > + >=20 > + @param[in] ImageHandle Image handle of this driver. >=20 > + >=20 > + @retval EFI_SUCCESS Initialization complete. >=20 > + @retval EFI_UNSUPPORTED The chipset is unsupported by this dri= ver. >=20 > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver. >=20 > + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaPolicyInitDxe ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_HANDLE SaHandle; >=20 > + VOID *SaPolicy; >=20 > + >=20 > + // >=20 > + // Call CreateSaDxeConfigBlocks to create & initialize platform policy > structure >=20 > + // and get all Intel default policy settings. >=20 > + // >=20 > + Status =3D CreateSaDxeConfigBlocks (&SaPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + // >=20 > + // Install SaInstallPolicyProtocol. >=20 > + // While installed, RC assumes the Policy is ready and finalized. So p= lease >=20 > + // update and override any setting before calling this function. >=20 > + // >=20 > + SaHandle =3D NULL; >=20 > + Status =3D SaInstallPolicyProtocol (SaHandle, SaPolicy); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeSiliconPolicyUpdateLate.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeSiliconPolicyUpdateLate.c > new file mode 100644 > index 0000000000..2eee9958be > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeSiliconPolicyUpdateLate.c > @@ -0,0 +1,97 @@ > +/** @file >=20 > + >=20 > + Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > + SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +**/ >=20 > + >=20 > +#include >=20 > +#include >=20 > +#include >=20 > +#include >=20 > + >=20 > +/** >=20 > + Initialize SA DXE Policy >=20 > + >=20 > + @param[in] ImageHandle Image handle of this driver. >=20 > + >=20 > + @retval EFI_SUCCESS Initialization complete. >=20 > + @retval EFI_UNSUPPORTED The chipset is unsupported by this dri= ver. >=20 > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver. >=20 > + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +SaPolicyInitDxe ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Initialize PCH DXE Policy >=20 > + >=20 > + @param[in] ImageHandle Image handle of this driver. >=20 > + >=20 > + @retval EFI_SUCCESS Initialization complete. >=20 > + @retval EFI_UNSUPPORTED The chipset is unsupported by this dri= ver. >=20 > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver. >=20 > + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +PchPolicyInitDxe ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Initialize GOP DXE Policy >=20 > + >=20 > + @param[in] ImageHandle Image handle of this driver. >=20 > + >=20 > + @retval EFI_SUCCESS Initialization complete. >=20 > + @retval EFI_UNSUPPORTED The chipset is unsupported by this dri= ver. >=20 > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver. >=20 > + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. >=20 > +**/ >=20 > +EFI_STATUS >=20 > +EFIAPI >=20 > +GopPolicyInitDxe ( >=20 > + IN EFI_HANDLE ImageHandle >=20 > + ); >=20 > + >=20 > +/** >=20 > + Performs silicon late policy update. >=20 > + >=20 > + The meaning of Policy is defined by silicon code. >=20 > + It could be the raw data, a handle, a Protocol, etc. >=20 > + >=20 > + The input Policy must be returned by SiliconPolicyDoneLate(). >=20 > + >=20 > + In FSP or non-FSP path, the board may use additional way to get >=20 > + the silicon policy data field based upon the input Policy. >=20 > + >=20 > + @param[in, out] Policy Pointer to policy. >=20 > + >=20 > + @return the updated policy. >=20 > +**/ >=20 > +VOID * >=20 > +EFIAPI >=20 > +SiliconPolicyUpdateLate ( >=20 > + IN OUT VOID *Policy >=20 > + ) >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + >=20 > + SaPolicyInitDxe (gImageHandle); >=20 > + PchPolicyInitDxe (gImageHandle); >=20 > + >=20 > + if (PcdGetBool (PcdIntelGopEnable)) { >=20 > + // >=20 > + // GOP Dxe Policy Initialization >=20 > + // >=20 > + Status =3D GopPolicyInitDxe (gImageHandle); >=20 > + RETURN_ERROR (Status); >=20 > + DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); >=20 > + } >=20 > + >=20 > + return Policy; >=20 > +} >=20 > + >=20 > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeSiliconPolicyUpdateLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeSiliconPolicyUpdateLib.inf > new file mode 100644 > index 0000000000..573dbfa04a > --- /dev/null > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpd= at > eLib/DxeSiliconPolicyUpdateLib.inf > @@ -0,0 +1,49 @@ > +## @file >=20 > +# Component information file for Silicon Policy Update Library >=20 > +# >=20 > +# Copyright (c) 2021, Intel Corporation. All rights reserved.
>=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D DxeSiliconUpdateLib >=20 > + FILE_GUID =3D C523609D-E354-416B-B24F-33468D4BD21= D >=20 > + MODULE_TYPE =3D DXE_DRIVER >=20 > + VERSION_STRING =3D 1.0 >=20 > + LIBRARY_CLASS =3D SiliconPolicyUpdateLib >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseLib >=20 > + PcdLib >=20 > + DebugLib >=20 > + UefiBootServicesTableLib >=20 > + DxeSaPolicyLib >=20 > + DxePchPolicyLib >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + MdeModulePkg/MdeModulePkg.dec >=20 > + TigerlakeSiliconPkg/SiPkg.dec >=20 > + MinPlatformPkg/MinPlatformPkg.dec >=20 > + TigerlakeOpenBoardPkg/OpenBoardPkg.dec >=20 > + IntelSiliconPkg/IntelSiliconPkg.dec >=20 > + >=20 > +[Sources] >=20 > + DxeSiliconPolicyUpdateLate.c >=20 > + DxeSaPolicyInit.c >=20 > + DxePchPolicyInit.c >=20 > + DxeGopPolicyInit.c >=20 > + >=20 > +[Pcd] >=20 > + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable >=20 > + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid >=20 > + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid >=20 > + >=20 > +[Protocols] >=20 > + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES >=20 > + gGopPolicyProtocolGuid ## PRODUCES >=20 > + >=20 > +[Depex] >=20 > + gEfiVariableArchProtocolGuid >=20 > -- > 2.24.0.windows.2