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boundary="_000_PH0PR05MB8702094CD8F4E78E627E9F85B9C19PH0PR05MB8702namp_" --_000_PH0PR05MB8702094CD8F4E78E627E9F85B9C19PH0PR05MB8702namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Reviewed-by: Andrei Warkentin ________________________________ From: Jeremy Linton Sent: Thursday, August 19, 2021 11:16 PM To: devel@edk2.groups.io Cc: pete@akeo.ie ; ardb+tianocore@kernel.org ; Andrei Warkentin ; Sunny.Wang@arm.com <= Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com ; Jeremy Linton ; Ren=E9 Treffer Subject: [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restric= tion The CM4 has an actual PCIe slot, so the device filtering need to be a little less restrictive WRT busses with more than 1 device given that switches can now appear in the topology. Since it is possible to start numbering the busses with a non-zero value, the bus restriction should be based on the secondary side of the root port. This isn't likely but its better than hard-coding the limit. Suggested-by: Ren=E9 Treffer Signed-off-by: Jeremy Linton --- .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 21 ++++++++++++++---= ---- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegme= ntLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentL= ib.c index 44ce3b4b99..6d15e82fa2 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c @@ -19,6 +19,7 @@ #include #include #include +#include typedef enum { PciCfgWidthUint8 =3D 0, @@ -78,6 +79,9 @@ PciSegmentLibGetConfigBase ( UINT64 Base; UINT64 Offset; UINT32 Dev; + UINT32 Bus; + UINT32 Data; + UINT32 HostPortSec; Base =3D PCIE_REG_BASE; Offset =3D Address & 0xFFF; /* Pick off the 4k register offset *= / @@ -89,17 +93,20 @@ PciSegmentLibGetConfigBase ( Base +=3D PCIE_EXT_CFG_DATA; if (mPciSegmentLastAccess !=3D Address) { Dev =3D EFI_PCI_ADDR_DEV (Address); + Bus =3D EFI_PCI_ADDR_BUS (Address); + HostPortSec =3D MmioRead8 (PCIE_REG_BASE + + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + /* - * Scan things out directly rather than translating the "bus" to a d= evice, etc.. - * only we need to limit each bus to a single device. + * There can only be a single device on bus 1 (downstream of root). + * Subsequent busses (behind a PCIe switch) can have more. */ - if (Dev < 1) { - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); - mPciSegmentLastAccess =3D Address; - } else { - mPciSegmentLastAccess =3D 0; + if (Dev > 0 && (Bus <=3D HostPortSec)) { return 0xFFFFFFFF; } + + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); + mPciSegmentLastAccess =3D Address; } } return Base + Offset; -- 2.13.7 --_000_PH0PR05MB8702094CD8F4E78E627E9F85B9C19PH0PR05MB8702namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
From: Jeremy Linton <jer= emy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <= ;ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com&= gt;; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@ar= m.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton= @arm.com>; Ren=E9 Treffer <treffer+groups.io@measite.de>
Subject: [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device = restriction
 
The CM4 has an actual PCIe slot, so the device fil= tering
need to be a little less restrictive WRT busses with more
than 1 device given that switches can now appear in the
topology. Since it is possible to start numbering the
busses with a non-zero value, the bus restriction should
be based on the secondary side of the root port. This
isn't likely but its better than hard-coding the limit.

Suggested-by: Ren=E9 Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
 .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c    | = 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegme= ntLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentL= ib.c
index 44ce3b4b99..6d15e82fa2 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c=
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c=
@@ -19,6 +19,7 @@
 #include <Library/PciSegmentLib.h>
 #include <Library/UefiLib.h>
 #include <IndustryStandard/Bcm2711.h>
+#include <IndustryStandard/Pci30.h>
 
 typedef enum {
   PciCfgWidthUint8 =3D 0,
@@ -78,6 +79,9 @@ PciSegmentLibGetConfigBase (
   UINT64        Base;
   UINT64        Offset;
   UINT32        Dev;
+  UINT32        Bus;
+  UINT32        Data;
+  UINT32        HostPortSec;
 
   Base =3D PCIE_REG_BASE;
   Offset =3D Address & 0xFFF;     &= nbsp;   /* Pick off the 4k register offset */
@@ -89,17 +93,20 @@ PciSegmentLibGetConfigBase (
     Base +=3D PCIE_EXT_CFG_DATA;
     if (mPciSegmentLastAccess !=3D Address) {
       Dev =3D EFI_PCI_ADDR_DEV (Address); +      Bus =3D EFI_PCI_ADDR_BUS (Address);
+      HostPortSec =3D MmioRead8 (PCIE_REG_BASE +<= br> +            &n= bsp;            = ;      PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);<= br> +
       /*
-       * Scan things out directly rather tha= n translating the "bus" to a device, etc..
-       * only we need to limit each bus to a= single device.
+       * There can only be a single device o= n bus 1 (downstream of root).
+       * Subsequent busses (behind a PCIe sw= itch) can have more.
        */
-      if (Dev < 1) {
-          MmioWrite32 (PCIE_R= EG_BASE + PCIE_EXT_CFG_INDEX, Address);
-          mPciSegmentLastAcce= ss =3D Address;
-      } else {
-          mPciSegmentLastAcce= ss =3D 0;
+      if (Dev > 0 && (Bus <=3D Host= PortSec)) {
           return 0xFFFFF= FFF;
       }
+
+      MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_I= NDEX, Address);
+      mPciSegmentLastAccess =3D Address;
     }
   }
   return Base + Offset;
--
2.13.7

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