* [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu
2021-08-20 4:16 [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Jeremy Linton
@ 2021-08-20 4:16 ` Jeremy Linton
2021-08-20 20:14 ` Andrei Warkentin
2021-08-20 20:31 ` Samer El-Haj-Mahmoud
2021-08-20 4:16 ` [PATCH v3 2/7] Platform/RaspberryPi: Break XHCI into its own SSDT Jeremy Linton
` (6 subsequent siblings)
7 siblings, 2 replies; 22+ messages in thread
From: Jeremy Linton @ 2021-08-20 4:16 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
Arm has standardized a PCI SMC conduit that can be used
to access the PCI config space in a standardized way. This
functionality doesn't yet exist in many OS/Distro's. Lets
add another advanced config item that allows the user
to toggle between presenting the XHCI on the base RPi4
as a platform device, or presenting this newer PCIe
conduit. The CM4 doesn't have an attached XHCI controller
soldered to the PCIe, so PCIe mode is the default.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 42 ++++++++++++++++++++++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 +++++++++
Platform/RaspberryPi/Include/ConfigVars.h | 4 +++
Platform/RaspberryPi/RPi3/RPi3.dsc | 6 ++++
Platform/RaspberryPi/RPi4/RPi4.dsc | 8 +++++
Platform/RaspberryPi/RaspberryPi.dec | 1 +
8 files changed, 84 insertions(+)
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 9e78cb47ad..87f6b4e7bb 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -43,6 +43,7 @@ extern UINT8 ConfigDxeStrings[];
STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol;
STATIC UINT32 mModelFamily = 0;
STATIC UINT32 mModelInstalledMB = 0;
+STATIC UINT32 mModelRevision = 0;
STATIC EFI_MAC_ADDRESS mMacAddress;
@@ -271,6 +272,40 @@ SetupVariables (
ASSERT_EFI_ERROR (Status);
}
+ if (mModelFamily >= 4) {
+ if (((mModelRevision >> 4) & 0xFF) == 0x14) {
+ /*
+ * Enable PCIe by default on CM4
+ */
+ Status = PcdSet32S (PcdXhciPci, 2);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ Size = sizeof (UINT32);
+ Status = gRT->GetVariable (L"XhciPci",
+ &gConfigDxeFormSetGuid,
+ NULL, &Size, &Var32);
+ if (EFI_ERROR (Status) || (Var32 == 0)) {
+ /*
+ * Enable XHCI by default
+ */
+ Status = PcdSet32S (PcdXhciPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ /*
+ * Enable PCIe
+ */
+ Status = PcdSet32S (PcdXhciPci, 1);
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ } else {
+ /*
+ * Disable PCIe and XHCI
+ */
+ Status = PcdSet32S (PcdXhciPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ }
+
Size = sizeof (AssetTagVar);
Status = gRT->GetVariable (L"AssetTag",
&gConfigDxeFormSetGuid,
@@ -888,6 +923,13 @@ ConfigInitialize (
DEBUG ((DEBUG_INFO, "Current Raspberry Pi installed RAM size is %d MB\n", mModelInstalledMB));
}
+ Status = mFwProtocol->GetModelRevision (&mModelRevision);
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "Couldn't get the Raspberry Pi revision: %r\n", Status));
+ } else {
+ DEBUG ((DEBUG_INFO, "Current Raspberry Pi revision %x\n", mModelRevision));
+ }
+
Status = SetupVariables ();
if (Status != EFI_SUCCESS) {
DEBUG ((DEBUG_ERROR, "Couldn't not setup NV vars: %r\n", Status));
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
index 4bb2d08550..e6e22ad82e 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
@@ -94,6 +94,7 @@
gRaspberryPiTokenSpaceGuid.PcdFanOnGpio
gRaspberryPiTokenSpaceGuid.PcdFanTemp
gRaspberryPiTokenSpaceGuid.PcdUartInUse
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci
[Depex]
gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
index 466fa852cb..5ec17072c3 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
@@ -57,6 +57,11 @@
#string STR_ADVANCED_FANTEMP_PROMPT #language en-US "ACPI fan temperature"
#string STR_ADVANCED_FANTEMP_HELP #language en-US "Cycle a fan at C"
+#string STR_ADVANCED_XHCIPCI_PROMPT #language en-US "ACPI XHCI/PCIe"
+#string STR_ADVANCED_XHCIPCI_HELP #language en-US "OS sees XHCI USB platform device or PCIe bridge"
+#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI"
+#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe"
+
#string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag"
#string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system Asset Tag"
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
index fa34eab809..18b3ec726e 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -56,6 +56,11 @@ formset
name = FanTemp,
guid = CONFIGDXE_FORM_SET_GUID;
+ efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA,
+ attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ name = XhciPci,
+ guid = CONFIGDXE_FORM_SET_GUID;
+
efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA,
attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
name = SystemTableMode,
@@ -212,6 +217,18 @@ formset
default = 60,
endnumeric;
endif;
+
+ suppressif ideqval XhciPci.Value == 2;
+ grayoutif NOT ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_ACPI;
+ oneof varid = XhciPci.Value,
+ prompt = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT),
+ help = STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP),
+ flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_XHCI), value = 0, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), value = 1, flags = 0;
+ endoneof;
+ endif;
+ endif;
#endif
string varid = AssetTag.AssetTag,
prompt = STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT),
diff --git a/Platform/RaspberryPi/Include/ConfigVars.h b/Platform/RaspberryPi/Include/ConfigVars.h
index 142317985a..a5b32b5284 100644
--- a/Platform/RaspberryPi/Include/ConfigVars.h
+++ b/Platform/RaspberryPi/Include/ConfigVars.h
@@ -77,6 +77,10 @@ typedef struct {
} ADVANCED_FANTEMP_VARSTORE_DATA;
typedef struct {
+ UINT32 Value;
+} ADVANCED_XHCIPCI_VARSTORE_DATA;
+
+typedef struct {
#define SYSTEM_TABLE_MODE_ACPI 0
#define SYSTEM_TABLE_MODE_BOTH 1
#define SYSTEM_TABLE_MODE_DT 2
diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RPi3/RPi3.dsc
index 1c8a5408e7..6ab5d1ae6d 100644
--- a/Platform/RaspberryPi/RPi3/RPi3.dsc
+++ b/Platform/RaspberryPi/RPi3/RPi3.dsc
@@ -520,6 +520,12 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberryPiTokenSpaceGuid|0x0|0
+ # Select XHCI/PCIe mode (not valid on rpi3)
+ #
+ # 0 - DISABLED
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc
index dcf9bb5f11..babcbb2f41 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -536,6 +536,14 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberryPiTokenSpaceGuid|0x0|0
+ # Select XHCI/PCIe mode
+ #
+ # 0 - XHCI Enabled (default on !cm4)
+ # 1 - PCIe Enabled
+ # 2 - PCIe Enabled (default on cm4)
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/RaspberryPi.dec
index 2ca25ff9e6..797be59274 100644
--- a/Platform/RaspberryPi/RaspberryPi.dec
+++ b/Platform/RaspberryPi/RaspberryPi.dec
@@ -71,3 +71,4 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x0000001E
gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|0|UINT32|0x0000001F
gRaspberryPiTokenSpaceGuid.PcdUartInUse|1|UINT32|0x00000021
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000022
--
2.13.7
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu
2021-08-20 4:16 ` [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu Jeremy Linton
@ 2021-08-20 20:14 ` Andrei Warkentin
2021-08-20 20:31 ` Samer El-Haj-Mahmoud
1 sibling, 0 replies; 22+ messages in thread
From: Andrei Warkentin @ 2021-08-20 20:14 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com
[-- Attachment #1: Type: text/plain, Size: 9202 bytes --]
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
________________________________
From: Jeremy Linton <jeremy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu
Arm has standardized a PCI SMC conduit that can be used
to access the PCI config space in a standardized way. This
functionality doesn't yet exist in many OS/Distro's. Lets
add another advanced config item that allows the user
to toggle between presenting the XHCI on the base RPi4
as a platform device, or presenting this newer PCIe
conduit. The CM4 doesn't have an attached XHCI controller
soldered to the PCIe, so PCIe mode is the default.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 42 ++++++++++++++++++++++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 +++++++++
Platform/RaspberryPi/Include/ConfigVars.h | 4 +++
Platform/RaspberryPi/RPi3/RPi3.dsc | 6 ++++
Platform/RaspberryPi/RPi4/RPi4.dsc | 8 +++++
Platform/RaspberryPi/RaspberryPi.dec | 1 +
8 files changed, 84 insertions(+)
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 9e78cb47ad..87f6b4e7bb 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -43,6 +43,7 @@ extern UINT8 ConfigDxeStrings[];
STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol;
STATIC UINT32 mModelFamily = 0;
STATIC UINT32 mModelInstalledMB = 0;
+STATIC UINT32 mModelRevision = 0;
STATIC EFI_MAC_ADDRESS mMacAddress;
@@ -271,6 +272,40 @@ SetupVariables (
ASSERT_EFI_ERROR (Status);
}
+ if (mModelFamily >= 4) {
+ if (((mModelRevision >> 4) & 0xFF) == 0x14) {
+ /*
+ * Enable PCIe by default on CM4
+ */
+ Status = PcdSet32S (PcdXhciPci, 2);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ Size = sizeof (UINT32);
+ Status = gRT->GetVariable (L"XhciPci",
+ &gConfigDxeFormSetGuid,
+ NULL, &Size, &Var32);
+ if (EFI_ERROR (Status) || (Var32 == 0)) {
+ /*
+ * Enable XHCI by default
+ */
+ Status = PcdSet32S (PcdXhciPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ /*
+ * Enable PCIe
+ */
+ Status = PcdSet32S (PcdXhciPci, 1);
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ } else {
+ /*
+ * Disable PCIe and XHCI
+ */
+ Status = PcdSet32S (PcdXhciPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ }
+
Size = sizeof (AssetTagVar);
Status = gRT->GetVariable (L"AssetTag",
&gConfigDxeFormSetGuid,
@@ -888,6 +923,13 @@ ConfigInitialize (
DEBUG ((DEBUG_INFO, "Current Raspberry Pi installed RAM size is %d MB\n", mModelInstalledMB));
}
+ Status = mFwProtocol->GetModelRevision (&mModelRevision);
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "Couldn't get the Raspberry Pi revision: %r\n", Status));
+ } else {
+ DEBUG ((DEBUG_INFO, "Current Raspberry Pi revision %x\n", mModelRevision));
+ }
+
Status = SetupVariables ();
if (Status != EFI_SUCCESS) {
DEBUG ((DEBUG_ERROR, "Couldn't not setup NV vars: %r\n", Status));
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
index 4bb2d08550..e6e22ad82e 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
@@ -94,6 +94,7 @@
gRaspberryPiTokenSpaceGuid.PcdFanOnGpio
gRaspberryPiTokenSpaceGuid.PcdFanTemp
gRaspberryPiTokenSpaceGuid.PcdUartInUse
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci
[Depex]
gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
index 466fa852cb..5ec17072c3 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
@@ -57,6 +57,11 @@
#string STR_ADVANCED_FANTEMP_PROMPT #language en-US "ACPI fan temperature"
#string STR_ADVANCED_FANTEMP_HELP #language en-US "Cycle a fan at C"
+#string STR_ADVANCED_XHCIPCI_PROMPT #language en-US "ACPI XHCI/PCIe"
+#string STR_ADVANCED_XHCIPCI_HELP #language en-US "OS sees XHCI USB platform device or PCIe bridge"
+#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI"
+#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe"
+
#string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag"
#string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system Asset Tag"
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
index fa34eab809..18b3ec726e 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -56,6 +56,11 @@ formset
name = FanTemp,
guid = CONFIGDXE_FORM_SET_GUID;
+ efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA,
+ attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ name = XhciPci,
+ guid = CONFIGDXE_FORM_SET_GUID;
+
efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA,
attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
name = SystemTableMode,
@@ -212,6 +217,18 @@ formset
default = 60,
endnumeric;
endif;
+
+ suppressif ideqval XhciPci.Value == 2;
+ grayoutif NOT ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_ACPI;
+ oneof varid = XhciPci.Value,
+ prompt = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT),
+ help = STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP),
+ flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_XHCI), value = 0, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), value = 1, flags = 0;
+ endoneof;
+ endif;
+ endif;
#endif
string varid = AssetTag.AssetTag,
prompt = STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT),
diff --git a/Platform/RaspberryPi/Include/ConfigVars.h b/Platform/RaspberryPi/Include/ConfigVars.h
index 142317985a..a5b32b5284 100644
--- a/Platform/RaspberryPi/Include/ConfigVars.h
+++ b/Platform/RaspberryPi/Include/ConfigVars.h
@@ -77,6 +77,10 @@ typedef struct {
} ADVANCED_FANTEMP_VARSTORE_DATA;
typedef struct {
+ UINT32 Value;
+} ADVANCED_XHCIPCI_VARSTORE_DATA;
+
+typedef struct {
#define SYSTEM_TABLE_MODE_ACPI 0
#define SYSTEM_TABLE_MODE_BOTH 1
#define SYSTEM_TABLE_MODE_DT 2
diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RPi3/RPi3.dsc
index 1c8a5408e7..6ab5d1ae6d 100644
--- a/Platform/RaspberryPi/RPi3/RPi3.dsc
+++ b/Platform/RaspberryPi/RPi3/RPi3.dsc
@@ -520,6 +520,12 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberryPiTokenSpaceGuid|0x0|0
+ # Select XHCI/PCIe mode (not valid on rpi3)
+ #
+ # 0 - DISABLED
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc
index dcf9bb5f11..babcbb2f41 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -536,6 +536,14 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberryPiTokenSpaceGuid|0x0|0
+ # Select XHCI/PCIe mode
+ #
+ # 0 - XHCI Enabled (default on !cm4)
+ # 1 - PCIe Enabled
+ # 2 - PCIe Enabled (default on cm4)
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/RaspberryPi.dec
index 2ca25ff9e6..797be59274 100644
--- a/Platform/RaspberryPi/RaspberryPi.dec
+++ b/Platform/RaspberryPi/RaspberryPi.dec
@@ -71,3 +71,4 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x0000001E
gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|0|UINT32|0x0000001F
gRaspberryPiTokenSpaceGuid.PcdUartInUse|1|UINT32|0x00000021
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000022
--
2.13.7
[-- Attachment #2: Type: text/html, Size: 14576 bytes --]
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu
2021-08-20 4:16 ` [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu Jeremy Linton
2021-08-20 20:14 ` Andrei Warkentin
@ 2021-08-20 20:31 ` Samer El-Haj-Mahmoud
1 sibling, 0 replies; 22+ messages in thread
From: Samer El-Haj-Mahmoud @ 2021-08-20 20:31 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org,
Andrei Warkentin (awarkentin@vmware.com), Sunny Wang,
Jeremy Linton, Samer El-Haj-Mahmoud
One feedback is to add the new HII setting to the README. Otherwise, looks good!
Reviewed-By: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
> -----Original Message-----
> From: Jeremy Linton <jeremy.linton@arm.com>
> Sent: Friday, August 20, 2021 12:16 AM
> To: devel@edk2.groups.io
> Cc: pete@akeo.ie; ardb+tianocore@kernel.org; Andrei Warkentin
> (awarkentin@vmware.com) <awarkentin@vmware.com>; Sunny Wang
> <Sunny.Wang@arm.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jeremy Linton <Jeremy.Linton@arm.com>
> Subject: [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu
>
> Arm has standardized a PCI SMC conduit that can be used
> to access the PCI config space in a standardized way. This
> functionality doesn't yet exist in many OS/Distro's. Lets
> add another advanced config item that allows the user
> to toggle between presenting the XHCI on the base RPi4
> as a platform device, or presenting this newer PCIe
> conduit. The CM4 doesn't have an attached XHCI controller
> soldered to the PCIe, so PCIe mode is the default.
>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 42
> ++++++++++++++++++++++
> .../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
> .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +++
> .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 +++++++++
> Platform/RaspberryPi/Include/ConfigVars.h | 4 +++
> Platform/RaspberryPi/RPi3/RPi3.dsc | 6 ++++
> Platform/RaspberryPi/RPi4/RPi4.dsc | 8 +++++
> Platform/RaspberryPi/RaspberryPi.dec | 1 +
> 8 files changed, 84 insertions(+)
>
> diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> index 9e78cb47ad..87f6b4e7bb 100644
> --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> @@ -43,6 +43,7 @@ extern UINT8 ConfigDxeStrings[];
> STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol;
> STATIC UINT32 mModelFamily = 0;
> STATIC UINT32 mModelInstalledMB = 0;
> +STATIC UINT32 mModelRevision = 0;
>
> STATIC EFI_MAC_ADDRESS mMacAddress;
>
> @@ -271,6 +272,40 @@ SetupVariables (
> ASSERT_EFI_ERROR (Status);
> }
>
> + if (mModelFamily >= 4) {
> + if (((mModelRevision >> 4) & 0xFF) == 0x14) {
> + /*
> + * Enable PCIe by default on CM4
> + */
> + Status = PcdSet32S (PcdXhciPci, 2);
> + ASSERT_EFI_ERROR (Status);
> + } else {
> + Size = sizeof (UINT32);
> + Status = gRT->GetVariable (L"XhciPci",
> + &gConfigDxeFormSetGuid,
> + NULL, &Size, &Var32);
> + if (EFI_ERROR (Status) || (Var32 == 0)) {
> + /*
> + * Enable XHCI by default
> + */
> + Status = PcdSet32S (PcdXhciPci, 0);
> + ASSERT_EFI_ERROR (Status);
> + } else {
> + /*
> + * Enable PCIe
> + */
> + Status = PcdSet32S (PcdXhciPci, 1);
> + ASSERT_EFI_ERROR (Status);
> + }
> + }
> + } else {
> + /*
> + * Disable PCIe and XHCI
> + */
> + Status = PcdSet32S (PcdXhciPci, 0);
> + ASSERT_EFI_ERROR (Status);
> + }
> +
> Size = sizeof (AssetTagVar);
> Status = gRT->GetVariable (L"AssetTag",
> &gConfigDxeFormSetGuid,
> @@ -888,6 +923,13 @@ ConfigInitialize (
> DEBUG ((DEBUG_INFO, "Current Raspberry Pi installed RAM size is %d MB\n",
> mModelInstalledMB));
> }
>
> + Status = mFwProtocol->GetModelRevision (&mModelRevision);
> + if (Status != EFI_SUCCESS) {
> + DEBUG ((DEBUG_ERROR, "Couldn't get the Raspberry Pi revision: %r\n",
> Status));
> + } else {
> + DEBUG ((DEBUG_INFO, "Current Raspberry Pi revision %x\n",
> mModelRevision));
> + }
> +
> Status = SetupVariables ();
> if (Status != EFI_SUCCESS) {
> DEBUG ((DEBUG_ERROR, "Couldn't not setup NV vars: %r\n", Status));
> diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
> b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
> index 4bb2d08550..e6e22ad82e 100644
> --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
> +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
> @@ -94,6 +94,7 @@
> gRaspberryPiTokenSpaceGuid.PcdFanOnGpio
> gRaspberryPiTokenSpaceGuid.PcdFanTemp
> gRaspberryPiTokenSpaceGuid.PcdUartInUse
> + gRaspberryPiTokenSpaceGuid.PcdXhciPci
>
> [Depex]
> gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid
> diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
> b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
> index 466fa852cb..5ec17072c3 100644
> --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
> +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
> @@ -57,6 +57,11 @@
> #string STR_ADVANCED_FANTEMP_PROMPT #language en-US "ACPI fan
> temperature"
> #string STR_ADVANCED_FANTEMP_HELP #language en-US "Cycle a fan at C"
>
> +#string STR_ADVANCED_XHCIPCI_PROMPT #language en-US "ACPI
> XHCI/PCIe"
> +#string STR_ADVANCED_XHCIPCI_HELP #language en-US "OS sees XHCI USB
> platform device or PCIe bridge"
> +#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI"
> +#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe"
> +
> #string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag"
> #string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system
> Asset Tag"
>
> diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
> b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
> index fa34eab809..18b3ec726e 100644
> --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
> +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
> @@ -56,6 +56,11 @@ formset
> name = FanTemp,
> guid = CONFIGDXE_FORM_SET_GUID;
>
> + efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA,
> + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> + name = XhciPci,
> + guid = CONFIGDXE_FORM_SET_GUID;
> +
> efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA,
> attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS |
> EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
> name = SystemTableMode,
> @@ -212,6 +217,18 @@ formset
> default = 60,
> endnumeric;
> endif;
> +
> + suppressif ideqval XhciPci.Value == 2;
> + grayoutif NOT ideqval SystemTableMode.Mode ==
> SYSTEM_TABLE_MODE_ACPI;
> + oneof varid = XhciPci.Value,
> + prompt = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT),
> + help = STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP),
> + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
> + option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_XHCI), value =
> 0, flags = DEFAULT;
> + option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), value =
> 1, flags = 0;
> + endoneof;
> + endif;
> + endif;
> #endif
> string varid = AssetTag.AssetTag,
> prompt = STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT),
> diff --git a/Platform/RaspberryPi/Include/ConfigVars.h
> b/Platform/RaspberryPi/Include/ConfigVars.h
> index 142317985a..a5b32b5284 100644
> --- a/Platform/RaspberryPi/Include/ConfigVars.h
> +++ b/Platform/RaspberryPi/Include/ConfigVars.h
> @@ -77,6 +77,10 @@ typedef struct {
> } ADVANCED_FANTEMP_VARSTORE_DATA;
>
> typedef struct {
> + UINT32 Value;
> +} ADVANCED_XHCIPCI_VARSTORE_DATA;
> +
> +typedef struct {
> #define SYSTEM_TABLE_MODE_ACPI 0
> #define SYSTEM_TABLE_MODE_BOTH 1
> #define SYSTEM_TABLE_MODE_DT 2
> diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc
> b/Platform/RaspberryPi/RPi3/RPi3.dsc
> index 1c8a5408e7..6ab5d1ae6d 100644
> --- a/Platform/RaspberryPi/RPi3/RPi3.dsc
> +++ b/Platform/RaspberryPi/RPi3/RPi3.dsc
> @@ -520,6 +520,12 @@
>
>
> gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberr
> yPiTokenSpaceGuid|0x0|0
>
> + # Select XHCI/PCIe mode (not valid on rpi3)
> + #
> + # 0 - DISABLED
> + #
> +
> gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0
> x0|0
> +
> #
> # Common UEFI ones.
> #
> diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc
> b/Platform/RaspberryPi/RPi4/RPi4.dsc
> index dcf9bb5f11..babcbb2f41 100644
> --- a/Platform/RaspberryPi/RPi4/RPi4.dsc
> +++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
> @@ -536,6 +536,14 @@
>
>
> gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberr
> yPiTokenSpaceGuid|0x0|0
>
> + # Select XHCI/PCIe mode
> + #
> + # 0 - XHCI Enabled (default on !cm4)
> + # 1 - PCIe Enabled
> + # 2 - PCIe Enabled (default on cm4)
> + #
> +
> gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0
> x0|0
> +
> #
> # Common UEFI ones.
> #
> diff --git a/Platform/RaspberryPi/RaspberryPi.dec
> b/Platform/RaspberryPi/RaspberryPi.dec
> index 2ca25ff9e6..797be59274 100644
> --- a/Platform/RaspberryPi/RaspberryPi.dec
> +++ b/Platform/RaspberryPi/RaspberryPi.dec
> @@ -71,3 +71,4 @@
> gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x0000001E
> gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|0|UINT32|0x0000001F
> gRaspberryPiTokenSpaceGuid.PcdUartInUse|1|UINT32|0x00000021
> + gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000022
> --
> 2.13.7
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 2/7] Platform/RaspberryPi: Break XHCI into its own SSDT
2021-08-20 4:16 [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Jeremy Linton
2021-08-20 4:16 ` [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu Jeremy Linton
@ 2021-08-20 4:16 ` Jeremy Linton
2021-08-20 20:15 ` Andrei Warkentin
2021-08-20 4:16 ` [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT Jeremy Linton
` (5 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Jeremy Linton @ 2021-08-20 4:16 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
Lets prepare to switch between XHCI and PCI by moving
the XHCI definition into its own SSDT. That way we can
select it based on the menu settings. The resource
producer/consumer flag is also corrected.
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 --
Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 ++++++++++++++--------
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 8 +++++
4 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index 1ddc9ca5fe..f3e8d950c1 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -38,6 +38,7 @@
SpcrPl011.aslc
Pptt.aslc
SsdtThermal.asl
+ Xhci.asl
[Packages]
ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
index 1ee6379f46..b594d50bdf 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
Scope (\_SB_)
{
include ("Pep.asl")
-#if (RPI_MODEL == 4)
- include ("Xhci.asl")
-#endif
Device (CPU0)
{
diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryPi/AcpiTables/Xhci.asl
index bc3fea60f9..9b37277956 100644
--- a/Platform/RaspberryPi/AcpiTables/Xhci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl
@@ -9,6 +9,8 @@
#include <IndustryStandard/Bcm2711.h>
+#include "AcpiTables.h"
+
/*
* The following can be used to remove parenthesis from
* defined macros that the compiler complains about.
@@ -24,12 +26,17 @@
*/
#define XHCI_REG_LENGTH 0x1000
-Device (SCB0) {
- Name (_HID, "ACPI0004")
- Name (_UID, 0x0)
- Name (_CCA, 0x0)
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
- Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+ Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
/*
* Container devices with _DMA must have _CRS, meaning SCB0
* to provide all resources that XHC0 consumes (except
@@ -57,15 +64,15 @@ Device (SCB0) {
Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
Return (RBUF)
- }
+ }
- Name (_DMA, ResourceTemplate() {
+ Name (_DMA, ResourceTemplate() {
/*
* XHC0 is limited to DMA to first 3GB. Note this
* only applies to PCIe, not GENET or other devices
* next to the A72.
*/
- QWordMemory (ResourceConsumer,
+ QWordMemory (ResourceProducer,
,
MinFixed,
MaxFixed,
@@ -79,10 +86,10 @@ Device (SCB0) {
,
,
)
- })
+ })
- Device (XHC0)
- {
+ Device (XHC0)
+ {
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x0) // _UID: Unique ID
Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute
@@ -131,5 +138,7 @@ Device (SCB0) {
Debug = "xHCI enable"
Store (0x6, CMND)
}
- }
-}
+ } // end XHC0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 87f6b4e7bb..7c5786303d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdSdIsArasan),
SsdtEmmcNameOpReplace
},
+#if (RPI_MODEL == 4)
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'),
+ 0,
+ PcdToken(PcdXhciPci),
+ NULL
+ },
+#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
0,
--
2.13.7
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 2/7] Platform/RaspberryPi: Break XHCI into its own SSDT
2021-08-20 4:16 ` [PATCH v3 2/7] Platform/RaspberryPi: Break XHCI into its own SSDT Jeremy Linton
@ 2021-08-20 20:15 ` Andrei Warkentin
0 siblings, 0 replies; 22+ messages in thread
From: Andrei Warkentin @ 2021-08-20 20:15 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com
[-- Attachment #1: Type: text/plain, Size: 4953 bytes --]
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
________________________________
From: Jeremy Linton <jeremy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH v3 2/7] Platform/RaspberryPi: Break XHCI into its own SSDT
Lets prepare to switch between XHCI and PCI by moving
the XHCI definition into its own SSDT. That way we can
select it based on the menu settings. The resource
producer/consumer flag is also corrected.
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 --
Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 ++++++++++++++--------
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 8 +++++
4 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index 1ddc9ca5fe..f3e8d950c1 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -38,6 +38,7 @@
SpcrPl011.aslc
Pptt.aslc
SsdtThermal.asl
+ Xhci.asl
[Packages]
ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
index 1ee6379f46..b594d50bdf 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
Scope (\_SB_)
{
include ("Pep.asl")
-#if (RPI_MODEL == 4)
- include ("Xhci.asl")
-#endif
Device (CPU0)
{
diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryPi/AcpiTables/Xhci.asl
index bc3fea60f9..9b37277956 100644
--- a/Platform/RaspberryPi/AcpiTables/Xhci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl
@@ -9,6 +9,8 @@
#include <IndustryStandard/Bcm2711.h>
+#include "AcpiTables.h"
+
/*
* The following can be used to remove parenthesis from
* defined macros that the compiler complains about.
@@ -24,12 +26,17 @@
*/
#define XHCI_REG_LENGTH 0x1000
-Device (SCB0) {
- Name (_HID, "ACPI0004")
- Name (_UID, 0x0)
- Name (_CCA, 0x0)
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
- Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+ Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
/*
* Container devices with _DMA must have _CRS, meaning SCB0
* to provide all resources that XHC0 consumes (except
@@ -57,15 +64,15 @@ Device (SCB0) {
Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
Return (RBUF)
- }
+ }
- Name (_DMA, ResourceTemplate() {
+ Name (_DMA, ResourceTemplate() {
/*
* XHC0 is limited to DMA to first 3GB. Note this
* only applies to PCIe, not GENET or other devices
* next to the A72.
*/
- QWordMemory (ResourceConsumer,
+ QWordMemory (ResourceProducer,
,
MinFixed,
MaxFixed,
@@ -79,10 +86,10 @@ Device (SCB0) {
,
,
)
- })
+ })
- Device (XHC0)
- {
+ Device (XHC0)
+ {
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x0) // _UID: Unique ID
Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute
@@ -131,5 +138,7 @@ Device (SCB0) {
Debug = "xHCI enable"
Store (0x6, CMND)
}
- }
-}
+ } // end XHC0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 87f6b4e7bb..7c5786303d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdSdIsArasan),
SsdtEmmcNameOpReplace
},
+#if (RPI_MODEL == 4)
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'),
+ 0,
+ PcdToken(PcdXhciPci),
+ NULL
+ },
+#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
0,
--
2.13.7
[-- Attachment #2: Type: text/html, Size: 8908 bytes --]
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT
2021-08-20 4:16 [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Jeremy Linton
2021-08-20 4:16 ` [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu Jeremy Linton
2021-08-20 4:16 ` [PATCH v3 2/7] Platform/RaspberryPi: Break XHCI into its own SSDT Jeremy Linton
@ 2021-08-20 4:16 ` Jeremy Linton
2021-08-20 20:15 ` Andrei Warkentin
2021-08-20 4:16 ` [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction Jeremy Linton
` (4 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Jeremy Linton @ 2021-08-20 4:16 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port on a machine without
a MCFG it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
Platform/RaspberryPi/AcpiTables/Pci.asl | 161 +++++++++++++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
3 files changed, 170 insertions(+)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+ Pci.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..dc2bd7bc9e
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,161 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...) __VA_ARGS__
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+ Scope (\_SB_)
+ {
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ Package (4) { 0x0000FFFF, 0, zero, 175 },
+ Package (4) { 0x0000FFFF, 1, zero, 176 },
+ Package (4) { 0x0000FFFF, 2, zero, 177 },
+ Package (4) { 0x0000FFFF, 3, zero, 178 }
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+
+ // bus numbers assigned to this root
+ WordBusNumber (
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ // 32-bit mmio window in 64-bit addr
+ QWordMemory (
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable
+ 0x00000000, // Granularity
+ 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
+ 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+ 2 // SANITIZED_PCIE_MMIO_LEN + 1
+ ,,,MMI1,,TypeTranslation
+ )
+
+ // root port registers, not to be used if SMCCC is utilized
+ QWordMemory (
+ ResourceConsumer, ,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable
+ 0x00000000, // Granularity
+ 0xFD500000, // Root port begin
+ 0xFD509FFF, // Root port end
+ 0x00000000, // no translation
+ 0x0000A000, // size
+ ,,
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+
+ // OS Control Handoff
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdXhciPci),
NULL
},
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+ PcdToken(PcdXhciPci),
+ 0,
+ NULL
+ },
#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT
2021-08-20 4:16 ` [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT Jeremy Linton
@ 2021-08-20 20:15 ` Andrei Warkentin
0 siblings, 0 replies; 22+ messages in thread
From: Andrei Warkentin @ 2021-08-20 20:15 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com
[-- Attachment #1: Type: text/plain, Size: 8925 bytes --]
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
________________________________
From: Jeremy Linton <jeremy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT
Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port on a machine without
a MCFG it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
Platform/RaspberryPi/AcpiTables/Pci.asl | 161 +++++++++++++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
3 files changed, 170 insertions(+)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+ Pci.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..dc2bd7bc9e
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,161 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...) __VA_ARGS__
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+ Scope (\_SB_)
+ {
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ Package (4) { 0x0000FFFF, 0, zero, 175 },
+ Package (4) { 0x0000FFFF, 1, zero, 176 },
+ Package (4) { 0x0000FFFF, 2, zero, 177 },
+ Package (4) { 0x0000FFFF, 3, zero, 178 }
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+
+ // bus numbers assigned to this root
+ WordBusNumber (
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ // 32-bit mmio window in 64-bit addr
+ QWordMemory (
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable
+ 0x00000000, // Granularity
+ 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
+ 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+ 2 // SANITIZED_PCIE_MMIO_LEN + 1
+ ,,,MMI1,,TypeTranslation
+ )
+
+ // root port registers, not to be used if SMCCC is utilized
+ QWordMemory (
+ ResourceConsumer, ,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable
+ 0x00000000, // Granularity
+ 0xFD500000, // Root port begin
+ 0xFD509FFF, // Root port end
+ 0x00000000, // no translation
+ 0x0000A000, // size
+ ,,
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+
+ // OS Control Handoff
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdXhciPci),
NULL
},
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+ PcdToken(PcdXhciPci),
+ 0,
+ NULL
+ },
#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7
[-- Attachment #2: Type: text/html, Size: 17443 bytes --]
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction
2021-08-20 4:16 [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Jeremy Linton
` (2 preceding siblings ...)
2021-08-20 4:16 ` [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT Jeremy Linton
@ 2021-08-20 4:16 ` Jeremy Linton
2021-08-20 20:16 ` Andrei Warkentin
2021-08-20 4:16 ` [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor Jeremy Linton
` (3 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Jeremy Linton @ 2021-08-20 4:16 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton, René Treffer
The CM4 has an actual PCIe slot, so the device filtering
need to be a little less restrictive WRT busses with more
than 1 device given that switches can now appear in the
topology. Since it is possible to start numbering the
busses with a non-zero value, the bus restriction should
be based on the secondary side of the root port. This
isn't likely but its better than hard-coding the limit.
Suggested-by: René Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..6d15e82fa2 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -19,6 +19,7 @@
#include <Library/PciSegmentLib.h>
#include <Library/UefiLib.h>
#include <IndustryStandard/Bcm2711.h>
+#include <IndustryStandard/Pci30.h>
typedef enum {
PciCfgWidthUint8 = 0,
@@ -78,6 +79,9 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;
+ UINT32 HostPortSec;
Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +93,20 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+ HostPortSec = MmioRead8 (PCIE_REG_BASE +
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+
/*
- * Scan things out directly rather than translating the "bus" to a device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus <= HostPortSec)) {
return 0xFFFFFFFF;
}
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction
2021-08-20 4:16 ` [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction Jeremy Linton
@ 2021-08-20 20:16 ` Andrei Warkentin
0 siblings, 0 replies; 22+ messages in thread
From: Andrei Warkentin @ 2021-08-20 20:16 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com, René Treffer
[-- Attachment #1: Type: text/plain, Size: 3243 bytes --]
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
________________________________
From: Jeremy Linton <jeremy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>; René Treffer <treffer+groups.io@measite.de>
Subject: [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction
The CM4 has an actual PCIe slot, so the device filtering
need to be a little less restrictive WRT busses with more
than 1 device given that switches can now appear in the
topology. Since it is possible to start numbering the
busses with a non-zero value, the bus restriction should
be based on the secondary side of the root port. This
isn't likely but its better than hard-coding the limit.
Suggested-by: René Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..6d15e82fa2 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -19,6 +19,7 @@
#include <Library/PciSegmentLib.h>
#include <Library/UefiLib.h>
#include <IndustryStandard/Bcm2711.h>
+#include <IndustryStandard/Pci30.h>
typedef enum {
PciCfgWidthUint8 = 0,
@@ -78,6 +79,9 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;
+ UINT32 HostPortSec;
Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +93,20 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+ HostPortSec = MmioRead8 (PCIE_REG_BASE +
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+
/*
- * Scan things out directly rather than translating the "bus" to a device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus <= HostPortSec)) {
return 0xFFFFFFFF;
}
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7
[-- Attachment #2: Type: text/html, Size: 5645 bytes --]
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor
2021-08-20 4:16 [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Jeremy Linton
` (3 preceding siblings ...)
2021-08-20 4:16 ` [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction Jeremy Linton
@ 2021-08-20 4:16 ` Jeremy Linton
2021-08-20 20:16 ` Andrei Warkentin
2021-08-22 13:37 ` Ard Biesheuvel
2021-08-20 4:16 ` [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4 Jeremy Linton
` (2 subsequent siblings)
7 siblings, 2 replies; 22+ messages in thread
From: Jeremy Linton @ 2021-08-20 4:16 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
The existing code fails to create/finish configuring the
pcie subsystem if it fails to get a linkup. This is reasonable
on the RPi4 because it generally won't happen, and the OS
could not see the root port. Now that the OS can see the
root port, its a bit odd if it only shows up when
something is plugged into the first slot. Lets move the
link up check into the config accessor where it will be used
to restrict sending CFG TLP's out the port when nothing is
plugged in. Thus avoiding a SERROR during probe.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 -----
.../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++++++
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
- if ((Data & 0x30) != 0x30) {
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
- return EFI_DEVICE_ERROR;
- }
-
if ((Data & 0x80) != 0x80) {
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 6d15e82fa2..b627e5730b 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase (
return 0xFFFFFFFF;
}
+ /* Don't probe slots if the link is down */
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((Data & 0x30) != 0x30) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+ return 0xFFFFFFFF;
+ }
+
MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
mPciSegmentLastAccess = Address;
}
--
2.13.7
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor
2021-08-20 4:16 ` [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor Jeremy Linton
@ 2021-08-20 20:16 ` Andrei Warkentin
2021-08-22 13:37 ` Ard Biesheuvel
1 sibling, 0 replies; 22+ messages in thread
From: Andrei Warkentin @ 2021-08-20 20:16 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com
[-- Attachment #1: Type: text/plain, Size: 3161 bytes --]
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
________________________________
From: Jeremy Linton <jeremy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor
The existing code fails to create/finish configuring the
pcie subsystem if it fails to get a linkup. This is reasonable
on the RPi4 because it generally won't happen, and the OS
could not see the root port. Now that the OS can see the
root port, its a bit odd if it only shows up when
something is plugged into the first slot. Lets move the
link up check into the config accessor where it will be used
to restrict sending CFG TLP's out the port when nothing is
plugged in. Thus avoiding a SERROR during probe.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 -----
.../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++++++
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
- if ((Data & 0x30) != 0x30) {
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
- return EFI_DEVICE_ERROR;
- }
-
if ((Data & 0x80) != 0x80) {
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 6d15e82fa2..b627e5730b 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase (
return 0xFFFFFFFF;
}
+ /* Don't probe slots if the link is down */
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((Data & 0x30) != 0x30) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+ return 0xFFFFFFFF;
+ }
+
MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
mPciSegmentLastAccess = Address;
}
--
2.13.7
[-- Attachment #2: Type: text/html, Size: 4785 bytes --]
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor
2021-08-20 4:16 ` [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor Jeremy Linton
2021-08-20 20:16 ` Andrei Warkentin
@ 2021-08-22 13:37 ` Ard Biesheuvel
2021-08-22 13:47 ` Ard Biesheuvel
1 sibling, 1 reply; 22+ messages in thread
From: Ard Biesheuvel @ 2021-08-22 13:37 UTC (permalink / raw)
To: Jeremy Linton
Cc: edk2-devel-groups-io, Peter Batard, Ard Biesheuvel,
Andrei Warkentin, Sunny Wang, Samer El-Haj-Mahmoud
On Fri, 20 Aug 2021 at 06:16, Jeremy Linton <jeremy.linton@arm.com> wrote:
>
> The existing code fails to create/finish configuring the
> pcie subsystem if it fails to get a linkup. This is reasonable
> on the RPi4 because it generally won't happen, and the OS
> could not see the root port. Now that the OS can see the
> root port, its a bit odd if it only shows up when
> something is plugged into the first slot. Lets move the
> link up check into the config accessor where it will be used
> to restrict sending CFG TLP's out the port when nothing is
> plugged in. Thus avoiding a SERROR during probe.
>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
How will this work when the PCIE/XHCI switch is in 'platform device' mode?
> ---
> .../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 -----
> .../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++++++
> 2 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> index 8587d2d36d..4d4c584726 100644
> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
> } while (((Data & 0x30) != 0x030) && (Timeout));
> DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
>
> - if ((Data & 0x30) != 0x30) {
> - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> - return EFI_DEVICE_ERROR;
> - }
> -
> if ((Data & 0x80) != 0x80) {
> DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
> return EFI_UNSUPPORTED;
> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> index 6d15e82fa2..b627e5730b 100644
> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> @@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase (
> return 0xFFFFFFFF;
> }
>
> + /* Don't probe slots if the link is down */
> + Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
> + if ((Data & 0x30) != 0x30) {
> + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> + return 0xFFFFFFFF;
> + }
> +
> MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
> mPciSegmentLastAccess = Address;
> }
> --
> 2.13.7
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor
2021-08-22 13:37 ` Ard Biesheuvel
@ 2021-08-22 13:47 ` Ard Biesheuvel
0 siblings, 0 replies; 22+ messages in thread
From: Ard Biesheuvel @ 2021-08-22 13:47 UTC (permalink / raw)
To: Jeremy Linton
Cc: edk2-devel-groups-io, Peter Batard, Ard Biesheuvel,
Andrei Warkentin, Sunny Wang, Samer El-Haj-Mahmoud
On Sun, 22 Aug 2021 at 15:37, Ard Biesheuvel <ardb@kernel.org> wrote:
>
> On Fri, 20 Aug 2021 at 06:16, Jeremy Linton <jeremy.linton@arm.com> wrote:
> >
> > The existing code fails to create/finish configuring the
> > pcie subsystem if it fails to get a linkup. This is reasonable
> > on the RPi4 because it generally won't happen, and the OS
> > could not see the root port. Now that the OS can see the
> > root port, its a bit odd if it only shows up when
> > something is plugged into the first slot. Lets move the
> > link up check into the config accessor where it will be used
> > to restrict sending CFG TLP's out the port when nothing is
> > plugged in. Thus avoiding a SERROR during probe.
> >
> > Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>
> How will this work when the PCIE/XHCI switch is in 'platform device' mode?
>
Never mind, that only affects the OS whereas this affects UEFI itself only.
> > ---
> > .../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 -----
> > .../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++++++
> > 2 files changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> > index 8587d2d36d..4d4c584726 100644
> > --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> > +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> > @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
> > } while (((Data & 0x30) != 0x030) && (Timeout));
> > DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
> >
> > - if ((Data & 0x30) != 0x30) {
> > - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> > - return EFI_DEVICE_ERROR;
> > - }
> > -
> > if ((Data & 0x80) != 0x80) {
> > DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
> > return EFI_UNSUPPORTED;
> > diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> > index 6d15e82fa2..b627e5730b 100644
> > --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> > +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> > @@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase (
> > return 0xFFFFFFFF;
> > }
> >
> > + /* Don't probe slots if the link is down */
> > + Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
> > + if ((Data & 0x30) != 0x30) {
> > + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> > + return 0xFFFFFFFF;
> > + }
> > +
> > MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
> > mPciSegmentLastAccess = Address;
> > }
> > --
> > 2.13.7
> >
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4
2021-08-20 4:16 [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Jeremy Linton
` (4 preceding siblings ...)
2021-08-20 4:16 ` [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor Jeremy Linton
@ 2021-08-20 4:16 ` Jeremy Linton
2021-08-20 20:16 ` Andrei Warkentin
2021-08-20 20:37 ` Samer El-Haj-Mahmoud
2021-08-20 4:16 ` [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support Jeremy Linton
2021-08-20 20:27 ` [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Samer El-Haj-Mahmoud
7 siblings, 2 replies; 22+ messages in thread
From: Jeremy Linton @ 2021-08-20 4:16 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
The CM4 has a number of carrier boards with PCIe
slots. With the PCIe changes in place its quite
possible to utilize a NVMe root device. Lets allow
people to boot from it.
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/RPi4/RPi4.dsc | 5 +++++
Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc
index babcbb2f41..25c29a0fbf 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -754,6 +754,11 @@
}
#
+ # NVMe boot devices
+ #
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
# UEFI application (Shell Embedded Boot Loader)
#
ShellPkg/Application/Shell/Shell.inf {
diff --git a/Platform/RaspberryPi/RPi4/RPi4.fdf b/Platform/RaspberryPi/RPi4/RPi4.fdf
index 3534cd3dc3..0c782d2f35 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.fdf
+++ b/Platform/RaspberryPi/RPi4/RPi4.fdf
@@ -283,6 +283,11 @@ READ_LOCK_STATUS = TRUE
INF EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf
#
+ # NVMe boot devices
+ #
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
# SCSI Bus and Disk Driver
#
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
--
2.13.7
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4
2021-08-20 4:16 ` [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4 Jeremy Linton
@ 2021-08-20 20:16 ` Andrei Warkentin
2021-08-20 20:37 ` Samer El-Haj-Mahmoud
1 sibling, 0 replies; 22+ messages in thread
From: Andrei Warkentin @ 2021-08-20 20:16 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com
[-- Attachment #1: Type: text/plain, Size: 1975 bytes --]
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
________________________________
From: Jeremy Linton <jeremy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4
The CM4 has a number of carrier boards with PCIe
slots. With the PCIe changes in place its quite
possible to utilize a NVMe root device. Lets allow
people to boot from it.
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/RPi4/RPi4.dsc | 5 +++++
Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc
index babcbb2f41..25c29a0fbf 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -754,6 +754,11 @@
}
#
+ # NVMe boot devices
+ #
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
# UEFI application (Shell Embedded Boot Loader)
#
ShellPkg/Application/Shell/Shell.inf {
diff --git a/Platform/RaspberryPi/RPi4/RPi4.fdf b/Platform/RaspberryPi/RPi4/RPi4.fdf
index 3534cd3dc3..0c782d2f35 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.fdf
+++ b/Platform/RaspberryPi/RPi4/RPi4.fdf
@@ -283,6 +283,11 @@ READ_LOCK_STATUS = TRUE
INF EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf
#
+ # NVMe boot devices
+ #
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
# SCSI Bus and Disk Driver
#
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
--
2.13.7
[-- Attachment #2: Type: text/html, Size: 3192 bytes --]
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4
2021-08-20 4:16 ` [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4 Jeremy Linton
2021-08-20 20:16 ` Andrei Warkentin
@ 2021-08-20 20:37 ` Samer El-Haj-Mahmoud
1 sibling, 0 replies; 22+ messages in thread
From: Samer El-Haj-Mahmoud @ 2021-08-20 20:37 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org,
Andrei Warkentin (awarkentin@vmware.com), Sunny Wang,
Jeremy Linton, Samer El-Haj-Mahmoud
Reviewed-By: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
> -----Original Message-----
> From: Jeremy Linton <jeremy.linton@arm.com>
> Sent: Friday, August 20, 2021 12:16 AM
> To: devel@edk2.groups.io
> Cc: pete@akeo.ie; ardb+tianocore@kernel.org; Andrei Warkentin
> (awarkentin@vmware.com) <awarkentin@vmware.com>; Sunny Wang
> <Sunny.Wang@arm.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jeremy Linton <Jeremy.Linton@arm.com>
> Subject: [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4
>
> The CM4 has a number of carrier boards with PCIe
> slots. With the PCIe changes in place its quite
> possible to utilize a NVMe root device. Lets allow
> people to boot from it.
>
> Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> Platform/RaspberryPi/RPi4/RPi4.dsc | 5 +++++
> Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc
> b/Platform/RaspberryPi/RPi4/RPi4.dsc
> index babcbb2f41..25c29a0fbf 100644
> --- a/Platform/RaspberryPi/RPi4/RPi4.dsc
> +++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
> @@ -754,6 +754,11 @@
> }
>
> #
> + # NVMe boot devices
> + #
> + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> + #
> # UEFI application (Shell Embedded Boot Loader)
> #
> ShellPkg/Application/Shell/Shell.inf {
> diff --git a/Platform/RaspberryPi/RPi4/RPi4.fdf
> b/Platform/RaspberryPi/RPi4/RPi4.fdf
> index 3534cd3dc3..0c782d2f35 100644
> --- a/Platform/RaspberryPi/RPi4/RPi4.fdf
> +++ b/Platform/RaspberryPi/RPi4/RPi4.fdf
> @@ -283,6 +283,11 @@ READ_LOCK_STATUS = TRUE
> INF
> EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.i
> nf
>
> #
> + # NVMe boot devices
> + #
> + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> + #
> # SCSI Bus and Disk Driver
> #
> INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> --
> 2.13.7
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support
2021-08-20 4:16 [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Jeremy Linton
` (5 preceding siblings ...)
2021-08-20 4:16 ` [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4 Jeremy Linton
@ 2021-08-20 4:16 ` Jeremy Linton
2021-08-20 20:15 ` Andrei Warkentin
2021-08-20 20:35 ` Samer El-Haj-Mahmoud
2021-08-20 20:27 ` [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Samer El-Haj-Mahmoud
7 siblings, 2 replies; 22+ messages in thread
From: Jeremy Linton @ 2021-08-20 4:16 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
Linux, for the time being has refused to support the Arm
standard SMCCC for PCIe configuration. Instead they
want to continue to maintain per device "quirks".
As the RPI isn't really ECAM this is a bit more
involved because the MCFG can't really describe
the root port+config registers situation. Further
platforms which support the SMCCC shouldn't have
a MCFG, so we need an additional way to tell linux
what it needs to know about this platform.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/Pci.asl | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
index dc2bd7bc9e..50fe2cbdf2 100644
--- a/Platform/RaspberryPi/AcpiTables/Pci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -62,6 +62,13 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
Package (4) { 0x0000FFFF, 3, zero, 178 }
})
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "linux-ecam-quirk-id", "bcm2711" },
+ }
+ })
+
// Root complex resources
Method (_CRS, 0, Serialized) {
Name (RBUF, ResourceTemplate () {
--
2.13.7
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support
2021-08-20 4:16 ` [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support Jeremy Linton
@ 2021-08-20 20:15 ` Andrei Warkentin
2021-08-20 20:35 ` Samer El-Haj-Mahmoud
1 sibling, 0 replies; 22+ messages in thread
From: Andrei Warkentin @ 2021-08-20 20:15 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com
[-- Attachment #1: Type: text/plain, Size: 1891 bytes --]
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
________________________________
From: Jeremy Linton <jeremy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support
Linux, for the time being has refused to support the Arm
standard SMCCC for PCIe configuration. Instead they
want to continue to maintain per device "quirks".
As the RPI isn't really ECAM this is a bit more
involved because the MCFG can't really describe
the root port+config registers situation. Further
platforms which support the SMCCC shouldn't have
a MCFG, so we need an additional way to tell linux
what it needs to know about this platform.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/Pci.asl | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
index dc2bd7bc9e..50fe2cbdf2 100644
--- a/Platform/RaspberryPi/AcpiTables/Pci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -62,6 +62,13 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
Package (4) { 0x0000FFFF, 3, zero, 178 }
})
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "linux-ecam-quirk-id", "bcm2711" },
+ }
+ })
+
// Root complex resources
Method (_CRS, 0, Serialized) {
Name (RBUF, ResourceTemplate () {
--
2.13.7
[-- Attachment #2: Type: text/html, Size: 3371 bytes --]
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support
2021-08-20 4:16 ` [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support Jeremy Linton
2021-08-20 20:15 ` Andrei Warkentin
@ 2021-08-20 20:35 ` Samer El-Haj-Mahmoud
1 sibling, 0 replies; 22+ messages in thread
From: Samer El-Haj-Mahmoud @ 2021-08-20 20:35 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org,
Andrei Warkentin (awarkentin@vmware.com), Sunny Wang,
Jeremy Linton, Samer El-Haj-Mahmoud
Reviewed-By: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
> -----Original Message-----
> From: Jeremy Linton <jeremy.linton@arm.com>
> Sent: Friday, August 20, 2021 12:16 AM
> To: devel@edk2.groups.io
> Cc: pete@akeo.ie; ardb+tianocore@kernel.org; Andrei Warkentin
> (awarkentin@vmware.com) <awarkentin@vmware.com>; Sunny Wang
> <Sunny.Wang@arm.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jeremy Linton <Jeremy.Linton@arm.com>
> Subject: [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support
>
> Linux, for the time being has refused to support the Arm
> standard SMCCC for PCIe configuration. Instead they
> want to continue to maintain per device "quirks".
>
> As the RPI isn't really ECAM this is a bit more
> involved because the MCFG can't really describe
> the root port+config registers situation. Further
> platforms which support the SMCCC shouldn't have
> a MCFG, so we need an additional way to tell linux
> what it needs to know about this platform.
>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> Platform/RaspberryPi/AcpiTables/Pci.asl | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl
> b/Platform/RaspberryPi/AcpiTables/Pci.asl
> index dc2bd7bc9e..50fe2cbdf2 100644
> --- a/Platform/RaspberryPi/AcpiTables/Pci.asl
> +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
> @@ -62,6 +62,13 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN",
> "RPI4PCIE", 2)
> Package (4) { 0x0000FFFF, 3, zero, 178 }
> })
>
> + Name (_DSD, Package () {
> + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
> + Package () {
> + Package () { "linux-ecam-quirk-id", "bcm2711" },
> + }
> + })
> +
> // Root complex resources
> Method (_CRS, 0, Serialized) {
> Name (RBUF, ResourceTemplate () {
> --
> 2.13.7
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit
2021-08-20 4:16 [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Jeremy Linton
` (6 preceding siblings ...)
2021-08-20 4:16 ` [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support Jeremy Linton
@ 2021-08-20 20:27 ` Samer El-Haj-Mahmoud
[not found] ` <7d39c23-6578-6bb9-ab5f-9d242d7ff42d@invisible.ca>
7 siblings, 1 reply; 22+ messages in thread
From: Samer El-Haj-Mahmoud @ 2021-08-20 20:27 UTC (permalink / raw)
To: Jeremy Linton, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org,
Andrei Warkentin (awarkentin@vmware.com), Sunny Wang,
Jeremy Linton, Jared McNeill, Samer El-Haj-Mahmoud
+Jared to review/test the series with NetBSD 10, which supports the DEN0115 interface (https://www.netbsd.org/changes/changes-10.0.html#port-evbarm)
> -----Original Message-----
> From: Jeremy Linton <jeremy.linton@arm.com>
> Sent: Friday, August 20, 2021 12:16 AM
> To: devel@edk2.groups.io
> Cc: pete@akeo.ie; ardb+tianocore@kernel.org; Andrei Warkentin
> (awarkentin@vmware.com) <awarkentin@vmware.com>; Sunny Wang
> <Sunny.Wang@arm.com>; Samer El-Haj-Mahmoud <Samer.El-Haj-
> Mahmoud@arm.com>; Jeremy Linton <Jeremy.Linton@arm.com>
> Subject: [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit
>
> A new Arm standard DEN0115A specifies how platforms that don't have
> standard ECAM can use the firmware to handle config read/write
> operations. This is mostly implemented in TFA but UEFI needs to assure
> that there is a description of the root complex in the ACPI namespace.
>
> This set adds that description based on a new menu item which toggles
> between XHCI platform description and PCIe via a BDS menu selection on
> the RPi4. The CM4 is really the platform that needs this as it has a
> PCIe slot. On that platform PCIe is enabled by default.
>
> v2->v3:
> Remove ACPI0004 container around PCI root bridge along with some
> whitespace/tweaks to the Pci.asl file.
> Add Linux quirk _DSD patch at the end.
>
> v1->v2:
> Use global shared interrupts in PCI PRT which is a pretty
> significant simplification.
> Modify bus max to use the secondary side of the root port for
> enforcing device limits
> Various other AML cleanups per Ard (drop redundant _DMA, bump UID
> to make it unique, etc)
> Break link status move into its own patch
> MADT->MCFG typos in various comments
> Commit message tweaking
>
> Jeremy Linton (7):
> Platform/RaspberryPi: Add XHCI/PCI selection menu
> Platform/RaspberryPi: Break XHCI into its own SSDT
> Platform/RaspberryPi: Add PCIe SSDT
> Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction
> Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor
> Platform/RaspberryPi: Enable NVMe boot on CM4
> Platform/RaspberryPi: Add Linux quirk support
>
> Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 4 +
> Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 -
> Platform/RaspberryPi/AcpiTables/Pci.asl | 168
> +++++++++++++++++++++
> Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 +++--
> Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 56 +++++++
> .../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
> .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +
> .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 +++
> Platform/RaspberryPi/Include/ConfigVars.h | 4 +
> Platform/RaspberryPi/RPi3/RPi3.dsc | 6 +
> Platform/RaspberryPi/RPi4/RPi4.dsc | 13 ++
> Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +
> Platform/RaspberryPi/RaspberryPi.dec | 1 +
> .../Bcm2711PciHostBridgeLibConstructor.c | 5 -
> .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 28 +++-
> 15 files changed, 323 insertions(+), 28 deletions(-)
> create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
>
> --
> 2.13.7
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply [flat|nested] 22+ messages in thread