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boundary="_000_PH0PR05MB870234EF953DA09650BDBD86B9C19PH0PR05MB8702namp_" --_000_PH0PR05MB870234EF953DA09650BDBD86B9C19PH0PR05MB8702namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Andrei Warkentin ________________________________ From: Jeremy Linton Sent: Thursday, August 19, 2021 11:16 PM To: devel@edk2.groups.io Cc: pete@akeo.ie ; ardb+tianocore@kernel.org ; Andrei Warkentin ; Sunny.Wang@arm.com <= Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com ; Jeremy Linton Subject: [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT Since we plan on toggling between XHCI and PCI the PCI root needs to be in its own SSDT. This is all thats needed of UEFI. The SMC conduit is provided directly to the running OS. When the OS detects this PCIe port on a machine without a MCFG it attempts to connect to the SMC conduit. The RPi definition doesn't have any power mgmt, and only provides a description of the root port. Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 + Platform/RaspberryPi/AcpiTables/Pci.asl | 161 +++++++++++++++++= ++++ Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 + 3 files changed, 170 insertions(+) create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf index f3e8d950c1..da2a6db85f 100644 --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf @@ -39,6 +39,7 @@ Pptt.aslc SsdtThermal.asl Xhci.asl + Pci.asl [Packages] ArmPkg/ArmPkg.dec @@ -59,6 +60,8 @@ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicDistributorBase gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi= /AcpiTables/Pci.asl new file mode 100644 index 0000000000..dc2bd7bc9e --- /dev/null +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl @@ -0,0 +1,161 @@ +/** @file + * + * Copyright (c) 2019 Linaro, Limited. All rights reserved. + * Copyright (c) 2021 Arm + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include "AcpiTables.h" + +/* + * The following can be used to remove parenthesis from + * defined macros that the compiler complains about. + */ +#define ISOLATE_ARGS(...) __VA_ARGS__ +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x + +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_W= INDOW) +#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMI= O_LEN) +#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM= _WIN) + +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2) +{ + Scope (\_SB_) + { + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_CCA, 0) // Mark the PCI noncoherent + + // PCIe can only DMA to first 3GB with early SOC's + // But we keep the restriction on the later ones + // To avoid DMA translation problems. + Name (_DMA, ResourceTemplate() { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + // PCI Routing Table + Name(_PRT, Package() { + Package (4) { 0x0000FFFF, 0, zero, 175 }, + Package (4) { 0x0000FFFF, 1, zero, 176 }, + Package (4) { 0x0000FFFF, 2, zero, 177 }, + Package (4) { 0x0000FFFF, 3, zero, 178 } + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + + // bus numbers assigned to this root + WordBusNumber ( + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + // 32-bit mmio window in 64-bit addr + QWordMemory ( + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + NonCacheable, ReadWrite, // cacheable + 0x00000000, // Granularity + 0, // SANITIZED_PCIE_PCI_MMIO_BEG= IN + 1, // SANITIZED_PCIE_MMIO_LEN + S= ANITIZED_PCIE_PCI_MMIO_BEGIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEG= IN - SANITIZED_PCIE_CPU_MMIO_WINDOW + 2 // SANITIZED_PCIE_MMIO_LEN + 1 + ,,,MMI1,,TypeTranslation + ) + + // root port registers, not to be used if SMCCC is utilized + QWordMemory ( + ResourceConsumer, , + MinFixed, MaxFixed, + NonCacheable, ReadWrite, // cacheable + 0x00000000, // Granularity + 0xFD500000, // Root port begin + 0xFD509FFF, // Root port end + 0x00000000, // no translation + 0x0000A000, // size + ,, + ) + }) // end Name(RBUF) + + // Work around ASL's inability to add in a resource definition + // or for that matter compute the min,max,len properly + CreateQwordField (RBUF, MMI1._MIN, MMIB) + CreateQwordField (RBUF, MMI1._MAX, MMIE) + CreateQwordField (RBUF, MMI1._TRA, MMIT) + CreateQwordField (RBUF, MMI1._LEN, MMIL) + Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB) + Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE) + Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT) + Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL) + + Return (RBUF) + } // end Method(_CRS) + + // OS Control Handoff + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + // See [1] 6.2.10, [2] 4.5 + Method(_OSC,4) { + // Note, This code is very similar to the code in the PCIe firmwar= e + // specification which can be used as a reference + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + // Mask out Native HotPlug + And(CTRL,0x1E,CTRL) + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } // PCI0 + } //end scope sb +} //end definition block diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 7c5786303d..4c40820858 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D { PcdToken(PcdXhciPci), NULL }, + { + SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'), + PcdToken(PcdXhciPci), + 0, + NULL + }, #endif { // DSDT SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0), -- 2.13.7 --_000_PH0PR05MB870234EF953DA09650BDBD86B9C19PH0PR05MB8702namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
From: Jeremy Linton <jer= emy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <= ;ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com&= gt;; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@ar= m.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton= @arm.com>
Subject: [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT
 
Since we plan on toggling between XHCI and PCI the= PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port on a machine without
a MCFG it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
 Platform/RaspberryPi/AcpiTables/AcpiTables.inf    = ; |   3 +
 Platform/RaspberryPi/AcpiTables/Pci.asl     =        | 161 +++++++++++++++++++++
 Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c |   6 +<= br>  3 files changed, 170 insertions(+)
 create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
   Pptt.aslc
   SsdtThermal.asl
   Xhci.asl
+  Pci.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
   gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
   gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
   gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi= /AcpiTables/Pci.asl
new file mode 100644
index 0000000000..dc2bd7bc9e
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,161 @@
+/** @file
+ *
+ *  Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ *  Copyright (c) 2021 Arm
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...)        &= nbsp;      __VA_ARGS__
+#define REMOVE_PARENTHESES(x)       &nb= sp;   ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW  REMOVE_PARENTHESES(PCIE_CPU_M= MIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN       &= nbsp; REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN   REMOVE_PARENTHESES(PCIE_= TOP_OF_MEM_WIN)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "= RPI4PCIE", 2)
+{
+  Scope (\_SB_)
+  {
+    Device(PCI0)
+    {
+      Name(_HID, EISAID("PNP0A08")) // = PCI Express Root Bridge
+      Name(_CID, EISAID("PNP0A03")) // = Compatible PCI Root Bridge
+      Name(_SEG, Zero) // PCI Segment Group numbe= r
+      Name(_BBN, Zero) // PCI Base Bus Number
+      Name(_CCA, 0)    // Mark the= PCI noncoherent
+
+      // PCIe can only DMA to first 3GB with earl= y SOC's
+      // But we keep the restriction on the later= ones
+      // To avoid DMA translation problems.
+      Name (_DMA, ResourceTemplate() {
+        QWordMemory (ResourceProducer,<= br> +          ,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0,
+          0x0,  &nb= sp;     // MIN
+          0xbfffffff, // MAX<= br> +          0x0,  &nb= sp;     // TRA
+          0xc0000000, // LEN<= br> +          ,
+          ,
+          )
+      })
+
+      // PCI Routing Table
+      Name(_PRT, Package() {
+        Package (4) { 0x0000FFFF, 0, ze= ro, 175 },
+        Package (4) { 0x0000FFFF, 1, ze= ro, 176 },
+        Package (4) { 0x0000FFFF, 2, ze= ro, 177 },
+        Package (4) { 0x0000FFFF, 3, ze= ro, 178 }
+      })
+
+      // Root complex resources
+      Method (_CRS, 0, Serialized) {
+        Name (RBUF, ResourceTemplate ()= {
+
+          // bus numbers assi= gned to this root
+          WordBusNumber (
+            Resourc= eProducer,
+            MinFixe= d, MaxFixed, PosDecode,
+            0, = ;  // AddressGranularity
+            0, = ;  // AddressMinimum - Minimum Bus Number
+            255, //= AddressMaximum - Maximum Bus Number
+            0, = ;  // AddressTranslation - Set to 0
+            256&nbs= p; // RangeLength - Number of Busses
+          )
+
+          // 32-bit mmio wind= ow in 64-bit addr
+          QWordMemory (
+            Resourc= eProducer, PosDecode,
+            MinFixe= d, MaxFixed,
+            NonCach= eable, ReadWrite,        // cacheable +            0x00000= 000,            = ;         // Granularity
+            0, = ;            &n= bsp;            = ;    // SANITIZED_PCIE_PCI_MMIO_BEGIN
+            1, = ;            &n= bsp;            = ;    // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BE= GIN
+            SANITIZ= ED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_= CPU_MMIO_WINDOW
+            2 =             &nb= sp;            =      // SANITIZED_PCIE_MMIO_LEN + 1
+            ,,,MMI1= ,,TypeTranslation
+          )
+
+          // root port regist= ers, not to be used if SMCCC is utilized
+          QWordMemory (
+            Resourc= eConsumer, ,
+            MinFixe= d, MaxFixed,
+            NonCach= eable, ReadWrite,        // cacheable +            0x00000= 000,            = ;         // Granularity
+            0xFD500= 000,            = ;         // Root port begin
+            0xFD509= FFF,            = ;         // Root port end
+            0x00000= 000,            = ;         // no translation
+            0x0000A= 000,            = ;         // size
+            ,,
+          )
+        }) // end Name(RBUF)
+
+        // Work around ASL's inability = to add in a resource definition
+        // or for that matter compute t= he min,max,len properly
+        CreateQwordField (RBUF, MMI1._M= IN, MMIB)
+        CreateQwordField (RBUF, MMI1._M= AX, MMIE)
+        CreateQwordField (RBUF, MMI1._T= RA, MMIT)
+        CreateQwordField (RBUF, MMI1._L= EN, MMIL)
+        Add (MMIB, SANITIZED_PCIE_PCI_M= MIO_BEGIN, MMIB)
+        Add (SANITIZED_PCIE_MMIO_LEN, S= ANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+        Subtract (MMIT, SANITIZED_PCIE_= PCI_MMIO_BEGIN, MMIT)
+        Add (SANITIZED_PCIE_MMIO_LEN, 1= , MMIL)
+
+        Return (RBUF)
+      } // end Method(_CRS)
+
+      // OS Control Handoff
+      Name(SUPP, Zero) // PCI _OSC Support Field = value
+      Name(CTRL, Zero) // PCI _OSC Control Field = value
+
+      // See [1] 6.2.10, [2] 4.5
+      Method(_OSC,4) {
+        // Note, This code is very simi= lar to the code in the PCIe firmware
+        // specification which can be u= sed as a reference
+        // Check for proper UUID
+        If(LEqual(Arg0,ToUUID("33D= B4D5B-1FF7-401C-9657-7441C03DD766"))) {
+          // Create DWord-adr= essable fields from the Capabilities Buffer
+          CreateDWordField(Ar= g3,0,CDW1)
+          CreateDWordField(Ar= g3,4,CDW2)
+          CreateDWordField(Ar= g3,8,CDW3)
+          // Save Capabilitie= s DWord2 & 3
+          Store(CDW2,SUPP) +          Store(CDW3,CTRL) +          // Mask out Native = HotPlug
+          And(CTRL,0x1E,CTRL)=
+          // Always allow nat= ive PME, AER (no dependencies)
+          // Never allow SHPC= (no SHPC controller in this system)
+          And(CTRL,0x1D,CTRL)=
+
+          If(LNotEqual(Arg1,O= ne)) { // Unknown revision
+            Or(CDW1= ,0x08,CDW1)
+          }
+
+          If(LNotEqual(CDW3,C= TRL)) {  // Capabilities bits were masked
+            Or(CDW1= ,0x10,CDW1)
+          }
+          // Update DWORD3 in= the buffer
+          Store(CTRL,CDW3) +          Return(Arg3)
+        } Else {
+          Or(CDW1,4,CDW1) // = Unrecognized UUID
+          Return(Arg3)
+        }
+      } // End _OSC
+    } // PCI0
+  } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D {
     PcdToken(PcdXhciPci),
     NULL
   },
+  {
+    SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),<= br> +    PcdToken(PcdXhciPci),
+    0,
+    NULL
+  },
 #endif
   { // DSDT
     SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7

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