From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (NAM12-MW2-obe.outbound.protection.outlook.com [40.107.244.74]) by mx.groups.io with SMTP id smtpd.web09.6380.1628264266596156801 for ; Fri, 06 Aug 2021 08:37:47 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@vmware.com header.s=selector2 header.b=Bp0cqnFw; spf=pass (domain: vmware.com, ip: 40.107.244.74, mailfrom: awarkentin@vmware.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=NH8x5YfhZLmsel8FdvBr1mngtFoiuT3KlK3BDPr/GXdWxcM81Ueg5S+O8pvhzzT70d2Vy1TmSxVviM7RJJLpAxfZYUIYhZamegr3APH/s0JbsnXVlPLiYG8tPD9kwSDJRDT2Wrhvh++nFk8DXivjqKx0FBrIUutxbYbJXzRRIQr/rJHa7nsx8/uOFkvv5Tz2fuEb1OQOuEBVvT64EGgAUe17yF4QVnIsfTVN3uqAv3UG3LUU9OpJngfmMeGHRLNbleGHOtdqU2BYUb5KmNdvc0il75HF0YoQP7cmFuU+o8vjMqVOoJJ8+kfiDzDRMppP7DXmqtciZmGXhgtfhrhZlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FVSEO8n4FOeD3mhAlKLDEYOooPCh5Xh3p10Pfa8bFec=; b=MeNwIz3fJ0kMMWOjupaE1GO+dRDAdfUP8aLve+jC8SBYaiZVeLPSHSUBFxZ03Ctfmwqs1I4tkZQ9DgrtY0cMkTAE+tL4hZjCGwRtwdqkp7NpMYmDizmpD4sFZccG/2agTme/VgB09KmXxaTks5IOdN8EjoqTKgHKOwFIaosxTnIjij2MnqWti+CypBV93fZHTfrnK4FhevVaKU0npMNVY4yPdxsyrB10E2/z9owTEjhAMDxH4Pt1B45A/VpMnjKV/9Oa0Dr0YhTmXQDSH51TsjzcrtUcNvyz+S35uzA3mTZksVuZxdMiEf+YXjsDnZEkLh9+cD8p7UFK9vG4PGVCgw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=vmware.com; dmarc=pass action=none header.from=vmware.com; dkim=pass header.d=vmware.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vmware.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FVSEO8n4FOeD3mhAlKLDEYOooPCh5Xh3p10Pfa8bFec=; b=Bp0cqnFwE+igCZJ6Mwbndh08RIY/uA9GFf1Zcwd4deaRu06Qf+RdbHu2uuUihwTVPUWKe9TH2uqm2N5Tj5J3W0EjCckIiiLL2rH4FN7tGpQ2lihudksqYnQ8UbbJAPwXgnplyEf8jSS1wKtM69BG2sbO78w9ZzWz9vqsZ3CUc/Y= Received: from PH0PR05MB8702.namprd05.prod.outlook.com (2603:10b6:510:b2::21) by PH0PR05MB7560.namprd05.prod.outlook.com (2603:10b6:510:1::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4394.12; Fri, 6 Aug 2021 15:37:42 +0000 Received: from PH0PR05MB8702.namprd05.prod.outlook.com ([fe80::2566:a48:8045:d0fa]) by PH0PR05MB8702.namprd05.prod.outlook.com ([fe80::2566:a48:8045:d0fa%6]) with mapi id 15.20.4394.015; Fri, 6 Aug 2021 15:37:42 +0000 From: "Andrei Warkentin" To: "devel@edk2.groups.io" , "jeremy.linton@arm.com" CC: "pete@akeo.ie" , "ardb+tianocore@kernel.org" , "Sunny.Wang@arm.com" , "samer.el-haj-mahmoud@arm.com" Subject: Re: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT Thread-Topic: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT Thread-Index: AQHXihgAoR4PrVYYHU6Bb5lsTUGUoKtmm+Wc Date: Fri, 6 Aug 2021 15:37:42 +0000 Message-ID: References: <20210805163551.488035-1-jeremy.linton@arm.com>,<20210805163551.488035-4-jeremy.linton@arm.com> In-Reply-To: <20210805163551.488035-4-jeremy.linton@arm.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=vmware.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 26a84865-7982-4bc2-62b7-08d958f02192 x-ms-traffictypediagnostic: PH0PR05MB7560: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6430; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 7ERm3nYrZHaSbCQHW/NkpFFnA85etwHiTMqfym394paMj9hePsBWm93InY3ps7tGRMB4MWQffAx/PxDyMKEFb339T0n/KORl/Jv7yyD7e6TghZK5fJevIPcfOueBiodXGtL3Ji/NdYM/2dWg9imtuQnsU+0vW9tAiXW8OKYPAatArIGNHUw9JpddQ8L5hu3h7zPaFer7dth/2cOevbruUebNbgdoc2reectCrWEHLXi2iw5hiCUY9Ma9eLLfEhK5DAxfnjpVBSGSsZKoPqNeYZF22tJfSMrQd5QB8g2v0zTOmYBch43szEuREHMorqTrNOnyBp5bLOHKglRstKVAvWH/vkjchybK6hpJteHcvJkOu1tUqq7DgCkKujABBXKKuJVURObY/VXmpFQq65cjIv5piaqx+4ZDW/UWUzJkaG68xS2jj6J2N1SgZOR+8YEDJ9TZIeON/Fwy3yT5OrBRsDEKpOMCQRjv3926b+uSJd+q3ekHPdeWQ/9cOeSpxNbsJrKTwX4XMwiewA0XeVQ9ku5YdQSL6akW71bg5G63xAcoGwg32pUkGl5k934WG8S26KD5y5LV6xClD1zXGlRTRn7CeaJlucBQ5PGCydVJnRYdRSkr2RYDNgJSukQ6Bj08Ui324GC/TzigRq+m1hP7RNtMul1pvc0tCxzqtPPLMS2o9xXjcPSi0DsH0IQX/AZhmA/Xg8VAlAI9Wa42g8vFAd7+3xIiv7BGOe8YHgbULIzmmjAT+pQEMSfc0m7n/lB/QvB7b00SPm2CAtskmh3oEBrzBpRj+3o9/SYXaz6mLTI= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PH0PR05MB8702.namprd05.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(366004)(396003)(136003)(346002)(39860400002)(376002)(66946007)(5660300002)(64756008)(52536014)(66556008)(66446008)(66476007)(38070700005)(76116006)(91956017)(55016002)(2906002)(33656002)(9686003)(166002)(122000001)(83380400001)(86362001)(38100700002)(19627405001)(4326008)(7696005)(30864003)(8676002)(26005)(316002)(8936002)(6506007)(45080400002)(71200400001)(110136005)(186003)(966005)(478600001)(53546011)(54906003);DIR:OUT;SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?1wf0RCAUmDz8Kq+gvMg233cRFDCfX+/bf0kaLIzFijBGMp2YUoFTRBTFj6If?= =?us-ascii?Q?4CeL9inZL5JM2KcwWZzDFoDF2IRcSe7tEMhjPepQhW9Z9/LJXCFv61X74scx?= =?us-ascii?Q?8KGoRjAz0DC3U5J0bUno5vgh3YZjs/+DpWrAbKBxUXojddrZNHqULwxZcbwJ?= =?us-ascii?Q?JPi7yxSWIlzLURDiMDhvKeqKbYmmr75sgj2lu7lqDERt7O1AmqDP9Q30o9nd?= =?us-ascii?Q?JpNcCaNvkxETh3bvhhJx4OWbJjo4T3mjNUW3mO4fjsZ+T0Be//sq+H6kLI7H?= =?us-ascii?Q?816fIe3m449jvjZbd23VkXdMiy1wF9wdtir4unwqYPHGL6Io4jgOd7TrHq++?= =?us-ascii?Q?luLVIHoC9DsQbYO/V5Bc+NVSmbqF+8SS+99whaAX8kHhOxuXD1qBX5fz4+Gb?= =?us-ascii?Q?WR3bgmRuRdKpzZ9Lku6DIAHguvZ6DpyynxC3L6YlHjlVbrXXb/uHCg084RIL?= =?us-ascii?Q?45zkeEomGQcsj65UFMYGqh/aqogLUAYPF4UITf0bVG2koq5i7UHIfHCxkrKI?= =?us-ascii?Q?Q+TxLNfro0XhePFF35zSqRkLE4qEvCqQUag/GlQ9NUwpaqx4BHpfuAaMs2ul?= =?us-ascii?Q?r9gMoMl4Oo0Fm4aGm0/QZfjt7v7D6nYBkD3LwGboNj0YC6TTss0nEREGAY4J?= =?us-ascii?Q?UqjU3udNHrLp7ZE7Dr8jxR4GW8qara2PSLyMcbGOVvQlOJMRpjPhKjeFgLqM?= =?us-ascii?Q?s+zY0FckOFo2md2QeB8wv2m7McVWX6naXf1v99z4TvpqZcZP/CwwlE1UcBD5?= =?us-ascii?Q?pRg5d3r/CjeNCftjlwvEtbOetJTE55JbieJR2M1cfADpPedHdkT5DaPBuFLB?= =?us-ascii?Q?DLjT8/4izR3726gKLp7gNts2jhAUFGw8Susj6S/67zVRL1r8EuCc0tkAHogw?= =?us-ascii?Q?UBWiKXXhyXZM51nz6JaNvfWjFTX8esH1W63vgiY1JE14jfunX8hK2d0FxiDo?= =?us-ascii?Q?M8a2kNOJE34xwX8TnC+eQADBxaUcH9Z6F11VLOmlszsxSBppxBYISKcBbWcB?= =?us-ascii?Q?miwyRf7glpKYiPxjChOhgCYZF0Zvtl+Vh5O6fixtjtQ39HyFSU0MBFliVDv0?= =?us-ascii?Q?uhmdlrmj6U7XCXc1vB89A2u77mdZq4ePWYwCW1j7CftO4xPY0SIfuYMg5vH0?= =?us-ascii?Q?pGu6KBzYz5S8QLmIVClxhtYocef3KLByBpAkSX6ZT5TE5xLzGAtaIBrS9rDJ?= =?us-ascii?Q?PcBiVEejYxwPlehIW6Xjn4KaKpienFAkw4B6zoHKVDD1qxasSqJCSkbqC8lt?= =?us-ascii?Q?4b8B5WLt6iKM87y1wKr89PbwimMrlWfKrcVhjZE8XeqTMscXNtDrvhyi/+WC?= =?us-ascii?Q?0jYOp/QFJLNtbvfqmxgackth?= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: vmware.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR05MB8702.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 26a84865-7982-4bc2-62b7-08d958f02192 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2021 15:37:42.6948 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b39138ca-3cee-4b4a-a4d6-cd83d9dd62f0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: f6VoHrC6NAEoknxcAPapuOEjVrM39HPUX6zmpT6kP7yMjBsLDBNvafNA2qYBSQP2XQsh8o5GO7hyHNKKOu/1Zg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR05MB7560 Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_PH0PR05MB87027050BEDEF7B1704D2F7AB9F39PH0PR05MB8702namp_" --_000_PH0PR05MB87027050BEDEF7B1704D2F7AB9F39PH0PR05MB8702namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Jeremy, MADT -> MCFG (and in other patches as well, where you refer to MADT) The other feedback that Ard provided makes sense to me as well. A -- Andrei Warkentin, Arm Enablement Architect, Cloud Platform Business Unit, VMware ________________________________ From: devel@edk2.groups.io on behalf of Jeremy Linto= n via groups.io Sent: Thursday, August 5, 2021 7:35 PM To: devel@edk2.groups.io Cc: pete@akeo.ie ; ardb+tianocore@kernel.org ; Andrei Warkentin ; Sunny.Wang@arm.com <= Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com ; Jeremy Linton Subject: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT Since we plan on toggling between XHCI and PCI the PCI root needs to be in its own SSDT. This is all thats needed of UEFI. The SMC conduit is provided directly to the running OS. When the OS detects this PCIe port, on a machine without a MADT it attempts to connect to the SMC conduit. The RPi definition doesn't have any power mgmt, and only provides a description of the root port. Signed-off-by: Jeremy Linton --- Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 + Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++= ++++ Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 + 3 files changed, 246 insertions(+) create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf index f3e8d950c1..da2a6db85f 100644 --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf @@ -39,6 +39,7 @@ Pptt.aslc SsdtThermal.asl Xhci.asl + Pci.asl [Packages] ArmPkg/ArmPkg.dec @@ -59,6 +60,8 @@ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicDistributorBase gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi= /AcpiTables/Pci.asl new file mode 100644 index 0000000000..34474f13ef --- /dev/null +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl @@ -0,0 +1,237 @@ +/** @file + * + * Copyright (c) 2019 Linaro, Limited. All rights reserved. + * Copyright (c) 2021 Arm + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include "AcpiTables.h" + +/* + * The following can be used to remove parenthesis from + * defined macros that the compiler complains about. + */ +#define ISOLATE_ARGS(...) __VA_ARGS__ +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x + +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_W= INDOW) +#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMI= O_LEN) +#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM= _WIN) + +/* + * According to UEFI boot log for the VLI device on Pi 4. + */ +#define RT_REG_LENGTH 0x1000 + +// copy paste job from juno +#define LNK_DEVICE(Unique_Id, Link_Name, irq) = \ + Device(Link_Name) { = \ + Name(_HID, EISAID("PNP0C0F")) = \ + Name(_UID, Unique_Id) = \ + Name(_PRS, ResourceTemplate() { = \ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq = } \ + }) = \ + Method (_CRS, 0) { Return (_PRS) } = \ + Method (_SRS, 1) { } = \ + Method (_DIS) { } = \ + } + +#define PRT_ENTRY(Address, Pin, Link) = \ + Package (4) { = \ + Address, /* uses the same format as _ADR */ = \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INT= B, 2-INTC, 3-INTD). */ \ + Link, /* Interrupt allocated via Link device. */ = \ + Zero /* global system interrupt number (no used) */ = \ + } +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) + +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2) +{ + Scope (\_SB_) + { + + Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x0) + Name (_CCA, 0x0) + + Method (_CRS, 0, Serialized) { + // Container devices with _DMA must have _CRS, + // meaning SCB0 to provide all resources that + // PCI0 consumes (except interrupts). + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, RT_REG_LENGTH - 1, MMBE) + Add (MMLE, RT_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Name (_DMA, ResourceTemplate() { + // PCIe can only DMA to first 3GB with early SOC's + // But we keep the restriction on the later ones + // To avoid DMA translation problems. + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + // + // PCI Root Complex + // + LNK_DEVICE(1, LNKA, 175) + LNK_DEVICE(2, LNKB, 176) + LNK_DEVICE(3, LNKC, 177) + LNK_DEVICE(4, LNKD, 178) + + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_CCA, 0) // Mark the PCI noncoherent + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + Name (_DMA, ResourceTemplate() { + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, LNKA), // INTA + ROOT_PRT_ENTRY(1, LNKB), // INTB + ROOT_PRT_ENTRY(2, LNKC), // INTC + ROOT_PRT_ENTRY(3, LNKD), // INTD + }) + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + QWordMemory ( // 32-bit BAR Windows in 64-bit addr + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + NonCacheable, ReadWrite, //cacheable? is that right? + 0x00000000, // Granularity + 0, // SANITIZED_PCIE_PCI_MMIO_B= EGIN + 1, // SANITIZED_PCIE_MMIO_LEN += SANITIZED_PCIE_PCI_MMIO_BEGIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_B= EGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW + 2 // SANITIZED_PCIE_MMIO_LEN += 1 + ,,,MMI1,,TypeTranslation + ) + }) // end Name(RBUF) + + // Work around ASL's inability to add in a resource definition + // or for that matter compute the min,max,len properly + CreateQwordField (RBUF, MMI1._MIN, MMIB) + CreateQwordField (RBUF, MMI1._MAX, MMIE) + CreateQwordField (RBUF, MMI1._TRA, MMIT) + CreateQwordField (RBUF, MMI1._LEN, MMIL) + Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB) + Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMI= E) + Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT) + Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL) + + Return (RBUF) + } // end Method(_CRS) + // + // OS Control Handoff + // + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + // See [1] 6.2.10, [2] 4.5 + Method(_OSC,4) { + // Note, This code is very similar to the code in the PCIe firmw= are + // specification which can be used as a reference + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) = { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + // Mask out Native HotPlug + And(CTRL,0x1E,CTRL) + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } // PCI0 + } //end SCB0 + } //end scope sb +} //end definition block diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c index 7c5786303d..4c40820858 100644 --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c @@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D { PcdToken(PcdXhciPci), NULL }, + { + SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'), + PcdToken(PcdXhciPci), + 0, + NULL + }, #endif { // DSDT SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0), -- 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78737): https://nam04.safelinks.protection.outlook.com/= ?url=3Dhttps%3A%2F%2Fedk2.groups.io%2Fg%2Fdevel%2Fmessage%2F78737&data= =3D04%7C01%7Cawarkentin%40vmware.com%7C991285544b1540eaa12908d9582f2169%7Cb= 39138ca3cee4b4aa4d6cd83d9dd62f0%7C0%7C0%7C637637781724835660%7CUnknown%7CTW= FpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3= D%7C1000&sdata=3DOE2b%2FCjUQIDZcMX%2BrrijX30WNaNI5GyS6h2O9gfPs94%3D&= ;reserved=3D0 Mute This Topic: https://nam04.safelinks.protection.outlook.com/?url=3Dhttp= s%3A%2F%2Fgroups.io%2Fmt%2F84688699%2F4387333&data=3D04%7C01%7Cawarkent= in%40vmware.com%7C991285544b1540eaa12908d9582f2169%7Cb39138ca3cee4b4aa4d6cd= 83d9dd62f0%7C0%7C0%7C637637781724835660%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4= wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=3D= Sg96lV58XqE6pN%2BeL8QXmQnX%2Bc%2BN02lLNHkMVXZpfi4%3D&reserved=3D0 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://nam04.safelinks.protection.outlook.com/?url=3Dhttps%3A= %2F%2Fedk2.groups.io%2Fg%2Fdevel%2Funsub&data=3D04%7C01%7Cawarkentin%40= vmware.com%7C991285544b1540eaa12908d9582f2169%7Cb39138ca3cee4b4aa4d6cd83d9d= d62f0%7C0%7C0%7C637637781724835660%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAw= MDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=3DyRoA%= 2FnUZ1u8Q1Xryo2r1%2BjWLhYJFk76nvx0aGR36VG8%3D&reserved=3D0 [awarkentin@= vmware.com] -=3D-=3D-=3D-=3D-=3D-=3D --_000_PH0PR05MB87027050BEDEF7B1704D2F7AB9F39PH0PR05MB8702namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hi Jeremy,

MADT -> MCFG (and in other patches as well, where you refer to MADT)

The other feedback that Ard provided makes sense to me as well.

A

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
From: devel@edk2.groups.io = <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <j= eremy.linton=3Darm.com@groups.io>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <= ;ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com&= gt;; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@ar= m.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton= @arm.com>
Subject: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSD= T
 
Since we plan on toggling between XHCI and PCI the= PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
 Platform/RaspberryPi/AcpiTables/AcpiTables.inf    = ; |   3 +
 Platform/RaspberryPi/AcpiTables/Pci.asl     =        | 237 +++++++++++++++++++++
 Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c |   6 +<= br>  3 files changed, 246 insertions(+)
 create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/Rasp= berryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
   Pptt.aslc
   SsdtThermal.asl
   Xhci.asl
+  Pci.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+  gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
   gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
   gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
   gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi= /AcpiTables/Pci.asl
new file mode 100644
index 0000000000..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ *  Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ *  Copyright (c) 2021 Arm
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...)        &= nbsp;      __VA_ARGS__
+#define REMOVE_PARENTHESES(x)       &nb= sp;   ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW  REMOVE_PARENTHESES(PCIE_CPU_M= MIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN       &= nbsp; REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN   REMOVE_PARENTHESES(PCIE_= TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH         = ;        0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq)     = ;            &n= bsp;            = ;   \
+  Device(Link_Name) {        =             &nb= sp;            =             &nb= sp;           \
+      Name(_HID, EISAID("PNP0C0F"))&nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;    \
+      Name(_UID, Unique_Id)   &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;         \
+      Name(_PRS, ResourceTemplate() {  =             &nb= sp;            =             &nb= sp; \
+          Interrupt(ResourceP= roducer, Level, ActiveHigh, Exclusive) { irq }   \
+      })       = ;            &n= bsp;            = ;            &n= bsp;            = ;             \=
+      Method (_CRS, 0) { Return (_PRS) } &nb= sp;            =             &nb= sp;           \
+      Method (_SRS, 1) { }    = ;            &n= bsp;            = ;            &n= bsp;          \
+      Method (_DIS) { }    &n= bsp;            = ;            &n= bsp;            = ;             \=
+  }
+
+#define PRT_ENTRY(Address, Pin, Link)      &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;   \
+        Package (4) {   =             &nb= sp;            =             &nb= sp;            =             &nb= sp;          \
+            Address= ,    /* uses the same format as _ADR */   &nb= sp;            =             &nb= sp;          \
+            Pin,&nb= sp;       /* The PCI pin number of the device= (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
+            Link,&n= bsp;      /* Interrupt allocated via Link device. = */            &= nbsp;           &nbs= p;      \
+            Zero&nb= sp;       /* global system interrupt number (= no used) */          &nbs= p;            &= nbsp;   \
+          }
+#define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x0000FFFF, Pin, L= ink)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "= RPI4PCIE", 2)
+{
+  Scope (\_SB_)
+  {
+
+    Device (SCB0) {
+      Name (_HID, "ACPI0004")
+      Name (_UID, 0x0)
+      Name (_CCA, 0x0)
+
+      Method (_CRS, 0, Serialized) {
+        // Container devices with _DMA = must have _CRS,
+        // meaning SCB0 to provide all = resources that
+        // PCI0 consumes (except interr= upts).
+        Name (RBUF, ResourceTemplate ()= {
+            QWordMe= mory (ResourceProducer,
+            &n= bsp;   ,
+            &n= bsp;   MinFixed,
+            &n= bsp;   MaxFixed,
+            &n= bsp;   NonCacheable,
+            &n= bsp;   ReadWrite,
+            &n= bsp;   0x0,
+            &n= bsp;   SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
+            &n= bsp;   SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
+            &n= bsp;   0x0,
+            &n= bsp;   0x1,         =             &nb= sp;      // LEN
+            &n= bsp;   ,
+            &n= bsp;   ,
+            &n= bsp;   MMIO
+            &n= bsp;   )
+        })
+        CreateQwordField (RBUF, MMIO._M= AX, MMBE)
+        CreateQwordField (RBUF, MMIO._L= EN, MMLE)
+        Add (MMBE, RT_REG_LENGTH - 1, M= MBE)
+        Add (MMLE, RT_REG_LENGTH - 1, M= MLE)
+        Return (RBUF)
+      }
+
+      Name (_DMA, ResourceTemplate() {
+        // PCIe can only DMA to first 3= GB with early SOC's
+        // But we keep the restriction = on the later ones
+        // To avoid DMA translation pro= blems.
+        QWordMemory (ResourceProducer,<= br> +            ,
+            MinFixe= d,
+            MaxFixe= d,
+            NonCach= eable,
+            ReadWri= te,
+            0x0, +            0x0,&nb= sp;       // MIN
+            0xbffff= fff, // MAX
+            0x0,&nb= sp;       // TRA
+            0xc0000= 000, // LEN
+            ,
+            ,
+            )
+      })
+
+      //
+      // PCI Root Complex
+      //
+      LNK_DEVICE(1, LNKA, 175)
+      LNK_DEVICE(2, LNKB, 176)
+      LNK_DEVICE(3, LNKC, 177)
+      LNK_DEVICE(4, LNKD, 178)
+
+      Device(PCI0)
+      {
+        Name(_HID, EISAID("PNP0A08= ")) // PCI Express Root Bridge
+        Name(_CID, EISAID("PNP0A03= ")) // Compatible PCI Root Bridge
+        Name(_SEG, Zero) // PCI Segment= Group number
+        Name(_BBN, Zero) // PCI Base Bu= s Number
+        Name(_CCA, 0)   = // Mark the PCI noncoherent
+
+        // Root Complex 0
+        Device (RP0) {
+         Name(_ADR, 0xF0000000)&nb= sp;   // Dev 0, Func 0
+        }
+
+        Name (_DMA, ResourceTemplate() = {
+          QWordMemory (Resour= ceConsumer,
+            ,
+            MinFixe= d,
+            MaxFixe= d,
+            NonCach= eable,
+            ReadWri= te,
+            0x0, +            0x0,&nb= sp;       // MIN
+            0xbffff= fff, // MAX
+            0x0,&nb= sp;       // TRA
+            0xc0000= 000, // LEN
+            ,
+            ,
+            )
+        })
+
+        // PCI Routing Table
+        Name(_PRT, Package() {
+          ROOT_PRT_ENTRY(0, L= NKA),   // INTA
+          ROOT_PRT_ENTRY(1, L= NKB),   // INTB
+          ROOT_PRT_ENTRY(2, L= NKC),   // INTC
+          ROOT_PRT_ENTRY(3, L= NKD),   // INTD
+        })
+        // Root complex resources
+        Method (_CRS, 0, Serialized) {<= br> +          Name (RBUF, Resourc= eTemplate () {
+            WordBus= Number ( // Bus numbers assigned to this root
+            &n= bsp; ResourceProducer,
+            &n= bsp; MinFixed, MaxFixed, PosDecode,
+            &n= bsp; 0,   // AddressGranularity
+            &n= bsp; 0,   // AddressMinimum - Minimum Bus Number
+            &n= bsp; 255, // AddressMaximum - Maximum Bus Number
+            &n= bsp; 0,   // AddressTranslation - Set to 0
+            &n= bsp; 256  // RangeLength - Number of Busses
+            )
+
+            QWordMe= mory ( // 32-bit BAR Windows in 64-bit addr
+            &n= bsp; ResourceProducer, PosDecode,
+            &n= bsp; MinFixed, MaxFixed,
+            &n= bsp; NonCacheable, ReadWrite,        //c= acheable? is that right?
+            &n= bsp; 0x00000000,          = ;           // Granularit= y
+            &n= bsp; 0,           &n= bsp;            = ;      // SANITIZED_PCIE_PCI_MMIO_BEGIN
+            &n= bsp; 1,           &n= bsp;            = ;      // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE= _PCI_MMIO_BEGIN
+            &n= bsp; SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SAN= ITIZED_PCIE_CPU_MMIO_WINDOW
+            &n= bsp; 2           &nb= sp;            =        // SANITIZED_PCIE_MMIO_LEN + 1
+            &n= bsp; ,,,MMI1,,TypeTranslation
+            )
+          }) // end Name(RBUF= )
+
+          // Work around ASL'= s inability to add in a resource definition
+          // or for that matt= er compute the min,max,len properly
+          CreateQwordField (R= BUF, MMI1._MIN, MMIB)
+          CreateQwordField (R= BUF, MMI1._MAX, MMIE)
+          CreateQwordField (R= BUF, MMI1._TRA, MMIT)
+          CreateQwordField (R= BUF, MMI1._LEN, MMIL)
+          Add (MMIB, SANITIZE= D_PCIE_PCI_MMIO_BEGIN, MMIB)
+          Add (SANITIZED_PCIE= _MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+          Subtract (MMIT, SAN= ITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+          Add (SANITIZED_PCIE= _MMIO_LEN, 1 , MMIL)
+
+          Return (RBUF)
+        } // end Method(_CRS)
+        //
+        // OS Control Handoff
+        //
+        Name(SUPP, Zero) // PCI _OSC Su= pport Field value
+        Name(CTRL, Zero) // PCI _OSC Co= ntrol Field value
+
+        // See [1] 6.2.10, [2] 4.5
+        Method(_OSC,4) {
+          // Note, This code = is very similar to the code in the PCIe firmware
+          // specification wh= ich can be used as a reference
+          // Check for proper= UUID
+          If(LEqual(Arg0,ToUU= ID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+            // Crea= te DWord-adressable fields from the Capabilities Buffer
+            CreateD= WordField(Arg3,0,CDW1)
+            CreateD= WordField(Arg3,4,CDW2)
+            CreateD= WordField(Arg3,8,CDW3)
+            // Save= Capabilities DWord2 & 3
+            Store(C= DW2,SUPP)
+            Store(C= DW3,CTRL)
+            // Mask= out Native HotPlug
+            And(CTR= L,0x1E,CTRL)
+            // Alwa= ys allow native PME, AER (no dependencies)
+            // Neve= r allow SHPC (no SHPC controller in this system)
+            And(CTR= L,0x1D,CTRL)
+
+            If(LNot= Equal(Arg1,One)) { // Unknown revision
+            &n= bsp; Or(CDW1,0x08,CDW1)
+            }
+
+            If(LNot= Equal(CDW3,CTRL)) {  // Capabilities bits were masked
+            &n= bsp; Or(CDW1,0x10,CDW1)
+            }
+            // Upda= te DWORD3 in the buffer
+            Store(C= TRL,CDW3)
+            Return(= Arg3)
+          } Else {
+            Or(CDW1= ,4,CDW1) // Unrecognized UUID
+            Return(= Arg3)
+          }
+        } // End _OSC
+      } // PCI0
+    } //end SCB0
+  } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/= RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] =3D {
     PcdToken(PcdXhciPci),
     NULL
   },
+  {
+    SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),<= br> +    PcdToken(PcdXhciPci),
+    0,
+    NULL
+  },
 #endif
   { // DSDT
     SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7



-=3D-=3D-=3D-=3D-=3D-=3D
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#78737): https://nam04.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fedk2.gr= oups.io%2Fg%2Fdevel%2Fmessage%2F78737&amp;data=3D04%7C01%7Cawarkentin%4= 0vmware.com%7C991285544b1540eaa12908d9582f2169%7Cb39138ca3cee4b4aa4d6cd83d9= dd62f0%7C0%7C0%7C637637781724835660%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA= wMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=3D= OE2b%2FCjUQIDZcMX%2BrrijX30WNaNI5GyS6h2O9gfPs94%3D&amp;reserved=3D0=
Mute This Topic: https://nam04.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fgroups.= io%2Fmt%2F84688699%2F4387333&amp;data=3D04%7C01%7Cawarkentin%40vmware.c= om%7C991285544b1540eaa12908d9582f2169%7Cb39138ca3cee4b4aa4d6cd83d9dd62f0%7C= 0%7C0%7C637637781724835660%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQ= IjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=3DSg96lV58X= qE6pN%2BeL8QXmQnX%2Bc%2BN02lLNHkMVXZpfi4%3D&amp;reserved=3D0
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://nam04.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fedk2.gr= oups.io%2Fg%2Fdevel%2Funsub&amp;data=3D04%7C01%7Cawarkentin%40vmware.co= m%7C991285544b1540eaa12908d9582f2169%7Cb39138ca3cee4b4aa4d6cd83d9dd62f0%7C0= %7C0%7C637637781724835660%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQI= joiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=3DyRoA%2FnUZ= 1u8Q1Xryo2r1%2BjWLhYJFk76nvx0aGR36VG8%3D&amp;reserved=3D0 [awarkentin@vmware.com]
-=3D-=3D-=3D-=3D-=3D-=3D


--_000_PH0PR05MB87027050BEDEF7B1704D2F7AB9F39PH0PR05MB8702namp_--