Reviewed-by: Andrei Warkentin ________________________________ From: Jeremy Linton Sent: Thursday, August 19, 2021 11:16 PM To: devel@edk2.groups.io Cc: pete@akeo.ie ; ardb+tianocore@kernel.org ; Andrei Warkentin ; Sunny.Wang@arm.com ; samer.el-haj-mahmoud@arm.com ; Jeremy Linton Subject: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor The existing code fails to create/finish configuring the pcie subsystem if it fails to get a linkup. This is reasonable on the RPi4 because it generally won't happen, and the OS could not see the root port. Now that the OS can see the root port, its a bit odd if it only shows up when something is plugged into the first slot. Lets move the link up check into the config accessor where it will be used to restrict sending CFG TLP's out the port when nothing is plugged in. Thus avoiding a SERROR during probe. Signed-off-by: Jeremy Linton --- .../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 ----- .../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++++++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c index 8587d2d36d..4d4c584726 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( } while (((Data & 0x30) != 0x030) && (Timeout)); DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout)); - if ((Data & 0x30) != 0x30) { - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data)); - return EFI_DEVICE_ERROR; - } - if ((Data & 0x80) != 0x80) { DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data)); return EFI_UNSUPPORTED; diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c index 6d15e82fa2..b627e5730b 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c @@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase ( return 0xFFFFFFFF; } + /* Don't probe slots if the link is down */ + Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); + if ((Data & 0x30) != 0x30) { + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data)); + return 0xFFFFFFFF; + } + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); mPciSegmentLastAccess = Address; } -- 2.13.7