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Fri, 20 Aug 2021 20:16:45 +0000 Received: from PH0PR05MB8702.namprd05.prod.outlook.com ([fe80::c88e:73c1:db37:5b94]) by PH0PR05MB8702.namprd05.prod.outlook.com ([fe80::c88e:73c1:db37:5b94%6]) with mapi id 15.20.4457.005; Fri, 20 Aug 2021 20:16:44 +0000 From: "Andrei Warkentin" To: Jeremy Linton , "devel@edk2.groups.io" CC: "pete@akeo.ie" , "ardb+tianocore@kernel.org" , "Sunny.Wang@arm.com" , "samer.el-haj-mahmoud@arm.com" Subject: Re: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor Thread-Topic: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor Thread-Index: AQHXlXolE34t5U3wjUyBobfCe4glcat81Z8u Date: Fri, 20 Aug 2021 20:16:44 +0000 Message-ID: References: <20210820041619.87248-1-jeremy.linton@arm.com> <20210820041619.87248-6-jeremy.linton@arm.com> In-Reply-To: <20210820041619.87248-6-jeremy.linton@arm.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; 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boundary="_000_PH0PR05MB87027DB6D0AA6EDA562B46E6B9C19PH0PR05MB8702namp_" --_000_PH0PR05MB87027DB6D0AA6EDA562B46E6B9C19PH0PR05MB8702namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Andrei Warkentin ________________________________ From: Jeremy Linton Sent: Thursday, August 19, 2021 11:16 PM To: devel@edk2.groups.io Cc: pete@akeo.ie ; ardb+tianocore@kernel.org ; Andrei Warkentin ; Sunny.Wang@arm.com <= Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com ; Jeremy Linton Subject: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into th= e cfg accessor The existing code fails to create/finish configuring the pcie subsystem if it fails to get a linkup. This is reasonable on the RPi4 because it generally won't happen, and the OS could not see the root port. Now that the OS can see the root port, its a bit odd if it only shows up when something is plugged into the first slot. Lets move the link up check into the config accessor where it will be used to restrict sending CFG TLP's out the port when nothing is plugged in. Thus avoiding a SERROR during probe. Signed-off-by: Jeremy Linton --- .../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c | 5 ---= -- .../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 7 +++= ++++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm27= 11PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711P= ciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c index 8587d2d36d..4d4c584726 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( } while (((Data & 0x30) !=3D 0x030) && (Timeout)); DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Timeout=3D%d\n", D= ata, Timeout)); - if ((Data & 0x30) !=3D 0x30) { - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data)); - return EFI_DEVICE_ERROR; - } - if ((Data & 0x80) !=3D 0x80) { DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=3D%x)\n", Data)= ); return EFI_UNSUPPORTED; diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegme= ntLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentL= ib.c index 6d15e82fa2..b627e5730b 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c @@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase ( return 0xFFFFFFFF; } + /* Don't probe slots if the link is down */ + Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); + if ((Data & 0x30) !=3D 0x30) { + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data= )); + return 0xFFFFFFFF; + } + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); mPciSegmentLastAccess =3D Address; } -- 2.13.7 --_000_PH0PR05MB87027DB6D0AA6EDA562B46E6B9C19PH0PR05MB8702namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
From: Jeremy Linton <jer= emy.linton@arm.com>
Sent: Thursday, August 19, 2021 11:16 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <= ;ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com&= gt;; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@ar= m.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton= @arm.com>
Subject: [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check = into the cfg accessor
 
The existing code fails to create/finish configuri= ng the
pcie subsystem if it fails to get a linkup. This is reasonable
on the RPi4 because it generally won't happen, and the OS
could not see the root port. Now that the OS can see the
root port, its a bit odd if it only shows up when
something is plugged into the first slot. Lets move the
link up check into the config accessor where it will be used
to restrict sending CFG TLP's out the port when nothing is
plugged in. Thus avoiding a SERROR during probe.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
 .../Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c = ;  | 5 -----
 .../Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c&nbs= p; | 7 +++++++
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm27= 11PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711P= ciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
   } while (((Data & 0x30) !=3D 0x030) && (Timeout));=
   DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Tim= eout=3D%d\n", Data, Timeout));
 
-  if ((Data & 0x30) !=3D 0x30) {
-    DEBUG ((DEBUG_ERROR, "PCIe link not ready (status= =3D%x)\n", Data));
-    return EFI_DEVICE_ERROR;
-  }
-
   if ((Data & 0x80) !=3D 0x80) {
     DEBUG ((DEBUG_ERROR, "PCIe link not in RC mod= e (status=3D%x)\n", Data));
     return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegme= ntLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentL= ib.c
index 6d15e82fa2..b627e5730b 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c=
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c=
@@ -105,6 +105,13 @@ PciSegmentLibGetConfigBase (
           return 0xFFFFF= FFF;
       }
 
+      /* Don't probe slots if the link is down */=
+      Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_M= ISC_PCIE_STATUS);
+      if ((Data & 0x30) !=3D 0x30) {
+          DEBUG ((DEBUG_ERROR= , "PCIe link not ready (status=3D%x)\n", Data));
+          return 0xFFFFFFFF;<= br> +      }
+
       MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_= CFG_INDEX, Address);
       mPciSegmentLastAccess =3D Address;
     }
--
2.13.7

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