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boundary="_000_PH0PR05MB8702E31339A2A814120A4062B9F39PH0PR05MB8702namp_" --_000_PH0PR05MB8702E31339A2A814120A4062B9F39PH0PR05MB8702namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Ok, I misunderstood the patch set (I thought the PciHostBridgeLib itself wo= uld eventually move to DEN0115). I still think that (in general) would be a good idea - if not for the benef= it of the Pi, then for the next upstreamed platform where you could avoid i= mplementing custom config access code... Reviewed-by: Andrei Warkentin -- Andrei Warkentin, Arm Enablement Architect, Cloud Platform Business Unit, VMware ________________________________ From: Andrei Warkentin Sent: Friday, August 6, 2021 7:02 PM To: devel@edk2.groups.io ; jeremy.linton@arm.com Cc: pete@akeo.ie ; ardb+tianocore@kernel.org ; Sunny.Wang@arm.com ; samer.el-haj-mahmoud@= arm.com ; Ren=E9 Treffer Subject: Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe = for CM4 Hi Jeremy, Is any of this still conceptually necessary if we adopt the SMCCC interface= within UEFI? Instead of assuming the first downstream bus is bus 1, could you read the s= econdary BN from the RP? -- Andrei Warkentin, Arm Enablement Architect, Cloud Platform Business Unit, VMware ________________________________ From: devel@edk2.groups.io on behalf of Jeremy Linto= n via groups.io Sent: Thursday, August 5, 2021 7:35 PM To: devel@edk2.groups.io Cc: pete@akeo.ie ; ardb+tianocore@kernel.org ; Andrei Warkentin ; Sunny.Wang@arm.com <= Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com ; Jeremy Linton ; Ren=E9 Treffer Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for = CM4 The CM4 has an actual pcie slot, so we need to move the linkup check to the configuration probe logic. Further the device restriction logic needs to be relaxed to support downstream PCIe switches. Suggested-by: Ren=E9 Treffer Signed-off-by: Jeremy Linton --- .../Bcm2711PciHostBridgeLibConstructor.c | 5 ----- .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++---= ---- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm27= 11PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711P= ciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c index 8587d2d36d..4d4c584726 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( } while (((Data & 0x30) !=3D 0x030) && (Timeout)); DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Timeout=3D%d\n", D= ata, Timeout)); - if ((Data & 0x30) !=3D 0x30) { - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data)); - return EFI_DEVICE_ERROR; - } - if ((Data & 0x80) !=3D 0x80) { DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=3D%x)\n", Data)= ); return EFI_UNSUPPORTED; diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegme= ntLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentL= ib.c index 44ce3b4b99..3ccc131eab 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c @@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase ( UINT64 Base; UINT64 Offset; UINT32 Dev; + UINT32 Bus; + UINT32 Data; Base =3D PCIE_REG_BASE; Offset =3D Address & 0xFFF; /* Pick off the 4k register offset *= / @@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase ( Base +=3D PCIE_EXT_CFG_DATA; if (mPciSegmentLastAccess !=3D Address) { Dev =3D EFI_PCI_ADDR_DEV (Address); + Bus =3D EFI_PCI_ADDR_BUS (Address); + /* - * Scan things out directly rather than translating the "bus" to a d= evice, etc.. - * only we need to limit each bus to a single device. + * There can only be a single device on bus 1 (downstream of root). + * Subsequent busses (behind a PCIe switch) can have more. */ - if (Dev < 1) { - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); - mPciSegmentLastAccess =3D Address; - } else { - mPciSegmentLastAccess =3D 0; + if (Dev > 0 && (Bus < 2)) { return 0xFFFFFFFF; } + + /* Don't probe slots if the link is down */ + Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); + if ((Data & 0x30) !=3D 0x30) { + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data= )); + return 0xFFFFFFFF; + } + + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); + mPciSegmentLastAccess =3D Address; } } return Base + Offset; -- 2.13.7 --_000_PH0PR05MB8702E31339A2A814120A4062B9F39PH0PR05MB8702namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Ok, I misunderstood the patch set (I thought the PciHostBridgeLib itse= lf would eventually move to DEN0115).

I still think that (in general) would be a good idea - if not for the benef= it of the Pi, then for the next upstreamed platform where you could avoid i= mplementing custom config access code...

Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
From: Andrei Warkentin <= awarkentin@vmware.com>
Sent: Friday, August 6, 2021 7:02 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; jeremy.linton= @arm.com <jeremy.linton@arm.com>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <= ;ardb+tianocore@kernel.org>; Sunny.Wang@arm.com <Sunny.Wang@arm.com&g= t;; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Ren= =E9 Treffer <treffer+groups.io@measite.de>
Subject: Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Twea= k PCIe for CM4
 
Hi Jeremy,

Is any of this still conceptually necessary if we adopt the SMCCC interface= within UEFI?

Instead of assuming the first downstream bus is bus 1, could you read the s= econdary BN from the RP?

--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
From: devel@edk2.groups.i= o <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <= ;jeremy.linton=3Darm.com@groups.io>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <= ;ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com&= gt;; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@ar= m.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton= @arm.com>; Ren=E9 Treffer <treffer+groups.io@measite.de>
Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PC= Ie for CM4
 
The CM4 has an actual pcie slot, so we need to m= ove the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.

Suggested-by: Ren=E9 Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
 .../Bcm2711PciHostBridgeLibConstructor.c     = ;      |  5 -----
 .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c   | 24 +++= ++++++++++++-------
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm27= 11PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711P= ciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHo= stBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
   } while (((Data & 0x30) !=3D 0x030) && (Timeout));=
   DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Tim= eout=3D%d\n", Data, Timeout));
 
-  if ((Data & 0x30) !=3D 0x30) {
-    DEBUG ((DEBUG_ERROR, "PCIe link not ready (status= =3D%x)\n", Data));
-    return EFI_DEVICE_ERROR;
-  }
-
   if ((Data & 0x80) !=3D 0x80) {
     DEBUG ((DEBUG_ERROR, "PCIe link not in RC mod= e (status=3D%x)\n", Data));
     return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegme= ntLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentL= ib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c=
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c=
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
   UINT64        Base;
   UINT64        Offset;
   UINT32        Dev;
+  UINT32        Bus;
+  UINT32        Data;
 
   Base =3D PCIE_REG_BASE;
   Offset =3D Address & 0xFFF;     &= nbsp;   /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
     Base +=3D PCIE_EXT_CFG_DATA;
     if (mPciSegmentLastAccess !=3D Address) {
       Dev =3D EFI_PCI_ADDR_DEV (Address); +      Bus =3D EFI_PCI_ADDR_BUS (Address);
+     
       /*
-       * Scan things out directly rather tha= n translating the "bus" to a device, etc..
-       * only we need to limit each bus to a= single device.
+       * There can only be a single device o= n bus 1 (downstream of root).
+       * Subsequent busses (behind a PCIe sw= itch) can have more.
        */
-      if (Dev < 1) {
-          MmioWrite32 (PCIE_R= EG_BASE + PCIE_EXT_CFG_INDEX, Address);
-          mPciSegmentLastAcce= ss =3D Address;
-      } else {
-          mPciSegmentLastAcce= ss =3D 0;
+      if (Dev > 0 && (Bus < 2)) {            return 0xFFFFF= FFF;
       }
+
+      /* Don't probe slots if the link is down */=
+      Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_M= ISC_PCIE_STATUS);
+      if ((Data & 0x30) !=3D 0x30) {
+          DEBUG ((DEBUG_ERROR= , "PCIe link not ready (status=3D%x)\n", Data));
+          return 0xFFFFFFFF;<= br> +      }
+
+      MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_I= NDEX, Address);
+      mPciSegmentLastAccess =3D Address;
     }
   }
   return Base + Offset;
--
2.13.7






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