From: "manickavasakam karpagavinayagam" <manickavasakamk@ami.com>
To: "Oram, Isaac W" <isaac.w.oram@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
Harikrishna Doppalapudi <Harikrishnad@ami.com>,
Manish Jha <manishj@ami.com>, Zachary Bobroff <zacharyb@ami.com>
Subject: Re: [EXTERNAL] RE: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.
Date: Tue, 7 Dec 2021 17:01:36 +0000 [thread overview]
Message-ID: <PH0PR10MB4408BC29589FF59C9A4524DABB6E9@PH0PR10MB4408.namprd10.prod.outlook.com> (raw)
In-Reply-To: <MW3PR11MB47473655C0654BB4DB3E464AD06E9@MW3PR11MB4747.namprd11.prod.outlook.com>
Isaac :
Thank you for your review comments. Please see the inline response and provide your comments if there is any.
-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@intel.com>
Sent: Monday, December 6, 2021 7:43 PM
To: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Harikrishna Doppalapudi <Harikrishnad@ami.com>; Manish Jha <manishj@ami.com>; Zachary Bobroff <zacharyb@ami.com>; Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Subject: [EXTERNAL] RE: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.
**CAUTION: The e-mail below is from an external source. Please exercise caution before opening attachments, clicking links, or following guidance.**
Manic,
Please run python \edk2\BaseTools\Scripts\PatchCheck.py -1 to verify your commit passes recommendations and fix the issues that this script highlights. This is documented somewhere in edk2 development process.
edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\JunctionCity\Library\IpmiPlatformHookLib\IpmiPlatformHookLib.c: Coding style issues:
- Line 22: Missing space before ( in "PlatformIpmiIoRangeSet("
- Line 47: Missing space after ,
Function comment block doesn't match current coding standards/style. Block is after prototype and not using doxygen identifiers.
[Manic] : We will correct it.
edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\JunctionCity\Library\PeiPlatformHookLib\PeiPlatformHooklib.c: Coding style
- Line 23: Missing line containing VOID, ) not indented
- Line 26 and 40: Missing space before (
- Line 37: Missing line containing VOID
- Line 25: Status not used for anything. I believe that this can cause compiler errors for some static analysis checks.
[Manic] : We will correct it.
edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo: Design suggestion.
- This is optional for you to implement. The underlying design is not very extensible. It might be nicer for all future derivative boards if there is an option to force it at build via a board ID FixedAtBuild PCD. Maybe a UINT8 with default 0x00. Then modify board detection to only get GPIO if it is zero, otherwise use the build value and skip detection. Then you don't have to maintain your own copy of this PEIM.
[Manic] : We will modify edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\Platform\Pei\PlatformInfo\PlatformInfo.c GetPlatformInfo() to check build time boardId PCD. If it is zero, regular code flow will be executed.
If not, we will use the build time boardID Pcd and return from the start of the function.
edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h
- I am not a lawyer, but I don't believe it is correct to add copyright to something that has not been changed from the original.
[Manic] : Will remove the copyright if the file content is not changed.
edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\JunctionCity\build_board.py
- typo JuctioCity
[Manic] : We will correct the typo
- It might be nicer to add this to the build_board.py that is used to build all the other Platform\Intel boards to be consistent. That would be good to discuss with Nate who knows this code better.
[Manic] : build_board.py is maintained separately for WilsonCityRvp/CooperCityRvp in the respective folders edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\WilsonCityRvp or CooperCityRvp. We followed the same and I believe this is a good approach.
edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
- We don't want to make these ever expanding. The problem is that if each board includes these, they get a large number of unnecessary components. I think that you want to either make custom copies in JunctionCity/Include/Dsc and /Fdf, or just put into your PlatformPkg.dsc and .fdf directly.
[Manic] : We will remove and move the changes from UbaRpBoards.dsc/ UbaDxeRpBoards.fdf to JunctionCity PlatformPkg.dsc and .fdf.
But TypeJunctionCity UBA folder will be present in the same location edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\Uba\UbaMain as like others TypeCooperCityRP, TypeWilsonCityRP and TypeWilsonCitySMT.
edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
- Typo: TypeJunctioCity
[Manic] : We will remove TypeJunctioCity.
edk2-platforms/Platform/Intel/Readme.md
- Line 63 is not needed. Line 62 identifies the family of boards, Junction City is just a board within the family. Please remove this line.
[Manic] : We will remove the line
edk2-platforms/Readme.md
- Line 251 is not needed, please do not add.
[Manic] : We will remove the line
The current implementation of PlatformPkg.dsc is ok. This feedback is optional for you to implement. However, you can include the WhitleyOpenBoardPkg\PlatformPkg.dsc and avoid a lot of duplicate code. I attached a patch with a sample of what that would look like. I did not get it fully building with IPMI and network advanced features. That should just take a little time to debug. Some issues with one or both of those advanced features interacting with other DSC content. Anyway, you can see that this is much simpler and shows only the differences from the parent reference board. It is not as easy to do the same thing with FDF, so we plan to break that content up in the future to make it sensible to modify reasonably.
[Manic] : Agreed. We will include WhitleyOpenBoardPkg\PlatformPkg.dsc in our JunctionCity\PlatformPkg.dsc and leave the FDF file as it is.
Regards,
Isaac
-----Original Message-----
From: manickavasakam karpagavinayagam <mailto:manickavasakamk@ami.com>
Sent: Monday, November 29, 2021 3:15 PM
To: mailto:devel@edk2.groups.io
Cc: Desimone, Nathaniel L <mailto:nathaniel.l.desimone@intel.com>; Oram, Isaac W <mailto:isaac.w.oram@intel.com>; DOPPALAPUDI, HARIKRISHNA <mailto:harikrishnad@ami.com>; Jha, Manish <mailto:manishj@ami.com>; Bobroff, Zachary <mailto:zacharyb@ami.com>; KARPAGAVINAYAGAM, MANICKAVASAKAM <mailto:manickavasakamk@ami.com>
Subject: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.
Support for JunctionCity Platform
- Add JunctionCity UBA's (Except GpioTable.c, IioBifurInit.c), all
other files in UBA folder are just name replacement (replaced TypeWilsonCity with TypeJunctionCity)
- Disabled Intel ME IDE-R devices, KT devices to avoid BIOS POST time
- JunctionCity has different SKU's. Apart from reading the GPIO's always forcing
board id to JunctionCity in GetPlatformInfo()
Cc: Nate DeSimone <mailto:nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <mailto:isaac.w.oram@intel.com>
Cc: Harikrishna Doppalapudi <mailto:harikrishnad@ami.com>
Cc: Manish Jha <mailto:manishj@ami.com>
Cc: Manickavasakam Karpagavinayagam <mailto:manickavasakamk@ami.com>
Cc: Zachary Bobroff <mailto:zacharyb@ami.com>
Signed-off-by: Manickavasakam Karpagavinayagam <mailto:manickavasakamk@ami.com>
---
Platform/Intel/Readme.md | 12 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc | 2 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c | 60 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf | 32 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c | 92 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf | 35 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.c | 741 +++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h | 90 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.inf | 64 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc | 996 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf | 821 ++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py | 127 +++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg | 37 +
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 1 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c | 11 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf | 2 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf | 8 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 100 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 119 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 116 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 58 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 128 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 45 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/AcpiTablePcds.c | 54 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/GpioTable.c | 296 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/IioBifurInit.c | 242 +++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/KtiEparam.c | 69 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PcdData.c | 275 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PchEarlyUpdate.c | 93 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInit.h | 78 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.c | 157 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf | 167 ++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SlotTable.c | 172 ++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SoftStrapFixup.c | 121 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/UsbOC.c | 127 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc | 9 +
Platform/Intel/build.cfg | 1 +
Readme.md | 1 +
Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h | 2 +
42 files changed, 5684 insertions(+)
diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index 965009ce21..dd02d1526d 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -60,6 +60,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
* The `CometlakeOpenBoardPkg` contains board implementations for CometLake systems.
* The `TigerlakeOpenBoardPkg` contains board implementations for TigerLake systems.
* The `WhitleyOpenBoardPkg` contains board implementations for Ice Lake-SP and Cooper Lake systems.
+* The `WhitleyOpenBoardPkg` contains board implementations for JunctionCity systems.
### **Supported Hardware**
@@ -89,6 +90,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
| TGL-U DDR4 RVP | TigerLake | TigerlakeOpenBoardPkg | TigerlakeURvp |
| Wilson City RVP | IceLake-SP (Xeon Scalable) | WhitleyOpenBoardPkg | WilsonCityRvp |
| Cooper City RVP | Copper Lake | WhitleyOpenBoardPkg | CooperCityRvp |
+| JunctionCity | IceLake-SP (Xeon Scalable) | WhitleyOpenBoardPkg | JunctionCity |
*Note: RVP = Reference and Validation Platform*
@@ -392,6 +394,16 @@ For PurleyOpenBoardPkg (TiogaPass)
**WhitleyOpenBoardPkg**
1. This firmware project has been tested booting to UEFI shell with headless serial console
+**JunctionCity**
+1. This firmware project has been tested booting to UEFI shell
+2. Booted to RHEL 8.2, Ubuntu 18.04 using U2 NVME Disk
+3. Booted to Windows 2019 using M2 SSD Disk
+4. Connected PCIE Network card and made sure PCIE card detected in POST and in OS
+5. Verified TPM offboard chip detection
+
+### **Known limitations**
+1. System boots very slow when booting to RHEL 8.2 OS using SATA drive
+
### **Package Builds**
In some cases, such as BoardModulePkg, a package may provide a set of functionality that is included in other
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
index 99ab0961ca..05d140898f 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
@@ -2,6 +2,7 @@
# Platform description.
#
# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -133,5 +134,6 @@
}
SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf
SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf
+ SecurityPkg/Tcg/Tcg2Acpi/Tcg2Acpi.inf
!endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c
new file mode 100644
index 0000000000..680b0ac6b7
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c
@@ -0,0 +1,60 @@
+/** @file
+ This file implements the IPMI Platform hook functions
+
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#define KCS_BASE_ADDRESS_MASK 0xFFF0
+#define NUMBER_OF_BYTES_TO_DECODE 0x10
+
+//
+// Prototype definitions for IPMI Platform Update Library
+//
+
+EFI_STATUS
+EFIAPI
+PlatformIpmiIoRangeSet(
+ UINT16 IpmiIoBase
+)
+/*++
+
+ Routine Description:
+
+ This function sets IPMI Io range
+
+ Arguments:
+
+ IpmiIoBase
+
+ Returns:
+
+ Status
+
+--*/
+{
+
+ EFI_STATUS Status;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi;
+
+ DynamicSiLibraryPpi = NULL;
+
+ DEBUG ((EFI_D_INFO, "PlatformIpmiIoRangeSet IpmiIoBase %x\n",IpmiIoBase));
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "PeiServicesLocatePpi for gDynamicSiLibraryPpiGuid failed. Status %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IpmiIoBase & KCS_BASE_ADDRESS_MASK), NUMBER_OF_BYTES_TO_DECODE);
+
+ return EFI_SUCCESS;
+
+}
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
new file mode 100644
index 0000000000..699d89b24a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Component description file for IPMI platform hook Library.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IpmiPlatformHookLib
+ FILE_GUID = A770BDB8-331A-4110-8B60-81FC17480B36
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IpmiPlatformHookLib
+
+[sources]
+ IpmiPlatformHookLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Ppis]
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Depex]
+ gDynamicSiLibraryPpiGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
new file mode 100644
index 0000000000..d2ccfebc43
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
@@ -0,0 +1,92 @@
+/** @file
+ PEI Library Functions. Initialize GPIOs
+
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/DebugLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <Library/PeiPlatformHooklib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+/**
+ Configure GPIO
+
+ @param[in] PlatformInfo
+**/
+VOID
+GpioInit (
+)
+{
+ EFI_STATUS Status;
+ Status = PlatformInitGpios();
+}
+
+/**
+ Disables ME PCI devices like IDE-R , KT
+
+ @param[in] None
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+DisableMEDevices (
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi;
+
+ DynamicSiLibraryPpi = NULL;
+
+ DEBUG ((DEBUG_INFO, "DisableMEDevices\n"));
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ //Disable IDE-R
+ //
+ DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+ PID_PSF1,
+ (R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+ (UINT32)~0,
+ B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+ );
+
+ //
+ //Disable KT
+ //
+ DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+ PID_PSF1,
+ (R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+ (UINT32)~0,
+ B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+ );
+ return EFI_SUCCESS;
+
+}
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInit (
+ )
+{
+
+ GpioInit();
+ DisableMEDevices ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
new file mode 100644
index 0000000000..fb3985c4e0
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
@@ -0,0 +1,35 @@
+## @file
+#
+# @copyright
+# Copyright 1999 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiPlatformHookLib
+ FILE_GUID = 6E9351C3-A17A-4ADF-8602-55B07962718F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiPlatformHookLib|PEIM PEI_CORE SEC
+
+[Sources]
+ PeiPlatformHooklib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ UbaGpioInitLib
+
+[Pcd]
+
+[Ppis]
+
+[Guids]
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.c
new file mode 100644
index 0000000000..acc9605df2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.c
@@ -0,0 +1,741 @@
+/** @file
+ Platform Info PEIM.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformInfo.h"
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Library/PchInfoLib.h>
+
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+#include <Library/UbaGpioPlatformConfig.h>
+#include <UncoreCommonIncludes.h>
+#include <PlatformInfoTypes.h>
+
+#include <Library/PeiServicesLib.h>
+
+#define TEMP_BUS_NUMBER (0x3F)
+
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformInfoPpi = {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPlatformInfoGuid,
+ NULL
+ };
+
+#define BOARD_ID_GPIO_PADS_NUMBER 6
+#define BOARD_REV_ID_GPIO_PADS_NUMBER 3
+
+//
+// These pads shall not be board specific as these are used for Board ID and Rev ID detection
+// Therefore can not be moved to UBA and are common for all Purley boards
+//
+GPIO_PAD mBoardId [BOARD_ID_GPIO_PADS_NUMBER] = {
+ // BoardId pads - PADCFG register for GPIO G12
+ // WARNING: The pad number must be obtained from board schematics
+ GPIO_SKL_H_GPP_G12,
+ GPIO_SKL_H_GPP_G13,
+ GPIO_SKL_H_GPP_G14,
+ GPIO_SKL_H_GPP_G15,
+ GPIO_SKL_H_GPP_G16,
+ GPIO_SKL_H_GPP_B19
+};
+
+GPIO_PAD mBoardRevId [BOARD_REV_ID_GPIO_PADS_NUMBER] = {
+ // Board RevId pads - Start from pad C12
+ // WARNING: This should be obtained from board schematics
+ GPIO_SKL_H_GPP_C12,
+ GPIO_SKL_H_GPP_C13,
+ GPIO_SKL_H_GPP_B9
+};
+
+GPIO_CONFIG mBoardAndRevIdConfig = {
+ // Board and Revision ID pads configuration required for proper reading the values
+ GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
+ GpioPlatformReset, GpioTermDefault, GpioLockDefault, GpioRxRaw1Default
+};
+
+
+VOID
+GpioConfigForBoardId (
+ VOID
+ )
+{
+ UINT8 i;
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;
+ PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;
+ PadConfig.Direction = mBoardAndRevIdConfig.Direction;
+ PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;
+ PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;
+ PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;
+ PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;
+ PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;
+ PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardId[i], &PadConfig);
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+
+VOID
+GpioConfigForBoardRevId (
+ VOID
+ )
+{
+ UINT8 i;
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;
+ PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;
+ PadConfig.Direction = mBoardAndRevIdConfig.Direction;
+ PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;
+ PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;
+ PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;
+ PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;
+ PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;
+ PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardRevId[i], &PadConfig);
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+/**
+
+ Reads GPIO pins to get Board ID value
+
+ @retval Status - Success if GPIO's are read properly
+
+**/
+EFI_STATUS
+GpioGetBoardId (
+ OUT UINT32 *BoardId
+ )
+{
+ EFI_STATUS Status = EFI_DEVICE_ERROR;
+ UINT32 Data32;
+ UINT8 i;
+ UINT32 BdId;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ if (BoardId == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ BdId = 0;
+
+ GpioConfigForBoardId ();
+
+ for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardId[i], &Data32);
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+ if (Data32) {
+ BdId = BdId | (1 << i);
+ }
+ }
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+ *BoardId = BdId;
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Reads GPIO pins to get Board Revision ID value
+
+ @retval Status - Success if GPIO's are read properly
+
+**/
+EFI_STATUS
+GpioGetBoardRevId (
+ OUT UINT32 *BoardRevId
+ )
+{
+ EFI_STATUS Status = EFI_DEVICE_ERROR;
+ UINT32 Data32;
+ UINT8 i;
+ UINT32 RevId;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ if (BoardRevId == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ RevId = 0;
+
+ GpioConfigForBoardRevId ();
+
+ for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++){
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardRevId[i], &Data32);
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+ if (Data32) {
+ RevId = RevId | (1 << i);
+ }
+ }
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+ *BoardRevId = RevId;
+ return EFI_SUCCESS;
+
+}
+
+/**
+
+ Returns the Model ID of the CPU.
+ Model ID = EAX[7:4]
+
+**/
+VOID
+GetCpuInfo (
+ UINT32 *CpuType,
+ UINT8 *CpuStepping
+ )
+
+{
+ UINT32 RegEax=0;
+
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
+
+ *CpuStepping = (UINT8) (RegEax & 0x0F);
+ *CpuType = (UINT32) (RegEax >> 4);
+}
+
+
+/**
+
+ GC_TODO: add routine description
+
+ @param BAR - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval None
+
+**/
+VOID
+InitGSX(
+ UINT32 *BAR,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param Data - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+ @retval EFI_UNSUPPORTED - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+GsxRead(
+ UINT32 *Data,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param Data - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval None
+
+**/
+VOID
+GetGsxBoardID(
+ BOARD_ID *Data,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+
+ EFI_STATUS Status;
+ UINT32 GSXIN[2];
+ UINT32 RetryCount;
+
+ RetryCount = 0;
+ GSXIN[0] = 0;
+ GSXIN[1] = 0;
+
+ do {
+ Status = GsxRead(GSXIN, PeiServices);
+
+ if(Status){
+ // if EFI_SUCCESS != Success then retry one more time
+ RetryCount ++;
+ }else{
+ // if EFI_SUCCESS read Board ID and exit
+ RetryCount = 0xFFFFFFFF;
+ }
+
+ if (GSXIN[0] & BIT0) {
+ Data->BoardID.BoardID0 = 1;
+ }
+
+ if (GSXIN[0] & BIT1) {
+ Data->BoardID.BoardID1 = 1;
+ }
+
+ if (GSXIN[0] & BIT2) {
+ Data->BoardID.BoardID2 = 1;
+ }
+
+ if (GSXIN[0] & BIT3) {
+ Data->BoardID.BoardID3 = 1;
+ }
+
+ if (GSXIN[0] & BIT4) {
+ Data->BoardID.BoardID4 = 1;
+ }
+
+ if (GSXIN[0] & BIT5) {
+ Data->BoardID.BoardRev0 = 1;
+ }
+
+ if (GSXIN[0] & BIT6) {
+ Data->BoardID.BoardRev1 = 1;
+ }
+
+ } while(RetryCount < 1);
+
+ if(Status){
+ //
+ // Unhable to read GSX HW error Hang the system
+ //
+ DEBUG ((EFI_D_ERROR, "ERROR: GSX HW is unavailable, SYSTEM HANG\n"));
+ CpuDeadLoop ();
+ }
+}
+
+/**
+ Get Platform Type by read Platform Data Region in SPI flash.
+ SPI Descriptor Mode Routines for Accessing Platform Info from Platform Data Region (PDR)
+
+ @param PeiServices - General purpose services available to every PEIM.
+ @param PlatformInfoHob - Platform Type is returned in PlatformInfoHob->BoardId
+
+ @retval Status EFI_SUCCESS - PDR read success
+ @retval Status EFI_INCOMPATIBLE_VERSION - PDR read but it is not valid Platform Type
+
+**/
+EFI_STATUS
+PdrGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ EFI_STATUS Status;
+ PCH_SPI_PROTOCOL *SpiPpi;
+ UINTN Size;
+
+ //
+ // Locate the SPI PPI Interface
+ //
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gPchSpiPpiGuid,
+ 0,
+ NULL,
+ &SpiPpi
+ );
+
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ // Read the PIT (Platform Info Table) from the SPI Flash Platform Data Region
+ //
+ Size = sizeof (EFI_PLATFORM_INFO);
+ Status = SpiPpi->FlashRead (
+ SpiPpi,
+ FlashRegionPlatformData,
+ PDR_REGION_START_OFFSET,
+ (UINT32) Size,
+ (UINT8 *) PlatformInfoHob
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ if ((PlatformInfoHob->BoardId >= TypePlatformMin) && (PlatformInfoHob->BoardId <= TypePlatformMax)) {
+ //
+ // Valid Platform Identified
+ //
+ DEBUG ((DEBUG_INFO, "Platform Info from PDR: Type = %x\n",PlatformInfoHob->BoardId));
+ } else {
+ //
+ // Reading PIT from SPI PDR Failed or a unknown platform identified
+ //
+ DEBUG ((EFI_D_ERROR, "PIT from SPI PDR reports Platform ID as %x. This is unknown ID. Assuming Greencity Platform!\n", PlatformInfoHob->BoardId));
+ PlatformInfoHob->BoardId = TypePlatformUnknown;
+ Status = EFI_INCOMPATIBLE_VERSION;
+ }
+ return Status;
+}
+
+VOID
+GatherQATInfo(OUT EFI_PLATFORM_INFO *PlatformInfoHob)
+/**
+
+ GC_TODO: add routine description
+
+ @param None
+
+ @ret None
+**/
+{
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ // Gpio programming to QAT board detection
+ PadConfig.PadMode = GpioPadModeGpio;
+ PadConfig.HostSoftPadOwn = GpioHostOwnDefault;
+ PadConfig.Direction = GpioDirIn;
+ PadConfig.OutputState = GpioOutLow;
+ PadConfig.InterruptConfig = GpioIntDis;
+ PadConfig.PowerConfig = GpioResetPwrGood;
+ PadConfig.ElectricalConfig = GpioTermNone;
+ PadConfig.LockConfig = GpioPadConfigLock;
+ PadConfig.OtherSettings = 00;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B3, &PadConfig);
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B3, &PlatformInfoHob->QATDis);
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B4, &PadConfig);
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B4, &PlatformInfoHob->QATSel);
+}
+
+EFI_STATUS
+GetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiServices - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_UNSUPPORTED - GC_TODO: add retval description
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+{
+
+
+ UINT32 BoardId;
+ UINT32 BoardRev;
+ EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;
+ EFI_STATUS Status;
+
+ PciCfgPpi = (**PeiServices).PciCfg;
+ ASSERT (PciCfgPpi != NULL);
+
+ PlatformInfoHob->BoardId = TypeNeonCityEPRP;
+ DEBUG ((DEBUG_INFO, "Use GPIO to read Board ID\n"));
+
+ Status = GpioGetBoardId (&BoardId);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));
+ return Status;
+ }
+ Status = GpioGetBoardRevId (&BoardRev);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));
+ return Status;
+ }
+ PlatformInfoHob->TypeRevisionId = BoardRev;
+
+ //
+ //Forcing the Board id to JunctionCity
+ //
+ PlatformInfoHob->BoardId = TypeJunctionCity;
+ DEBUG ((DEBUG_INFO, "Board ID = TypeJunctionCity\n"));
+
+ GatherQATInfo(PlatformInfoHob);
+
+ DEBUG ((DEBUG_INFO, "Board Rev.: %d\n", BoardRev));
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function initializes the board related flag to indicates if
+ PCH and Lan-On-Motherboard (LOM) devices is supported.
+
+**/
+VOID
+GetPchLanSupportInfo(
+ IN EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ PlatformInfoHob->PchData.LomLanSupported = 0;
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiVariable - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+EFIAPI
+GetIioCommonRcPlatformSetupPolicy(
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+ {
+ UINT8 IsocEn;
+
+ CopyMem (&IsocEn, (UINT8 *)PcdGetPtr(PcdSocketCommonRcConfig) + OFFSET_OF(SOCKET_COMMONRC_CONFIGURATION, IsocEn), sizeof(UINT8));
+
+ PlatformInfoHob->SysData.IsocEn = IsocEn; // ISOC enabled
+
+ return EFI_SUCCESS;
+}
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiVariable - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+EFIAPI
+GetIioPlatformSetupPolicy(
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Platform Type detection. Because the PEI globle variable
+ is in the flash, it could not change directly.So use
+ 2 PPIs to distinguish the platform type.
+
+ @param FfsHeader - Pointer to Firmware File System file header.
+ @param PeiServices - General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS - Memory initialization completed successfully.
+ @retval Others - All other error conditions encountered result in an ASSERT.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformInfoInit (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;
+ EFI_PLATFORM_INFO PlatformInfoHob;
+ EFI_PLATFORM_INFO tempPlatformInfoHob;
+ UINT8 ChipId;
+ UINT32 Delay;
+ UINT32 CpuType;
+ UINT8 CpuStepping;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PciCfgPpi = (**PeiServices).PciCfg;
+ if (PciCfgPpi == NULL) {
+ DEBUG ((EFI_D_ERROR, "\nError! PlatformInfoInit() - PeiServices is a NULL Pointer!!!\n"));
+ ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Locate Variable PPI
+ //
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, &PeiVariable);
+
+ (*PeiServices)->SetMem (&PlatformInfoHob, sizeof (PlatformInfoHob), 0);
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ // --------------------------------------------------
+ //
+ // Detect the iBMC SIO for CV/CRB Platforms
+ // 0x2E/0x2F decoding has been enabled in MonoStatusCode PEIM.
+ //
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_UNLOCK);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_CHIP_ID_REG);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ ChipId = IoRead8 (PILOTIV_SIO_DATA_PORT);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_LOCK);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+
+ if (EFI_ERROR (Status))
+ {
+ DEBUG((EFI_D_ERROR, "LocatePpi Error in PlatformInfo.c !\n"));
+ }
+
+ Status = GetIioPlatformSetupPolicy (&PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetIioCommonRcPlatformSetupPolicy (&PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update PCH Type
+ //
+ PlatformInfoHob.PchType = DynamicSiLibraryPpi->GetPchSeries ();
+ PlatformInfoHob.PchSku = DynamicSiLibraryPpi->GetPchLpcDeviceId ();
+ PlatformInfoHob.PchRevision = (UINT8) DynamicSiLibraryPpi->PchStepping ();
+ PlatformInfoHob.MaxNumOfPchs = 1;
+ Status = EFI_SUCCESS;
+
+ if(!EFI_ERROR(Status)) {
+ Status = GetPlatformInfo (PeiServices, &PlatformInfoHob);
+ if(EFI_ERROR (Status)) {
+ Status = PdrGetPlatformInfo (PeiServices, &tempPlatformInfoHob);
+ PlatformInfoHob.BoardId = tempPlatformInfoHob.BoardId;
+ PlatformInfoHob.TypeRevisionId = tempPlatformInfoHob.TypeRevisionId;
+ if (EFI_ERROR(Status)) {
+ PlatformInfoHob.BoardId = TypePlatformUnknown;
+ }
+ }
+ } else {
+ PlatformInfoHob.BoardId = TypePlatformUnknown;
+ }
+
+ //
+ // Update IIO Type
+ //
+ PlatformInfoHob.IioRevision = 0;
+
+
+ //
+ // Get Subtractive decode enable bit from descriptor
+ //
+
+ if (DynamicSiLibraryPpi->PchIsGbeRegionValid () == FALSE) {
+ PlatformInfoHob.PchData.GbeRegionInvalid = 1;
+ } else {
+ PlatformInfoHob.PchData.GbeRegionInvalid = 0;
+ }
+ GetPchLanSupportInfo (&PlatformInfoHob);
+ PlatformInfoHob.PchData.GbePciePortNum = 0xFF;
+ PlatformInfoHob.PchData.GbePciePortNum = (UINT8) DynamicSiLibraryPpi->PchGetGbePortNumber ();
+ PlatformInfoHob.PchData.GbeEnabled = DynamicSiLibraryPpi->PchIsGbePresent ();
+ PlatformInfoHob.PchData.PchStepping = (UINT8) DynamicSiLibraryPpi->PchStepping ();
+
+ PlatformInfoHob.SysData.SysSioExist = (UINT8)IsSioExist();
+
+ GetCpuInfo (&CpuType, &CpuStepping);
+ PlatformInfoHob.CpuType = CpuType;
+ PlatformInfoHob.CpuStepping = CpuStepping;
+
+ //
+ // Set default memory topology to DaisyChainTopology. This should be modified in UBA board
+ // specific file.
+ //
+ (*PeiServices)->SetMem (&PlatformInfoHob.MemoryTopology, sizeof (PlatformInfoHob.MemoryTopology), DaisyChainTopology);
+
+ //
+ // Set default memory type connector to DimmConnectorPth. This should be modified in UBA board
+ // specific file.
+ //
+ (*PeiServices)->SetMem (&PlatformInfoHob.MemoryConnectorType, sizeof (PlatformInfoHob.MemoryConnectorType), DimmConnectorPth);
+
+ //
+ // Build HOB for setup memory information
+ //
+ BuildGuidDataHob (
+ &gEfiPlatformInfoGuid,
+ &(PlatformInfoHob),
+ sizeof (EFI_PLATFORM_INFO)
+ );
+
+ Status = (**PeiServices).InstallPpi (PeiServices, &mPlatformInfoPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Save PlatformInfoHob.BoardId in CMOS
+ //
+ IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_LO);
+ IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)PlatformInfoHob.BoardId);
+
+ IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_HI);
+ IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)((PlatformInfoHob.PcieRiser2Type << 4) + (PlatformInfoHob.PcieRiser1Type)));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h
new file mode 100644
index 0000000000..bb00b2cc75
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h
@@ -0,0 +1,90 @@
+/** @file
+ Platform Info Driver.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INFO_INTERNAL_H_
+#define _PLATFORM_INFO_INTERNAL_H_
+
+#include <PiPei.h>
+#include <Ppi/CpuIo.h>
+#include <Ppi/Spi.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PlatformHooksLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Guid/SocketVariable.h>
+#include <Guid/SetupVariable.h>
+#include <Guid/PlatformInfo.h>
+#include <IndustryStandard/Pci22.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Platform.h>
+#include "SioRegs.h"
+#include <Register/PchRegsSpi.h>
+#include <PchAccess.h>
+#include <Register/PchRegsLpc.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Register/Cpuid.h>
+
+#define EFI_PLATFORMINFO_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('P', 'I', 'N', 'F')
+
+//
+// CPU Model
+//
+#define INVALID_MODEL 0x0
+
+#define R_SB_SPI_FDOC 0xB0
+#define R_SB_SPI_FDOD 0xB4
+#define SPI_OPCODE_READ_INDEX 4
+#define PDR_REGION_START_OFFSET 0x0
+
+typedef union BOARD_ID
+{
+ struct{
+ UINT8 BoardID0 :1;
+ UINT8 BoardID1 :1;
+ UINT8 BoardID2 :1;
+ UINT8 BoardID3 :1;
+ UINT8 BoardID4 :1;
+ UINT8 BoardRev0 :1;
+ UINT8 BoardRev1 :1;
+ UINT8 Rsvd :1;
+ }BoardID;
+}BOARD_ID;
+
+typedef union RISER_ID
+{
+ struct{
+ UINT8 RiserID0 :1;
+ UINT8 RiserID1 :1;
+ UINT8 RiserID2 :1;
+ UINT8 RiserID3 :1;
+ UINT8 Rsvd :4;
+ }RiserID;
+}RISER_ID;
+
+
+
+EFI_STATUS
+PdrGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ );
+
+EFI_STATUS
+GPIOGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+);
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.inf
new file mode 100644
index 0000000000..41c072e29e
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.inf
@@ -0,0 +1,64 @@
+## @file
+# PlatformInfo PEIM
+#
+# @copyright
+# Copyright 2009 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformInfo
+ FILE_GUID = 0CEBAC0F-9349-44EC-A2DC-E07F34D412B3
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformInfoInit
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ PlatformInfo.c
+ PlatformInfo.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ PcdLib
+ DebugLib
+ HobLib
+ IoLib
+ PlatformHooksLib
+ PeiServicesLib
+
+[Pcd]
+ gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig
+
+[Guids]
+ gEfiPlatformInfoGuid
+ gEfiSetupVariableGuid
+
+[Ppis]
+ gPchSpiPpiGuid
+ gEfiPeiReadOnlyVariable2PpiGuid
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Depex]
+ gPchSpiPpiGuid AND
+ gEfiPeiReadOnlyVariable2PpiGuid AND
+ gDynamicSiLibraryPpiGuid
+
+
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
new file mode 100644
index 0000000000..62d4ea68b0
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
@@ -0,0 +1,996 @@
+## @file
+# X64 Platform with 64-bit DXE.
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ BOARD_NAME = JunctionCity
+ PLATFORM_NAME = $(BOARD_NAME)
+ PLATFORM_GUID = F5798629-30B2-42EC-A1CA-825FEAA8A22A
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(RP_PKG)
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08
+ FLASH_DEFINITION = $(RP_PKG)/$(BOARD_NAME)/PlatformPkg.fdf
+ PLATFORM_SI_PACKAGE = ClientOneSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE = WhitleySiliconBinPkg
+ PEI_ARCH = IA32
+ DXE_ARCH = X64
+
+!if $(CPUTARGET) == "CPX"
+ DEFINE FSP_BIN_PKG = CedarIslandFspBinPkg
+ DEFINE IIO_INSTANCE = Skx
+!elseif $(CPUTARGET) == "ICX"
+ DEFINE FSP_BIN_PKG = WhitleyFspBinPkg
+ DEFINE IIO_INSTANCE = Icx
+!else
+ DEFINE IIO_INSTANCE = UnknownCpu
+!endif
+
+ #
+ # Platform On/Off features are defined here
+ #
+ !include $(RP_PKG)/PlatformPkgConfig.dsc
+
+ #
+ # MRC common configuration options defined here
+ #
+ !include $(SILICON_PKG)/MrcCommonConfig.dsc
+
+[Packages]
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+
+ !include $(FSP_BIN_PKG)/DynamicExPcd.dsc
+ !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc
+ !include $(RP_PKG)/DynamicExPcd.dsc
+
+ !include $(RP_PKG)/Uba/UbaCommon.dsc
+ !include $(RP_PKG)/Uba/UbaRpBoards.dsc
+
+ !include $(RP_PKG)/Include/Dsc/EnablePerformanceMonitoringInfrastructure.dsc
+
+ !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+# Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
+
+[DefaultStores]
+ 0|STANDARD
+ 1|MANUFACTURING
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag]
+ #
+ # MinPlatform control flags
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE
+
+ # don't degrade 64bit MMIO space to 32-bit
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
+
+ # Server doesn't support capsule update on Reset.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+
+ gEfiCpRcPkgTokenSpaceGuid.Reserved15|TRUE
+
+!if ($(CPUTARGET) == "ICX")
+ gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|FALSE
+!endif # $(CPUTARGET) == "ICX"
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE
+ gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|TRUE
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE
+
+ ## Uncomment for better boot performance
+# gPerfOptTokenSpaceGuid.PcdPreUefiLegacyEnable|FALSE
+# gPerfOptTokenSpaceGuid.PcdLocalVideoEnable|FALSE
+
+ gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE
+
+ ## This PCD specified whether ACPI SDT protocol is installed.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ## This PCD specifies whether FPGA routine will be active
+ gSocketPkgFpgaGuid.PcdSktFpgaActive|TRUE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == TRUE
+ gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|TRUE
+!endif
+
+ ## This PCD specifies whether or not to enable the High Speed UART
+ gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
+
+[PcdsFixedAtBuild]
+ gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption|2
+
+ ## MinPlatform Boot Stage Selector
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ # Stage 6 - boot with advanced features enabled
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6
+
+!if $(TARGET) == "RELEASE"
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # Enable asserts, prints, code, clear memory, and deadloops on asserts.
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # Built in messages: Error, MTRR, info, load, warn, init
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # This is set to INT3 (0x2) for Simics source level debugging
+!endif
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4449204C45544E49 # "INTEL ID"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x2100000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gCpuPkgTokenSpaceGuid.PcdPlatformType|2
+ gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000
+
+ #PcdCpuMicrocodePatchRegionSize = PcdFlashNvStorageMicrocodeSize - (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x1FFF70
+
+ #
+ # This controls the NEM code region cached during SEC
+ # It usually isn't necessary to match exactly the FV layout in the FDF file.
+ # It is a performance optimization to have it match the flash region exactly
+ # as then no extra reads are done to load unused flash into cache.
+ #
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0xFFC00000
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x00400000
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000
+
+ #
+ # Mode | FSP_MODE | PcdFspModeSelection
+ # ------------------|----------|--------------------
+ # FSP Dispatch Mode | 1 | 0
+ # FSP API Mode | 0 | 1
+ #
+!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000
+!else
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
+!endif
+ gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
+
+ #
+ # These will be initialized during build
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x00000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase|0x00000000
+
+ ## Specifies delay value in microseconds after sending out an INIT IPI.
+ # @Prompt Configure delay value after send an INIT IPI
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
+ ## Specifies max supported number of Logical Processors.
+ # @Prompt Configure max supported number of Logical Processorss
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
+
+ gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x2
+
+ gPlatformTokenSpaceGuid.PcdUboDev|0x08
+ gPlatformTokenSpaceGuid.PcdUboFunc|0x02
+ gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
+ gPlatformTokenSpaceGuid.PcdSupportLegacyStack|FALSE
+
+ ## Defines the ACPI register set base address.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Timer IO Port Address
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500
+
+ ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # @Prompt ACPI Hardware PCI Bus Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00
+
+ ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Device Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F
+
+ ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Function Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02
+
+ ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044
+
+ ## Defines the bit mask that must be set to enable the APIC hardware register BAR.
+ # @Prompt ACPI Hardware PCI Bar Enable BitMask
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80
+
+ ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Bar Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040
+
+ ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.
+ # @Prompt Offset to 32-bit Timer register in ACPI BAR
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008
+
+!if $(CPUTARGET) == "ICX"
+ #
+ # ACPI PCD custom override
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013
+!endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET)
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+ # Enable DDRT scheduler debug features for power on
+ gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault|TRUE
+
+ # Disable Fast Warm Boot for Whitley Openboard Package
+ gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault|FALSE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable|FALSE
+!endif
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x74
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x75
+
+ #
+ # PlatformInitPreMem
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA30
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x100
+
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved15|0
+
+ !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc
+
+[PcdsFixedAtBuild.IA32]
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
+!if ($(FSP_MODE) == 0)
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0
+!endif
+
+[PcdsFixedAtBuild.X64]
+ # Change PcdBootManagerMenuFile to UiApp
+ ##
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+ gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0xC00000
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
+
+ #
+ # AcpiPlatform
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08
+
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|FALSE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00}
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}
+ gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x0, 0x0, 0x1F, 0x0}
+ gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x01
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1900
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|9999
+
+[PcdsPatchableInModule]
+ #
+ # These debug options are patcheable so that they can be manipulated during debug (if memory is updateable)
+ #
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 # Enable status codes for debug, progress, and errors
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 # Displayed messages: Error, Info, warn
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0
+
+!if $(PREMEM_PAGE_ALLOC_SUPPORT) == FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0x130000
+!endif
+
+[PcdsDynamicExDefault.IA32]
+!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000
+!endif
+
+
+[PcdsDynamicExHii]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|L"1GPageTable"|gEfiGenericVariableGuid|0x0|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+ gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|L"MemoryCheck"|gPlatformTokenSpaceGuid|0x0|0
+ gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|L"UefiOptimizedBoot"|gCpPlatTokenSpaceGuid|0x0|TRUE
+ gPlatformModuleTokenSpaceGuid.PcdBootState|L"BootState"|gEfiGenericVariableGuid|0x0|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+ gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|L"BootDeviceScratchPad"|gEfiGenericVariableGuid|0x0|FALSE
+
+[PcdsDynamicExDefault]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmPhysicalPresence|TRUE
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE
+ gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable|FALSE
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE
+
+ gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0
+
+ #Platform should change it to by code
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0xAAAA0000
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0xAA33AA22
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE
+
+ #
+ # CPU features related PCDs.
+ #
+ gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle
+ gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x01
+
+ ## Put fTPM guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } }
+ ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc } }
+ ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } }
+
+ #TPM2.0#
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|0
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE
+
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0x102b
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0x0522
+
+ gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x000C
+ gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x0011
+ gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|4
+ gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x600C0
+
+[PcdsDynamicExDefault.X64]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
+
+ #
+ # Set video to 1024x768 resolution
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768
+
+[PcdsDynamicExDefault]
+
+!if $(CPUTARGET) == "CPX"
+ !include $(RP_PKG)/StructurePcdCpx.dsc
+!else
+ !include $(RP_PKG)/StructurePcd.dsc
+!endif
+
+[PcdsFeatureFlag]
+!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |TRUE
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |TRUE
+ gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|TRUE
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |FALSE
+ gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|FALSE
+!endif
+
+[Defines]
+!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
+ DEFINE SECURE_BOOT_ENABLE = TRUE
+!endif
+
+ !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
+!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses]
+
+ #
+ # Simics source level debugging requires the non-null version of PeCoffExtraActionLib
+ #
+!if $(TARGET) == "DEBUG"
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+!else
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+!endif
+
+ #
+ # Basic
+ #
+
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+ #
+ # Framework
+ #
+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+ FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
+
+ SiliconPolicyInitLib|WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf
+!if ($(FSP_MODE) == 0)
+ SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.inf
+!else
+ SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf
+!endif
+
+ SetupLib|WhitleySiliconPkg/Library/SetupLib/SetupLib.inf
+
+ #
+ # ToDo: Can we use BaseAcpiTimerLib from MinPlatform?
+ #
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf
+
+ MultiPlatSupportLib|$(RP_PKG)/Library/MultiPlatSupportLib/MultiPlatSupportLib.inf
+ ReadFfsLib|$(RP_PKG)/Library/ReadFfsLib/ReadFfsLib.inf
+ PlatformSetupVariableSyncLib|$(RP_PKG)/Library/PlatformSetupVariableSyncLibNull/PlatformSetupVariableSyncLibNull.inf
+ PlatformVariableHookLib |$(RP_PKG)/Library/PlatformVariableHookLibNull/PlatformVariableHookLibNull.inf
+
+ PlatformBootManagerLib|$(PLATFORM_PKG)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+ SerialPortLib|$(RP_PKG)/Library/SerialPortLib/SerialPortLib.inf
+ PlatformHooksLib|$(RP_PKG)/Library/PlatformHooksLib/PlatformHooksLib.inf
+
+ CmosAccessLib|BoardModulePkg/Library/CmosAccessLib/CmosAccessLib.inf
+ PlatformCmosAccessLib|$(RP_PKG)/Library/PlatformCmosAccessLib/PlatformCmosAccessLib.inf
+ SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
+ TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
+
+ #
+ # MinPlatform uses port 80, we don't want to assume HW
+ #
+ PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
+
+ TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull.inf
+ Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf
+ AslUpdateLib|$(PLATFORM_PKG)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
+ PciSegmentInfoLib|$(PLATFORM_PKG)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+ PlatformOpromPolicyLib|$(RP_PKG)/Library/PlatformOpromPolicyLibNull/PlatformOpromPolicyLibNull.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
+
+[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+ FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
+ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
+ FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
+ FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+
+ FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
+ FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
+ FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
+
+[LibraryClasses.Common.SEC]
+ #
+ # SEC phase
+ #
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+
+ PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf
+ VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf
+
+[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+ #
+ # ToDo: Can we remove
+ #
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+
+
+ PeiPlatformHookLib|$(RP_PKG)/$(BOARD_NAME)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
+ PlatformClocksLib|$(RP_PKG)/Library/PlatformClocksLib/Pei/PlatformClocksLib.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
+
+ ReportFvLib|$(RP_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf
+
+[LibraryClasses.Common.PEIM]
+ #
+ # Library instance consumed by MinPlatformPkg PlatformInit modules.
+ #
+ ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SetCacheMtrrLib|$(RP_PKG)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+ ResetSystemLib|MdeModulePkg/Library/PeiResetSystemLib/PeiResetSystemLib.inf
+
+!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable == TRUE
+ IpmiPlatformHookLib| $(RP_PKG)/$(BOARD_NAME)/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
+!endif
+
+
+[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+
+ Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.inf
+ TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf
+
+ BiosIdLib|BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+
+ Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf
+ BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf
+ BoardBootManagerLib|MinPlatformPkg/Bds/Library/BoardBootManagerLibNull/BoardBootManagerLibNull.inf
+
+ CompressDxeLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf
+
+[LibraryClasses.Common.DXE_SMM_DRIVER]
+ SpiFlashCommonLib|$(RP_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf
+ MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf
+ Tcg2PhysicalPresenceLib|SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/SmmTcg2PhysicalPresenceLib.inf
+
+[LibraryClasses.Common.SMM_CORE]
+ S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
+
+[LibraryClasses.Common]
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ PeiLib|MinPlatformPkg/Library/PeiLib/PeiLib.inf
+
+[Components.IA32]
+ UefiCpuPkg/SecCore/SecCore.inf
+
+ !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ #
+ # Beware of circular dependencies on PCD if you want to use another DebugLib instance.
+ #
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf # Include FSP DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSilicon.inf # Include FvLateSilicon DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateOpenBoard.inf # Include FvLateBoard DynamicEx PCD
+ }
+ $(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
+ $(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+ $(RP_PKG)/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+ $(RP_PKG)/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
+
+ $(RP_PKG)/$(BOARD_NAME)/Platform/Pei/PlatformInfo/PlatformInfo.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ <LibraryClasses>
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitPreMemLib.inf
+ }
+ $(PLATFORM_PKG)/PlatformInit/ReportFv/ReportFvPei.inf
+
+ $(PLATFORM_PKG)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf{
+ <LibraryClasses>
+ SiliconWorkaroundLib|WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf
+ }
+ $(RP_PKG)/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+ <LibraryClasses>
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
+ }
+
+ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+!if ($(FSP_MODE) == 0)
+ IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+!endif
+
+ $(RP_PKG)/BiosInfo/BiosInfo.inf
+
+ WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+
+ UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {
+ <LibraryClasses>
+ !if $(PERFORMANCE_ENABLE) == TRUE
+ TimerLib|UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf
+ !endif
+ }
+
+[Components.X64]
+ !include WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
+
+ $(RP_PKG)/Platform/Dxe/PlatformType/PlatformType.inf
+
+ MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf
+
+ MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+ $(RP_PKG)/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ UefiCpuPkg/CpuDxe/CpuDxe.inf
+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+
+ $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf
+
+ $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf {
+ <LibraryClasses>
+ BoardAcpiEnableLib|$(RP_PKG)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+ }
+
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf {
+ <LibraryClasses>
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitDxeLib.inf
+ }
+ $(RP_PKG)/Platform/Dxe/S3NvramSave/S3NvramSave.inf {
+!if ($(FSP_MODE) == 0)
+ <BuildOptions>
+ *_*_*_CC_FLAGS = -D FSP_API_MODE
+!endif
+ }
+
+ $(PLATFORM_PKG)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+
+ $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+
+ MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+ BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
+
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+ #
+ # SiliconPkg code for Platform Integration are defined here
+ #
+!if $(CPUTARGET) == "CPX"
+ DEFINE CPU_CPX_SUPPORT = TRUE
+!else
+ DEFINE CPU_CPX_SUPPORT = FALSE
+!endif
+[PcdsFixedAtBuild]
+!if ($(CPU_SKX_ONLY_SUPPORT) == TRUE)
+ gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |FALSE
+!endif
+[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]
+ ResetSystemLib|MdeModulePkg/Library/DxeResetSystemLib/DxeResetSystemLib.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ ResetSystemLib|MdeModulePkg/Library/RuntimeResetSystemLib/RuntimeResetSystemLib.inf
+
+
+###################################################################################################
+#
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process. They can be
+# applied for any modules or only those modules with the specific
+# module style (EDK or EDKII) specified in [Components] section.
+#
+###################################################################################################
+[BuildOptions.Common.EDKII]
+# Append build options for EDK and EDKII drivers (= is Append, == is Replace)
+!if $(CRB_FLAG_ENABLE) == TRUE
+ DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG
+!else
+ DEFINE CRB_EDKII_BUILD_OPTIONS =
+!endif
+
+!if $(DEBUG_FLAGS_ENABLE) == TRUE
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!else
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!endif
+
+!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE
+ DEFINE SPARING_SCRATCHPAD_OPTION = -D SPARING_SCRATCHPAD_SUPPORT
+!else
+ DEFINE SPARING_SCRATCHPAD_OPTIONS =
+!endif
+
+!if $(SCRATCHPAD_DEBUG) == TRUE
+ DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG
+!else
+ DEFINE SCRATCHPAD_DEBUG_OPTION =
+!endif
+
+!if $(PCH_SERVER_BIOS_ENABLE) == TRUE
+ DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1
+!else
+ DEFINE PCH_BUILD_OPTION =
+!endif
+
+!if $(SERVER_BIOS_ENABLE) == TRUE
+ DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1
+!else
+ DEFINE SERVER_BUILD_OPTION =
+!endif
+
+DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"
+
+DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"
+
+DEFINE IE_PATH = -D IE_PATH="Ie/v1"
+
+DEFINE NVDIMM_OPTIONS =
+
+!if $(CPUTARGET) == "ICX"
+ DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST
+!elseif $(CPUTARGET) == "CPX"
+ DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_HOST -D B0_HOST
+!endif
+
+DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D MAX_SOCKET=$(MAX_SOCKET) -D MAX_CORE=$(MAX_CORE) -D MAX_THREAD=$(MAX_THREAD)
+
+DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2
+!else
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3
+!endif
+
+DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D MAX_DRAM_CLUSTERS=1
+
+DEFINE LT_BUILD_OPTIONS = -D LT_FLAG
+
+DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1
+
+#
+# MAX_KTI_PORTS needs to be updated based on the silicon type
+#
+!if $(CPUTARGET) == "CPX"
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6
+!else
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3
+!endif
+
+DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D MAX_LOGIC_IIO_STACK=8
+
+DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_BUILD_OPTION)
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(CRB_EDKII_BUILD_OPTIONS) $(EDKII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX_SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP_BUILD_OPTIONS)
+
+DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0
+
+!if $(LINUX_GCC_BUILD) == TRUE
+ DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD
+!else
+ DEFINE EDK2_LINUX_BUILD_OPTIONS =
+!endif
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS)
+
+DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)
+
+DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D ESPI_ENABLE
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS)
+
+ MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819
+ GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+#
+# Enable source level debugging for RELEASE build
+#
+!if $(TARGET) == "RELEASE"
+ DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =
+
+ MSFT:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi
+ MSFT:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7
+ MSFT:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG
+ GCC:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
+ GCC:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
+!endif
+
+#
+# Override ASL Compiler parameters in tools_def.template.
+#
+ *_*_*_ASL_FLAGS == -vr -we -oi
+#
+# Override the VFR compile flags to speed the build time
+#
+
+*_*_*_VFR_FLAGS == -n
+
+#
+# add to the build options for DXE/SMM drivers to remove the log message:
+# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!
+#
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
+[BuildOptions]
+ GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers -Wno-unused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types -mabi=ms
+ GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ MSFT:*_*_*_CC_FLAGS = /FAsc
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
new file mode 100644
index 0000000000..deaac1bd7a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
@@ -0,0 +1,821 @@
+## @file
+# FDF file of platform with 64-bit DXE
+# This package provides platform specific modules and flash layout information.
+#
+# @copyright
+# Copyright 2006 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+DEFINE PLATFORM_PKG = MinPlatformPkg
+
+# 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
+DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x90 # FV Header plus FFS header
+
+DEFINE VPD_HEADER_SIZE = 0x00000090
+
+!if $(FSP_MODE) == 0
+ DEFINE FSP_BIN_DIR = Api
+!else
+ DEFINE FSP_BIN_DIR = Dispatch
+!endif
+
+#
+# Note: FlashNv PCD naming conventions are as follows:
+# Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
+# Others should be examined with an effort to work toward this guideline.
+# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
+# PcdFlash*Size is a hex count of the length of the FD or FV
+# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
+#
+# Also all values will have a PCD assigned so that they can be used in the system, and
+# the FlashMap edit tool can be used to change the values here, without effecting the code.
+# This requires all code to only use the PCD tokens to recover the values.
+
+
+#
+# 16MiB Total FLASH Image (visible in memory mapped IO)
+#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
+
+################################################################################
+#
+# FD SECPEI
+#
+# Contains all the SEC and PEI modules
+#
+# Layout: (Low address to high address)
+#
+# FvBsp for board specific components
+# FvPostMemory for compressed post memory MinPlatform spec required components
+# FvFspS for compressed post memory silicon initialization components
+# FvPostMemorySilicon for silicon components
+# FvFspM for pre memory silicon initialization components
+# FvPreMemorySilicon for silicon components
+# FvFspT for temp RAM silicon initilization components
+# FvBspPreMemory for board specific components required to intialize memory
+# FvAdvancedPreMemory FV for advanced features components
+# FvPreMemory for components required by MinPlatform spec and to initialize memory
+# FvPreMemorySecurity FV for stage 6 required components
+# Contains reset vector
+#
+################################################################################
+
+[FD.SecPei]
+ BaseAddress = 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase #The base address of the FLASH Device
+ Size = 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize #The size in bytes of the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x360
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ # At this time, the FSP FV must be aligned at the same address they were built to, 0xFFD00000
+ # This will be corrected in the future.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00040000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x00221000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00006000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize = 0x00009000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset = 0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ FV = FvBsp
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ FV = FvPostMemory
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd
+
+ #
+ # Shared FV layout
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+ FV = FvBspPreMemory
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+ FV = FvPreMemory
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Set duplicate PCD
+ # These should not need to be changed
+ #
+
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+
+ #
+ # For API mode, wrappers have some duplicate PCD as well
+ #
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
+
+################################################################################
+#
+# FD Main
+#
+# All DXE modules and other regions
+#
+# Layout: (Low address to high address)
+#
+# FvAdvanced for advanced feature components
+# Assorted advanced feature FV
+# FvSecurity for MinPlatform spec required components needed to boot securely
+# FvOsBoot for MinPlatform spec required components needed to boot OS
+# FvLateSilicon for silicon specific components
+# FvUefiBoot for MinPlatform spec required components needed to boot to UEFI shell
+#
+################################################################################
+[FD.Main]
+ BaseAddress = 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase # The base address of the FLASH Device
+ Size = 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize # The size in bytes of the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x9C0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ # These are out of flash layout order because FvAdvanced gets any remaining space
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00040000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00230000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x0004C000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ FV = FvAdvanced
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ FV = FvSecurity
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+ FV = FvOsBoot
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+ FV = FvUefiBoot
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+################################################################################
+#
+# FD BINARY
+#
+# Contains the OPROM and other binary modules
+#
+# Layout: (Low address to high address)
+#
+# FvOpRom containing pre-built components
+# FvAcmRegion containing ACM related content
+# FV Header + Blank Space (1K)
+# Policy block (3K)
+# Blank space to align ACM on 64K boundary (60K)
+# ACM binary
+# FvMicrocode containing microcode update patches
+# Unformatted region for PCI Gen 3 Data
+# FvVpd containing PCD VPD data
+# FvWhea for WHEA data recording
+# FvNvStorageVariable for UEFI Variable storage
+# FvNvStorageEventLog for NV Store management
+# FvNvStorageFtwWorking for Fault Tolerant Write solution
+# FvNvStorageFtwSpare for Fault Tolerant Write solution
+#
+################################################################################
+[FD.Binary]
+ BaseAddress = 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase
+ Size = 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2E0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize = 0x00100000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize = 0x00050000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = 0x000D0000
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize = 0x00010000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize = 0x00030000
+ #
+ # These four items are tightly coupled.
+ # The spare area size must be >= the first three areas.
+ #
+ # There isn't really a benefit to a larger spare area unless the FLASH device
+ # block size is larger than the size specified.
+ #
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0003C000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize = 0x00002000
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Calculate Offsets Once (You should not need to modify this section)
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = 0x00000000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically
+ #
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+
+ #
+ # FV Layout (You should not need to modify this section)
+ #
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ FV = FvOprom
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ FV = FvAcm
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ FV = FvMicrocode
+
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+ FV = FvVPD
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ FV = FvWhea
+
+ #
+ # Do not modify.
+ # See comments in size discussion above. These four areas are tightly coupled and should be modified with utmost care.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+
+ #
+ # Calculate base addresses (You should not need to modify this section)
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE)
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE)
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # ACM details
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize = 0x3000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize = 0x00040000
+
+ #
+ # Other duplicate PCD
+ #
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
+ SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
+################################################################################
+#
+# FD FPGA
+#
+# Contains the FPGA modules
+#
+################################################################################
+
+[FD.Fpga]
+ BaseAddress = 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase #The base address of the FPGA Device ( 4G - 48M )
+ Size = 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize #The size in bytes of the FPGA Device ( 32M )
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2000
+
+ 0x00000000|0x02000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize
+ FV = FvFpga
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvSecurityPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 40ab290f-8494-41cf-b302-31b178b4ce0b
+
+ !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+
+[FV.FvPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
+
+ INF UefiCpuPkg/SecCore/SecCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
+ INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+
+ INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+
+ INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
+
+ INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
+
+ FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi
+ SECTION UI = "DynamicSiLibraryPei"
+ }
+
+ INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
+
+ INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+
+ INF WhitleyOpenBoardPkg/$(BOARD_NAME)/Platform/Pei/PlatformInfo/PlatformInfo.inf
+
+ #
+ # UBA common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf
+
+ INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+
+ INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
+
+ FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi
+ SECTION UI = "SiliconPolicyInitPreAndPostMem"
+ }
+
+ INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+
+ !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf
+
+ INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+ INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ !if $(FSP_MODE) == 0
+ FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi
+ SECTION UI = "CsrPseudoOffsetInitPeim"
+ }
+ FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi
+ SECTION UI = "RegAccessPeim"
+ }
+ FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi
+ SECTION UI = "SiliconDataInitPeim"
+ }
+ INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+ INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+ !endif
+
+ FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b {
+ SECTION FV_IMAGE = FvSecurityPreMemory
+ }
+
+[FV.FvAdvancedPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 09f25d44-b2ef-4225-8b2e-e0e094b51775
+
+ !include AdvancedFeaturePkg/Include/PreMemory.fdf
+
+[FV.FvBspPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e6c65995-8c2d-4119-a52d-7dbf1acb45a1
+
+ FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 {
+ SECTION FV_IMAGE = FvAdvancedPreMemory
+ }
+
+#
+# FvPostMemory includes common hardware, common core variable services, load and invoke DXE etc
+#
+[FV.FvPostMemoryUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA
+
+[FV.FvPostMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 3298afc4-c484-47f1-a65a-5917a54b5e8c
+
+ FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvPostMemoryUncompressed
+ }
+ }
+
+#
+# FvBsp includes board specific components
+#
+[FV.FvBspUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e4c65347-fd90-4143-8a41-113e1015fe07
+
+[FV.FvBsp]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 9e151cf3-ca90-444f-b33b-a9941cbc772f
+
+ FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvBspUncompressed
+ }
+ }
+
+[FV.FvUefiBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = C4D3B0E2-FB26-44f8-A05B-E95895FCB960
+
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
+
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
+ #ATA for IDE/AHCI/RAID support
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+ INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+ FILE DRIVER = 85299F8F-F2B9-4487-AF60-231434A5EFF6 {
+ SECTION PE32 = edk2-non-osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpeedAst2500Gop.efi
+ }
+
+
+[FV.FvUefiBoot]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = ab9fe87b-1e37-440c-91cc-9aea03ce7bec
+
+ FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvUefiBootUncompressed
+ }
+ }
+
+[FV.FvOsBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
+
+ #
+ # DXE Phase modules
+ #
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+
+ FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 {
+ SECTION UI = "FvLateSilicon"
+ SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv
+ }
+
+ INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+
+ !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf
+
+ #
+ # UBA DXE common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf
+ !include WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
+ INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf
+ INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+ !if ($(FSP_MODE) == 1)
+ INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf
+ !else
+ INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+ !endif
+
+ INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+ INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 {
+ SECTION UI = "FvLateOpenBoard"
+ SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv
+ }
+
+ INF MdeModulePkg/Universal/Metronome/Metronome.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
+ INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV.
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
+
+ INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+
+ INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+ INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+
+ INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
+
+ INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+
+ INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+
+ # UEFI USB stack
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+ INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+ INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf
+ INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
+
+[FV.FvOsBoot]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = c7488640-5f51-4969-b63b-89fc369e1725
+
+ FILE FV_IMAGE = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOsBootUncompressed
+ }
+ }
+
+[FV.FvSecuritySilicon]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = AD262F8D-BDED-4668-A8D4-8BC73516652F
+
+ !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf
+
+[FV.FvSecurityUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 03E25550-89A5-4ee6-AF60-DB0553D91FD2
+
+ FILE FV_IMAGE = 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecuritySilicon
+ }
+ }
+
+[FV.FvSecurity]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 68134833-2ff6-4d22-973b-575d0eae8ffd
+
+ FILE FV_IMAGE = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecurityUncompressed
+ }
+ }
+
+[FV.FvAdvancedUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 70aeaf57-4997-49ce-a4f7-122980745670
+
+ !include AdvancedFeaturePkg/Include/PostMemory.fdf
+
+[FV.FvAdvanced]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = f21ee7a1-53a9-453d-aee3-b6a5c25bada5
+
+ FILE FV_IMAGE = 70aeaf57-4997-49ce-a4f7-122980745670 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvAdvancedUncompressed
+ }
+ }
+
+#
+# FV for all Microcode Updates.
+#
+[FV.FvMicrocode]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ LOCK_STATUS = FALSE
+ FvNameGuid = D2C29BA7-3809-480F-9C3D-DE389C61425A
+
+!if $(CPUTARGET) == "CPX"
+ INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+!else
+ INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+!endif
+
+
+[FV.FvVPD]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ LOCK_STATUS = FALSE
+ FvNameGuid = FFC29BA7-3809-480F-9C3D-DE389C61425A
+ FILE RAW = FF7DB236-F856-4924-90F8-CDF12FB875F3 {
+ $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin
+ }
+
+#
+# Various Vendor UEFI Drivers (OROMs).
+#
+[FV.FvOpromUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = B6EDE22C-DE30-45fa-BB09-CA202C1654B7
+
+[FV.FvOprom]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD
+
+ FILE FV_IMAGE = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOpromUncompressed
+ }
+ }
+
+[FV.FvWhea]
+ BlockSize = 0x1000
+ NumBlocks = 0x30
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = d6a1cd70-4b33-4994-a6ea-375f2ccc5437
+
+#
+# FV For ACM Binary.
+#
+[FV.FvAcm]
+ BlockSize = 0x1000
+ NumBlocks = 0x50
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 11668261-8A8D-47ca-9893-052D24435E59
+
+[FV.FvFpga]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 974650E7-6DFE-4998-A124-CEDEC5C9B47D
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py
new file mode 100644
index 0000000000..f50d786845
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py
@@ -0,0 +1,127 @@
+# @ build_board.py
+# Extensions for building JunctioCity using build_bios.py
+#
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+"""
+This module serves as a sample implementation of the build extension
+scripts
+"""
+
+import os
+import sys
+
+def pre_build_ex(config, functions):
+ """Additional Pre BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: nothing
+ """
+ print("pre_build_ex")
+ config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"],
+ 'Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ # set BUILD_DIR path
+ config["BUILD_DIR"] = os.path.join('Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ config["BUILD_X64"] = os.path.join(config["BUILD_DIR_PATH"], 'X64')
+ config["BUILD_IA32"] = os.path.join(config["BUILD_DIR_PATH"], 'IA32')
+
+ if not os.path.isdir(config["BUILD_DIR_PATH"]):
+ try:
+ os.makedirs(config["BUILD_DIR_PATH"])
+ except OSError:
+ print("Error while creating Build folder")
+ sys.exit(1)
+
+ #@todo: Replace this with PcdFspModeSelection
+ if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=0"
+ else:
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=1"
+
+ if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+ raise ValueError("FSP API Mode is currently unsupported on Ice Lake Xeon Scalable")
+ return None
+
+def _merge_files(files, ofile):
+ with open(ofile, 'wb') as of:
+ for x in files:
+ if not os.path.exists(x):
+ return
+
+ with open(x, 'rb') as f:
+ of.write(f.read())
+
+def build_ex(config, functions):
+ """Additional BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("build_ex")
+ fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+ binary_fd = os.path.join(fv_path, "BINARY.fd")
+ main_fd = os.path.join(fv_path, "MAIN.fd")
+ secpei_fd = os.path.join(fv_path, "SECPEI.fd")
+ board_fd = config["BOARD"].upper()
+ final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+ _merge_files((binary_fd, main_fd, secpei_fd), final_fd)
+ return None
+
+
+def post_build_ex(config, functions):
+ """Additional Post BIOS build function
+
+ :param config: The environment variables to be used in the post
+ build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("post_build_ex")
+ fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+ board_fd = config["BOARD"].upper()
+ final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+ final_ifwi = os.path.join(fv_path, "{}.bin".format(board_fd))
+
+ ifwi_ingredients_path = os.path.join(config["WORKSPACE_PLATFORM_BIN"], "Ifwi", config["BOARD"])
+ flash_descriptor = os.path.join(ifwi_ingredients_path, "FlashDescriptor.bin")
+ intel_me = os.path.join(ifwi_ingredients_path, "Me.bin")
+ _merge_files((flash_descriptor, intel_me, final_fd), final_ifwi)
+ if os.path.isfile(final_fd):
+ print("IFWI image can be found at {}".format(final_ifwi))
+ return None
+
+
+def clean_ex(config, functions):
+ """Additional clean function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("clean_ex")
+ return None
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
new file mode 100644
index 0000000000..602987b922
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
@@ -0,0 +1,37 @@
+# @ build_config.cfg
+# This is the JunctionCity board specific build settings
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN = edk2-non-osi/Platform/Intel/WhitleyOpenBoardBinPkg
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = WhitleyOpenBoardPkg
+PROJECT = WhitleyOpenBoardPkg/JunctionCity
+BOARD = JunctionCity
+FLASH_MAP_FDF = WhitleyOpenBoardPkg/FspFlashOffsets.fdf
+PROJECT_DSC = WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
+BOARD_PKG_PCD_DSC = WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
+ADDITIONAL_SCRIPTS = WhitleyOpenBoardPkg/JunctionCity/build_board.py
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS = -D CPUTARGET=ICX -D RP_PKG=WhitleyOpenBoardPkg -D SILICON_PKG=WhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=64 -D MAX_THREAD=2 -D PLATFORM_PKG=MinPlatformPkg
+MAX_SOCKET = 4
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = TRUE
+FSP_BIN_PKG = WhitleyFspBinPkg
+FSP_PKG_NAME = WhitleyFspPkg
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
+BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
index 363d4e4059..d3d8bc84e7 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
@@ -136,6 +136,7 @@
gEfiPlatformTypeWilsonCitySMTProtocolGuid = { 0xEE55562D, 0x4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } }
gEfiPlatformTypeCooperCityRPProtocolGuid = { 0x45c302e1, 0x4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } }
+ gEfiPlatformTypeJunctionCityProtocolGuid = { 0xB1C2B1C9, 0xB606, 0x4B62, { 0x9D, 0x78, 0xCB, 0xD6, 0x0F, 0xF9, 0x0D, 0x0C } }
#
# UBA_END
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
index 212103f483..6cfa43a59d 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
@@ -3,6 +3,7 @@
@copyright
Copyright 2014 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -88,6 +89,16 @@ BoardInitDxeDriverEntry (
ASSERT_EFI_ERROR (Status);
break;
+ case TypeJunctionCity:
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiPlatformTypeJunctionCityProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ break;
+
default:
// CAN'T GO TO HERE.
ASSERT (FALSE);
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
index 206d95658a..8948ab1f0a 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
@@ -3,6 +3,7 @@
#
# @copyright
# Copyright 2014 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -62,6 +63,7 @@
gEfiPlatformTypeIsoscelesPeakProtocolGuid #PRODUCER
gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER
gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER
+ gEfiPlatformTypeJunctionCityProtocolGuid #PRODUCER
[FixedPcd]
gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
index fcf147885f..e20c576028 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
@@ -3,6 +3,7 @@
#
# @copyright
# Copyright 2012 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -27,3 +28,10 @@ INF $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdate
INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
+
+#
+# Platform TypeJunctioCity
+#
+INF $(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
+INF $(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
+INF $(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
new file mode 100644
index 0000000000..b6b81f188c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
@@ -0,0 +1,100 @@
+/** @file
+ IIO Config Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "IioCfgUpdateDxe.h"
+
+EFI_STATUS
+UpdateJunctionCityIioConfig (
+ IN IIO_GLOBALS *IioGlobalData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeJunctionCityIioConfigTable =
+{
+ PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+ PLATFORM_IIO_CONFIG_UPDATE_VERSION,
+
+ IioBifurcationTable,
+ sizeof(IioBifurcationTable),
+ UpdateJunctionCityIioConfig,
+ IioSlotTable,
+ sizeof(IioSlotTable)
+
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+IioCfgUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeJunctionCity\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_1,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_2,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_3,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
new file mode 100644
index 0000000000..53d3a49f9a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
@@ -0,0 +1,119 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIOCFG_UPDATE_DXE_H_
+#define _IIOCFG_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Protocol/UbaCfgDb.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Mcp0,
+ Iio_Mcp1,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ VPP_PORT_0 = 0,
+ VPP_PORT_1,
+ VPP_PORT_2,
+ VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE 1
+#define DISABLE 0
+#define NO_SLT_IMP 0xFF
+#define SLT_IMP 1
+#define HIDE 1
+#define NOT_HIDE 0
+#define VPP_PORT_0 0
+#define VPP_PORT_1 1
+#define VPP_PORT_MAX 0xFF
+#define VPP_ADDR_MAX 0xFF
+#define PWR_VAL_MAX 0xFF
+#define PWR_SCL_MAX 0xFF
+
+static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =
+{
+ // Neon City IIO bifurcation table (Based on Neon City Block Diagram rev 0.6)
+ { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 },
+ { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 },
+ { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+};
+
+static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] = {
+ // Port | Slot | Inter | Power Limit | Power Limit | Hot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden
+ // Index | | lock | Scale | Value | Plug | Port | Addr | Cap | VppPort | VppAddr |
+ { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C , HIDE },//Oculink
+ { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C , HIDE },//Oculink
+ { PORT_1C_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 118 (MRL in J65)
+ { PORT_3A_INDEX, 2 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
+ { PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
+ { PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
+ { PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_0_INDEX , 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287)
+ { SOCKET_1_INDEX +
+ PORT_1A_INDEX, 4 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x44 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x46 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x46 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_3C_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port
+};
+
+#endif //_IIOCFG_UPDATE_DXE_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
new file mode 100644
index 0000000000..13d88a3748
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IioCfgUpdateDxeJunctionCity
+ FILE_GUID = 9E1DECF5-C606-44A2-B99D-5BF4222A174C
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = IioCfgUpdateEntry
+
+[sources]
+ IioCfgUpdateDxe.c
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeJunctionCityProtocolGuid
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
new file mode 100644
index 0000000000..37e9c6a9e6
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
@@ -0,0 +1,116 @@
+/** @file
+ Slot Data Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "SlotDataUpdateDxe.h"
+
+UINT8
+GetTypeJunctionCityIOU0Setting (
+ UINT8 IOU0Data
+)
+{
+ //
+ // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
+ //
+ IOU0Data = IIO_BIFURCATE_xxx8xxx8;
+ return IOU0Data;
+}
+
+UINT8
+GetTypeJunctionCityIOU2Setting (
+ UINT8 SkuPersonalityType,
+ UINT8 IOU2Data
+)
+{
+ return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeJunctionCityBroadwayTable[] = {
+ {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+ {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
+ {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+
+PLATFORM_SLOT_UPDATE_TABLE TypeJunctionCitySlotTable =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2 TypeJunctionCitySlotTable2 =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0,
+ GetTypeJunctionCityIOU2Setting
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+SlotDataUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeJunctionCity\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformSlotDataDxeGuid,
+ &TypeJunctionCitySlotTable,
+ sizeof(TypeJunctionCitySlotTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformSlotDataDxeGuid,
+ &TypeJunctionCitySlotTable2,
+ sizeof(TypeJunctionCitySlotTable2)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
new file mode 100644
index 0000000000..e59e70c9ee
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
@@ -0,0 +1,58 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SLOT_DATA_UPDATE_DXE_H_
+#define _SLOT_DATA_UPDATE_DXE_H_
+
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Mcp0,
+ Iio_Mcp1,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ Bw5_Addr_0 = 0,
+ Bw5_Addr_1,
+ Bw5_Addr_2,
+ Bw5_Addr_3,
+ Bw5_Addr_Max
+} BW5_ADDRESS;
+
+#endif //_SLOT_DATA_UPDATE_DXE_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
new file mode 100644
index 0000000000..8f107b9c42
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SlotDataUpdateDxeJunctionCity
+ FILE_GUID = 98750E94-CCCB-45AA-9259-3CF7F8C43C33
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SlotDataUpdateEntry
+
+[sources]
+ SlotDataUpdateDxe.c
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeJunctionCityProtocolGuid
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
new file mode 100644
index 0000000000..f4d50beec8
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
@@ -0,0 +1,128 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "UsbOcUpdateDxe.h"
+
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+ UsbOverCurrentPinSkip, //Port00: BMC
+ UsbOverCurrentPinSkip, //Port01: BMC
+ UsbOverCurrentPin0, //Port02: Rear Panel
+ UsbOverCurrentPin1, //Port03: Rear Panel
+ UsbOverCurrentPin1, //Port04: Rear Panel
+ UsbOverCurrentPinSkip, //Port05: NC
+ UsbOverCurrentPinSkip, //Port06: NC
+ UsbOverCurrentPin4, //Port07: Type A internal
+ UsbOverCurrentPinSkip, //Port08: NC
+ UsbOverCurrentPinSkip, //Port09: NC
+ UsbOverCurrentPin6, //Port10: Front Panel
+ UsbOverCurrentPinSkip, //Port11: NC
+ UsbOverCurrentPin6, //Port12: Front Panel
+ UsbOverCurrentPinSkip, //Port13: NC
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+ UsbOverCurrentPin6, //Port01: Front Panel
+ UsbOverCurrentPin6, //Port02: Front Panel
+ UsbOverCurrentPin0, //Port03: Rear Panel
+ UsbOverCurrentPin1, //Port04: Rear Panel
+ UsbOverCurrentPin1, //Port05: Rear Panel
+ UsbOverCurrentPinSkip, //Port06: NC
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB2_PHY_PARAMETERS TypeJunctionCityUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+ {3, 0, 3, 1}, // PP0
+ {5, 0, 3, 1}, // PP1
+ {3, 0, 3, 1}, // PP2
+ {0, 5, 1, 1}, // PP3
+ {3, 0, 3, 1}, // PP4
+ {3, 0, 3, 1}, // PP5
+ {3, 0, 3, 1}, // PP6
+ {3, 0, 3, 1}, // PP7
+ {2, 2, 1, 0}, // PP8
+ {6, 0, 2, 1}, // PP9
+ {2, 2, 1, 0}, // PP10
+ {6, 0, 2, 1}, // PP11
+ {0, 5, 1, 1}, // PP12
+ {7, 0, 2, 1}, // PP13
+ };
+
+EFI_STATUS
+TypeJunctionCityPlatformUsbOcUpdateCallback (
+ IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings,
+ IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings,
+ IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams
+)
+{
+ *Usb20OverCurrentMappings = &TypeJunctionCityUsb20OverCurrentMappings[0];
+ *Usb30OverCurrentMappings = &TypeJunctionCityUsb30OverCurrentMappings[0];
+
+ *Usb20AfeParams = TypeJunctionCityUsb20AfeParams;
+ return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE TypeJunctionCityUsbOcUpdate =
+{
+ PLATFORM_USBOC_UPDATE_SIGNATURE,
+ PLATFORM_USBOC_UPDATE_VERSION,
+ TypeJunctionCityPlatformUsbOcUpdateCallback
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+UsbOcUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((EFI_D_INFO, "UBA:UsbOcUpdate-TypeJunctionCity\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gDxePlatformUbaOcConfigDataGuid,
+ &TypeJunctionCityUsbOcUpdate,
+ sizeof(TypeJunctionCityUsbOcUpdate)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
new file mode 100644
index 0000000000..2ba90c7598
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
@@ -0,0 +1,27 @@
+/** @file
+
+ @copyright
+ Copyright 2015 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _USBOC_UPDATE_DXE_H_
+#define _USBOC_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+
+
+#endif //_USBOC_UPDATE_DXE_H_
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
new file mode 100644
index 0000000000..0f8e953e2b
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
@@ -0,0 +1,45 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = UsbOcUpdateDxeJunctionCity
+ FILE_GUID = 5149EA77-8FCC-41B4-A8D0-CE652E817FD0
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = UsbOcUpdateEntry
+
+[sources]
+ UsbOcUpdateDxe.c
+ UsbOcUpdateDxe.h
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeJunctionCityProtocolGuid
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/AcpiTablePcds.c
new file mode 100644
index 0000000000..25bbf30dab
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/AcpiTablePcds.c
@@ -0,0 +1,54 @@
+/** @file
+ ACPI table pcds update.
+
+ @copyright
+ Copyright 2015 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo.h>
+#include <UncoreCommonIncludes.h>
+#include <Cpu/CpuIds.h>
+
+EFI_STATUS
+TypeJunctionCityPlatformUpdateAcpiTablePcds (
+ VOID
+ )
+{
+ CHAR8 AcpiName10nm[] = "EPRP10NM"; // USED for identify ACPI table for 10nm in systmeboard dxe driver
+ CHAR8 OemTableIdXhci[] = "xh_nccrb";
+
+ UINTN Size;
+ EFI_STATUS Status;
+
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ DEBUG ((EFI_D_INFO, "Uba Callback: PlatformUpdateAcpiTablePcds entered\n"));
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+ //#
+ //#ACPI items
+ //#
+ Size = AsciiStrSize (AcpiName10nm);
+ Status = PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiName10nm);
+ DEBUG ((DEBUG_INFO, "%a TypeJunctionCity ICX\n", __FUNCTION__));
+ ASSERT_EFI_ERROR (Status);
+
+ Size = AsciiStrSize (OemTableIdXhci);
+ Status = PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/GpioTable.c
new file mode 100644
index 0000000000..2d1e46b143
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/GpioTable.c
@@ -0,0 +1,296 @@
+/** @file
+
+ @copyright
+ Copyright 2020 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaGpioUpdateLib.h>
+
+#include <Library/GpioLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <GpioPinsSklH.h>
+#include <Library/PcdLib.h>
+
+//
+// Board : Wilson City RP
+//
+static GPIO_INIT_CONFIG mGpioTableJunctionCity [] =
+ {
+ {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N //IRQ_ESPI_FPGA_PCH_ALERT1_N PU not used
+ {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0
+ {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1
+ {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2
+ {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3
+ {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
+ {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
+ {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
+ {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N //PU_LPC_CLKRUN_N PU not used
+ {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI
+ {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10
+ {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N //PU_LPC_PME_N PU not used
+ {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N //PU_IRQ_PCH_SCI_WHEA_N PU not used
+ {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N //TP_PCH_GPP_A_13
+ {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N
+ {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_15_FM_SUSACK_N //TP_PCH_GPP_A_15
+ {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16 //FM_PCHIE_BMC_N
+ {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16 //FM_BMC_PCHIE_N
+ {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS //IRQ_BMC_PCH_SMI_LPC_N
+// GPIO_SKL_H_GPP_A19 - Not Owned by BIOS //ME Recovery Jumper FM_ME_RCVR_N
+ {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20 //FM_BMC_READY_N
+ {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21
+ {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22
+ {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23
+ {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0
+ {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1
+ {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N
+ {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}}, //PU_SATA_EN
+// GPIO_SKL_H_GPP_B4 - Not Owned by BIOS //ME SMB Alert MGPIO IRQ_SML1_PMBUS_ALERT
+ {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1 //TP_PCH_GPP_B_5
+ {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2 //TP_PCH_GPP_B_6
+ {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7
+ {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8
+ {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2 //TP_PCH_GPP_B_9
+ {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N
+// GPIO_SKL_H_GPP_B11 - Not Owned by BIOS //ME SMB Alert_EN MGPIO FM_PMBUS_ALERT_BUF_EN_N
+ {GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N //FM_GLOBAL_RST_WARN_N
+ {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_13_RST_PLTRST_N
+ {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
+ {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N
+ {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N
+ {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N
+ {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT //PU_NO_REBOOT Spare
+ {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5 //TP_PCH_GPP_B19
+ {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N
+ {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21
+ {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE //FM_USB_PWR_EN
+ {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N
+// GPIO_SKL_H_GPP_C0 - Not Owned by BIOS //ME SMBCLK
+// GPIO_SKL_H_GPP_C1 - Not Owned by BIOS //ME SMBDATA
+ {GPIO_SKL_H_GPP_C2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP //IRQ_SMB_ALERT_N_TLS_EN_STRP
+// GPIO_SKL_H_GPP_C3 - Not Owned by BIOS //ME SML0CLK
+// GPIO_SKL_H_GPP_C4 - Not Owned by BIOS //ME SML0DATA
+ {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N
+// GPIO_SKL_H_GPP_C6 - Not Owned by BIOS //ME SML1CLK
+// GPIO_SKL_H_GPP_C7 - Not Owned by BIOS //ME SML1DATA
+ {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N
+ {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_9_FM_MFG_MODE
+ {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//GPP_C_10_FM_PCH_SATA_RAID_KEY
+ {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N //FM_BOARD_REV_ID0
+ {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0 //FM_BOARD_REV_ID1
+ {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1 //FM_BOARD_REV_ID2
+ {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N //TP_PCH_GPP_C_14
+ {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0 //TP_PCH_GPP_C_15
+ {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1 //TP_PCH_GPP_C_16
+ {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0 //TP_PCH_GPP_C_17
+ {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1 //TP_PCH_GPP_C_18
+// GPIO_SKL_H_GPP_C19 - Not Owned by BIOS //SMBus Smbus Mux GPIO reset GPP_C_19_RST_SMB_HOST_PCH_MUX_N
+// GPIO_SKL_H_GPP_C20 - Not Owned by BIOS //ME PROCHOT MGPIO GPP_C_20_FM_THROTTLE_N
+ {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N //TP_PCH_GPP_C_21
+ {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N //FM_BMC_PCH_SCI_LPC_N
+ {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N
+ {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntNmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
+ {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset,GpioTermNone, GpioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N
+ {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR //TP_PCH_GPP_D_2
+ {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT //TP_PCH_GPP_D_3
+ {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA
+ {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5 //FM_OCP_MOD1_PRSNT_N
+ {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6
+ {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7
+ {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL //TP_PCH_GPP_D_8
+ {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9
+ {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP_D_10
+ {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11
+ {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1 //TP_PCH_GPP_D_12
+ {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL //TP_PCH_GPP_D_13
+ {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA //TP_PCH_GPP_D_14
+ {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0
+ {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1 //FM_SLOT1_PRSNT
+ {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2 //FM_SLOT2_PRSNT
+ {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N //TP_PCH_GPP_D_18
+ {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R
+ {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20
+ {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21
+ {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22
+ {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23
+ {GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N //TP_PCH_GPP_E_0
+ {GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N //TP_PCH_GPP_E_1
+ {GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N //TP_PCH_GPP_E_2
+ {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N
+ {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4 //FM_CPU0_SSD0_PRSNT_N
+ {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5 //FM_CPU0_SSD1_PRSNT_N
+ {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E_6 //FM_CPU0_SSD2_PRSNT_N
+ {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N
+ {GPIO_SKL_H_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N //FM_CPU0_SSD3_PRSNT_N
+ {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N
+ {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N
+ {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N
+ {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N
+ {GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N //FM_OCP_MOD2_PRSNT_N
+ {GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N //TP_PCH_GPP_F_1
+ {GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N //FM_EDSFF0_PRSNT0_N
+ {GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N //FM_EDSFF0_PRSNT1_N
+ {GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N //FM_BIOS_USB_RECOVERY
+ {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N
+ {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK //FM_EDSFF1_PRSNT0_N
+ {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI //FM_EDSFF1_PRSNT1_N
+ {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS //FM_EDSFF2_PRSNT0_N
+ {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO //FM_EDSFF2_PRSNT1_N
+ {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK
+ {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD
+ {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1
+ {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0
+ {GPIO_SKL_H_GPP_F14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N //TP_PCH_GPP_F14
+ {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N //FM_EDSFF3_PRSNT0_N
+ {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N //FM_EDSFF3_PRSNT1_N
+ {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N //FM_EDSFF4_PRSNT0_N
+ {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N //FM_EDSFF4_PRSNT1_N
+ {GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL //FM_EDSFF5_PRSNT0_N
+ {GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA //FM_EDSFF5_PRSNT1_N
+ {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21
+ {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK
+ {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD
+ {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0 //FM_BOARD_SKU_ID0
+ {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1 //FM_BOARD_SKU_ID1
+ {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2 //FM_BOARD_SKU_ID2
+ {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3 //FM_BOARD_SKU_ID3
+ {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4 //FM_BOARD_SKU_ID4
+ {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5 //FM_BOARD_SKU_ID5
+ {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6 //FM_MIDPLANE_PCH_ID0
+ {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7 //FM_MIDPLANE_PCH_ID1
+ {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0 //FM_PCH_GPP_G8
+ {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1 //FM_PCH_GPP_G9
+ {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2 //FM_PCH_GPP_G10
+ {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3 //FM_PCH_GPP_G11
+ {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_12_GSXDOUT //IRQ_FORCE_NM_THROTTLE_N
+ {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1 //TP_PCH_GPP_G_13
+ {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2 //TP_PCH_GPP_G_14
+ {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3 //TP_PCH_GPP_G_15
+ {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4 //TP_PCH_GPP_G_16
+ {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE
+ {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N
+ {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N
+ {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}}, //TP_PCH_GPP_G_20
+ {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N //TP_PCH_GPP_G_21
+ {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP_G_22
+ {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23
+ {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2 //FM_CLKREQ_M2_SSD_A_N
+ {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N //FM_CLKREQ_M2_SSD_B_N
+ {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0 //FM_ROWOL_ENABLE
+ {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1 //FM_ROWOL_LATCH
+ {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4 //TP_PCH_GPP_H_4
+ {GPIO_SKL_H_GPP_H5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_5_FM_CLKREQ_M2_1_N //TP_PCH_GPP_H_5
+ {GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N //TP_PCH_GPP_H_6
+ {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3 //TP_PCH_GPP_H_7
+ {GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N //TP_PCH_GPP_H_8
+ {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5 //TP_PCH_GPP_H_9
+// GPIO_SKL_H_GPP_H10 - Not Owned by BIOS //ME SML2CLK
+// GPIO_SKL_H_GPP_H11 - Not Owned by BIOS //ME SML2DATA
+ {GPIO_SKL_H_GPP_H12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE //IRQ_SML2_ALERT_N
+ {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N
+ {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N
+ {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N //TP_PCH_GPP_H_19
+ {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL //TP_PCH_GPP_H_20
+ {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N //TP_PCH_GPP_H_21
+ {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL //TP_PCH_GPP_H_22
+ {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23
+ {GPIO_SKL_H_GPP_I0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0
+ {GPIO_SKL_H_GPP_I1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1
+ {GPIO_SKL_H_GPP_I2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2
+ {GPIO_SKL_H_GPP_I3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3
+ {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I_4
+ {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I_5
+ {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I_6
+ {GPIO_SKL_H_GPP_I7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7
+ {GPIO_SKL_H_GPP_I8, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N
+ {GPIO_SKL_H_GPP_I9, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N
+ {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10 //FM_BIOS_MRC_DEBUG_MSG_DIS_N
+// GPIO_SKL_H_GPP_I11 - Not Owned by BIOS
+// GPIO_SKL_H_GPD0 - Not Owned by BIOS //ME FIVRBREAK
+ {GPIO_SKL_H_GPD1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_1_PU_ACPRESENT
+ {GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N //RST_BMC_SRST_N
+ {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N
+ {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_4_FM_SLPS3_N
+ {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_5_FM_SLPS4_N
+ {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_6_FM_SLPA_N
+ {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_7_TP_GPD_7
+ {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK
+ {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_9_TP_GPD_9_SLP
+ {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_10_FM_SLPS5_N
+ {GPIO_SKL_H_GPD11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N
+ {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0
+ {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1
+ {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2
+ {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3
+ {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4
+ {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5
+ {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6
+ {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7
+ {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8
+ {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9
+ {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10
+ {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11
+ {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12
+ {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13
+ {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14
+ {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15
+ {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16
+ {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17
+ {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18
+ {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19
+ {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20
+ {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21
+ {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22
+ {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23
+ {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH
+ {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0
+ {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1
+ {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN
+ {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV
+ {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0
+ {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1
+ {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER
+ {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN
+ {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT
+ {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N
+// GPIO_SKL_H_GPP_K11 - Not Owned by BIOS
+ {GPIO_SKL_H_GPP_L2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0
+ {GPIO_SKL_H_GPP_L3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1
+ {GPIO_SKL_H_GPP_L4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2
+ {GPIO_SKL_H_GPP_L5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3
+ {GPIO_SKL_H_GPP_L6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4
+ {GPIO_SKL_H_GPP_L7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5
+ {GPIO_SKL_H_GPP_L8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6
+ {GPIO_SKL_H_GPP_L9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7
+ {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK
+ {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0
+ {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1
+ {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2
+ {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3
+ {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4
+ {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5
+ {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6
+ {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7
+ {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK
+};
+
+EFI_STATUS
+TypeJunctionCityInstallGpioData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformGpioInitDataGuid,
+ &mGpioTableJunctionCity,
+ sizeof(mGpioTableJunctionCity)
+ );
+ Status = PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableJunctionCity));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/IioBifurInit.c
new file mode 100644
index 0000000000..4c376964e2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/IioBifurInit.c
@@ -0,0 +1,242 @@
+/** @file
+ IIO Config Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 = 0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Iou3,
+ Iio_Iou4,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ VPP_PORT_0 = 0,
+ VPP_PORT_1,
+ VPP_PORT_2,
+ VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE 1
+#define DISABLE 0
+
+static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] =
+{
+
+ { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_x4x4xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+
+ { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_xxx8x4x4, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }
+};
+//[-start-210223-Enhance_Dynamic_Type9-modify]//
+static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] = {
+ // Port Index | Slot |Interlock |power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard |ExtnCard |ExtnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard Hotplug|ExtnCard Hotplug|Max Retimer|
+ // | | |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port |Vpp Address | |
+ {SOCKET_0_INDEX +
+ PORT_1A_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1C_INDEX, 2 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1D_INDEX, 3 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2C_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4A_INDEX, 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5A_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+
+ {SOCKET_1_INDEX +
+ PORT_1A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2A_INDEX, 9 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2C_INDEX, 10 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4A_INDEX, 11 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4B_INDEX, 12 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4C_INDEX, 13 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5A_INDEX, 14 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }
+};
+
+EFI_STATUS
+UpdateJunctionCityIioConfig (
+ IN IIO_GLOBALS *IioGlobalData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeJunctionCityIioConfigTable =
+{
+ PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+ PLATFORM_IIO_CONFIG_UPDATE_VERSION_2,
+
+ IioBifurcationTable,
+ sizeof(IioBifurcationTable),
+ UpdateJunctionCityIioConfig,
+ IioSlotTable,
+ sizeof(IioSlotTable)
+};
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+TypeJunctionCityIioPortBifurcationInit (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+ PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX *PlatformIioInfoPtr;
+ UINTN PlatformIioInfoSize;
+
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ //
+ // This is config for ICX
+ //
+ PlatformIioInfoPtr = &TypeJunctionCityIioConfigTable;
+ PlatformIioInfoSize = sizeof(TypeJunctionCityIioConfigTable);
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_1,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_2,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_3,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/KtiEparam.c
new file mode 100644
index 0000000000..1ec1424d23
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/KtiEparam.c
@@ -0,0 +1,69 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <KtiSetupDefinitions.h>
+#include <UbaKti.h>
+
+extern EFI_GUID gPlatformKtiEparamUpdateDataGuid;
+
+ALL_LANES_EPARAM_LINK_INFO KtiJunctionCityIcxAllLanesEparamTable[] = {
+ //
+ // SocketID, Freq, Link, TXEQL, CTLEPEAK
+ // Please propagate changes to WilsonCitySMT and WilsonCityModular UBA KtiEparam tables
+ //
+ //
+ // Socket 0
+ //
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE},
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE},
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE},
+ //
+ // Socket 1
+ //
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2A31383F, ADAPTIVE_CTLE},
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A30393F, ADAPTIVE_CTLE},
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2C34373F, ADAPTIVE_CTLE}
+};
+
+PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeJunctionCityIcxKtiEparamUpdate = {
+ PLATFORM_KTIEP_UPDATE_SIGNATURE,
+ PLATFORM_KTIEP_UPDATE_VERSION,
+ KtiJunctionCityIcxAllLanesEparamTable,
+ sizeof (KtiJunctionCityIcxAllLanesEparamTable),
+ NULL,
+ 0
+};
+
+
+EFI_STATUS
+TypeJunctionCityInstallKtiEparamData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformKtiEparamUpdateDataGuid,
+ &TypeJunctionCityIcxKtiEparamUpdate,
+ sizeof(TypeJunctionCityIcxKtiEparamUpdate)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PcdData.c
new file mode 100644
index 0000000000..901e2b8f32
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PcdData.c
@@ -0,0 +1,275 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <ImonVrSvid.h>
+#include <Library/MemVrSvidMapLib.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/UbaPcdUpdateLib.h>
+#include <Library/PcdLib.h>
+#include <UncoreCommonIncludes.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <CpuAndRevisionDefines.h>
+
+#define GPIO_SKL_H_GPP_B20 0x01010014
+
+VOID TypeJunctionCityPlatformUpdateVrIdAddress (VOID);
+
+/**
+ Update JunctionCity IMON SVID Information
+
+ retval N/A
+**/
+VOID
+TypeJunctionCityPlatformUpdateImonAddress (
+ VOID
+ )
+{
+ VCC_IMON *VccImon = NULL;
+ UINTN Size = 0;
+
+ Size = sizeof (VCC_IMON);
+ VccImon = (VCC_IMON *) PcdGetPtr (PcdImonAddr);
+ if (VccImon == NULL) {
+ DEBUG ((EFI_D_ERROR, "UpdateImonAddress() - PcdImonAddr == NULL\n"));
+ return;
+ }
+
+ VccImon->VrSvid[0] = PcdGet8 (PcdWilsonCitySvidVrP1V8);
+ VccImon->VrSvid[1] = PcdGet8 (PcdWilsonCitySvidVrVccAna);
+ VccImon->VrSvid[2] = IMON_ADDR_LIST_END; // End array with 0xFF
+
+ PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon);
+}
+
+/**
+ Update WilsonCity VR ID SVID Information
+
+ retval N/A
+**/
+VOID
+TypeJunctionCityPlatformUpdateVrIdAddress (
+ VOID
+ )
+{
+ MEM_SVID_MAP *MemSvidMap = NULL;
+ UINTN Size = 0;
+
+ Size = sizeof (MEM_SVID_MAP);
+ MemSvidMap = (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap);
+ if (MemSvidMap == NULL) {
+ DEBUG ((EFI_D_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap == NULL\n"));
+ return;
+ }
+ /*
+ Map VR ID Address to Memory controller
+ The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, and 0x16.
+ Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (VR ID's 0x10 and 0x12).
+ Those are typically shared such that MC0/MC2 share the same DDR VR (as they are on the same side of the CPU)
+ and MC1/MC3 share the other. Depending on motherboard layout and other design constraints, this could change
+ BIT 4 => 0 or 1, SVID BUS\Interface 0 or 1 respectively
+ BIT 0:3 => SVID ADDRESS
+ */
+
+ MemSvidMap->Socket[0].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[0].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[1].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[1].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[2].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[2].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[3].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[3].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[4].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[4].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[5].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[5].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[6].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[6].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[7].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[7].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+
+ PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap);
+}
+
+EFI_STATUS
+TypeJunctionCityPlatformPcdUpdateCallback (
+ VOID
+)
+{
+ CHAR8 FamilyName[] = "Whitley";
+
+ CHAR8 BoardName[] = "EPRP";
+ UINT32 Data32;
+ UINTN Size;
+ UINTN PlatformFeatureFlag = 0;
+
+ CHAR16 PlatformName[] = L"TypeJunctionCity";
+ UINTN PlatformNameSize = 0;
+ EFI_STATUS Status;
+
+ //#Integer for BoardID, must match the SKU number and be unique.
+ Status = PcdSet16S (PcdOemSkuBoardID , TypeJunctionCity);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet16S (PcdOemSkuBoardFamily , 0x30);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Number of Sockets on Board.
+ Status = PcdSet32S (PcdOemSkuBoardSocketCount, 2);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Max channel and max DIMM
+ Status = PcdSet32S (PcdOemSkuMaxChannel , 8);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSetBoolS (PcdOemSkuDimmLayout, TRUE);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //Update Onboard Video Controller PCI Ven_id, Dev_id
+ Status = PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //#
+ //# Misc.
+ //#
+ //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF
+ Status = PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //SDP Active Flag
+ Status = PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Zero terminated string to ID family
+ Size = AsciiStrSize (FamilyName);
+ Status = PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Zero terminated string to Board Name
+ Size = AsciiStrSize (BoardName);
+ Status = PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ PlatformNameSize = sizeof (PlatformName);
+ Status = PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)PlatformNameSize);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNameSize, PlatformName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# FeaturesBasedOnPlatform
+ Status = PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)PlatformFeatureFlag);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Assert GPIO
+ Data32 = 0;
+ Status = PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# UplinkPortIndex
+ Status = PcdSet8S (PcdOemSkuUplinkPortIndex, 5);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ DEBUG ((EFI_D_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\n"));
+ Status = TypeJunctionCityPlatformUpdateAcpiTablePcds ();
+ //# BMC Pcie Port Number
+ PcdSet8S (PcdOemSkuBmcPciePortNumber, 5);
+ ASSERT_EFI_ERROR(Status);
+
+ //# Board Type Bit Mask
+ PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4));
+ ASSERT_EFI_ERROR(Status);
+
+ //Update IMON Address
+ TypeJunctionCityPlatformUpdateImonAddress ();
+
+ return Status;
+}
+
+PLATFORM_PCD_UPDATE_TABLE TypeJunctionCityPcdUpdateTable =
+{
+ PLATFORM_PCD_UPDATE_SIGNATURE,
+ PLATFORM_PCD_UPDATE_VERSION,
+ TypeJunctionCityPlatformPcdUpdateCallback
+};
+
+EFI_STATUS
+TypeJunctionCityInstallPcdData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPcdConfigDataGuid,
+ &TypeJunctionCityPcdUpdateTable,
+ sizeof(TypeJunctionCityPcdUpdateTable)
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PchEarlyUpdate.c
new file mode 100644
index 0000000000..e8cc05155a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PchEarlyUpdate.c
@@ -0,0 +1,93 @@
+/** @file
+ Pch Early update.
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+#include <Library/UbaPchEarlyUpdateLib.h>
+
+#include <PchAccess.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+EFI_STATUS
+TypeJunctionCityPchLanConfig (
+ IN SYSTEM_CONFIGURATION *SystemConfig
+)
+{
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+ EFI_STATUS Status;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ DynamicSiLibraryPpi->GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableByGpio);
+ DynamicSiLibraryPpi->PchDisableGbe ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+TypeJunctionCityOemInitLateHook (
+ IN SYSTEM_CONFIGURATION *SystemConfig
+)
+{
+ return EFI_SUCCESS;
+}
+
+
+PLATFORM_PCH_EARLY_UPDATE_TABLE TypeJunctionCityPchEarlyUpdateTable =
+{
+ PLATFORM_PCH_EARLY_UPDATE_SIGNATURE,
+ PLATFORM_PCH_EARLY_UPDATE_VERSION,
+ TypeJunctionCityPchLanConfig,
+ TypeJunctionCityOemInitLateHook
+};
+
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+EFIAPI
+TypeJunctionCityPchEarlyUpdate(
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PeiServicesLocatePpi (
+ &gUbaConfigDatabasePpiGuid,
+ 0,
+ NULL,
+ &UbaConfigPpi
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPchEarlyConfigDataGuid,
+ &TypeJunctionCityPchEarlyUpdateTable,
+ sizeof(TypeJunctionCityPchEarlyUpdateTable)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInit.h
new file mode 100644
index 0000000000..1c596a30c4
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInit.h
@@ -0,0 +1,78 @@
+/** @file
+ PeiBoardInit.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_BOARD_INIT_PEIM_H_
+#define _PEI_BOARD_INIT_PEIM_H_
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Ppi/UbaCfgDb.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+// TypeJunctionCity
+EFI_STATUS
+TypeJunctionCityPlatformUpdateUsbOcMappings (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityPlatformUpdateAcpiTablePcds (
+ VOID
+);
+
+EFI_STATUS
+TypeJunctionCityInstallClockgenData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityInstallPcdData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityPchEarlyUpdate (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityIioPortBifurcationInit (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityInstallSlotTableData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityInstallKtiEparamData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+// TypeJunctionCity
+EFI_STATUS
+TypeJunctionCityInstallGpioData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+) ;
+
+EFI_STATUS
+TypeJunctionCityInstallSoftStrapData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+#endif // _PEI_BOARD_INIT_PEIM_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.c
new file mode 100644
index 0000000000..7895f4d975
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.c
@@ -0,0 +1,157 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+/**
+ The constructor function for Board Init Libray.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Table initialization successfully.
+ @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table.
+**/
+
+#include "PeiBoardInit.h"
+#include <UncoreCommonIncludes.h>
+#include <Library/PchMultiPchBase.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+EFI_STATUS
+EFIAPI
+TypeJunctionCityPeiBoardInitLibConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UBA_CONFIG_DATABASE_PPI *UbaConfigPpi;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+ UINT8 SocketIndex;
+ UINT8 ChannelIndex;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
+
+ if (PlatformInfo->BoardId == TypeJunctionCity) {
+
+ DEBUG ((EFI_D_INFO, "PEI UBA init BoardId 0x%X: JunctionCity\n", PlatformInfo->BoardId));
+
+ // Socket 0 has SMT DIMM connector, Socket 1 has PTH DIMM connector
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) {
+ for (ChannelIndex = 0; ChannelIndex < MAX_CH; ChannelIndex++) {
+ switch (SocketIndex) {
+ case 0:
+ PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorSmt;
+ break;
+ case 1:
+ // Fall through since socket 1 is PTH type
+ default:
+ // Use the more restrictive type as the default case
+ PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorPth;
+ break;
+ }
+ }
+ }
+
+ BuildGuidDataHob (
+ &gEfiPlatformInfoGuid,
+ &(PlatformInfo),
+ sizeof (EFI_PLATFORM_INFO)
+ );
+
+ Status = PeiServicesLocatePpi (
+ &gUbaConfigDatabasePpiGuid,
+ 0,
+ NULL,
+ &UbaConfigPpi
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->InitSku (
+ UbaConfigPpi,
+ PlatformInfo->BoardId,
+ NULL,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = TypeJunctionCityInstallGpioData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallPcdData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallSoftStrapData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityPchEarlyUpdate (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityPlatformUpdateUsbOcMappings (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallSlotTableData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallKtiEparamData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) {
+
+ //
+ // Set default memory type connector.
+ // Socket 0: DimmConnectorSmt
+ // Socket 1: DimmConnectorPth
+ //
+ if (SocketIndex % 2 == 0) {
+ (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorSmt);
+ } else {
+ (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorPth);
+ }
+ }
+
+ //
+ // Initialize InterposerType to InterposerUnknown
+ //
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; ++SocketIndex) {
+ PlatformInfo->InterposerType[SocketIndex] = InterposerUnknown;
+ }
+
+ //
+ // TypeJunctionCityIioPortBifurcationInit will use PlatformInfo->InterposerType for PPO.
+ //
+ Status = TypeJunctionCityIioPortBifurcationInit (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ }
+ return Status;
+}
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf
new file mode 100644
index 0000000000..ee6fdb95ff
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf
@@ -0,0 +1,167 @@
+## @file
+# Component information file for BoardInitLib in PEI post memory phase.
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+# @par Specification Reference:
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TypeJunctionCityPeiBoardInitLib
+ FILE_GUID = F92478AE-058E-4E2A-939C-B806D461398E
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL|PEIM
+ CONSTRUCTOR = TypeJunctionCityPeiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PeiServicesLib
+ HobLib
+ PeiServicesTablePointerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+
+[Sources]
+ PeiBoardInitLib.c
+ GpioTable.c
+ PcdData.c
+ UsbOC.c
+ AcpiTablePcds.c
+ IioBifurInit.c
+ SlotTable.c
+ KtiEparam.c
+ PchEarlyUpdate.c
+ SoftStrapFixup.c
+ PeiBoardInit.h
+
+[FixedPcd]
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardID
+ gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardName
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel
+ gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed
+ gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue
+ gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber
+ gOemSkuTokenSpaceGuid.PcdOemTableIdXhci
+ gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex
+ gPlatformTokenSpaceGuid.PcdBoardTypeBitmask
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna
+ gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr
+ gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap
+
+ gPlatformTokenSpaceGuid.PcdMemInterposerMap
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId
+
+[Ppis]
+ gUbaConfigDatabasePpiGuid
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Guids]
+ gPlatformGpioInitDataGuid
+
+[Depex]
+ gDynamicSiLibraryPpiGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SlotTable.c
new file mode 100644
index 0000000000..963515ea41
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SlotTable.c
@@ -0,0 +1,172 @@
+/** @file
+ Slot Table Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+#define PCI_DEVICE_ON_BOARD_TRUE 0
+#define PCI_DEVICE_ON_BOARD_FALSE 1
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Iou3,
+ Iio_Iou4,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ Bw5_Addr_0 = 0,
+ Bw5_Addr_1,
+ Bw5_Addr_2,
+ Bw5_Addr_3,
+ Bw5_Addr_Max
+} BW5_ADDRESS;
+
+static UINT8 TypeJunctionCityPchPciSlotImpementedTableData[] = {
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 0
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 3
+ PCI_DEVICE_ON_BOARD_TRUE, // Root Port 4
+ PCI_DEVICE_ON_BOARD_TRUE, // Root Port 5
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18
+ PCI_DEVICE_ON_BOARD_FALSE // Root Port 19
+};
+
+UINT8
+GetTypeJunctionCityIOU0Setting (
+ UINT8 IOU0Data
+)
+{
+ //
+ // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
+ //
+ IOU0Data = IIO_BIFURCATE_xxx8xxx8;
+ return IOU0Data;
+}
+
+UINT8
+GetTypeJunctionCityIOU2Setting (
+ UINT8 SkuPersonalityType,
+ UINT8 IOU2Data
+)
+{
+ return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeJunctionCityBroadwayTable[] = {
+ {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+ {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
+ {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+
+PLATFORM_SLOT_UPDATE_TABLE TypeJunctionCitySlotTable =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2 TypeJunctionCitySlotTable2 =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0,
+ GetTypeJunctionCityIOU2Setting
+};
+
+PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeJunctionCityPchPciSlotImplementedTable = {
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ TypeJunctionCityPchPciSlotImpementedTableData
+};
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+TypeJunctionCityInstallSlotTableData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformSlotDataGuid,
+ &TypeJunctionCitySlotTable,
+ sizeof(TypeJunctionCitySlotTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformSlotDataGuid2,
+ &TypeJunctionCitySlotTable2,
+ sizeof(TypeJunctionCitySlotTable2)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPciSlotImplementedGuid,
+ &TypeJunctionCityPchPciSlotImplementedTable,
+ sizeof(TypeJunctionCityPchPciSlotImplementedTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SoftStrapFixup.c
new file mode 100644
index 0000000000..541961b020
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SoftStrapFixup.c
@@ -0,0 +1,121 @@
+/** @file
+ Soft Strap update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSoftStrapUpdateLib.h>
+
+PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeJunctionCitySoftStrapTable[] =
+{
+// SoftStrapNumber, LowBit, BitLength, Value
+ {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary Mux Select
+ {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control
+ {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2)
+ {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3)
+ {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select between sSATA Port 2 and PCIe Port 8)
+ {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_GP2)
+ {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_GP3)
+ {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled
+ {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2
+ {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3
+ {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0
+ {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1
+ {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2
+ {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3
+ {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4
+ {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2
+ {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5
+ {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6
+ {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7
+ {19, 26, 1, 0x1 }, // Statically assign PCH PCIe NP8 Uplink to act as Downlink or Uplink(PCIEUDS)
+ {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address
+ {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address
+ {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable
+ {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect
+ {88, 8, 2, 0x3 }, // Root Port Configuration 0
+ {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between SATA Port 0 and PCIe Port 12
+ {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between SATA Port 1 and PCIe Port 13
+ {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between SATA Port 2 and PCIe Port 14
+ {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between SATA Port 3 and PCIe Port 15
+ {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between SATA Port 4 and PCIe Port 16
+ {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between SATA Port 5 and PCIe Port 17
+ {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between SATA Port 6 and PCIe Port 18
+ {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between SATA Port 7 and PCIe Port 19
+ {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0 and PCIe Port 12
+ {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1 and PCIe Port 13
+ {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2 and PCIe Port 14
+ {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3 and PCIe Port 15
+ {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4 and PCIe Port 16
+ {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5 and PCIe Port 17
+ {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6 and PCIe Port 18
+ {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7 and PCIe Port 19
+ {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection
+ {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled
+ {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled
+// {133, 1, 1, 0x1 }, // Dual I/O Read Enabled
+// {133, 2, 1, 0x1 }, // Quad Output Read Enabled
+// {133, 3, 1, 0x1 }, // Quad I/O Read Enabled
+// {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode
+// {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable
+// {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency
+// {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode
+
+//
+// END OF LIST
+//
+ {0, 0, 0, 0}
+};
+
+UINT32
+TypeJunctionCitySystemBoardRevIdValue (VOID)
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT(GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return 0xFF;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
+ return PlatformInfo->TypeRevisionId;
+}
+
+VOID
+TypeJunctionCityPlatformSpecificUpdate (
+ IN OUT UINT8 *FlashDescriptorCopy
+ )
+{
+}
+
+PLATFORM_PCH_SOFTSTRAP_UPDATE TypeJunctionCitySoftStrapUpdate =
+{
+ PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE,
+ PLATFORM_SOFT_STRAP_UPDATE_VERSION,
+ TypeJunctionCitySoftStrapTable,
+ TypeJunctionCityPlatformSpecificUpdate
+};
+
+EFI_STATUS
+TypeJunctionCityInstallSoftStrapData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPchSoftStrapConfigDataGuid,
+ &TypeJunctionCitySoftStrapUpdate,
+ sizeof(TypeJunctionCitySoftStrapUpdate)
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/UsbOC.c
new file mode 100644
index 0000000000..eaf59de869
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/UsbOC.c
@@ -0,0 +1,127 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+
+#include <Library/PcdLib.h>
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+ UsbOverCurrentPin0,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin2,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin7,
+ UsbOverCurrentPin7,
+ UsbOverCurrentPin6,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPin6,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPin5,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+ UsbOverCurrentPin0,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin2,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB2_PHY_PARAMETERS TypeJunctionCityUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+ {3, 0, 3, 1}, // PP0
+ {5, 0, 3, 1}, // PP1
+ {3, 0, 3, 1}, // PP2
+ {0, 5, 1, 1}, // PP3
+ {3, 0, 3, 1}, // PP4
+ {3, 0, 3, 1}, // PP5
+ {3, 0, 3, 1}, // PP6
+ {3, 0, 3, 1}, // PP7
+ {2, 2, 1, 0}, // PP8
+ {6, 0, 2, 1}, // PP9
+ {2, 2, 1, 0}, // PP10
+ {6, 0, 2, 1}, // PP11
+ {0, 5, 1, 1}, // PP12
+ {7, 0, 2, 1}, // PP13
+ };
+
+EFI_STATUS
+TypeJunctionCityPlatformUsbOcUpdateCallback (
+ IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings,
+ IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings,
+ IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams
+)
+{
+ *Usb20OverCurrentMappings = &TypeJunctionCityUsb20OverCurrentMappings[0];
+ *Usb30OverCurrentMappings = &TypeJunctionCityUsb30OverCurrentMappings[0];
+
+ *Usb20AfeParams = TypeJunctionCityUsb20AfeParams;
+ return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE TypeJunctionCityUsbOcUpdate =
+{
+ PLATFORM_USBOC_UPDATE_SIGNATURE,
+ PLATFORM_USBOC_UPDATE_VERSION,
+ TypeJunctionCityPlatformUsbOcUpdateCallback
+};
+
+EFI_STATUS
+TypeJunctionCityPlatformUpdateUsbOcMappings (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ //#
+ //# USB, see PG 104 in GZP SCH
+ //#
+
+// USB2 USB3 Port OC
+//
+//Port00: PORT5 Back Panel ,OC0#
+//Port01: PORT2 Back Panel ,OC0#
+//Port02: PORT3 Back Panel ,OC1#
+//Port03: PORT0 NOT USED ,NA
+//Port04: BMC1.0 ,NA
+//Port05: INTERNAL_2X5_A ,OC2#
+//Port06: INTERNAL_2X5_A ,OC2#
+//Port07: NOT USED ,NA
+//Port08: EUSB (AKA SSD) ,NA
+//Port09: INTERNAL_TYPEA ,OC6#
+//Port10: PORT1 Front Panel ,OC5#
+//Port11: NOT USED ,NA
+//Port12: BMC2.0 ,NA
+//Port13: PORT4 Front Panel ,OC5#
+
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPeiPlatformUbaOcConfigDataGuid,
+ &TypeJunctionCityUsbOcUpdate,
+ sizeof(TypeJunctionCityUsbOcUpdate)
+ );
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
index f37093bccd..f527632f4f 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
@@ -3,6 +3,7 @@
#
# @copyright
# Copyright 2012 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -16,6 +17,7 @@ $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf {
NULL|$(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Pei/PeiBoardInitLib.inf
NULL|$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Pei/PeiBoardInitLib.inf
NULL|$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.inf
+ NULL|$(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf
#
#### NO PLATFORM SPECIFIC LIBRARY CLASSES AFTER THIS LINE!!!!
#
@@ -50,3 +52,10 @@ $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.i
$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
+
+#
+# Platform TypeJunctionCity
+#
+$(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
+$(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
+$(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
index 2827334797..de656633cd 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -67,3 +67,4 @@ TigerlakeURvp = TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg
CooperCityRvp = WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg
WilsonCityRvp = WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
BoardTiogaPass = PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg
+JunctionCity = WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
diff --git a/Readme.md b/Readme.md
index 62876b4b7d..78771ff82d 100644
--- a/Readme.md
+++ b/Readme.md
@@ -248,6 +248,7 @@ they will be documented with the platform.
* [Comet Lake](Platform/Intel/CometlakeOpenBoardPkg)
* [Tiger Lake](Platform/Intel/TigerlakeOpenBoardPkg)
* [Whitley/Cedar Island](Platform/Intel/WhitleyOpenBoardPkg)
+* [Whitley/JunctionCity](Platform/Intel/WhitleyOpenBoardPkg)
For more information, see the
[EDK II Minimum Platform Specification](https://nam12.safelinks.protection.outlook.com/?url=https%3A%2F%2Fedk2-docs.gitbooks.io%2Fedk-ii-minimum-platform-specification&data=04%7C01%7Cmanickavasakamk%40ami.com%7C1d8711b0b291459a3f4308d9b91a7fb1%7C27e97857e15f486cb58e86c2b3040f93%7C1%7C0%7C637744345773826034%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=oc27EnL6kTkkoOZiRovSGL3qhw5te%2FhU3u4dhjSBMus%3D&reserved=0).
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
index ca91434663..bdbf6a8d02 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
@@ -2,6 +2,7 @@
@copyright
Copyright 2020 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -63,6 +64,7 @@ typedef enum {
TypeArcherCityXPV,
TypeBigPineKey,
TypeExperWorkStationRP,
+ TypeJunctionCity,
EndOfEfiPlatformTypeEnum
} EFI_PLATFORM_TYPE;
--
2.25.0.windows.1
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next prev parent reply other threads:[~2021-12-07 17:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-29 23:15 [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform manickavasakam karpagavinayagam
2021-12-07 0:42 ` Oram, Isaac W
2021-12-07 17:01 ` manickavasakam karpagavinayagam [this message]
2021-12-07 19:32 ` [EXTERNAL] " Oram, Isaac W
2021-12-08 14:26 ` manickavasakam karpagavinayagam
2021-12-08 0:56 ` manickavasakam karpagavinayagam
2021-12-08 1:25 ` Sureshkumar Ponnusamy
2021-12-08 18:46 ` Oram, Isaac W
2021-12-08 19:26 ` Sureshkumar Ponnusamy
2021-12-14 0:10 ` Nate DeSimone
2021-12-14 15:05 ` [EXTERNAL] " manickavasakam karpagavinayagam
2021-12-15 22:17 ` [edk2-devel] " Nate DeSimone
2021-12-16 15:29 ` manickavasakam karpagavinayagam
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