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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Oro6lZ00eVDhk1WaAANxcw81x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="wT8NGy/b"; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Ray, Could you help to review and merge this Vtd driver patch to edk2platforms b= ranch? This patch is used to fix a bug about missing to mask one-shot bits when wr= ite VTD GCMD_REG register. Here is the PR of this patch. https://github.com/tianocore/edk2-platforms/pull/125 Thank you. BR Sheng Wei > -----Original Message----- > From: Huang, Jenny > Sent: Thursday, February 29, 2024 3:10 PM > To: devel@edk2.groups.io; Sheng, W > Cc: Ni, Ray ; Chaganty, Rangasai V > > Subject: RE: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Reset the one-shot= bits > before modifing GCMD_REG >=20 > Reviewed-by: Jenny Huang >=20 > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Sheng, W > Sent: Monday, February 19, 2024 7:37 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Chaganty, Rangasai V > ; Huang, Jenny > Subject: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Reset the one-shot bit= s > before modifing GCMD_REG >=20 > Here is the process of modify GCMD_REG. > Read GSTS_REG > Reset the one-shot bits. > Modify the target comamnd value. > Write the command value to GCMD_REG. > Wait until GSTS_REG indicates command is serviced. >=20 > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Jenny Huang > Signed-off-by: Sheng Wei > --- > .../Feature/VTd/IntelVTdCoreDxe/VtdReg.c | 13 ++---- > .../VTd/IntelVTdCorePei/IntelVTdDmar.c | 9 +--- > .../VTd/IntelVTdDmarPei/IntelVTdDmar.c | 43 +++++++++--------- > .../Feature/VTd/IntelVTdDxe/VtdReg.c | 44 +++++++++---------- > .../Feature/VTd/IntelVTdPmrPei/VtdReg.c | 1 + > .../IntelVTdPeiDxeLib/IntelVTdPeiDxeLib.c | 12 ++--- > 6 files changed, 51 insertions(+), 71 deletions(-) >=20 > diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/VtdReg.c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/VtdReg.c > index edeb4b3ff..21e2d5f1b 100644 > --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/VtdReg.c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/VtdReg.c > @@ -112,13 +112,8 @@ PerpareCacheInvalidationInterface ( > // Enable the queued invalidation interface through the Global Command > Register. >=20 > // When enabled, hardware sets the QIES field in the Global Status Reg= ister. >=20 > // >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - Reg32 |=3D B_GMCD_REG_QIE; >=20 > - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32); >=20 > - DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface. GCMD_REG = =3D > 0x%x\n", Reg32)); >=20 > - do { >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - } while ((Reg32 & B_GSTS_REG_QIES) =3D=3D 0); >=20 > + DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface.\n")); >=20 > + VtdLibSetGlobalCommandRegisterBits (VtdUnitBaseAddress, > B_GMCD_REG_QIE); >=20 >=20 >=20 > VTdLogAddEvent (VTDLOG_DXE_QUEUED_INVALIDATION, > VTD_LOG_QI_ENABLE, VtdUnitBaseAddress); >=20 >=20 >=20 > @@ -577,7 +572,7 @@ DumpVtdCapRegs ( > IN VTD_CAP_REG *CapReg >=20 > ) >=20 > { >=20 > - DEBUG((DEBUG_INFO, " CapReg - 0x%x\n", CapReg->Uint64)); >=20 > + DEBUG((DEBUG_INFO, " CapReg - 0x%lx\n", CapReg->Uint64)); >=20 > DEBUG((DEBUG_INFO, " ND - 0x%x\n", CapReg->Bits.ND)); >=20 > DEBUG((DEBUG_INFO, " AFL - 0x%x\n", CapReg->Bits.AFL)); >=20 > DEBUG((DEBUG_INFO, " RWBF - 0x%x\n", CapReg->Bits.RWBF)); >=20 > @@ -737,7 +732,7 @@ DumpVtdIfError ( > if (HasError) { >=20 > REPORT_STATUS_CODE (EFI_ERROR_CODE, PcdGet32 > (PcdErrorCodeVTdError)); >=20 > DEBUG((DEBUG_INFO, "\n#### ERROR ####\n")); >=20 > - DumpVtdRegs (mVtdUnitInformation[Num].VtdUnitBaseAddress); > + DumpVtdRegs (mVtdUnitInformation[Num].VtdUnitBaseAddress); >=20 > DEBUG((DEBUG_INFO, "#### ERROR ####\n\n")); >=20 > // >=20 > // Clear >=20 > diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCorePei/IntelVTdDmar.= c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCorePei/IntelVTdDmar.= c > index 93207ba52..549313dbf 100644 > --- > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCorePei/IntelVTdDmar.= c > +++ > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCorePei/IntelVTdDmar.= c > @@ -120,13 +120,8 @@ PerpareCacheInvalidationInterface ( > // Enable the queued invalidation interface through the Global Command > Register. >=20 > // When enabled, hardware sets the QIES field in the Global Status Reg= ister. >=20 > // >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - Reg32 |=3D B_GMCD_REG_QIE; >=20 > - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32); >=20 > - DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface. GCMD_REG = =3D > 0x%x\n", Reg32)); >=20 > - do { >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - } while ((Reg32 & B_GSTS_REG_QIES) =3D=3D 0); >=20 > + DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface.\n")); >=20 > + VtdLibSetGlobalCommandRegisterBits (VtdUnitBaseAddress, > B_GMCD_REG_QIE); >=20 >=20 >=20 > VTdLogAddEvent (VTDLOG_PEI_QUEUED_INVALIDATION, > VTD_LOG_QI_ENABLE, VtdUnitBaseAddress); >=20 >=20 >=20 > diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.= c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.= c > index e1b867973..533fb2b9a 100644 > --- > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.= c > +++ > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.= c > @@ -20,6 +20,18 @@ > #include >=20 > #include "IntelVTdDmarPei.h" >=20 >=20 >=20 > +VOID >=20 > +SetGlobalCommandRegisterBits ( >=20 > + IN UINTN VtdUnitBaseAddress, >=20 > + IN UINT32 BitMask >=20 > + ); >=20 > + >=20 > +VOID >=20 > +ClearGlobalCommandRegisterBits ( >=20 > + IN UINTN VtdUnitBaseAddress, >=20 > + IN UINT32 BitMask >=20 > + ); >=20 > + >=20 > /** >=20 > Flush VTD page table and context table memory. >=20 >=20 >=20 > @@ -58,6 +70,7 @@ FlushWriteBuffer ( >=20 >=20 > if (CapReg.Bits.RWBF !=3D 0) { >=20 > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > + Reg32 =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits >=20 > MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | > B_GMCD_REG_WBF); >=20 > do { >=20 > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > @@ -104,11 +117,7 @@ PerpareCacheInvalidationInterface ( > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > if ((Reg32 & B_GSTS_REG_QIES) !=3D 0) { >=20 > DEBUG ((DEBUG_INFO,"Queued Invalidation Interface was enabled.\n")); >=20 > - Reg32 &=3D (~B_GSTS_REG_QIES); >=20 > - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32); >=20 > - do { >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0); >=20 > + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, > B_GMCD_REG_QIE); >=20 > MmioWrite64 (VtdUnitBaseAddress + R_IQA_REG, 0); >=20 > } >=20 >=20 >=20 > @@ -144,13 +153,8 @@ PerpareCacheInvalidationInterface ( > // Enable the queued invalidation interface through the Global Command > Register. >=20 > // When enabled, hardware sets the QIES field in the Global Status Reg= ister. >=20 > // >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - Reg32 |=3D B_GMCD_REG_QIE; >=20 > - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32); >=20 > - DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface. GCMD_REG = =3D > 0x%x\n", Reg32)); >=20 > - do { >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - } while ((Reg32 & B_GSTS_REG_QIES) =3D=3D 0); >=20 > + DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface.\n")); >=20 > + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_QIE); >=20 >=20 >=20 > return EFI_SUCCESS; >=20 > } >=20 > @@ -165,16 +169,9 @@ DisableQueuedInvalidationInterface ( > IN VTD_UNIT_INFO *VTdUnitInfo >=20 > ) >=20 > { >=20 > - UINT32 Reg32; >=20 > - >=20 > if (VTdUnitInfo->EnableQueuedInvalidation !=3D 0) { >=20 > - Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + R_GSTS_REG); >=20 > - Reg32 &=3D (~B_GMCD_REG_QIE); >=20 > - MmioWrite32 (VTdUnitInfo->VtdUnitBaseAddress + R_GCMD_REG, > Reg32); >=20 > - DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface. GCMD_REG > =3D 0x%x\n", Reg32)); >=20 > - do { >=20 > - Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + > R_GSTS_REG); >=20 > - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0); >=20 > + DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface.\n")); >=20 > + ClearGlobalCommandRegisterBits (VTdUnitInfo->VtdUnitBaseAddress, > B_GMCD_REG_QIE); >=20 >=20 >=20 > if (VTdUnitInfo->QiDescBuffer !=3D NULL) { >=20 > FreePages(VTdUnitInfo->QiDescBuffer, EFI_SIZE_TO_PAGES (VTdUnitInf= o- > >QiDescBufferSize)); >=20 > @@ -206,7 +203,7 @@ QueuedInvalidationCheckFault ( > if (FaultReg & (B_FSTS_REG_IQE | B_FSTS_REG_ITE | B_FSTS_REG_ICE)) { >=20 > IqercdReg.Uint64 =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + > R_IQERCD_REG); >=20 >=20 >=20 > - DEBUG((DEBUG_ERROR, "Detect Queue Invalidation Error [0x%08x] - > IQERCD [0x%016lx]\n", FaultReg, IqercdReg.Uint64)); >=20 > + DEBUG((DEBUG_ERROR, "VTD 0x%x Detect Queue Invalidation Error > [0x%08x] - IQERCD [0x%016lx]\n", VTdUnitInfo->VtdUnitBaseAddress, > FaultReg, IqercdReg.Uint64)); >=20 >=20 >=20 > MmioWrite32 (VTdUnitInfo->VtdUnitBaseAddress + R_FSTS_REG, > FaultReg); >=20 > return RETURN_DEVICE_ERROR; >=20 > @@ -763,7 +760,7 @@ EnableVTdTranslationProtection ( >=20 >=20 > if (VtdUnitInfo->ExtRootEntryTable !=3D 0) { >=20 > DEBUG ((DEBUG_INFO, "EnableVtdDmar (%d) ExtRootEntryTable 0x%x\n", > Index, VtdUnitInfo->ExtRootEntryTable)); >=20 > - Status =3D EnableDmar (VtdUnitInfo, VtdUnitInfo->ExtRootEntryTable= | > BIT11); > + Status =3D EnableDmar (VtdUnitInfo, VtdUnitInfo->ExtRootEntryTable= | > BIT11); >=20 > } else { >=20 > DEBUG ((DEBUG_INFO, "EnableVtdDmar (%d) RootEntryTable 0x%x\n", > Index, VtdUnitInfo->RootEntryTable)); >=20 > Status =3D EnableDmar (VtdUnitInfo, VtdUnitInfo->RootEntryTable); >=20 > diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg= .c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > index 30dab4a64..2c48eefe9 100644 > --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > @@ -12,6 +12,18 @@ VTD_UNIT_INFORMATION > *mVtdUnitInformation; >=20 >=20 > BOOLEAN mVtdEnabled; >=20 >=20 >=20 > +VOID >=20 > +SetGlobalCommandRegisterBits ( >=20 > + IN UINTN VtdUnitBaseAddress, >=20 > + IN UINT32 BitMask >=20 > + ); >=20 > + >=20 > +VOID >=20 > +ClearGlobalCommandRegisterBits ( >=20 > + IN UINTN VtdUnitBaseAddress, >=20 > + IN UINT32 BitMask >=20 > + ); >=20 > + >=20 > /** >=20 > Flush VTD page table and context table memory. >=20 >=20 >=20 > @@ -47,6 +59,7 @@ FlushWriteBuffer ( >=20 >=20 > if (mVtdUnitInformation[VtdIndex].CapReg.Bits.RWBF !=3D 0) { >=20 > Reg32 =3D MmioRead32 > (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG); >=20 > + Reg32 =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits >=20 > MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + > R_GCMD_REG, Reg32 | B_GMCD_REG_WBF); >=20 > do { >=20 > Reg32 =3D MmioRead32 > (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GSTS_REG); >=20 > @@ -93,11 +106,7 @@ PerpareCacheInvalidationInterface ( > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > if ((Reg32 & B_GSTS_REG_QIES) !=3D 0) { >=20 > DEBUG ((DEBUG_ERROR,"Queued Invalidation Interface was enabled.\n"))= ; >=20 > - Reg32 &=3D (~B_GSTS_REG_QIES); >=20 > - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32); >=20 > - do { >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0); >=20 > + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, > B_GMCD_REG_QIE); >=20 > } >=20 >=20 >=20 > // >=20 > @@ -132,13 +141,8 @@ PerpareCacheInvalidationInterface ( > // Enable the queued invalidation interface through the Global Command > Register. >=20 > // When enabled, hardware sets the QIES field in the Global Status Reg= ister. >=20 > // >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - Reg32 |=3D B_GMCD_REG_QIE; >=20 > - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32); >=20 > - DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface. GCMD_REG = =3D > 0x%x\n", Reg32)); >=20 > - do { >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - } while ((Reg32 & B_GSTS_REG_QIES) =3D=3D 0); >=20 > + DEBUG ((DEBUG_INFO, "Enable Queued Invalidation Interface.\n")); >=20 > + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_QIE); >=20 >=20 >=20 > return EFI_SUCCESS; >=20 > } >=20 > @@ -153,19 +157,13 @@ DisableQueuedInvalidationInterface ( > IN UINTN VtdIndex >=20 > ) >=20 > { >=20 > - UINT32 Reg32; >=20 > VTD_UNIT_INFORMATION *VTdUnitInfo; >=20 >=20 >=20 > VTdUnitInfo =3D &mVtdUnitInformation[VtdIndex]; >=20 >=20 >=20 > if (VTdUnitInfo->EnableQueuedInvalidation !=3D 0) { >=20 > - Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + R_GSTS_REG); >=20 > - Reg32 &=3D (~B_GMCD_REG_QIE); >=20 > - MmioWrite32 (VTdUnitInfo->VtdUnitBaseAddress + R_GCMD_REG, > Reg32); >=20 > - DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface. GCMD_REG > =3D 0x%x\n", Reg32)); >=20 > - do { >=20 > - Reg32 =3D MmioRead32 (VTdUnitInfo->VtdUnitBaseAddress + > R_GSTS_REG); >=20 > - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0); >=20 > + DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface.\n")); >=20 > + ClearGlobalCommandRegisterBits (VTdUnitInfo->VtdUnitBaseAddress, > B_GMCD_REG_QIE); >=20 >=20 >=20 > if (VTdUnitInfo->QiDescBuffer !=3D NULL) { >=20 > FreePages(VTdUnitInfo->QiDescBuffer, EFI_SIZE_TO_PAGES (VTdUnitInf= o- > >QiDescBufferSize)); >=20 > @@ -198,7 +196,7 @@ QueuedInvalidationCheckFault ( > if (FaultReg & (B_FSTS_REG_IQE | B_FSTS_REG_ITE | B_FSTS_REG_ICE)) { >=20 > IqercdReg.Uint64 =3D MmioRead64 > (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_IQERCD_REG); >=20 >=20 >=20 > - DEBUG((DEBUG_ERROR, "Detect Queue Invalidation Error [0x%08x] - > IQERCD [0x%016lx]\n", FaultReg, IqercdReg.Uint64)); >=20 > + DEBUG((DEBUG_ERROR, "VTD 0x%x Detect Queue Invalidation Error > [0x%08x] - IQERCD [0x%016lx]\n", > mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress, FaultReg, > IqercdReg.Uint64)); >=20 >=20 >=20 > MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + > R_FSTS_REG, FaultReg); >=20 > return RETURN_DEVICE_ERROR; >=20 > @@ -802,7 +800,7 @@ DumpVtdCapRegs ( > IN VTD_CAP_REG *CapReg >=20 > ) >=20 > { >=20 > - DEBUG((DEBUG_INFO, " CapReg - 0x%x\n", CapReg->Uint64)); >=20 > + DEBUG((DEBUG_INFO, " CapReg - 0x%016lx\n", CapReg->Uint64)); >=20 > DEBUG((DEBUG_INFO, " ND - 0x%x\n", CapReg->Bits.ND)); >=20 > DEBUG((DEBUG_INFO, " AFL - 0x%x\n", CapReg->Bits.AFL)); >=20 > DEBUG((DEBUG_INFO, " RWBF - 0x%x\n", CapReg->Bits.RWBF)); >=20 > @@ -833,7 +831,7 @@ DumpVtdECapRegs ( > IN VTD_ECAP_REG *ECapReg >=20 > ) >=20 > { >=20 > - DEBUG((DEBUG_INFO, " ECapReg - 0x%x\n", ECapReg->Uint64)); >=20 > + DEBUG((DEBUG_INFO, " ECapReg - 0x%016lx\n", ECapReg->Uint64)); >=20 > DEBUG((DEBUG_INFO, " C - 0x%x\n", ECapReg->Bits.C)); >=20 > DEBUG((DEBUG_INFO, " QI - 0x%x\n", ECapReg->Bits.QI)); >=20 > DEBUG((DEBUG_INFO, " DT - 0x%x\n", ECapReg->Bits.DT)); >=20 > diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Vtd= Reg.c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > index 2e252fe5b..03b39d183 100644 > --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > @@ -54,6 +54,7 @@ FlushWriteBuffer ( >=20 >=20 > if (CapReg.Bits.RWBF !=3D 0) { >=20 > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > + Reg32 =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits >=20 > MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | > B_GMCD_REG_WBF); >=20 > do { >=20 > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > diff --git > a/Silicon/Intel/IntelSiliconPkg/Library/IntelVTdPeiDxeLib/IntelVTdPeiDxeL= ib.c > b/Silicon/Intel/IntelSiliconPkg/Library/IntelVTdPeiDxeLib/IntelVTdPeiDxeL= ib.c > index 3e22c3d92..135e740d6 100644 > --- > a/Silicon/Intel/IntelSiliconPkg/Library/IntelVTdPeiDxeLib/IntelVTdPeiDxeL= ib.c > +++ > b/Silicon/Intel/IntelSiliconPkg/Library/IntelVTdPeiDxeLib/IntelVTdPeiDxeL= ib.c > @@ -1497,6 +1497,7 @@ VtdLibFlushWriteBuffer ( >=20 >=20 > if (CapReg.Bits.RWBF !=3D 0) { >=20 > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > + Reg32 =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits >=20 > MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | > B_GMCD_REG_WBF); >=20 > do { >=20 > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > @@ -1664,7 +1665,6 @@ VtdLibDisableQueuedInvalidationInterface ( > IN UINTN VtdUnitBaseAddress >=20 > ) >=20 > { >=20 > - UINT32 Reg32; >=20 > QI_256_DESC QiDesc; >=20 >=20 >=20 > QiDesc.Uint64[0] =3D QI_IWD_TYPE; >=20 > @@ -1674,14 +1674,8 @@ VtdLibDisableQueuedInvalidationInterface ( >=20 >=20 > VtdLibSubmitQueuedInvalidationDescriptor (VtdUnitBaseAddress, &QiDesc, > TRUE); >=20 >=20 >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - Reg32 &=3D (~B_GMCD_REG_QIE); >=20 > - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32); >=20 > - >=20 > - DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface. [%x] > GCMD_REG =3D 0x%x\n", VtdUnitBaseAddress, Reg32)); >=20 > - do { >=20 > - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); >=20 > - } while ((Reg32 & B_GSTS_REG_QIES) !=3D 0); >=20 > + DEBUG ((DEBUG_INFO, "Disable Queued Invalidation Interface. [%x]\n", > VtdUnitBaseAddress)); >=20 > + VtdLibClearGlobalCommandRegisterBits (VtdUnitBaseAddress, > B_GMCD_REG_QIE); >=20 >=20 >=20 > MmioWrite64 (VtdUnitBaseAddress + R_IQA_REG, 0); >=20 > } >=20 > -- > 2.26.2.windows.1 >=20 >=20 >=20 > -=3D-=3D-=3D-=3D-=3D-=3D > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#115617): > https://edk2.groups.io/g/devel/message/115617 > Mute This Topic: https://groups.io/mt/104461797/2558558 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [w.sheng@intel.com] > -=3D-=3D-=3D-=3D-=3D-=3D >=20 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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